Solid-state imaging sensor, method for controlling same, and solid-state imaging system

Abstract

The invention provides a solid imaging sensor, which comprises a 2D pixel array, each array unit of the 2D pixel array comprises a photosensitive unit and a pixel reading unit, each photosensitive unit comprises a photodiode and a transmission transistor connected with the photodiode, and the pixel reading unit is arranged corresponding to at least one photosensitive unit; the row parallel change detection circuit is used for carrying out brightness change detection based on the light response signal of the corresponding light sensing unit; the row parallel ADC circuit is used for performing analog-to-digital conversion on a light response signal of the corresponding light sensing unit; the line scanning control circuit is used for outputting line control signals to the photosensitive units and the pixel reading units; the plurality of groups of longitudinal wires are used for connecting a part of or all array units in the 2D pixel array to the corresponding change detection circuits and / or ADC (Analog to Digital Converter) conversion circuits; and the switch control circuit group is used for controlling the connection relation between each array unit and the change detection circuit as well as the ADC conversion circuit so as to switch the working mode of each array unit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a solid-state imaging sensor, a control method, and a solid-state imaging system. Background Art

[0002] Traditional triangulation ranging systems use a linear photosensitive array and a light source combination. By irradiating the measured scene with a light source, the distance is measured. In this system, the photosensitive linear array directly extracts the optical signal. The following problems exist: the brightness of the measured scene is non-uniform, and a stronger light source is required for supplementary lighting to improve the signal-to-noise ratio, which in turn increases the system power consumption, and the strong light is also unfavorable for the safety of the human eye; in addition, the signal generated by the photosensitive array for the light intensity is linearly proportional, and the dynamic range is small; finally, since the optical signal is an analog signal, AD conversion is required. Generally, there is only 1 ADC on each chip, resulting in a long AD conversion time and affecting the frame rate. In summary, how to improve the accuracy, dynamic range, and frame rate of such systems in complex environments is an important issue.

[0003] DVS (Dynamic Vision Sensor) / EVS (Event Vision Sensor) is a sensor circuit technology that can efficiently extract the brightness change information of each pixel (for convenience, hereinafter collectively referred to as DVS). Refer to the attached Figure 1 , this circuit technology realizes the brightness change detection function through a logarithmic transformation module of photocurrent, a change integration and reset module, and a quantization module. Among them, the logarithmic transformation module realizes the high dynamic range of DVS, the change integration and reset module realizes the real-time high-speed detection of light intensity changes, and the quantization module realizes the analog-to-digital conversion function. Figure 1 In the circuit shown, in order to further improve the performance of the circuit, a driving ability enhancement module is also added between the logarithmic transformation module and the change integration and reset module. For a detailed description of DVS, reference can be made to the Chinese patent "Photosensitive Element Array for Detecting Time-Related Image Data" with the publication number CN101204079A, which will not be further elaborated here.

[0004] Traditional DVSs adopt a 2D parallel architecture. The complex structure of DVSs determines that it is difficult to make individual pixels small without using 3D-Cu-Cu interconnection technology. If it is necessary to make individual pixels, for example, smaller than 3um, then the Cu-Cu interconnection technology becomes essential. For example, the Chinese invention patent with the publication number CN113170064 A discloses a solid-state imaging element, an imaging device, and a method for controlling a solid-state imaging element. The solid-state imaging element is provided with a photoelectric conversion element, a charge storage unit, a transfer transistor, a detection unit, and a connection transistor. The photoelectric conversion element generates charges through photoelectric conversion. The charge storage unit stores charges and generates a voltage corresponding to the amount of the charges. The transfer transistor transfers the charges from the photoelectric conversion element to the charge storage unit. The detection unit detects whether the change amount of the photocurrent corresponding to the amount of the charges exceeds a predetermined threshold. The connection transistor connects the charge storage unit and the detection unit and transfers the photocurrent. This invention enables the solid-state imaging element for detecting address events to further capture images. However, the DVS circuit used in this invention is 2D parallel distributed and exists within the pixel array. The circuit scale of the DVS is large, and the corresponding chip cost is high. Only by adopting 3D stacking can the DVS function be realized in a small area.

[0005] Therefore, how to implement DVS signal processing for small pixels in a non-3D Cu-Cu interconnection sensor process becomes a technical difficulty. Summary of the Invention

[0006] Based on the above background, the purpose of the present invention is to provide a solid-state imaging sensor, which realizes the DVS function and the conventional photosensitive function of the entire array without increasing the design difficulty of pixels through the time-division multiplexing of the 1D parallel distributed DVS circuit and the ADC conversion circuit outside the pixel array.

[0007] To achieve the above purpose, the present invention adopts the following technical solutions:

[0008] The first aspect of the present invention provides a solid-state imaging sensor, including:

[0009] A 2D pixel array, each array unit of which includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 1 transfer transistor connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transfer transistor;

[0010] A row parallel change detection circuit, which includes multiple change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array and is used for detecting the change in light brightness based on the light response signals of at least one corresponding photosensitive unit;

[0011] A row-parallel ADC circuit, which includes a plurality of ADC conversion circuits, and each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used for performing analog-to-digital conversion on the optical response signals of at least one photosensitive unit corresponding thereto;

[0012] A row scanning control circuit, which is used for outputting row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array;

[0013] Multiple groups of vertical traces, each group of vertical traces includes a plurality of connection lines, wherein the first connection line connects a global signal, the second connection line is used for connecting at least a part or all of the array units in at least one column of the 2D pixel array to the corresponding change detection circuit, and the third connection line is used for connecting at least a part or all of the array units in at least one column of the 2D pixel array to the corresponding ADC conversion circuit;

[0014] And a switch control circuit group, which includes a plurality of switch control circuits, and each switch control circuit is coupled between the array unit and the change detection circuit and the ADC conversion circuit through the vertical traces, and is used for controlling the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, and further switching the working mode of each array unit.

[0015] In some embodiments, one end of the photodiode in each photosensitive unit is connected to a power supply, and the other end is connected to one source / drain end of a transfer transistor, and the other source / drain end of the transfer transistor is connected to a pixel readout unit;

[0016] Each pixel readout unit respectively includes a reset transistor, an amplification transistor and a strobe transistor. One source / drain end of the reset transistor is connected to one source / drain end of the transfer transistor and the gate of the amplification transistor, the other source / drain end of the reset transistor is connected to the second connection line in the vertical trace, one source / drain end of the amplification transistor is connected to the first connection line in the vertical trace, the other source / drain end is connected to one source / drain end of the strobe transistor, and the other source / drain end of the strobe transistor is connected to the third connection line in the vertical trace; the gates of the transfer transistor, the reset transistor and the strobe transistor are respectively connected to the row control signal output end of the row scanning control circuit.

[0017] In some embodiments, the change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit, and the current-voltage conversion unit is connected to the corresponding connection line in the vertical trace through the switch control circuit.

[0018] In some embodiments, the current-voltage conversion unit is used for performing logarithmic conversion on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

[0019] In some embodiments, the current-voltage conversion unit includes:

[0020] At least one opto-current transistor and at least one amplification transistor, wherein one source / drain terminal of the opto-current transistor is directly or through a current mirror mirroring transistor coupled to a power supply, and the other source / drain terminal is directly connected to the second connection line through at least one switching transistor in a switching control circuit. One source / drain terminal of the local amplification transistor is connected to the gate of the opto-current transistor for outputting a voltage corresponding to the opto-current, and the other source / drain terminal is grounded;

[0021] And a bias current generation circuit for providing a bias current when the amplification transistor operates.

[0022] In some embodiments, the current-voltage conversion unit includes:

[0023] At least two opto-current transistors and at least two local amplification transistors, wherein one source / drain terminal of the first opto-current transistor is directly or through a current mirror mirroring transistor coupled to a power supply, and the other source / drain terminal is connected to one source / drain terminal of the second opto-current transistor and the gate of the second local amplification transistor; the other source / drain terminal of the second opto-current transistor is connected to the gate of the first local amplification transistor and is connected to the second connection line through one switching transistor in a switching control circuit; one source / drain terminal of the second local amplification transistor is coupled to the gate of the first opto-current transistor for outputting a voltage corresponding to the opto-current, and the other source / drain terminal is connected to the gate of the second opto-current transistor and one source / drain terminal of the first local amplification transistor, and the other source / drain terminal of the first local amplification transistor is grounded;

[0024] Alternatively, at least two opto-current transistors and at least one local amplification transistor, wherein one source / drain terminal of the first opto-current transistor is directly or through a current mirror mirroring transistor coupled to a power supply, and the other source / drain terminal is connected to one source / drain terminal and the gate of the second opto-current transistor; the other source / drain terminal of the second opto-current transistor is connected to the gate of the local amplification transistor and is connected to the second connection line through one switching transistor in a switching control circuit; one source / drain terminal of the local amplification transistor is coupled to the gate of the first opto-current transistor for outputting a voltage corresponding to the opto-current, and the other source / drain terminal is grounded;

[0025] And a bias current generation circuit for providing a bias current when the amplification transistor and the local amplification transistor operate.

[0026] In some embodiments, each switch control circuit includes at least three switching transistors. One source / drain terminal of the first switching transistor is connected to a first voltage, and the other source / drain terminal is connected to the second connection line. One source / drain terminal of the second switching transistor is connected to the photocurrent transistor in the current-voltage conversion unit, and the other source / drain terminal is connected to the second connection line. One source / drain terminal of the third switching transistor is connected to the third connection line and the input terminal of the ADC conversion circuit, and the other source / drain terminal is coupled to a current source. The gate of the first switching transistor is coupled to a first control signal, the gate of the second switching transistor is coupled to a second control signal, and the gate of the third switching transistor is coupled to a third control signal. The first control signal and the third control signal are in-phase and inverted signals from the same source.

[0027] In some embodiments, the row-parallel change detection circuit and the row-parallel ADC circuit are respectively located on two sides of the 2D pixel array.

[0028] In some embodiments, a reset control unit is further configured in each change detection circuit. The reset control unit is used to reset the change detection circuit based on a reset control signal. The reset control signal is dedicated to each change detection circuit, or is shared by some or all of the change detection circuits.

[0029] In some embodiments, the 2D pixel array further includes array units that are directly or through a switch control circuit connected only to the change detection circuit, and / or array units that are directly or through a switch control circuit connected only to the ADC conversion circuit.

[0030] In some embodiments, the photodiodes in the 2D pixel array include different types of photodiodes.

[0031] In some embodiments, some of the photodiodes in the 2D pixel array are designed to receive infrared light, and some of the photodiodes are designed to receive visible light including RGB.

[0032] In some embodiments, the photodiodes in the 2D pixel array are designed to have photosensitive areas of different sizes.

[0033] In some embodiments, the solid-state imaging sensor further includes:

[0034] Multiple counters, each counter is shared by at least one of the change detection circuits and at least one of the ADC conversion circuits.

[0035] In some embodiments, the counter is placed around the 2D pixel array or in the row-parallel change detection circuit, and is multiplexed for the change detection circuit and the ADC conversion circuit through switching, or is placed in the row-parallel ADC circuit and is multiplexed for the ADC conversion circuit and the change detection circuit through switching.

[0036] The second aspect of the present invention provides a control method for a solid imaging sensor as described in the first aspect above, including:

[0037] The switch control circuit group controls the on / off of the switching transistors in each switch control circuit based on a mode transformation instruction, so that the array units are respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array units to operate in different modes:

[0038] When at least a part or all of the photosensitive units and the corresponding pixel readout units in at least one column of the 2D pixel array are connected to the ADC conversion circuit, the array units where these photosensitive units are located operate in the CIS readout mode;

[0039] When at least a part or all of the photosensitive units and some transistors in the corresponding pixel readout units in at least one column of the 2D pixel array are connected to the change detection circuit, the array units where these photosensitive units are located operate in the DVS readout mode.

[0040] In some embodiments, based on the different operating modes of the array units, the solid imaging sensor can be switched to operate in one of the following several modes:

[0041] CIS readout mode;

[0042] DVS readout mode;

[0043] CIS frame readout and DVS frame readout are alternated;

[0044] Or, DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through row-by-row staggered readout or different-row time-division multiplexing.

[0045] The third aspect of the present invention further provides a solid imaging system, including:

[0046] A solid imaging sensor as described in the first aspect above;

[0047] An active light source, which is used to provide a light source for the DVS readout mode of the solid imaging sensor;

[0048] And a processor, which is integrated on the solid imaging sensor or independently configured and is equipped with a triangulation ranging calculation unit;

[0049] Among them, the solid-state imaging sensor is used to collect light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event according to the brightness change of the light reflected by the object to be measured based on the DVS readout mode. The processor is used to calculate the distance of the object to be measured through triangulation based on the brightness change event, and then obtain a 3D imaging signal, thereby realizing 2D and 3D fusion imaging.

[0050] The beneficial technical effects of the present invention are as follows:

[0051] The solid imaging sensor of the present invention realizes the DVS function and conventional photosensitivity function of the whole array without increasing the difficulty of pixel design by time-sharing multiplexing of 1D parallel distributed DVS circuits and ADC conversion circuits outside the pixel array, thus overcoming the defects of large circuit scale for realizing the DVS function and high chip cost caused by using Cu-Cu high-density 3D stacking process in order to reduce the area. The solid imaging sensor and solid imaging system of the present invention can work in a variety of readout modes as needed, and can obtain RGB images based on CIS readout mode, and can obtain area array distance information by triangulation based on DVS readout mode. Compared with the traditional triangulation ranging sensor based on CIS linear array plus ADC, the triangulation ranging based on DVS in the present invention has a higher frame rate, a larger dynamic range, and can realize 2D and 3D fusion imaging, so it has better adaptability to application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a circuit schematic diagram of a DVS circuit in the prior art.

[0053] Figure 2 FIG. 4 is a schematic structural diagram of a solid-state imaging sensor embodiment of the present invention.

[0054] Figure 3 FIG. 4 is a partial circuit schematic diagram of a solid-state imaging sensor embodiment of the present invention.

[0055] Figure 4 Several other exemplary circuit schematic diagrams of the current-voltage conversion unit of the change detection circuit in the solid-state imaging sensor embodiment of the present invention.

[0056] Figure 5 FIG. 4 is another exemplary circuit schematic diagram of an array unit in an embodiment of a solid-state imaging sensor of the present invention.

[0057] Figure 6 The present invention provides a circuit diagram of a solid-state imaging sensor embodiment in which a reset control circuit is added to the row parallel change detection circuit.

[0058] Figure 7Schematic diagram showing different connection relationships of photodiodes configured in a photosensitive unit in an embodiment of the solid imaging sensor of the present invention.

[0059] Figure 8 Schematic diagram showing photosensitive units configured with different types and sizes of photodiodes in an embodiment of the solid imaging sensor of the present invention.

[0060] Figure 9 Schematic diagram showing the first arrangement mode of counters in an embodiment of the solid imaging sensor of the present invention.

[0061] Figure 10 Schematic diagram showing the second arrangement mode of counters in an embodiment of the solid imaging sensor of the present invention.

[0062] Figure 11 Schematic diagram showing the third arrangement mode of counters in an embodiment of the solid imaging sensor of the present invention. Detailed implementation manners

[0063] To further understand the present invention, the preferred implementation manners of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0064] Refer to Appendix Figure 2 and 3 , an embodiment of the present invention provides a solid imaging sensor, including:

[0065] A 2D pixel array 10, which includes 480x360 array units. Each array unit includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and a transfer transistor connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transfer transistor;

[0066] A row parallel change detection circuit (i.e., a row parallel DVS circuit) 11, which includes a plurality of change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used for performing light intensity change detection based on the light response signals of at least one photosensitive unit corresponding thereto;

[0067] A row parallel ADC circuit 12, which includes a plurality of ADC conversion circuits. Each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used for performing analog-to-digital conversion on the light response signals of at least one photosensitive unit corresponding thereto;

[0068] A row scan control circuit 13, which is used for outputting row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array;

[0069] Multiple sets of vertical traces, each set of vertical traces including a plurality of connection lines, wherein the first connection line connects a global signal (i.e., power supply VDD, which is used to supply power or a certain voltage to each array unit and belongs to a column global signal; and this signal will also be connected to the same signal of other columns at the top level in most designs, serving as a global signal), the second connection line is used to connect some or all of the array units in at least one column of the 2D pixel array to the corresponding change detection circuit, and the third connection line is used to connect some or all of the array units in at least one column of the 2D pixel array to the corresponding ADC conversion circuit;

[0070] And a switch control circuit group, which includes a plurality of switch control circuits. Each switch control circuit is coupled between the array unit and the change detection circuit and the ADC conversion circuit via the vertical traces, and is used to control the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, thereby switching the working mode of each array unit.

[0071] See Appendix Figure 2 In the present illustrated example, the row-parallel change detection circuit and the row-parallel ADC circuit are respectively located on both sides of the 2D pixel array. By adopting this layout method, the layout and traces of the entire sensor chip can be better optimized, and it is more convenient for fabrication. In another embodiment, the row-parallel change detection circuit and the row-parallel ADC circuit may also be located on the same side of the 2D pixel array, which is not limited herein.

[0072] See Appendix Figure 3 In the present illustrated example, 4 array units (respectively located in rows 20, 21, 22, and 23) in a certain column ( Figure 3 the 12th column is shown in

[0073] of the 2D pixel array are shown) are connected to an ADC conversion circuit in the row-parallel ADC circuit and a change detection circuit in the row-parallel change detection circuit through a set of vertical traces and a switch control circuit.

[0074] Each pixel readout unit includes a reset transistor RST, an amplification transistor AMP, and a strobe transistor SEL respectively. One source / drain terminal of the reset transistor RST is connected to one source / drain terminal of the transfer transistor TRG and the gate of the amplification transistor AMP. The other source / drain terminal of the reset transistor RST is connected to the second connection line in the longitudinal trace. One source / drain terminal of the amplification transistor AMP is connected to the first connection line in the longitudinal trace, and the other source / drain terminal is connected to one source / drain terminal of the strobe transistor SEL. The other source / drain terminal of the strobe transistor SEL is connected to the third connection line in the longitudinal trace. The gates of the transfer transistor TRG, the reset transistor RST, and the strobe transistor SEL are respectively connected to the row control signal output terminals of the row scanning control circuit.

[0075] See the appendix Figure 3 , in this illustrated example, the change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit (the division of each unit can be referred to in the appendix Figure 1 ). Among them, the current-voltage conversion unit is connected to the corresponding connection line in the longitudinal trace through the switch control circuit, and is used to perform logarithmic conversion on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

[0076] See the appendix Figure 3 , in this illustrated example, the current-voltage conversion unit includes a photocurrent transistor LOG and an amplification transistor AMP1. One source / drain terminal of the photocurrent transistor LOG is coupled to the power supply VDD, and the other source / drain terminal is directly connected to the second connection line through a switching transistor SW_EVS in the switch control circuit. The gate is connected to one source / drain terminal of the amplification transistor AMP1 and is used to output the voltage V corresponding to the photocurrent sf , and the other source / drain terminal of the amplification transistor AMP1 is grounded. It also includes a bias current generation circuit composed of a transistor LMP, which is used to provide the bias current when the amplification transistor AMP1 works.

[0077] See the appendix Figure 4(a), In another illustrated example, the current-voltage conversion unit includes two photocurrent transistors LOG1 and LOG2, and two local amplification transistors AMP1 and AMP2. One source / drain terminal of the first photocurrent transistor LOG1 is coupled to the power supply VDD, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor LOG2 and the gate of the second local amplification transistor AMP2. The other source / drain terminal of the second photocurrent transistor LOG2 is connected to the gate of the first local amplification transistor AMP1 and is connected to the second connection line through a switching transistor in the switch control circuit. One source / drain terminal of the second local amplification transistor AMP2 is coupled to the gate of the first photocurrent transistor LOG1 and is used to output the voltage corresponding to the photocurrent, and the other source / drain terminal is connected to the gate of the second photocurrent transistor LOG2 and one source / drain terminal of the first local amplification transistor AMP1. The other source / drain terminal of the first local amplification transistor AMP1 is grounded. A bias current generation circuit composed of a transistor LMP is further included for providing a bias current when the amplification transistor operates.

[0078] See the appendix Figure 4 (b), In another illustrated example, the current-voltage conversion unit includes two photocurrent transistors LOG1 and LOG2, and one local amplification transistor AMP1. One source / drain terminal of the first photocurrent transistor LOG1 is coupled to the power supply VDD, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor LOG2 and the gate. The other source / drain terminal of the second photocurrent transistor LOG2 is connected to the gate of the local amplification transistor AMP1 and is connected to the second connection line through a switching transistor in the switch control circuit. One source / drain terminal of the local amplification transistor AMP1 is coupled to the gate of the first photocurrent transistor and is used to output the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded.

[0079] It should be noted that in another illustrated example, the current-voltage conversion unit can also be set as Figure 4 (c) The circuit shown. The above circuits can all achieve the function of logarithmically converting the photocurrent generated by the photosensitive unit into a voltage, and specific limitations are not made here.

[0080] It should be noted that in the above embodiments, the source / drain terminal of the photocurrent transistor LOG or LOG1 is coupled to the power supply VDD through the capacitor C4 and the current mirror mirror transistor (see the appendix Figure 3 ). The function of the current mirror mirror transistor is to obtain the total current value and copy it to other branches in a certain proportion for regulation.

[0081] See the appendix Figure 3, in the illustrated example, each switch control circuit includes at least 3 switch transistors. One source / drain terminal of the first switch transistor SW_CIS is connected to the first voltage VRST, and the other source / drain terminal is connected to the second connection line. One source / drain terminal of the second switch transistor SW_EVS is connected to the photoelectric current transistor in the current-voltage conversion unit, and the other source / drain terminal is connected to the second connection line. One source / drain terminal of the third switch transistor SW_CIS2 is connected to the third connection line and the input terminal of the ADC conversion circuit, and the other source / drain terminal is coupled to the current source. Figure 3 The current source shown in [the text] includes a transistor LMN, and the current magnitude of this branch is controlled by the gate voltage LM_BIAS. In another embodiment, the current source here can also be composed of two folded cascode transistors or other methods, which are not limited herein. At the same time, the gate of the first switch transistor SW_CIS is coupled to the first control signal XMODE_CIS, the gate of the second switch transistor SW_EVS is coupled to the second control signal MODE_EVS, the gate of the third switch transistor SW_CIS2 is coupled to the third control signal MODE_CIS, and the first control signal XMODE_CIS and the third control signal MODE_CIS are in-phase inverted signals from the same source.

[0082] It should be noted that in the above example, only one necessary switch transistor among the related switch transistors is shown. In another embodiment, in addition to the one necessary switch transistor shown, additional switch transistors can also be added to the connections of each device to further optimize or enrich the circuit function, which is not limited herein.

[0083] See the appendix Figure 5 , in another illustrated example of the present invention, each array unit of the 2D pixel array includes 4 photosensitive units and one pixel readout unit. Each photosensitive unit includes 1 photodiode and a transfer transistor TRG connected thereto. The pixel readout unit is provided corresponding to 4 photosensitive units and includes a reset transistor RST, an amplification transistor AMP, and a strobe transistor SEL.

[0084] Adopting this design can further reduce the area of each array unit, and each array unit can include different photosensitive units, and each photosensitive unit is configured with different types of photodiodes, making its applicable scenarios more flexible and accurate.

[0085] See the appendix Figure 6 , in another illustrated example of the present invention, a reset control circuit is also configured in each change detection circuit. The reset control circuit is used to reset the change detection circuit based on the reset control signal. The reset control signal can be dedicated to each change detection circuit, or shared by some or all of the change detection circuits.

[0086] See the appendixFigure 7 , in another exemplary embodiment of the present invention, each array unit of the 2D pixel array further includes a photosensitive unit (or photodiode pixel) that is only connected to the row-parallel change detection circuit or only connected to the row-parallel ADC circuit, making the layout or function of the entire array more flexible and adaptable.

[0087] Alternatively, in another exemplary embodiment of the present invention, the 2D pixel array may also be provided with array units that are directly or through a switch control circuit only connected to the change detection circuit, and / or array units that are directly or through a switch control circuit only connected to the ADC conversion circuit, making the layout or function of the entire array more flexible and adaptable.

[0088] See the appendix Figure 8 , in another exemplary embodiment of the present invention, the photodiodes in the 2D pixel array may adopt different types of photodiodes. For example, some photodiodes are designed to receive infrared light, and some photodiodes are designed to receive visible light including RGB, including different types of photodiodes that respectively receive light in different wavelength bands such as red, green, and blue light. Each type of photodiode only receives visible light in a specific wavelength band. For example, some pixels can only receive red light, some pixels can only receive green light, etc., and they are arranged in an RGB alternating pattern. The photodiodes can also be designed to have different sizes of photosensitive areas, making the layout or function of the entire array more flexible.

[0089] In another exemplary embodiment of the present invention, the solid-state imaging sensor further includes a plurality of counters, and each counter is shared by at least one change detection circuit and at least one ADC conversion circuit. Compared with the prior art where each ADC conversion circuit and change detection circuit are configured with their own counters, the solution of the present invention can further save chip volume and reduce costs.

[0090] See the appendix Figure 9 , in one arrangement, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit) and the row-parallel ADC circuit are arranged on both sides of the 2D pixel array, and a plurality of counters are arranged around the 2D pixel array.

[0091] See the appendix Figure 10 , in another arrangement, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit), the row-parallel ADC circuit, and a plurality of counters are arranged on the same side of the 2D pixel array.

[0092] See the appendix Figure 11 , in another arrangement, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit) and the row-parallel ADC circuit are arranged on the same side of the 2D pixel array, and a plurality of counters are arranged on the other side.

[0093] In another arrangement, the counter can also be placed in the parallel change detection circuit and multiplexed by switching for the change detection circuit and the ADC conversion circuit, or placed in the row-parallel ADC circuit and multiplexed by switching for the ADC conversion circuit and the change detection circuit, which is not limited herein.

[0094] An embodiment of the present invention also provides a control method for the solid-state imaging sensor shown above, including:

[0095] The switch control circuit group controls the on / off of the switching transistors in each switch control circuit based on the mode change instruction, so that the array units are respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array units to operate in different modes:

[0096] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and the corresponding pixel readout units are connected to the ADC conversion circuit, the array units where these photosensitive units are located operate in the CIS readout mode;

[0097] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and some transistors in the corresponding pixel readout units are connected to the change detection circuit, the array units where these photosensitive units are located operate in the DVS readout mode.

[0098] See the appendix Figure 3 , based on the shown example, in the CIS working mode, XMODE_CIS = 0, MODE_EVS = 0, MODE_CIS = 1;

[0099] SW_CIS (P-type transistor), SW_CIS2 (N-type transistor) are turned on, the RST transistor in the pixel readout unit is connected to the corresponding voltage VRST, and the photodiode signal is transmitted to the ADC conversion circuit;

[0100] SW_EVS is turned off, and the photodiode signal will not be transmitted to the DVS processing circuit.

[0101] In the DVS working mode, XMODE_CIS = 1, MODE_EVS = 1, MODE_CIS = 0;

[0102] SW_CIS and SW_CIS2 are turned off, and the photodiode signal will not be transmitted to the ADC conversion circuit;

[0103] SW_EVS is turned on, the photodiode is connected to the source / drain terminal of the logarithmic conversion transistor LOG through the TRG transistor, RST transistor, and SW_EVS transistor, and the output signal of the photodiode is output to the DVS processing circuit through the TRG transistor.

[0104] Based on the above description, the solid-state imaging sensor of the present invention can support the following operating modes:

[0105] Single-mode operation: CIS mode and DVS mode;

[0106] Asynchronous hybrid mode: Alternate CIS frame readout and DVS frame readout.

[0107] The sensor generally performs progressive scanning (or every N-line scanning), progressive readout (or sequential readout of every N lines) until the entire array is read out as one frame.

[0108] Furthermore, it can also support:

[0109] Synchronous hybrid mode: This mode is the main usage mode of the sensor of the present invention. DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through the method of staggered readout by rows or time-division multiplexing of different rows, and then realize simultaneous readout of DVS frames and CIS frames.

[0110] Specifically, the way that DVS and CIS perform staggered readout by rows is as follows:

[0111] Read the first row of CIS, and then read the first row of DVS;

[0112] Read the second row of CIS, and then read the second row of DVS;

[0113] ……

[0114] Read the last row of CIS, and then read the last row of DVS.

[0115] Or, perform DVS readout by combining every 3 rows of pixels, aiming to increase the photosensitive area to match the size of the reflected light spot. The readout method is as follows:

[0116] Read the first row of CIS, the second row of CIS, and the third row of CIS;

[0117] Read the DVS readout combined from the 1st to 3rd rows;

[0118] Read the fourth row of CIS, the fifth row of CIS, and the sixth row of CIS;

[0119] Read the DVS readout combined from the 4th to 6th rows;

[0120] ……

[0121] In this example, performing DVS readout by combining 3 rows of pixels is just an example. The specific number of rows for combination for DVS readout can be determined according to needs and is not limited here.

[0122] The DVS and CIS can be read out by time-division multiplexing of different rows. It can be that one or several rows are read in the DVS mode first and then in the CIS mode. In the CIS readout mode, the pixels do not need to output signals to the ADC during the exposure process, so the column bus does not need to be occupied. At this time, the DVS or CIS readout of other rows can be performed, so as to further realize the reasonable utilization of the readout time by taking advantage of the repeated use of time, and then improve the readout frame rate of the sensor chip.

[0123] Specifically, the time-division multiplexing readout method of the DVS and CIS is as follows:

[0124] The first row is read in the DVS mode, and then the first row is read in the CIS mode. During the exposure process, the second row is read in the DVS mode at the same time;

[0125] Then the second row is read in the CIS mode. During the exposure process, the third row is read in the DVS mode at the same time;

[0126] ……

[0127] Finally, the last row is read in the DVS mode, and then the last row is read in the CIS mode.

[0128] Or, the pixels of the first to third rows are combined for DVS readout, and then the first row, the second row, and the third row are read in the CIS mode in sequence. During the exposure process of the third row, the pixels of the fourth to sixth rows are combined for DVS readout;

[0129] Then the fourth row, the fifth row, and the sixth row are read in the CIS mode in sequence. During the exposure process of the sixth row, the pixels of the seventh to ninth rows are combined for DVS readout;

[0130] ……

[0131] Finally, the last few rows are read in the DVS mode, and then read in the CIS mode row by row.

[0132] In the above examples, the exposure process is included in the readout process.

[0133] In this example, the combination of the pixels of the first to third rows for DVS readout is only an example. The specific number of rows for combination for DVS readout can be determined according to needs and is not limited here.

[0134] In another embodiment of the present invention, some rows in the sensor can also be selected as the effective readout area, and all the pixels in the effective readout area are read as one frame. For example, the odd rows such as 1, 3, 5, 7 are selected as the first effective readout area, and the even rows such as 2, 4, 6, 8 are selected as the second effective readout area.

[0135] At this time, the sensor can also perform staggered readout by rows based on different effective readout areas. For example:

[0136] The first row is read in the CIS mode;

[0137] Second - row DVS readout;

[0138] Third - row CIS readout;

[0139] Fourth - row DVS readout;

[0140] ……

[0141] Although this readout method will result in the loss of information of some rows and reduce the resolution, it can improve the frame rate and can be adopted according to actual requirements.

[0142] The embodiment of the present invention also provides a solid - state imaging system, including:

[0143] The solid - state imaging sensor as described in the foregoing embodiment;

[0144] An active light source, which is used to provide a light source for the DVS readout mode of the solid - state imaging sensor;

[0145] And a processor, which is integrated on the solid - state imaging sensor or independently configured and is configured with a triangulation ranging calculation unit;

[0146] Wherein, the solid - state imaging sensor is used to collect the light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event according to the brightness change of the light reflected by the object to be measured based on the DVS readout mode. The processor is used to calculate the distance of the object to be measured by triangulation based on the brightness change event, and then obtain a 3D imaging signal, so as to realize 2D - and - 3D fusion imaging.

[0147] Based on the above - mentioned system, the present invention realizes 2D imaging and DVS triangulation ranging simultaneously without significantly increasing the chip area and generates matching 2D / 3D information. At the same time, since the RGB information obtained by 2D imaging and the distance information obtained by DVS triangulation ranging come from the same optical window, the matching of RGB and D (distance) is automatically realized, which also provides high - quality information for subsequent signal processing.

[0148] The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A solid-state imaging sensor, characterized in that, Comprising: A 2D pixel array, each array unit of which includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 1 transfer transistor connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transfer transistor; A row-parallel change detection circuit, which includes a plurality of change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column in the 2D pixel array, and is used for performing light brightness change detection based on the light response signals of at least one corresponding photosensitive unit; A row-parallel ADC circuit, which includes a plurality of ADC conversion circuits. Each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column in the 2D pixel array, and is used for performing analog-to-digital conversion on the light response signals of at least one corresponding photosensitive unit; A row scan control circuit, which is used for outputting row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array; Multiple groups of vertical traces, each group of vertical traces includes several connection lines. Among them, the first connection line connects the global signal, the second connection line is used for connecting at least a part or all of the array units in at least one column in the 2D pixel array to the corresponding change detection circuit, and the third connection line is used for connecting at least a part or all of the array units in at least one column in the 2D pixel array to the corresponding ADC conversion circuit; And a switch control circuit group, which includes a plurality of switch control circuits. Each switch control circuit is coupled between the array unit, the change detection circuit and the ADC conversion circuit through the vertical traces, and is used for controlling the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, and further switching the working mode of each array unit.

2. The solid-state imaging sensor according to claim 1, wherein, One end of the photodiode in each photosensitive unit is connected to the power supply, and the other end is connected to one source / drain end of the transfer transistor. The other source / drain end of the transfer transistor is connected to the pixel readout unit; Each pixel readout unit respectively includes a reset transistor, an amplification transistor and a strobe transistor. Among them, one source / drain end of the reset transistor is connected to one source / drain end of the transfer transistor and the gate of the amplification transistor, the other source / drain end of the reset transistor is connected to the second connection line in the vertical traces, one source / drain end of the amplification transistor is connected to the first connection line in the vertical traces, the other source / drain end is connected to one source / drain end of the strobe transistor, and the other source / drain end of the strobe transistor is connected to the third connection line in the vertical traces; The gates of the transfer transistor, the reset transistor and the strobe transistor are respectively connected to the row control signal output end of the row scan control circuit.

3. The solid-state imaging sensor according to claim 2, characterized in that, The change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit. The current-voltage conversion unit is connected to the corresponding connection line in the vertical traces through the switch control circuit.

4. The solid-state imaging sensor according to claim 3, wherein, The current-voltage conversion unit is used for performing logarithmic conversion on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

5. The solid-state imaging sensor according to claim 4, wherein The current-voltage conversion unit includes: At least one photocurrent transistor and at least one local amplification transistor, wherein one source / drain terminal of the photocurrent transistor is coupled to a power supply directly or through a current mirror mirroring transistor, and the other source / drain terminal is directly connected to the second connection line through at least one switching transistor in a switch control circuit; one source / drain terminal of the local amplification transistor is connected to the gate of the photocurrent transistor for outputting a voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; And a bias current generation circuit for providing a bias current when the amplification transistor operates.

6. The solid-state imaging sensor according to claim 4, wherein The current-voltage conversion unit includes: At least two photocurrent transistors and at least two local amplification transistors, wherein one source / drain terminal of the first photocurrent transistor is coupled to a power supply directly or through a current mirror mirroring transistor, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor and the gate of the second local amplification transistor; the other source / drain terminal of the second photocurrent transistor is connected to the gate of the first local amplification transistor and is connected to the second connection line through a switching transistor in the switch control circuit; one source / drain terminal of the second local amplification transistor is coupled to the gate of the first photocurrent transistor for outputting a voltage corresponding to the photocurrent, and the other source / drain terminal is connected to the gate of the second photocurrent transistor and one source / drain terminal of the first local amplification transistor, and the other source / drain terminal of the first local amplification transistor is grounded; Alternatively, at least two photocurrent transistors and at least one local amplification transistor, wherein one source / drain terminal of the first photocurrent transistor is coupled to a power supply directly or through a current mirror mirroring transistor, and the other source / drain terminal is connected to one source / drain terminal and the gate of the second photocurrent transistor; the other source / drain terminal of the second photocurrent transistor is connected to the gate of the local amplification transistor and is connected to the second connection line through a switching transistor in the switch control circuit; one source / drain terminal of the local amplification transistor is coupled to the gate of the first photocurrent transistor for outputting a voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; And a bias current generation circuit for providing a bias current when the amplification transistor and the local amplification transistor operate.

7. The solid-state imaging sensor according to any one of claims 4 to 6, characterized in that, Each of the switch control circuits includes at least three switching transistors, wherein one source / drain terminal of the first switching transistor is connected to a first voltage, and the other source / drain terminal is connected to the second connection line; one source / drain terminal of the second switching transistor is connected to the photocurrent transistor in the current-voltage conversion unit, and the other source / drain terminal is connected to the second connection line; one source / drain terminal of the third switching transistor is connected to the third connection line and the input terminal of the ADC conversion circuit, and the other source / drain terminal is coupled to a current source; the gate of the first switching transistor is coupled to a first control signal, the gate of the second switching transistor is coupled to a second control signal, the gate of the third switching transistor is coupled to a third control signal, and the first control signal and the third control signal are in-phase and inverted signals of the same source.

8. The solid-state imaging sensor according to claim 1, wherein, The row-parallel change detection circuit and the row-parallel ADC circuit are respectively located on both sides of the 2D pixel array.

9. The solid-state imaging sensor according to claim 3, wherein Each change detection circuit is also configured with a reset control circuit, which is used to reset the change detection circuit based on a reset control signal. The reset control signal is dedicated to each change detection circuit, or is shared by some or all of the change detection circuits.

10. The solid-state imaging sensor according to any one of claims 1-6, characterized in that, The 2D pixel array further includes array units that are directly or through a switch control circuit connected only to the change detection circuit, and / or array units that are directly or through a switch control circuit connected only to the ADC conversion circuit.

11. The solid-state imaging sensor according to claim 1, wherein The photodiodes in the 2D pixel array include different types of photodiodes.

12. The solid-state imaging sensor according to claim 11, wherein, Some of the photodiodes in the 2D pixel array are designed to receive infrared light, and some of the photodiodes are designed to receive visible light including RGB.

13. The solid-state imaging sensor according to claim 11, characterized in that, The photodiodes in the 2D pixel array are designed to have photosensitive areas of different sizes.

14. The solid-state imaging sensor according to any one of claims 1-6, 8-9 or 11-13, characterized in that, It further includes: Multiple counters, each counter is shared by at least one of the change detection circuits and at least one ADC conversion circuit.

15. The solid-state imaging sensor according to claim 14, wherein, The counters are placed around the 2D pixel array, or placed in the row-parallel change detection circuit, and are time-division multiplexed for the change detection circuit and the ADC conversion circuit through switching, or placed in the row-parallel ADC circuit, and are time-division multiplexed for the ADC conversion circuit and the change detection circuit through switching.

16. A control method for a solid-state imaging sensor according to any one of claims 1-15, characterized in that, It includes: The switch control circuit group controls the on / off of the switching transistors in each switch control circuit based on a mode transformation instruction, so that the array units are respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array units to operate in different modes: When some or all of the photosensitive units in at least one column of the 2D pixel array and the corresponding pixel readout units are connected to the ADC conversion circuit, the array units where these photosensitive units are located operate in the CIS readout mode; When some of the transistors in some or all of the photosensitive units in at least one column of the 2D pixel array and the corresponding pixel readout units are connected to the change detection circuit, the array units where these photosensitive units are located operate in the DVS readout mode.

17. The control method of the solid-state imaging sensor according to claim 16, characterized in that, Based on the different operating modes of the array units, the solid-state imaging sensor can be switched to operate in one of the following several modes: CIS readout mode; DVS readout mode; CIS frame readout and DVS frame readout alternate; Or, DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through row-by-row staggered readout or different-row time-division multiplexing.

18. A solid imaging system, characterized in that, It includes: The solid-state imaging sensor according to any one of claims 1-15; An active light source, which is used to provide a light source for the DVS readout mode of the solid-state imaging sensor; And a processor, which is integrated on the solid-state imaging sensor or independently configured, and is configured with a triangulation ranging calculation unit; Among them, the solid-state imaging sensor is used to collect the light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event based on the DVS readout mode according to the brightness change of the light reflected by the object to be measured. The processor is used to calculate the distance of the object to be measured through triangulation ranging based on the brightness change event, and then obtain a 3D imaging signal, so as to realize 2D and 3D fusion imaging.

Images