Solid-state imaging sensor, method for controlling same, and solid-state imaging system

Abstract

The invention provides a solid imaging sensor, which comprises a 2D pixel array, each array unit of the 2D pixel array comprises a photosensitive unit and a pixel reading unit, each photosensitive unit comprises a photodiode and a transmission transistor connected with the photodiode, and the pixel reading unit is arranged corresponding to at least one photosensitive unit; the row parallel change detection circuit is used for carrying out brightness change detection based on the light response signal of the corresponding light sensing unit; the row parallel ADC circuit is used for performing analog-to-digital conversion on a light response signal of the corresponding light sensing unit; the line scanning control circuit is used for outputting line control signals to the photosensitive units and the pixel reading units; the first group of longitudinal wires and the second group of longitudinal wires are used for connecting part of or all array units in the 2D pixel array to the corresponding change detection circuits and / or ADC conversion circuits; and the switch control circuit group is used for controlling the connection relation between each array unit and the change detection circuit as well as the ADC conversion circuit so as to switch the working mode of each array unit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a solid imaging sensor, a control method, and a solid imaging system. Background Art

[0002] Traditional triangulation ranging systems use a linear photosensitive array and a light source combination. By irradiating a light source on the scene to be measured, the distance is measured. In this system, the linear photosensitive array directly extracts optical signals. The following problems exist: the brightness of the scene to be measured is non-uniform, and a stronger light source is required for fill light to improve the signal-to-noise ratio, which increases the power consumption of the system. The strong light is also not beneficial to the safety of the human eye; in addition, the signal generated by the photosensitive array for the light intensity is in a linear proportion, and the dynamic range is small; finally, since the optical signal is an analog signal, AD conversion is required. Generally, there is only 1 ADC on each chip, resulting in a long AD conversion time and affecting the frame rate. In summary, how to improve the accuracy, dynamic range, and frame rate of such systems in complex environments is an important topic.

[0003] DVS (Dynamic Vision Sensor) / EVS (Event Vision Sensor) is a sensor circuit technology that can efficiently extract the brightness change information of each pixel (hereinafter collectively referred to as DVS for convenience). See the attached Figure 1 , this circuit technology realizes the brightness change detection function through a logarithmic transformation module of photocurrent, a change integration and reset module, and a quantization module. Among them, the logarithmic transformation module realizes the high dynamic range of DVS, the change integration and reset module realizes the real-time high-speed detection of light intensity changes, and the quantization module realizes the analog-to-digital conversion function. Figure 1 In the circuit shown, in order to further improve the performance of the circuit, a driving ability enhancement module is also added between the logarithmic transformation module and the change integration and reset module. For a detailed description of DVS, reference can be made to the Chinese patent "Photosensitive Element Array for Detecting Time-Related Image Data" with the publication number CN101204079A, which will not be further elaborated here.

[0004] Traditional DVS adopts a 2D parallel architecture. The complex structure of DVS determines that it is difficult to make a single pixel small without using 3D-Cu-Cu interconnection technology. If it is necessary to make a single pixel, for example, less than 3um, then the Cu-Cu interconnection technology becomes a must.

[0005] For example, a Chinese invention patent with the publication number CN113170064 A discloses a solid-state imaging element, an imaging device, and a method for controlling the solid-state imaging element. The solid-state imaging element is provided with a photoelectric conversion element, a charge storage unit, a transfer transistor, a detection unit, and a connection transistor. The photoelectric conversion element generates charges through photoelectric conversion. The charge storage unit stores charges and generates a voltage corresponding to the amount of the charges. The transfer transistor transfers the charges from the photoelectric conversion element to the charge storage unit. The detection unit detects whether the change amount of the photocurrent corresponding to the amount of the charges exceeds a predetermined threshold. The connection transistor connects the charge storage unit and the detection unit and transfers the photocurrent. This invention enables the solid-state imaging element for detecting address events to further capture images. However, the DVS circuit used in this invention is 2D parallelly distributed within the pixel array, and the circuit scale of the DVS is large, corresponding to a high chip cost. Only by using 3D stacking can the DVS function be achieved in a small area.

[0006] For example, an international patent with the publication number WO 2020158583 A1 discloses a solid-state imaging device and an imaging device, including a pixel array unit having a plurality of pixel blocks arranged in a matrix form; and a driving circuit that causes a first pixel block in which an address event ignition is detected among the plurality of pixel blocks to generate a pixel signal. Each pixel block includes: a first photoelectric conversion element that generates charges corresponding to the amount of incident light; a detection unit that detects an address event ignition based on the charges generated by the first photoelectric conversion element; a second photoelectric conversion element that generates charges corresponding to the amount of incident light; and a pixel circuit that generates a pixel signal based on the charges generated by the second photoelectric conversion element. The purpose of this patent is to reduce the time displacement between event detection and gradient acquisition. However, this patent only relates to the sharing of DVS circuits within the pixel array based on Cu-Cu stacking.

[0007] Therefore, how to implement DVS signal processing for small pixels in a non-3D Cu-Cu interconnect sensor process has become a technical difficulty. Summary of the Invention

[0008] Based on the above background, the purpose of the present invention is to provide a solid-state imaging sensor, which realizes the DVS function and the conventional photosensitive function of the entire array without increasing the design difficulty of pixels through the time-division multiplexing of 1D parallelly distributed DVS circuits and ADC conversion circuits outside the pixel array.

[0009] To achieve the above purpose, the present invention adopts the following technical solutions:

[0010] The first aspect of the present invention provides a solid-state imaging sensor, including:

[0011] A 2D pixel array, each array unit of which includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 2 transfer transistors connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transfer transistors;

[0012] A row-parallel change detection circuit, which includes a plurality of change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used to perform light intensity change detection based on the light response signals of at least one corresponding photosensitive unit;

[0013] A row-parallel ADC circuit, which includes a plurality of ADC conversion circuits. Each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used to perform analog-to-digital conversion on the light response signals of at least one corresponding photosensitive unit;

[0014] A row scan control circuit, which is used to output row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array;

[0015] Multiple groups of first longitudinal traces, each group of first longitudinal traces including at least one connection line, which is used to connect at least a part or all of the photosensitive units in at least one column of the 2D pixel array to the corresponding change detection circuit;

[0016] Multiple groups of second longitudinal traces, each group of second longitudinal traces including several connection lines. Part of the connection lines are used to connect global signals, and the other part of the connection lines are used to connect at least a part or all of the photosensitive units and pixel readout units in at least one column of the 2D pixel array to the corresponding ADC conversion circuit;

[0017] Wherein, the row scan control circuit controls the opening and closing of the transistors in the photosensitive unit and / or the pixel readout unit by outputting row control signals, and further controls the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, so as to switch the working modes of each array unit.

[0018] In some embodiments, one end of the photodiode in each photosensitive unit is connected to a power supply, and the other end is connected to one source / drain end of each of the two transfer transistors. The other source / drain end of the first transfer transistor is connected to the connection line in the first longitudinal trace, and the other source / drain end of the second transfer transistor is connected to the pixel readout unit;

[0019] Each pixel readout unit includes a reset transistor, an amplification transistor, and a strobe transistor. One source / drain terminal of the reset transistor is connected to the second connection line in the second longitudinal trace, and the other source / drain terminal is connected to the source / drain terminal of the second transfer transistor and the gate of the amplification transistor. One source / drain terminal of the amplification transistor is connected to the first connection line in the second longitudinal trace, and the other source / drain terminal is connected to one source / drain terminal of the strobe transistor. The other source / drain terminal of the strobe transistor is connected to the third connection line in the second longitudinal trace;

[0020] The first connection line and the second connection line in the second longitudinal trace are connected to the global signal, the third connection line is connected to the ADC conversion circuit, and the gates of the first transfer transistor, the second transfer transistor, the reset transistor, and the strobe transistor are respectively connected to the row control signal output terminal of the row scanning control circuit.

[0021] In some embodiments, the change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit. The current-voltage conversion unit is connected to the connection line in the first longitudinal trace.

[0022] In some embodiments, the current-voltage conversion unit is configured to perform a logarithmic transformation on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

[0023] In some embodiments, the current-voltage conversion unit includes:

[0024] At least one photocurrent transistor and at least one local amplification transistor. One source / drain terminal of the photocurrent transistor is coupled to a power supply directly or through a current mirror mirroring transistor, and the other source / drain terminal is connected to the gate of the local amplification transistor and the connection line in the first longitudinal trace; One source / drain terminal of the local amplification transistor is connected to the gate of the first photocurrent transistor for outputting the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded;

[0025] And a bias current generation circuit for providing a bias current when the amplification transistor operates.

[0026] In some embodiments, the current-voltage conversion unit includes:

[0027] At least two photocurrent transistors and at least two local amplification transistors, wherein one source / drain terminal of the first photocurrent transistor is directly or through a current mirror mirroring transistor coupled to a power supply, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor and the gate of the second local amplification transistor; the other source / drain terminal of the second photocurrent transistor is connected to the gate of the local first amplification transistor and to the connection line in the first longitudinal trace; one source / drain terminal of the local second amplification transistor is coupled to the gate of the first photocurrent transistor for outputting a voltage corresponding to the photocurrent, and the other source / drain terminal is connected to the gate of the second photocurrent transistor and one source / drain terminal of the local first amplification transistor, and the other source / drain terminal of the local first amplification transistor is grounded;

[0028] Alternatively, at least two photocurrent transistors and at least one local amplification transistor, wherein one source / drain terminal of the first photocurrent transistor is directly or through a current mirror mirroring transistor coupled to a power supply, and the other source / drain terminal is connected to one source / drain terminal and the gate of the second photocurrent transistor; the other source / drain terminal of the second photocurrent transistor is connected to the gate of the local amplification transistor and to the connection line in the first longitudinal trace; one source / drain terminal of the local amplification transistor is coupled to the gate of the first photocurrent transistor for outputting a voltage corresponding to the photocurrent, and the other source / drain terminal is grounded;

[0029] And a bias current generation circuit for providing a bias current when the local amplification transistor operates.

[0030] In some embodiments, the row parallel change detection circuit and the row parallel ADC circuit are respectively located on both sides of the 2D pixel array.

[0031] In some embodiments, a reset control circuit is further configured in each change detection circuit, and the reset control circuit is used to reset the change detection circuit based on a reset control signal, and the reset control signal is dedicated to each change detection circuit or is shared by some or all of the change detection circuits.

[0032] In some embodiments, the 2D pixel array further includes array units that are directly or through a switch control circuit only connected to the change detection circuit, and / or array units that are directly or through a switch control circuit only connected to the ADC conversion circuit.

[0033] In some embodiments, the photodiodes in the 2D pixel array include different types of photodiodes.

[0034] In some embodiments, some of the photodiodes in the 2D pixel array are designed to receive infrared light, and some of the photodiodes are designed to receive visible light including RGB.

[0035] In some embodiments, the photodiodes in the 2D pixel array are designed to have photosensitive areas of different sizes.

[0036] In some embodiments, the solid-state imaging sensor further includes:

[0037] A plurality of counters, each counter being shared by at least one of the change detection circuits and at least one ADC conversion circuit.

[0038] In some embodiments, the counters are arranged around the 2D pixel array, or placed in the row-parallel change detection circuit and multiplexed by switching for time-sharing use by the change detection circuit and the ADC conversion circuit, or placed in the row-parallel ADC circuit and multiplexed by switching for time-sharing use by the ADC conversion circuit and the change detection circuit.

[0039] The second aspect of the present invention provides a control method for a solid-state imaging sensor as described in the first aspect above, including:

[0040] The row scanning control circuit outputs a row control signal to control the opening and closing of transistors in the photosensitive unit and / or the pixel readout unit, so that the array unit is respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array unit to operate in different modes:

[0041] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and the corresponding pixel readout units are connected to the ADC conversion circuit, the array unit where the part of the photosensitive units is located operates in the CIS readout mode;

[0042] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and some transistors in the corresponding pixel readout units are connected to the change detection circuit, the array unit where the part of the photosensitive units is located operates in the DVS readout mode.

[0043] In some embodiments, based on the different operating modes of the array unit, the solid-state imaging sensor can be switched to operate in one of the following several modes:

[0044] CIS readout mode;

[0045] DVS readout mode;

[0046] CIS frame readout and DVS frame readout are performed alternately;

[0047] Or, DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through row-by-row staggered readout or different-row time-sharing multiplexing.

[0048] In some embodiments, in the DVS readout mode, a transfer transistor in the photosensitive unit connecting the photodiode to the pixel readout unit is controlled to be turned on in a preset interval, and a reset transistor in the pixel readout unit is controlled to be fully turned on;

[0049] In the CIS readout mode, the transfer transistor in the photosensitive unit connecting the photodiode to the change detection circuit is controlled to be turned on in a preset interval.

[0050] A third aspect of the present invention further provides a solid-state imaging system, comprising:

[0051] The solid-state imaging sensor as described in the first aspect above;

[0052] An active light source for providing light for a DVS readout mode of a solid-state imaging sensor;

[0053] and a processor, the processor being integrated on the solid imaging sensor or independently configured and being configured with a triangulation distance calculation unit;

[0054] Among them, the solid-state imaging sensor is used to collect light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event according to the brightness change of the light reflected by the object to be measured based on the DVS readout mode. The processor is used to calculate the distance of the object to be measured through triangulation based on the brightness change event, and then obtain a 3D imaging signal, thereby realizing 2D and 3D fusion imaging.

[0055] The beneficial technical effects of the present invention are as follows:

[0056] The solid imaging sensor of the present invention realizes the DVS function and conventional photosensitivity function of the whole array without increasing the difficulty of pixel design by time-sharing multiplexing of 1D parallel distributed DVS circuits and ADC conversion circuits outside the pixel array, thus overcoming the defects of large circuit scale for realizing the DVS function and high chip cost caused by using Cu-Cu high-density 3D stacking process in order to reduce the area. The solid imaging sensor and solid imaging system of the present invention can work in a variety of readout modes as needed, and can obtain RGB images based on CIS readout mode, and can obtain area array distance information by triangulation based on DVS readout mode. Compared with the traditional triangulation ranging sensor based on CIS linear array plus ADC, the triangulation ranging based on DVS in the present invention has a higher frame rate, a larger dynamic range, and can realize 2D and 3D fusion imaging, so it has better adaptability to application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a circuit schematic diagram of a DVS circuit in the prior art.

[0058] Figure 2 Schematic diagram of the structure of an embodiment of the solid imaging sensor of the present invention.

[0059] Figure 3 Partial circuit schematic diagram of an embodiment of the solid imaging sensor of the present invention.

[0060] Figure 4 Additional several example circuit schematic diagrams of the current-voltage conversion unit of the change detection circuit in an embodiment of the solid imaging sensor of the present invention.

[0061] Figure 5 Another example circuit schematic diagram of the array unit in an embodiment of the solid imaging sensor of the present invention.

[0062] Figure 6 Circuit schematic diagram of the row parallel change detection circuit with a reset control circuit added in an embodiment of the solid imaging sensor of the present invention.

[0063] Figure 7 Schematic diagram showing different connection relationships of the photodiodes configured in the photosensitive unit in an embodiment of the solid imaging sensor of the present invention.

[0064] Figure 8 Schematic diagram showing different types and sizes of photodiodes configured in the photosensitive unit in an embodiment of the solid imaging sensor of the present invention.

[0065] Figure 9 Schematic diagram of the first arrangement mode of the counter in an embodiment of the solid imaging sensor of the present invention.

[0066] Figure 10 Schematic diagram of the second arrangement mode of the counter in an embodiment of the solid imaging sensor of the present invention.

[0067] Figure 11 Schematic diagram of the third arrangement mode of the counter in an embodiment of the solid imaging sensor of the present invention. Detailed implementation manners

[0068] To further understand the present invention, the preferred implementation manners of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0069] See Appendix Figure 2 and 3 , an embodiment of the present invention provides a solid imaging sensor, including:

[0070] A 2D pixel array 10, which includes 480 x 360 array units. Each array unit includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 2 transfer transistors connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transfer transistors;

[0071] A row-parallel change detection circuit (i.e., a row-parallel DVS circuit) 11, which includes multiple change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used to perform light intensity change detection based on the light response signals of at least one corresponding photosensitive unit;

[0072] A row-parallel ADC circuit 12, which includes multiple ADC conversion circuits. Each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used to perform analog-to-digital conversion on the light response signals of at least one corresponding photosensitive unit;

[0073] A row scan control circuit 13, which is used to output row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array;

[0074] Multiple groups of first longitudinal traces. Each group of first longitudinal traces includes at least one connection line, and is used to connect at least a part or all of the photosensitive units in at least one column of the 2D pixel array to the corresponding change detection circuit;

[0075] Multiple groups of second longitudinal traces. Each group of second longitudinal traces includes several connection lines. Part of the connection lines are used to connect global signals, and the other part of the connection lines are used to connect at least a part or all of the photosensitive units and pixel readout units in at least one column of the 2D pixel array to the corresponding ADC conversion circuit;

[0076] Wherein, the row scan control circuit 13 controls the opening and closing of the transistors in the photosensitive unit and / or pixel readout unit by outputting row control signals, and further controls the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, so as to switch the working mode of each array unit.

[0077] See the appendix Figure 2 , in the present illustrated example, the row-parallel change detection circuit and the row-parallel ADC circuit are respectively located on both sides of the 2D pixel array. By adopting this layout method, the layout and routing of the entire sensor chip can be better optimized, and it is more convenient for preparation. In another embodiment, the row-parallel change detection circuit and the row-parallel ADC circuit can also be located on the same side of the 2D pixel array, which is not limited herein.

[0078] See the appendix Figure 3 , the present illustrated example shows a certain column in the 2D pixel array ( Figure 3Four array units (located in the 20th, 21st, 22nd, and 23rd rows respectively) in the 12th column shown in the figure are connected to a change detection circuit in the row parallel change detection circuit (i.e., the row parallel DVS circuit) through the connection lines in the first longitudinal trace (located on the left side of the array unit), and are connected to an ADC conversion circuit in the row parallel ADC circuit through the connection lines in the second longitudinal trace (located on the right side of the array unit).

[0079] Among them, one end of the photodiode in the photosensitive unit of each array unit is connected to the power supply (ground or low voltage or negative voltage), and the other end is connected to one source / drain terminal of each of the two transfer transistors TRG1 and TRG2. The other source / drain terminal of the first transfer transistor TRG2 is connected to the connection line in the first longitudinal trace, and the other source / drain terminal of the second transfer transistor TRG1 is connected to the pixel readout unit;

[0080] Each pixel readout unit respectively includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One source / drain terminal of the reset transistor RST is connected to the second connection line in the second longitudinal trace, and the other source / drain terminal is connected to the source / drain terminal of the second transfer transistor TRG1 and the gate of the amplification transistor AMP. One source / drain terminal of the amplification transistor AMP is connected to the first connection line in the second longitudinal trace, and the other source / drain terminal is connected to one source / drain terminal of the selection transistor SEL. The other source / drain terminal of the selection transistor SEL is connected to the third connection line in the second longitudinal trace;

[0081] The gates of the first transfer transistor TRG2, the second transfer transistor TRG1, the reset transistor RST, and the selection transistor SEL are respectively connected to the row control signal output terminal of the row scanning control circuit.

[0082] In this embodiment, the connection line in the first longitudinal trace is connected to the change detection circuit. The first connection line in the second longitudinal trace is connected to the power supply VDD as a global signal, the second connection line is connected to the power supply VRST as a global signal, the third connection line is connected to the ADC conversion circuit, and is coupled to a current source. Figure 3 The current source shown in the figure includes a transistor LMN, and the current magnitude of this branch is controlled by the gate voltage LM_BIAS. In other embodiments, the current source here can also be composed of two folded cascode transistors or other methods, which are not limited here. Figure 3 The COL_VDD and COL_VRST signals shown in the figure are power supply lines or fixed voltage lines, providing power or a certain voltage for each array unit, belonging to column global signals; and in most designs, this signal will also be connected to the same signal of other columns at the top level as a global signal.

[0083] See the appendix Figure 3, in the present exemplary embodiment, the change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit (for the division of each unit, refer to the appendix Figure 1 ). Among them, the current-voltage conversion unit is connected to the connection line in the first longitudinal trace, and is used to perform logarithmic conversion on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

[0084] Refer to the appendix Figure 3 , in the present exemplary embodiment, the current-voltage conversion unit includes a photocurrent transistor LOG and a local amplification transistor AMP1. One source / drain terminal of the photocurrent transistor LOG is coupled to the power supply VDD, and the other source / drain terminal is connected to the gate of the local amplification transistor AMP1 and the connection line in the first longitudinal trace; one source / drain terminal of the local amplification transistor AMP1 is connected to the gate of the first photocurrent transistor LOG, and is used to output the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; it also includes a bias current generation circuit composed of a transistor LMP, which is used to provide the bias current when the amplification transistor AMP1 works.

[0085] Refer to the appendix Figure 4 (a), in another exemplary embodiment, the current-voltage conversion unit includes two photocurrent transistors LOG1 and LOG2 and two local amplification transistors AMP1 and AMP2. One source / drain terminal of the first photocurrent transistor LOG1 is coupled to the power supply VDD, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor LOG2 and the gate of the second local amplification transistor AMP2; the other source / drain terminal of the second photocurrent transistor LOG2 is connected to the gate of the first local amplification transistor AMP1 and the connection line in the first longitudinal trace; one source / drain terminal of the second local amplification transistor AMP2 is coupled to the gate of the first photocurrent transistor LOG1, and is used to output the voltage corresponding to the photocurrent, and the other source / drain terminal is connected to the gate of the second photocurrent transistor LOG2 and one source / drain terminal of the first local amplification transistor AMP1, and the other source / drain terminal of the first local amplification transistor AMP1 is grounded; it also includes a bias current generation circuit composed of a transistor LMP, which is used to provide the bias current when the amplification transistors AMP1 and AMP2 work.

[0086] Refer to the appendix Figure 4(b), In another illustrated example, the current-voltage conversion unit includes two photocurrent transistors LOG1 and LOG2 and a local amplification transistor AMP1. One source / drain terminal of the first photocurrent transistor LOG1 is coupled to the power supply VDD, and the other source / drain terminal is connected to one source / drain terminal and the gate of the second photocurrent transistor LOG2; the other source / drain terminal of the second photocurrent transistor LOG2 is connected to the gate of the local amplification transistor AMP1 and to the connection line in the first longitudinal trace; one source / drain terminal of the local amplification transistor AMP1 is coupled to the gate of the first photocurrent transistor for outputting the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; a bias current generation circuit composed of a transistor LMP is further included for providing the bias current when the amplification transistor AMP1 operates.

[0087] It should be noted that, in another illustrated example, the current-voltage conversion unit can also be set as Figure 4 the circuit shown in (c). The above circuits can all implement the function of logarithmically transforming the photocurrent generated by the photosensitive unit to generate a voltage, and specific limitations are not made here.

[0088] It should be noted that, in the above embodiments, the source / drain terminal of the photocurrent transistor LOG or LOG1 is coupled to the power supply VDD through a capacitor C4 and a current mirror mirror transistor (see the appendix Figure 3 ), and the function of the current mirror mirror transistor is to obtain the total current value and copy it to other branches in a certain proportion for regulation.

[0089] See the appendix Figure 5 , in another illustrated example of the present invention, each array unit of the 2D pixel array includes 4 photosensitive units and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 2 transmission transistors TRG1 and TRG2 connected thereto. The pixel readout unit is provided corresponding to 4 photosensitive units and includes a reset transistor RST, an amplification transistor AMP, and a strobe transistor SEL.

[0090] Adopting this design can further reduce the area of each array unit, and each array unit includes different photosensitive units, and each photosensitive unit is configured with different types of photodiodes, making it more flexible and accurate in applicable scenarios.

[0091] See the appendix Figure 6 , in another illustrated example of the present invention, a reset control circuit is further configured in each change detection circuit. The reset control circuit is used to reset the change detection circuit based on a reset control signal. The reset control signal can be dedicated to each change detection circuit or shared by some or all of the change detection circuits.

[0092] See the appendix Figure 7, in another exemplary embodiment of the present invention, each array unit of the 2D pixel array further includes a photosensitive unit (or photodiode pixel) that is only connected to the row-parallel change detection circuit or only connected to the row-parallel ADC circuit, making the layout or function of the entire array more flexible and adaptable.

[0093] Alternatively, in another exemplary embodiment of the present invention, the 2D pixel array may also be provided with array units that are directly or through a switch control circuit only connected to the change detection circuit, and / or array units that are directly or through a switch control circuit only connected to the ADC conversion circuit, making the layout or function of the entire array more flexible and adaptable.

[0094] See attached Figure 8 , in another exemplary embodiment of the present invention, the photodiodes in the 2D pixel array can use different types of photodiodes. For example, some photodiodes are designed to receive infrared light, and some photodiodes are designed to receive visible light including RGB, including different types of photodiodes that respectively receive light in different bands such as red, green, and blue light. Each type of photodiode only receives visible light in a specific band. For example, some pixels can only receive red light, some pixels can only receive green light, etc., and they are arranged in an RGB alternating pattern. The photodiodes can also be designed to have different sizes of photosensitive areas, making the layout or function of the entire array more flexible.

[0095] In another exemplary embodiment of the present invention, the solid-state imaging sensor further includes a plurality of counters, and each counter is shared by at least one change detection circuit and at least one ADC conversion circuit. Compared with the prior art where each ADC conversion circuit and change detection circuit are configured with their own counters, the solution of the present invention can further save chip volume and reduce costs.

[0096] See attached Figure 9 , in one placement method, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit) and the row-parallel ADC circuit are placed on both sides of the 2D pixel array, and a plurality of counters are placed around the 2D pixel array.

[0097] See attached Figure 10 , in another placement method, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit), the row-parallel ADC circuit, and a plurality of counters are placed on the same side of the 2D pixel array.

[0098] See attached Figure 11 , in another placement method, the row-parallel change detection circuit (i.e., the row-parallel DVS circuit) and the row-parallel ADC circuit are placed on the same side of the 2D pixel array, and a plurality of counters are placed on the other side.

[0099] In another arrangement, the counter can also be placed in the parallel change detection circuit and multiplexed for the change detection circuit and the ADC conversion circuit by switching, or placed in the row-parallel ADC circuit and multiplexed for the ADC conversion circuit and the change detection circuit by switching, which is not limited herein.

[0100] An embodiment of the present invention also provides a control method for the solid-state imaging sensor shown above, including:

[0101] The row scanning control circuit outputs a row control signal to control the opening and closing of transistors in the photosensitive unit and / or the pixel readout unit, so that the array unit is respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array unit to operate in different modes:

[0102] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and the corresponding pixel readout units are connected to the ADC conversion circuit, the array unit where these photosensitive units are located operates in the CIS readout mode;

[0103] When at least a part or all of the photosensitive units in at least one column of the 2D pixel array and some transistors in the corresponding pixel readout units are connected to the change detection circuit, the array unit where these photosensitive units are located operates in the DVS readout mode.

[0104] See the appendix Figure 3 , based on the shown example, when the transfer transistor TRG2 connected to the photodiode in the photosensitive unit of the pixel array is turned on and the transfer transistor TRG1 is turned off, this photosensitive unit is connected to the corresponding change detection circuit (i.e., the DVS circuit), so that this photosensitive unit operates in the DVS readout mode, and multiple photosensitive units can share the current-voltage conversion unit in the DVS circuit.

[0105] Further, in the DVS readout mode, TRG1 can be controlled in a semi-open state and RST can be controlled in a fully open state to cope with the solar black spot problem, and at the same time, it can also solve the problem of excessive current caused by similar solar black spots.

[0106] Solar black spots mainly refer to the situation where, in the presence of strong light, the photocurrent generated by the photodiode is too large. At this time, a part of the switching transistor on the other side of the photodiode also needs to be turned on to conduct the excess current to other paths to prevent damage due to excessive current.

[0107] When the transfer transistor TRG2 connected to the photodiode in the photosensitive unit of the pixel array is turned off, the transfer transistor TRG1 is turned on, and SEL in the pixel readout unit is in a conducting state, this photosensitive unit is connected to the corresponding ADC conversion circuit, so that this photosensitive unit operates in the CIS readout mode, and multiple photosensitive units can share the ADC conversion circuit.

[0108] Furthermore, in the CIS readout mode, TRG2 can be controlled in a semi-open state to address the solar black spot problem.

[0109] Based on the above description, the solid-state imaging sensor of the present invention can support the following operating modes:

[0110] Single-mode operation: CIS mode and DVS mode;

[0111] Asynchronous hybrid mode: Alternate readout of CIS frames and DVS frames.

[0112] The sensor generally performs progressive scanning (or progressive N-line scanning) and progressive readout (or sequential readout of every N lines) until the entire array is read out as one frame.

[0113] Furthermore, it can also support:

[0114] Synchronous hybrid mode: This is the main usage mode of the sensor of the present invention. DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through row-by-row staggered readout or time-division multiplexing of different rows, and then achieve simultaneous readout of DVS frames and CIS frames.

[0115] Specifically, the row-by-row staggered readout method for DVS and CIS is as follows:

[0116] Read the first row of CIS, and then read the first row of DVS;

[0117] Read the second row of CIS, and then read the second row of DVS;

[0118] ……

[0119] Read the last row of CIS, and then read the last row of DVS.

[0120] Alternatively, every 3 pixel rows are combined for DVS readout to increase the photosensitive area and match the size of the reflected light spot. The readout method is as follows:

[0121] Read the first row of CIS, the second row of CIS, and the third row of CIS;

[0122] Read the combined DVS of rows 1 - 3;

[0123] Read the fourth row of CIS, the fifth row of CIS, and the sixth row of CIS;

[0124] Read the combined DVS of rows 4 - 6;

[0125] ……

[0126] In this example, the DVS readout by merging 3 rows of pixels is just an example. The specific number of rows to be merged for DVS readout can be determined according to needs and is not limited here.

[0127] For DVS and CIS, through time-division multiplexing readout of different rows, it can be that one or several rows first read in DVS mode and then in CIS mode. In the CIS readout mode, the pixels do not need to output signals to the ADC during the exposure process, so the column bus does not need to be occupied. At this time, DVS or CIS readout of other rows can be performed, thereby further realizing the reasonable utilization of the readout time by taking advantage of the repeated use of time, and then improving the readout frame rate of the sensor chip.

[0128] Specifically, the time-division multiplexing readout method for DVS and CIS is as follows:

[0129] Read the first row in DVS mode, then read the first row in CIS mode, and simultaneously read the second row in DVS mode during the exposure process;

[0130] Then read the second row in CIS mode, and simultaneously read the third row in DVS mode during the exposure process;

[0131] ……

[0132] Finally, read the last row in DVS mode, and then read the last row in CIS mode.

[0133] Or, merge the pixels of the 1st - 3rd rows for DVS readout, then read the first row, the second row, and the third row in CIS mode in sequence, and merge the pixels of the 4th - 6th rows for DVS readout during the exposure process of the third row;

[0134] Then read the fourth row, the fifth row, and the sixth row in CIS mode in sequence, and merge the pixels of the 7th - 9th rows for DVS readout during the exposure process of the sixth row;

[0135] ……

[0136] Finally, read the last few rows in DVS mode, and then read them row by row in CIS mode.

[0137] In the above examples, the exposure process is included in the readout process.

[0138] In this example, the merging of the pixels of the 1st - 3rd rows for DVS readout is just an example. The specific number of rows to be merged for DVS readout can be determined according to needs and is not limited here.

[0139] In another embodiment of the present invention, some rows in the sensor can also be selected as the effective readout area, and all the pixels in the effective readout area are read as one frame. For example, select odd rows such as 1, 3, 5, 7 as the first effective readout area, and even rows such as 2, 4, 6, 8 as the second effective readout area.

[0140] At this time, the sensor can also perform staggered row-by-row reading based on different effective readout regions. For example:

[0141] The first row of CIS is read out;

[0142] The second row of DVS is read out;

[0143] The third row of CIS is read out;

[0144] The fourth row of DVS is read out;

[0145] ……

[0146] Although this readout method will result in the loss of information in some rows and reduce the resolution, it can improve the frame rate and can be adopted according to actual needs.

[0147] The embodiment of the present invention also provides a solid imaging system, including:

[0148] The solid imaging sensor as described in the foregoing embodiment;

[0149] An active light source, which is used to provide a light source for the DVS readout mode of the solid imaging sensor;

[0150] And a processor, which is integrated on the solid imaging sensor or independently configured and is configured with a triangulation distance calculation unit;

[0151] Among them, the solid imaging sensor is used to collect the light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event based on the brightness change of the light reflected by the object to be measured in the DVS readout mode. The processor is used to calculate the distance of the object to be measured by triangulation based on the brightness change event, and then obtain a 3D imaging signal, so as to realize 2D and 3D fusion imaging.

[0152] Based on the above system, the present invention realizes 2D imaging and DVS triangulation ranging simultaneously without significantly increasing the chip area, and generates matching 2D / 3D information. At the same time, since the RGB information obtained by 2D imaging and the distance information obtained by DVS triangulation ranging come from the same optical window, the matching of RGB and D (distance) is automatically realized, which also provides high-quality information for subsequent signal processing.

[0153] The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A solid-state imaging sensor, characterized in that, Comprising: A 2D pixel array, each array unit of which includes a photosensitive unit and a pixel readout unit. Each photosensitive unit includes 1 photodiode and 2 transmission transistors connected thereto. The pixel readout unit is provided corresponding to at least one photosensitive unit and includes several transistors connected to the transmission transistors; A row-parallel change detection circuit, which includes multiple change detection circuits. Each change detection circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used for performing light luminance change detection based on the light response signals of at least one corresponding photosensitive unit; A row-parallel ADC circuit, which includes multiple ADC conversion circuits. Each ADC conversion circuit is configured corresponding to at least a part or all of the photosensitive units in at least one column of the 2D pixel array, and is used for performing analog-to-digital conversion on the light response signals of at least one corresponding photosensitive unit; A row scan control circuit, which is used for outputting row control signals to each photosensitive unit and pixel readout unit in the 2D pixel array; Multiple groups of first longitudinal traces, each group of first longitudinal traces including at least one connection line, and being used for connecting at least a part or all of the photosensitive units in at least one column of the 2D pixel array to the corresponding change detection circuit; Multiple groups of second longitudinal traces, each group of second longitudinal traces including several connection lines, wherein a part of the connection lines are used for connecting global signals, and another part of the connection lines are used for connecting at least a part or all of the photosensitive units and pixel readout units in at least one column of the 2D pixel array to the corresponding ADC conversion circuit; Wherein, the row scan control circuit controls the opening and closing of the transistors in the photosensitive unit and / or pixel readout unit by outputting row control signals, and further controls the connection relationship between each array unit and the change detection circuit and the ADC conversion circuit, so as to switch the working modes of each array unit.

2. The solid-state imaging sensor according to claim 1, wherein, One end of the photodiode in each photosensitive unit is connected to the power supply, and the other end is connected to each one of the source / drain ends of the two transmission transistors. The other source / drain end of the first transmission transistor is connected to the connection line in the first longitudinal trace, and the other source / drain end of the second transmission transistor is connected to the pixel readout unit; Each pixel readout unit respectively includes a reset transistor, an amplification transistor and a strobe transistor. Wherein, one source / drain end of the reset transistor is connected to the second connection line in the second longitudinal trace, and the other source / drain end is connected to the source / drain end of the second transmission transistor and the gate of the amplification transistor. One source / drain end of the amplification transistor is connected to the first connection line in the second longitudinal trace, and the other source / drain end is connected to one source / drain end of the strobe transistor. The other source / drain end of the strobe transistor is connected to the third connection line in the second longitudinal trace; The first connection line and the second connection line in the second longitudinal trace are connected to global signals, the third connection line is connected to the ADC conversion circuit, and the gates of the first transmission transistor, the second transmission transistor, the reset transistor and the strobe transistor are respectively connected to the row control signal output ends of the row scan control circuit.

3. The solid-state imaging sensor according to claim 2, wherein, The change detection circuit includes a current-voltage conversion unit, a change integration and reset unit, and a quantization unit. The current-voltage conversion unit is connected to the connection line in the first longitudinal trace.

4. The solid-state imaging sensor according to claim 3, wherein, The current-voltage conversion unit is configured to perform a logarithmic conversion on the photocurrent generated by the photosensitive unit in the corresponding array unit to generate a voltage.

5. The solid-state imaging sensor according to claim 4, wherein, The current-voltage conversion unit includes: At least one photocurrent transistor and at least one local amplification transistor. One source / drain terminal of the photocurrent transistor is directly or coupled to the power supply through a current mirror mirroring transistor, and the other source / drain terminal is connected to the gate of the local amplification transistor and the connection line in the first longitudinal trace. One source / drain terminal of the local amplification transistor is connected to the gate of the first photocurrent transistor and is configured to output the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; And a bias current generation circuit for providing a bias current when the amplification transistor operates.

6. The solid-state imaging sensor according to claim 4, wherein, The current-voltage conversion unit includes: At least two photocurrent transistors and at least two local amplification transistors. One source / drain terminal of the first photocurrent transistor is directly or coupled to the power supply through a current mirror mirroring transistor, and the other source / drain terminal is connected to one source / drain terminal of the second photocurrent transistor and the gate of the second local amplification transistor. The other source / drain terminal of the second photocurrent transistor is connected to the gate of the first local amplification transistor and is connected to the connection line in the first longitudinal trace. One source / drain terminal of the second local amplification transistor is coupled to the gate of the first photocurrent transistor and is configured to output the voltage corresponding to the photocurrent, and the other source / drain terminal is connected to the gate of the second photocurrent transistor and one source / drain terminal of the first local amplification transistor, and the other source / drain terminal of the first local amplification transistor is grounded; Alternatively, at least two photocurrent transistors and at least one local amplification transistor. One source / drain terminal of the first photocurrent transistor is directly or coupled to the power supply through a current mirror mirroring transistor, and the other source / drain terminal is connected to one source / drain terminal and the gate of the second photocurrent transistor. The other source / drain terminal of the second photocurrent transistor is connected to the gate of the local amplification transistor and is connected to the connection line in the first longitudinal trace. One source / drain terminal of the local amplification transistor is coupled to the gate of the first photocurrent transistor and is configured to output the voltage corresponding to the photocurrent, and the other source / drain terminal is grounded; And a bias current generation circuit for providing a bias current when the local amplification transistor operates.

7. The solid-state imaging sensor according to claim 1, wherein The row-parallel change detection circuit and the row-parallel ADC circuit are respectively located on both sides of the 2D pixel array.

8. The solid-state imaging sensor according to claim 3, wherein, Each change detection circuit is further configured with a reset control circuit. The reset control circuit is configured to reset the change detection circuit based on a reset control signal, and the reset control signal is dedicated to each change detection circuit or shared by some or all of the change detection circuits.

9. The solid-state imaging sensor according to any one of claims 1 to 8, characterized in that, The 2D pixel array further includes array units that are directly or connected to the change detection circuit only through a switch control circuit, and / or array units that are directly or connected to the ADC conversion circuit only through a switch control circuit.

10. The solid-state imaging sensor according to claim 1, wherein, The photodiodes in the 2D pixel array include different types of photodiodes.

11. The solid-state imaging sensor according to claim 10, characterized in that, In the 2D pixel array, some photodiodes are designed to receive infrared light, and some photodiodes are designed to receive visible light including RGB.

12. The solid-state imaging sensor according to claim 10, wherein The photodiodes in the 2D pixel array are designed to have photosensitive areas of different sizes.

13. The solid-state imaging sensor according to any one of claims 1-8 or 10-12, characterized in that, It further includes: A plurality of counters, each counter being shared by at least one of the change detection circuits and at least one ADC conversion circuit.

14. The solid-state imaging sensor according to claim 13, wherein, The counters are arranged around the 2D pixel array, or placed in the row-parallel change detection circuit and multiplexed by switching for time-sharing use by the change detection circuit and the ADC conversion circuit, or placed in the row-parallel ADC circuit and multiplexed by switching for time-sharing use by the ADC conversion circuit and the change detection circuit.

15. A control method for a solid-state imaging sensor according to any one of claims 1-14, characterized in that, It includes: The row scan control circuit outputs a row control signal to control the opening and closing of transistors in the photosensitive unit and / or the pixel readout unit, so that the array unit is respectively connected to the change detection circuit or the ADC conversion circuit, and further enables the array unit to operate in different modes: When at least a part or all of the photosensitive units in at least one column in the 2D pixel array and the corresponding pixel readout units are connected to the ADC conversion circuit, the array unit where the part of the photosensitive units is located operates in the CIS readout mode; When at least a part or all of the photosensitive units in at least one column in the 2D pixel array and some transistors in the corresponding pixel readout units are connected to the change detection circuit, the array unit where the part of the photosensitive units is located operates in the DVS readout mode.

16. The control method of the solid-state imaging sensor according to claim 15, characterized in that, Based on the different operating modes of the array unit, the solid-state imaging sensor can be switched to operate in one of the following several modes: CIS readout mode; DVS readout mode; CIS frame readout and DVS frame readout alternate; Or, DVS and CIS achieve frame synchronization acquisition of laser ranging and background light imaging through row-by-row staggered reading or different-row time-sharing multiplexing.

17. The control method of the solid-state imaging sensor according to claim 15 or 16, characterized in that: In the DVS readout mode, the transfer transistor connecting the photodiode to the pixel readout unit in the photosensitive unit is controlled to be turned on in a preset interval, and the reset transistors in the pixel readout unit are controlled to be fully turned on; In the CIS readout mode, the transfer transistor connecting the photodiode to the change detection circuit in the photosensitive unit is controlled to be turned on in a preset interval.

18. A solid imaging system, characterized in that, It includes: The solid-state imaging sensor according to any one of claims 1-14; An active light source, which is used to provide a light source for the DVS readout mode of the solid-state imaging sensor; And a processor, the processor is integrated on the solid-state imaging sensor or independently configured, and is configured with a triangulation distance calculation unit; Wherein, the solid-state imaging sensor is used to collect the light reflected by the object to be measured, obtain a 2D detection signal based on the CIS readout mode, and output a brightness change event according to the brightness change of the light reflected by the object to be measured based on the DVS readout mode, and the processor is used to calculate the distance of the object to be measured by triangulation based on the brightness change event, and further obtain a 3D imaging signal, so as to realize 2D and 3D fusion imaging.

Images