Method of operating image sensor having pixel array and image sensor

Abstract

A method of operating an image sensor having a pixel array and an image sensor are provided. The method may include: outputting a row control signal to a pixel row in a pixel array at a first time; sampling a first output signal from a first pixel in the row of pixels at a second time; and sampling a second output signal from a second pixel in the pixel row at a third time after the second time. The row control signal may reach a first pixel in the row of pixels at a first row propagation delay after a first time. The row control signal may reach a second pixel in the row of pixels at a second row propagation delay after the first time. A difference between the second time and the third time may be equal to a difference between the first row propagation delay and the second row propagation delay.

Description

Technical Field

[0001] The present invention generally relates to imaging systems, and more particularly, to image sensors having large pixel arrays. Background Art

[0002] An image sensor may include a large pixel array having thousands of rows and thousands of columns. The image sensor may include row control circuitry for providing row control signals to different pixel rows in the array via corresponding row control lines.

[0003] Designing an image sensor with a large pixel array can be challenging. When the pixel array is very large, the row control lines can exhibit large RC (resistance-capacitance) time constants across the array, which can introduce significant delays during readout or integration. These time delays can limit the performance of the image sensor. The embodiments herein arise in this context. Summary of the Invention

[0004] According to a first aspect, there is provided a method of operating an image sensor having a pixel array, the method comprising: outputting, using a row driver circuit, a row control signal to a pixel row in the pixel array at a first time; sampling, using a first sampling circuit, a first output signal from a first pixel in the pixel row at a second time; and sampling, using a second sampling circuit, a second output signal from a second pixel in the pixel at a third time after the second time.

[0005] According to a second aspect, there is provided an image sensor, the image sensor comprising: a pixel array; a plurality of row driver circuits configured to output row control signals to corresponding pixel rows in the array; a reference pixel row; and an asynchronous sampling circuit having a plurality of sampling circuits, wherein each of the plurality of sampling circuits includes a first input coupled to a pixel column in the array and a second input coupled to the reference pixel row.

[0006] According to a third aspect, there is provided an image sensor, the image sensor comprising: a pixel array; a first row driver circuit configured to output a row control signal to a pixel row in the array; a timing pixel row disposed along an edge of the pixel array; a second row driver circuit configured to output a row control signal to the timing pixel row; and a delay circuit coupled between the first row driver circuit and the second row driver circuit. Brief Description of the Drawings

[0007] Figure 1 is a schematic diagram of an exemplary system having an image sensor according to some embodiments.

[0008] Figure 2 is a schematic diagram of an exemplary pixel array and associated row and column control circuits according to some embodiments.

[0009] Figure 3 is a circuit diagram of an exemplary image pixel according to some embodiments.

[0010] Figure 4 is a timing diagram showing that row timing can be reduced via pipelining and asynchronous sampling according to some embodiments.

[0011] Figure 5 is a timing diagram showing the operation of an image sensor array according to some embodiments.

[0012] Figure 6 is configured to perform according to some embodiments Figure 5 a schematic diagram of an image sensor circuit for the operations shown.

[0013] Figure 7 is a flowchart of exemplary steps for operating according to some embodiments Figures 1 to 6 an image sensor circuit of the type shown. Detailed Description

[0014] Embodiments of the technology of the present invention relate to image sensors. Those skilled in the art should understand that the exemplary embodiments of the present invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order to avoid unnecessarily obscuring the embodiments of the present invention.

[0015] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include an image sensor that collects incoming light to capture an image. The image sensor may include a pixel array, sometimes referred to as an image sensor pixel or an imaging pixel. The image sensor pixels include photosensitive elements, such as photodiodes, that convert incoming light into an image signal. The image sensor may include hundreds, thousands, or millions of imaging pixels. The image sensor may include control circuitry (such as driver circuitry for selectively accessing pixels) and readout circuitry for reading out an image signal corresponding to the charge generated by the photosensitive elements.

[0016] Figure 1 is a diagram of an exemplary imaging and response system that includes an imaging system that uses an image sensor to capture an image. Figure 1The system 100 can be an electronic device, such as a camera, a cellular phone, a video camera, or other electronic devices that capture digital image data, can be a vehicle safety system (e.g., an active braking system or other vehicle safety systems), or can be a surveillance system. As Figure 1 shown, the system 100 can include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). The imaging system 10 can include a camera, such as camera module 12. The camera module 12 can include one or more image sensors 14, such as in an image sensor array integrated circuit, and one or more lenses. During an image capture operation, each lens can focus light onto the associated image sensor 14. The image sensor 14 can include photosensitive elements that convert incoming light into digital data, such as image sensor pixels. The image sensor 14 can include hundreds of pixels, thousands of pixels, millions of pixels, or any desired number of pixels.

[0017] Each image sensor in the camera module 12 can be the same, or different types of image sensors can be present in a given image sensor array integrated circuit. In some examples, the image sensor 14 can also include bias circuits, sample and hold circuits, correlated double sampling (CDS) circuits, amplifier circuits, analog-to-digital converter circuits, data output circuits, memory, buffer circuits, and / or addressing circuits. Static and video image data from the image sensor 14 can be provided to the image processing and data formatting circuit 16 via path 28. The image processing and data formatting circuit 16 can be used to perform image processing functions, such as data formatting, adjusting white balance and exposure, implementing video image stabilization, or face detection. The image processing and data formatting circuit 16 can additionally or alternatively be used to compress the original camera image file (e.g., compressed into a Joint Photographic Experts Group or JPEG format) when needed.

[0018] In one exemplary arrangement, such as a system-on-chip (SoC) arrangement, the sensor 14 and the image processing and data formatting circuit 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, the sensor 14 and the image processing circuit 16 can be formed on separate semiconductor substrates. For example, the sensor 14 and the image processing circuit 16 can be formed on separate substrates that are vertically stacked relative to each other.

[0019] Imaging system 10 may transfer the acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include input-output device 22 and storage and processing circuitry 24. Host subsystem 20 may include processing software for detecting objects in the image, detecting the movement of the objects between image frames, determining the distance to the objects in the image, or filtering or otherwise processing the images provided by imaging system 10. For example, the image processing and data formatting circuitry 16 of imaging system 10 may transfer the acquired image data to the storage and processing circuitry 24 of host subsystem 20.

[0020] If desired, system 100 may provide a number of advanced functions for the user. For example, in a computer or mobile phone, the ability to run user applications may be provided for the user. For these functions, the input-output device 22 of host subsystem 20 may include a keyboard, input-output ports, buttons, and a display, as well as storage and processing circuitry 24. The storage and processing circuitry 24 of host subsystem 20 may include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid state drive, etc.). The storage and processing circuitry 24 may additionally or alternatively include a microprocessor, a microcontroller, a digital signal processor, and / or an application specific integrated circuit.

[0021] Figure 2 An example of the arrangement of Figure 1 image sensor 14 is shown. As Figure 2 shown, image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44, sometimes referred to as control and processing logic, may be Figure 1 a part of the image processing and data formatting circuitry 16 in

[0022] Figure 3 a circuit diagram of an exemplary image sensor pixel 34. As Figure 3As shown, the image sensor pixel 34 may include a photosensitive element such as a photodiode PD and a charge transfer transistor such as charge transfer transistor T1, which has a first source-drain terminal coupled to the photodiode PD, a second source-drain terminal coupled to a floating diffusion node FD, and a gate terminal configured to receive a charge transfer control signal TX. The p-type (anode) terminal of the photodiode PD is coupled to a ground power supply line, sometimes also referred to as a ground wire or ground. The charge transfer transistor T1 is sometimes referred to as a charge transfer gate. The floating diffusion node FD is sometimes referred to as a floating diffusion region.

[0023] The pixel 34 may further include a reset transistor T2, which has a drain terminal coupled to a positive power supply line provided with VDD thereon, a source terminal coupled to the floating diffusion node FD, and a gate terminal configured to receive a reset control signal RST. When referring to the current conducting terminals of a metal oxide semiconductor (MOS) transistor, the terms "source" terminal and "drain" terminal may be used interchangeably and are sometimes referred to as "source-drain" terminals. For example, the drain terminal of the reset transistor T2 may be referred to as its first source-drain terminal, and the source terminal of the reset transistor T2 may be referred to as its second source-drain terminal, or vice versa.

[0024] The image pixel 34 may further include a source follower transistor T3, which has a drain terminal coupled to the positive power supply line, a gate terminal coupled to the floating diffusion node FD, and a source terminal. The source follower transistor T3 is sometimes simply referred to as a "source follower". The pixel 34 may also include a row selection transistor T4, which has a drain terminal coupled to the source terminal of the source follower T3, a gate terminal configured to receive a row selection control signal RS, and a source terminal coupled to a corresponding column line 38. The column line 38 may be coupled to more than 10 pixels in a pixel column, 10 to 100 pixels in a column, hundreds of pixels in a column, or thousands of pixels in a column. The column line 38 is sometimes referred to as a pixel output line or a pixel output column line.

[0025] In Figure 3 the example, the transistors T1-T4 may all be n-type metal oxide semiconductor (NMOS) transistors. In other embodiments, at least some of the transistors T1-T4 may alternatively be implemented as p-type metal oxide semiconductor (PMOS) transistors. In other embodiments, the imaging pixel 34 may optionally include four or more n-channel and / or p-channel transistors. Where the pixel 34 includes four transistors T1-T4 Figure 3The examples are merely illustrative. In other embodiments, the imaging pixel 34 may include a plurality of photodiodes coupled to a shared floating diffusion node, fewer than four transistors, more than four transistors, five or more transistors, six or more transistors, one or more storage capacitors, one or more storage nodes, one or more mode switching transistors, a multi-conversion gain component, a bloom control component, and / or other pixel structures. The imaging pixel 34 may be a rolling shutter type pixel or a global shutter type pixel, such as a pixel including an additional storage node coupled between the photodiode and the floating diffusion region.

[0026] Return reference Figure 2 , the row control circuit 40 may receive a row address from the control and processing circuit 44 and may provide corresponding row control signals to the image pixels 34 through one or more control paths 36. The row control signals may include a pixel reset control signal, a charge transfer control signal, an overflow control signal, a row selection control signal, a dual conversion gain control signal, and / or any other desired pixel control signals.

[0027] The column control and readout circuit 42 may be coupled to one or more columns of the pixel array 32 via one or more wires (such as column lines 38). A given column line 38 may be coupled to the columns of the image pixels 34 in the image pixel array 32 and may be used to read out the image signal from the image pixels 34 and to provide a bias signal (e.g., a bias current or a bias voltage) to the image pixels 34. In some examples, each pixel column may be coupled to a corresponding column line 38. The column lines 38 are sometimes referred to as pixel output column lines.

[0028] For an image pixel readout operation, the row driver circuit 40 may be used to select a row of pixels in the image pixel array 32, and the image data associated with the image pixels 34 in that pixel row may be read out by the column readout circuit 42 on the column lines 38. The column readout circuit 42 may include column circuits, such as a column amplifier for amplifying the signal read out from the array 32, a sample and hold (S / H) circuit for sampling and storing the signal read out from the array 32, an analog-to-digital converter (ADC) circuit for converting the read out analog signal into a corresponding digital signal, and / or a column memory for storing the read out signal and any other desired data. The column control and readout circuit 42 may output the digital pixel readout value to the control and processing logic 44 via the line 26.

[0029] The pixel array 32 can have any number of rows and columns. Generally speaking, the size of the image pixel array 32 and the number of rows and columns in the array 32 will depend on the specific implementation of the image sensor 14. Although "rows" and "columns" are generally described herein as horizontal and vertical respectively, the terms row and column can be used interchangeably and can refer to any grid-like structure. Features described herein as "rows" can be arranged vertically, and features described herein as "columns" can be arranged horizontally. In other embodiments, the pixel array 32 can be grouped into blocks or sub-regions of equal or different sizes. For example, the pixel array can be divided into four regions of equal size and area. Generally speaking, the pixel array can be divided into more than four sub-regions, four to ten sub-regions, 10 to 20 sub-regions, 20 to 50 sub-regions, or 50 to 100 sub-regions, which are independently controlled, addressed, and read out.

[0030] The pixel array 32 can include a color filter array having a plurality of color filter elements, and the color filter array allows a single image sensor to sample light of different colors. For example, image sensor pixels (such as the image pixels in the array 32) can include a color filter array, and the color filter array allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. The red, green, and blue image sensor pixels can be arranged, for example, in a Bayer mosaic pattern. The Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are opposite each other along the diagonal, and adjacent to the red image pixel that is opposite the blue image pixel along the diagonal. Another example is that broadband image pixels having broadband color filter elements (such as, transparent color filter elements, yellow color filter elements, etc.) can be used to replace the green pixels in the Bayer pattern. These examples are merely illustrative, and generally speaking, color filter elements of any desired color and pattern can be formed above any desired number of image pixels 34.

[0031] The image sensor 14 can sometimes include a very large pixel array. For example, a large pixel array can include thousands of columns and / or thousands of rows. As described above in connection with Figure 2As described, the row control circuit 40 can be used to provide row control signals to corresponding rows of pixels in the pixel array 32 via corresponding row control lines 36. The pixel array can be read out row by row. In a scenario where each row of pixels includes thousands or tens of thousands of pixels (columns), the row control line 36 can exhibit a large RC (resistance-capacitance) time constant, which results in a gradually increasing propagation delay across the width (horizontal dimension) of the pixel array. Similarly, the output column line 38 can also exhibit a long stabilization time across the length (vertical dimension) of the pixel array. The pixel readout timing can be determined by ensuring that all columns are stable within the desired limits defined by minimizing artifacts as a result of residual errors. For example, in the worst case, a 10% column stabilization error may result in a residual error of -20 dB relative to the signal of interest. A desired goal may be to achieve a column stabilization error of less than 1% (as an example). For large pixel arrays, the propagation delay across the row line 36 can be an important factor in determining the overall frame rate of the image sensor. Such limitations are complex for more complex pixels with two or more readouts on a row-by-row basis.

[0032] Figure 4 is a timing diagram illustrating that row timing may be reduced according to some embodiments. Curve 50 may represent a pixel column output waveform in column i, while curve 52 may represent a pixel column output waveform in column j. Column i may represent a column closer to a peripheral row driver for driving pixels in that column, while column j may represent another column farther from a peripheral row driver for driving pixels in that column. Signal level Vx may represent a minimum signal level at which the column output signal needs to be stable to meet design criteria. Conventional readout methods employing synchronous sampling operations may exhibit a reduced frame rate. In Figure 2 In the example of , the synchronous sampling operation of columns i and j can occur at the earliest at time t_sett2, because the waveform 52 in column j will not settle to level Vx before time t_sett2. This need to wait for the signal from another column to settle will limit the ability to increase the overall frame rate in this sampling scheme.

[0033] According to an embodiment, image sensor 14 may be provided with means for asynchronously sampling different column lines. The asynchronous column path sampling time may be related to the propagation delay across the row dimension so that the row propagation delay and the asynchronous sampling time will exhibit the same timing distribution. Image sensor 14 may also include means for outputting the asynchronous column samples to a synchronous digital data path. Figure 4 In the example of , waveform 50 may be sampled at a first (earlier) time t1, while waveform 52 may be asynchronously sampled at a second time t2. Sampling waveform 50 at the earlier time t1 may help reduce the row time by Δt and thus may increase the frame rate. Such asynchronous sampling of column signals may be achieved by pipelining different row readout operations.

[0034] Figure 5 is a timing diagram showing the operation of an image sensor array that exhibits improved row timing due to pipelining and asynchronous sampling. The "nearest column" may refer to the column physically closest to the row driver located at the peripheral edge of the image pixel array. The "farthest column" may refer to the column physically farthest from the peripheral row driver. As Figure 2 shown in the example of Figure 6 in an image sensor architecture that includes a peripheral row driver disposed only along one edge of the image pixel array, the nearest column will be the first (leftmost) column and the farthest column will be the last (rightmost) column. As

[0035] Figure 5 shown in the example of Figure 2 in an image sensor architecture that includes peripheral row drivers disposed along two opposite edges of the image pixel array, the nearest column will be either the leftmost or rightmost column, while the farthest column will be either of the middle (center) columns in the array. Figure 5 shows operations associated with reading out signals from one or more rows of image sensor pixels. The pixel row currently being read out is sometimes referred to and defined herein as the "active row". At time t0, a reset signal for resetting the floating diffusion nodes in each pixel along a given pixel row may be synchronously emitted. The terms "emit", "output", and "assert" may sometimes be used interchangeably herein to refer to a signal that is driven from a previous (old or idle) value to a new value for reading or otherwise actively accessing a given pixel row. Such reset signals are sometimes referred to as floating diffusion reset (FDR) row control signals. The floating diffusion reset row control signal may be output by a row driver within the row control circuit 40 (see

[0036] and may propagate to successive columns in the active row via an increasing row propagation delay time. As Figure 2 shown, the FDR signal may propagate to the nearest column after a row propagation delay Px, and may propagate to the farthest column after a row propagation delay Py. The difference in the row propagation delay time between the nearest column and the farthest column is equal to the propagation delay difference ΔP, where ΔP is equal to Py minus Px.

[0036] When the FDR signal reaches the nearest column at a propagation delay Px after time t0, the floating diffusion nodes are reset, and then the corresponding reset values may be read out from the pixels in the nearest column at time t2. The reset values are read out via the column lines 38 coupled to the nearest column. The read out reset values may stabilize to an acceptable level after a column path stabilization time (R), where "R" represents reset. The column path stabilization time (R) may be a function of the total number of pixels coupled to the column lines 38, the total capacitance of the column lines 38, and the length of the column lines 38 between the active row and the column control and readout circuit 42 (see Figure 2)。After the reset value of the nearest column has stabilized, the reset value of the nearest column can be sampled at time t2. Then, the sampled reset value of the nearest column can be converted from an analog voltage value to a corresponding digital code, as indicated by the "ADC conversion" step after time t2 in Figure 5 .

[0037] When the FDR signal arrives at the farthest column at a propagation delay Py after time t0, the floating diffusion node is reset, and then the corresponding reset value can be read out from the pixels in the farthest column at time t1. The reset value is read out via the column line 38 coupled to the farthest column. The read reset value can stabilize to an acceptable level after the column path stabilization time (R). The column path stabilization time (R) can be a function of the total number of pixels coupled to the column line 38, the total capacitance of the column line 38, and the length of the column line 38 between the active row and the column control and readout circuit 42 (see Figure 2 ). After the reset value of the farthest column has stabilized, the reset value of the farthest column can be sampled at time t3. Then, the sampled reset value of the farthest column can be converted from an analog voltage value to a corresponding digital code, as indicated by the "ADC conversion" step after time t3 in Figure 5 .

[0038] Here, the time delay between the nearest reset (R) sampling time and the farthest reset (R) sampling time can be equal to the propagation delay difference ΔP between the nearest column and the farthest column, as shown in Figure 5 . Generally speaking, the sampling times of different columns can occur asynchronously at different times depending on the increasing row propagation delay associated with each successive column along a given row. In other words, the column path sampling time is adjusted based on the propagation delay when the row signal propagates across a given row. This allows pipelining or overlapping of row operations (e.g., by allowing columns to be sampled at an earlier time than would be required based on a synchronous sampling scheme).

[0039] At time t2, the charge transfer (TX) signal for transferring the accumulated charge from the photodiode PD to the floating diffusion node FD in each pixel along the pixel row can be synchronously emitted. Such charge transfer signals are sometimes referred to as charge transfer row control signals. The charge transfer row control signals can be output by the row driver within the row control circuit 40 (see Figure 2 ) and can propagate to successive columns in the active row via an increasing row propagation delay time. As shown in Figure 5 , the TX signal can propagate to the nearest column after a row propagation delay Px', and can propagate to the farthest column after a row propagation delay Py'. The difference in the row propagation delay times between the nearest column and the farthest column can be equal to the TX propagation difference ΔP', which is equal to Py' minus Px'.

[0040] Here, the charge transfer signal can be synchronously emitted even before the reset value of the farthest column is fully stable. As Figure 5 shown, the propagation delay Px' of the nearest column and the end of the subsequent column path stabilization time (S) occur during the column path stabilization time (R) of the farthest column. In other words, due to the associated row propagation delay, the emission of the TX signal can be pipelined (overlapped) with the column path stabilization time of the farthest column.

[0041] When the TX signal arrives at the nearest column at a certain propagation delay Px' after time t2, the floating diffusion node receives the accumulated charge and then can read out the corresponding signal (S) value from the pixels in the nearest column. The signal value is read out via the column line 38 coupled to the nearest column. The read-out signal value can be stabilized to an acceptable level after the column path stabilization time (S), where "S" represents the image signal. The column path stabilization time (S) can be a function of the total number of pixels coupled to the column line 38, the total capacitance of the column line 38, and the length of the column line 38 between the active row and the column control and readout circuit 42 (see Figure 2 ). After the signal value of the nearest column has been stabilized, the signal value of the nearest column can be sampled at time t5. There can be a blank time period between the end of the column path stabilization time (S) and time t5, shown as Tblank in the example of Figure 5 . Then, the sampled signal value of the nearest column can be converted from an analog voltage value to a corresponding digital code, as indicated by the "ADC conversion" step after time t5 in Figure 5 .

[0042] When the TX signal arrives at the farthest column at a certain propagation delay Py' after time t2, the floating diffusion node receives the accumulated charge and then can read out the corresponding signal (S) value from the pixels in the farthest column at time t4. The signal value is read out via the column line 38 coupled to the farthest column. The read-out signal value can be stabilized to an acceptable level after the column path stabilization time (S). The column path stabilization time (S) can be a function of the total number of pixels coupled to the column line 38, the total capacitance of the column line 38, and the length of the column line 38 between the active row and the column control and readout circuit 42 (see Figure 2 ).

[0043] At time t5, before the signal value of the farthest column has been fully stabilized, the FDR signal for the next row of pixels in the nearest column can be synchronously emitted. In other words, due to the associated row propagation delay, the emission of the FDR signal can be pipelined (overlapped) with the column path stabilization time of the farthest column.

[0044] After the signal value of the farthest column has been stabilized, the signal value of the farthest column can be sampled at time t6. Then, the sampled signal value of the farthest column can be converted from an analog voltage value to a corresponding digital code, asFigure 5 as indicated by the "ADC conversion" step after time t6.

[0045] Here, the time delay between the sampling time of the nearest signal (S) and the sampling time of the farthest signal (S) can be equal to or approximately equal to the propagation delay difference ΔP between the nearest column and the farthest column. Generally speaking, the sampling times of different columns can occur asynchronously at different times depending on the increasing row propagation delay associated with each successive column along a given row. The operations for reading out the alternating reset values and signal values can continue in this way to support a correlated double sampling (CDS) readout scheme.

[0046] Performing pipelining and asynchronous sampling on different pixel columns as described above can be technically advantageous and beneficial for reducing or eliminating the duration of Tblank, which can optimize the frame rate, even for very large image sensor arrays. Such an increase in frame rate can be achieved without compromising performance. This technique thus compensates for the varying propagation delays in the row driver to increase the image sensor frame rate.

[0047] Figure 6 configured to perform Figure 5 a schematic diagram of an image sensor circuit for performing the operations shown. As Figure 6 shown, the image sensor 14 can include a pixel array 32 having a plurality of pixel rows, a first timing row 72-R configured to facilitate sampling of the reset (R) value, a second timing row 72-S configured to facilitate sampling of the signal (S) value, and a sampling block such as an asynchronous sampling circuit 80. The asynchronous sampling circuit 80 can include a plurality of sample and hold (sample) circuits 82. Each pixel row can receive row control signals from a corresponding row driver (RD) circuit 41. Figure 6 Each row driver circuit 41 in

[0048] In Figure 6 the example of, row driver circuits 41 disposed on opposite edges of the array 32 can be used to drive the pixel array 32. In such a configuration, the column closest to the row driver circuit 41 on the left edge of the array 32 is the leftmost column (as Figure 6as shown in the top plan view), and the column on the left edge of the array 32 that is farthest from the row driver circuit 41 is the left column in the middle column pair of the array 32. Similarly, the column on the right edge of the array 32 that is closest to the row driver circuit 41 is the rightmost column, and the column on the right edge of the array 32 that is farthest from the row driver circuit 41 is the right column in the middle column pair of the array 32.

[0049] The timing row 72-R can be set along the edge of the pixel array 32 that is physically closest to the asynchronous sampling circuit 80. In Figure 6 this case, this edge is the bottom edge. The timing row 72-R can be used for sampling of reset values. The timing row 72-R can have the same structure as any pixel row in the pixel array 32, such that the propagation delay in the row direction matches the propagation delay of the active row 70 that is currently being read out. Thus, the timing row 72-R is sometimes referred to herein as a reference pixel row or a reference pixel line. A row driver circuit 41' provided on the opposite edge of the pixel array 32 can also be used to drive the timing row 72-R. The row control signal that feeds the timing row 72-R output from the row driver circuit 41 can be delayed relative to the row control signal that feeds the active row 70 output from the row driver circuit 41 by an amount of delay provided by the first delay circuit 74, which is provided in Figure 6 the orientation and is provided somewhere along the left edge of the pixel array 32. The amount of delay provided by the first delay circuit 74 can be equal to the column path stabilization time that stabilizes the signal on the column path 38.

[0050] The timing row 72-S can be set along the edge of the pixel array 32 that is physically closest to the asynchronous sampling circuit 80. The timing row 72-S can be used for sampling of signal values. The timing row 72-S can be formed adjacent to the timing row 72-R. The timing row 72-S can have the same structure as any pixel row in the pixel array 32, such that the propagation delay in the row direction matches the propagation delay of the active row 70 that is currently being read out. The timing rows 72-S and 72-R can thus also have the same structure. Thus, the timing row 72-S is sometimes also referred to herein as a reference pixel row or a reference pixel line. A row driver circuit 41' provided on the opposite edge of the pixel array 32 can also be used to drive the timing row 72-S. The row control signal that feeds the timing row 72-S output from the row driver circuit 41' can be delayed relative to the row control signal that feeds the active row 70 output from the row driver circuit 41 by an amount of delay provided by the second delay circuit 74, which is provided in Figure 6 the orientation and is provided somewhere along the right edge of the pixel array 32. The amount of delay provided by the second delay circuit 74 can be equal to the column path stabilization time that stabilizes the signal on the column path 38.

[0051] For a given pixel read out from an active row 70 in column j, the pixel value PIXcolj will be read out via the corresponding column line 38. The pixel value PIXcolj may be sampled at the corresponding sample and hold (S / H) circuit 82 within the asynchronous sampling circuit 80. The sample and hold circuit 82 is sometimes referred to as a sampling circuit. The asynchronous sampling circuit 80 may include as many sampling circuits 82 as the total number of columns within the pixel array 32, or may include fewer sampling circuits 82 than the total number of columns within the pixel array 32 (i.e., quantized sampling, described below).

[0052] The sample and hold circuit 82 may be triggered using a sampling signal RDcolj output from a logic gate such as a logic "OR" gate 84. Thus, the sampling signal RDcolj is sometimes referred to as a sampling circuit trigger signal. The logic "OR" gate 84 may have a first input coupled to pixels in the timing row 72-R in column j and may have a second input coupled to pixels in the timing row 72-S in column j. Configured in this manner, the sampling of any given column j in the pixel array may be triggered asynchronously based on the column path settling time provided by the delay circuit 74 and the row propagation delay of the row control signals output by the row driver circuit 41' to propagate one of the timing rows down to column j. This sampling scheme is exemplary. If desired, the asynchronous sampling may optionally be retimed by a retiming clock.

[0053] In Figure 6 the example, each pixel column in the array 32 may be routed to a corresponding sampling circuit 82 to uniquely sample the output value of that column. This is illustrative. In other embodiments, the sampling signal RDcol from one column may be used to asynchronously sample signals from two or more columns (e.g., sample a column group). This technique is sometimes referred to as quantized sampling. For example, in the case of two-column quantized sampling, the sampling signal RDcol2 from column 2 may be used to trigger the sampling of the pixel values PIXcol1 and PIXcol2 output from columns 1 and 2, while the RDcol4 from column 4 may be used to trigger the sampling of the pixel values PIXcol3 and PIXLcol4 output from columns 3 and 4, and so on. As another example, in the case of three-column quantized sampling, the sampling signal RDcol3 from column 3 may be used to trigger the sampling of the pixel values PIXcol1, PIXcol2, PIXcol3 output from columns 1 to 3, while the RDcol6 from column 6 may be used to trigger the sampling of the pixel values PIXcol4, PIXcol5, and PIXcol6 output from columns 4 to 6, and so on. In other words, each sampling circuit 82 may have an input coupled to multiple columns of pixels in the array.

[0054] where the asynchronous sampling employs two separate timing / reference rows 72-R and 72-S Figure 6The examples are illustrative. In other embodiments, a single timing row may be used to generate the reset and signal asynchronous sampling / trigger signal RDcolj. The single timing row may be implemented as two or more parallel clocked rows, and the outputs of these rows are averaged to remove undesirable per-element random variations. Wherein a row driver circuit is used to drive the pixel array 32 from both sides of the array Figure 6 The examples are also illustrative. If desired, the techniques described herein may also be applied to image sensor architectures having row driver circuits 41 disposed only on one side of the array, such as Figure 2 shown in the example.

[0055] Figure 7 is a flowchart of illustrative steps for operating an image sensor circuit of the type described in connection with Figures 1 to 6 During the operation of block 700, a floating diffusion reset (FDR) signal is synchronously emitted for the entire active row. This corresponds to Figure 5 the operation at time t0 in

[0056] After this synchronous emission, the FDR control signal propagates down the active row of pixels, first reaching the nearest column, and then reaching each successive column along the row at progressively later times until finally reaching the farthest column. After the FDR signal reaches the pixels in a particular column, that pixel is reset to the reset voltage, and the corresponding reset value may be output to the associated pixel output column line. The reset value will stabilize on the pixel output column line after the column path settling time. Figure 6 ). Figure 5 In the example of

[0057] During the operation of block 702, the asynchronous sampling circuit 80 (e.g., see Figure 6 ) may be used to asynchronously sample the reset values output from successive pixel columns. In Figure 2 the example, the reset value from the nearest column may be sampled at time t2, while the reset value from the farthest column may be sampled at time t3. The reset values from the intermediate pixel columns between the nearest and farthest columns may be sampled at some time between t2 and t3. If desired, groups of pixel columns may be sampled simultaneously to achieve quantization sampling.

[0058] During the operation of block 704, the sampled reset values may be converted into corresponding digital codes. Each sampled reset value may be converted using a corresponding analog-to-digital converter (ADC) that may be coupled to the output of the sample-and-hold circuit 82 in Figure 5The operation at time t2 in. The synchronous transmission of the TX signal can occur before the remaining values in the farthest column have stabilized on the pixel output column lines. After this synchronous transmission, the TX control signal will propagate down the active row of the pixels, first reaching the nearest column, and then reaching each successive column along that row at progressively later times until finally reaching the farthest column. After the TX signal reaches the pixels in a particular column, the accumulated charge is transferred to the floating diffusion region in that pixel, and the corresponding image signal value can be output to the associated pixel output column line. The signal value will stabilize on the pixel output column line after the column path settling time.

[0059] During the operation of block 708, an asynchronous sampling circuit 80 (e.g., see Figure 6 ) can be used to asynchronously sample the signal values output from successive pixel columns. In Figure 5 's example, the signal value from the nearest column can be sampled at time t5, while the reset value from the farthest column can be sampled at time t6. The signal values from the intermediate pixel columns between the nearest and farthest columns can be sampled at some time between t5 and t6. If desired, groups of pixel columns can be sampled simultaneously to achieve quantization sampling.

[0060] During the operation of block 710, the sampled signal values can be converted into corresponding digital codes. A corresponding analog-to-digital converter (ADC) that can be coupled to the output of the sample-and-hold circuit 82 in Figure 6 and can be included within the readout circuit 42 in Figure 2 can be used to convert each of the sampled signal values. The ADC conversion for each pixel column can occur asynchronously at different times, followed by the asynchronous sampling of each signal value.

[0061] During the operation of block 712, components in the control circuits 42 or 44 in Figure 2 or in the image processing and data formatting circuit 16 in Figure 1 can be used to calculate the difference between the converted reset value (digital reset code) obtained from block 704 and the converted signal value (digital signal code) obtained from block 710 to perform correlated double sampling (CDS). Performing correlated double sampling in this way can be technically beneficial for removing or reducing unwanted noise sources that may potentially corrupt the accuracy of the measured signal.

[0062] The use of the correlated double sampling readout scheme is merely illustrative. If desired, other types of image sensor readout schemes may optionally be employed. As an example, a single sampling scheme may be used, where only one signal sample is taken from each pixel without any prior reset operation. As another example, a multi-sampling scheme may be used where multiple signal samples are taken continuously and then averaged to reduce the effects of random noise, which may help improve the signal-to-noise ratio. As yet another example, a correlated multi-sampling (CMS) scheme may be used that combines CDS with multiple signal samples taken continuously after the reset operation.

[0063] The above is merely illustrative, and various modifications may be made to the described embodiments. The above embodiments may be implemented singly or in any combination.

Claims

1. A method of operating an image sensor having a pixel array, the method comprising: Outputting a row control signal to a row of pixels in the pixel array at a first time using a row driver circuit; sampling, using a first sampling circuit, a first output signal from a first pixel in the pixel row at a second time; as well as A second output signal from a second pixel among the pixels is sampled at a third time after the second time using a second sampling circuit.

2. The method according to claim 1, further comprising: receiving the row control signal at the first pixel in the row of pixels at a first row propagation delay after the first time; as well as The row control signal at the second pixel in the row of pixels is received at a second row propagation delay after the first time, wherein a difference between the third time and the second time is equal to a difference between the second row propagation delay and the first row propagation delay.

3. The method according to claim 1, wherein: The first output signal from the first pixel in the pixel row settles on a first column line within a first column path settling time; and The first output signal from the first pixel in the row of pixels is sampled at the second time after the first output signal has settled on the first column line.

4. The method of claim 3, wherein the second output signal from the second pixel in the pixel row is stabilized on a second column line within a second column path stabilization time, the method further comprising: With the row driver circuit, an additional row control signal is output to the row of pixels in the pixel array before the second output signal has stabilized on the second column line.

5. The method according to claim 4, wherein: Outputting the row control signal includes: outputting a reset control signal to the pixel row in the pixel array; and Outputting the additional row control signal includes outputting a charge transfer signal to the row of pixels in the pixel array.

6. The method according to claim 5, further comprising: After sampling the first output signal, converting the first output signal into a first digital code; as well as After sampling the second output signal, the second output signal is converted into a second digital code.

7. The method according to claim 1, further comprising: One or more additional output signals from one or more additional pixels in the row of pixels are sampled at the second time using the first sampling circuit.

8. The method according to claim 1, further comprising: A trigger signal is output to the first sampling circuit using a timing pixel row having the same structure as the pixel row.

9. An image sensor, comprising: Pixel array; a plurality of row driver circuits configured to output row control signals to corresponding rows of pixels in the array; reference pixel row; and An asynchronous sampling circuit having a plurality of sampling circuits, wherein each sampling circuit of the plurality of sampling circuits includes a first input coupled to a column of pixels in the array and a second input coupled to the reference pixel row.

10. The image sensor according to claim 9, further comprising: an additional row driver circuit configured to output a row control signal to the reference pixel row; and A delay circuit is coupled between the plurality of row driver circuits and the additional row driver circuit.

11. The image sensor of claim 10 , wherein the delay circuit is configured to provide an amount of delay equal to a column path settling time, and wherein a signal output from a given pixel in the array settles on a column line coupled to the given pixel within the column path settling time.

12. The image sensor according to claim 9, further comprising: An additional reference pixel row is disposed adjacent to the reference pixel row.

13. The image sensor according to claim 12, further comprising: A logic gate having a first input coupled to a first pixel in the reference pixel row, a second input coupled to a second pixel in the additional reference pixel row, and an output coupled to one of the plurality of sampling circuits. The image sensor of claim 13 , wherein the logic gate comprises a logical OR gate.

15. The image sensor according to claim 9, further comprising: an additional plurality of row driver circuits configured to output row control signals to corresponding rows of pixels in the array, wherein the plurality of row driver circuits are disposed along a first edge of the array, and wherein the additional plurality of row driver circuits are disposed along a second edge of the array; a first additional row driver circuit disposed along the first edge of the array and configured to output a row control signal to the reference pixel row; a second additional row driver circuit disposed along the second edge of the array and configured to output a row control signal to the reference pixel row; a first delay circuit coupled between the plurality of row driver circuits and the first additional row driver circuit; and A second delay circuit is coupled between the additional plurality of row driver circuits and the second additional row driver circuit.

16. The image sensor of claim 9, wherein the first input of each of the plurality of sampling circuits is coupled to a plurality of columns of pixels in the array.

17. An image sensor, comprising: Pixel array; a first row driver circuit configured to output a row control signal to a row of pixels in the array; a timing pixel row, the timing pixel row being arranged along an edge of the pixel array; a second row driver circuit configured to output a row control signal to the clocked pixel row; and A delay circuit is coupled between the first row driver circuit and the second row driver circuit.

18. The image sensor according to claim 17, further comprising: An additional timing pixel row is arranged adjacent to the timing pixel row, wherein the timing pixel row is configured to generate a trigger signal for sampling a reset value from the pixel array, and wherein the additional timing pixel row is configured to generate a trigger signal for sampling a signal value from the pixel array.

19. The image sensor according to claim 18, further comprising: an asynchronous sampling circuit having a plurality of sampling circuits, wherein each sampling circuit of the plurality of sampling circuits has a first input coupled to a corresponding pixel column in the array and has a second input configured to receive a first signal from a first pixel in the clocked pixel row or a second signal from a second pixel in the additional clocked pixel row.

20. The image sensor of claim 19, wherein the first input of each of the plurality of sampling circuits is coupled to a plurality of columns of pixels in the array.

Images