Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electrical system are provided. The semiconductor device includes: a substrate including a cell array region and a connection region; a plurality of ground selection gate patterns spaced apart from each other; a plurality of unit gate patterns vertically stacked on the plurality of ground selection gate patterns; separation structures vertically extending into the cell gate pattern and disposed between the plurality of ground selection gate patterns and spaced apart from each other in the first direction in the connection region; and dummy vertical structures disposed between the separation structures adjacent in the first direction and between the first ground selection gate pattern and a second ground selection gate pattern adjacent to the first ground selection gate pattern. Each of the dummy vertical structures includes a vertical portion vertically extending into the cell gate pattern and an extending portion horizontally protruding from the vertical portion.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10 - 2023 - 0196247, filed with the Korean Intellectual Property Office on December 29, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device and an electronic system including the semiconductor device. Background art

[0004] Semiconductor devices capable of storing a large amount of data may be required to meet the data storage requirements of electronic systems. Therefore, technologies for increasing the data storage capacity of semiconductor devices are being studied. For example, as one of the methods for increasing the data storage capacity of semiconductor devices, semiconductor devices including three - dimensionally arranged memory cells instead of two - dimensionally arranged memory cells have been proposed. Summary of the invention

[0005] Some example embodiments provide a semiconductor device with improved reliability and integration.

[0006] Some example embodiments provide an electronic system including the semiconductor device.

[0007] The example embodiments are not limited to solving the above - mentioned problems, and the embodiments may solve other problems not mentioned. The example embodiments will be described below, and those skilled in the art will clearly understand variations of the example embodiments from the following description.

[0008] According to some example embodiments, a semiconductor device may include: a substrate including a cell array region and a connection region; a plurality of ground - select gate patterns, wherein each ground - select gate pattern is spaced apart from each other and is disposed at the same horizontal height with respect to the top surface of the substrate;

[0009] a plurality of cell gate patterns vertically stacked on the plurality of ground - select gate patterns; a plurality of isolation structures, wherein each isolation structure vertically extends into the cell gate patterns and is disposed between corresponding ground - select gate patterns of the plurality of ground - select gate patterns and is spaced apart from each other in a first direction in the connection region; and a plurality of dummy vertical structures disposed between a first isolation structure and a second isolation structure adjacent to each other in the first direction and between a first ground - select gate and a second ground - select pattern, wherein each of the dummy vertical structures includes a vertical portion vertically extending into the cell gate patterns and an extension portion horizontally protruding from the vertical portion at the same horizontal height as the ground - select gate patterns, and the extension portions of each of the dummy vertical structures are connected to each other and are in contact with the first isolation structure and the second isolation structure.

[0010] According to some example embodiments, a semiconductor device may include: a substrate including a cell array region and a connection region; a first isolation structure extending in a first direction parallel to a top surface of the substrate; a stacked structure disposed between first isolation structures adjacent to each other in a second direction perpendicular to the first direction and including gate patterns and interlayer insulating layers stacked vertically on the substrate alternately; the gate patterns including a plurality of ground select gate patterns and a plurality of cell gate patterns, wherein each of the ground select gate patterns is spaced apart from each other at the same horizontal height with respect to the top surface of the substrate, and the plurality of cell gate patterns are stacked vertically on the plurality of ground select gate patterns; a second isolation structure extending into a plurality of cell gate patterns adjacent to each other in the second direction and disposed between the ground select gate patterns and spaced apart from each other in the connection region in the first direction; a first dummy vertical structure disposed between second isolation structures adjacent to each other in the first direction and between ground select gate patterns adjacent to each other in the second direction; and a second dummy vertical structure extending into the stacked structure in the connection region, wherein each of the first dummy vertical structure and the second dummy vertical structure includes a vertical portion extending vertically into the cell gate patterns and an extension portion horizontally protruding from the vertical portion at the same horizontal height as the ground select gate patterns, and each extension portion of the first dummy vertical structure is connected to each other and contacts the second isolation structures adjacent to each other in the first direction.

[0011] According to some example embodiments, an electrical system may include: a semiconductor device including a substrate having a cell array region and a connection region; a plurality of ground select gate patterns, wherein each of the ground select gate patterns is spaced apart from each other and disposed at the same horizontal height with respect to the top surface of the substrate; a plurality of cell gate patterns stacked vertically on the plurality of ground select gate patterns; an isolation structure extending vertically into the cell gate patterns and disposed between adjacent ground select patterns among the plurality of ground select gate patterns and spaced apart from each other in the connection region in a first direction; and a dummy vertical structure between adjacent isolation structures and between adjacent ground select gate patterns; and input / output pads electrically connected to a peripheral circuit; and a controller electrically connected to the semiconductor device through the input / output pads and controlling the semiconductor device, wherein each of the dummy vertical structures includes a vertical portion extending vertically into the cell gate patterns and an extension portion horizontally protruding from the vertical portion at the same horizontal height as the ground select gate patterns, and each extension portion of the dummy vertical structures is connected to each other and contacts the isolation structures adjacent to each other in the first direction.

[0012] Specific details of other embodiments are included in the detailed description and the drawings. Description of the Drawings

[0013] Example embodiments will be understood more clearly from the following brief description in conjunction with the accompanying drawings. The drawings illustrate non-limiting example embodiments described herein.

[0014] Figure 1 is a diagram schematically showing an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0015] Figure 2 is a perspective view schematically showing an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0016] Figure 3 and Figure 4 are cross-sectional views schematically showing a semiconductor package according to some example embodiments of the present disclosure.

[0017] Figure 5 is a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0018] Figure 6A , Figure 6B , Figure 6C and Figure 6D are cross-sectional views of a semiconductor device taken along lines A-A', B-B', C-C' and D-D' according to different some example embodiments of the present disclosure. Figure 5

[0019] Figure 7A is a plan view showing a ground selection gate pattern arranged in a stacked structure according to some example embodiments of the present disclosure.

[0020] Figure 7B is a plan view showing a cell gate pattern arranged in a stacked structure according to some example embodiments of the present disclosure.

[0021] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E are cross-sectional views of a semiconductor device taken along line A-A' according to different some example embodiments of the present disclosure. Figure 5

[0022] Figure 9A is a plan view of a semiconductor device according to some example embodiments of the present disclosure.

[0023] Figure 9B is a plan view showing a cell gate pattern arranged in a stacked structure according to some example embodiments of the present disclosure.

[0024] Figure 9C ​​It is a plan view showing a ground selection gate pattern disposed in a stacked structure according to some example embodiments of the present disclosure.

[0025] Figure 9D It is a cross-sectional view of a semiconductor device taken along line D-D' according to some different example embodiments of the present disclosure. Figure 9A

[0026] Figure 10A and Figure 10B It is a plan view of a semiconductor device according to some different example embodiments of the present disclosure.

[0027] Figure 11 It is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure.

[0028] Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A It is a diagram showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and shows a cross-section taken along line A-A'. Figure 5

[0029] Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B It is a diagram showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and shows a cross-section taken along line B-B'. Figure 5

[0030] Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C and Figure 18C It is a diagram showing a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure, and shows a cross-section taken along line C-C'. Figure 5 DETAILED DESCRIPTION

[0031] Hereinafter, with reference to the accompanying drawings, a semiconductor device and an electronic system including the semiconductor device according to some example embodiments of the present disclosure will be described in detail.

[0032] ​​​​It should be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, it can be directly connected or coupled to the other element or directly on the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "contacting" or "in contact with" another element (or any form of the word "contact" is used), there are no intervening elements at the point of contact.

[0033] As used herein, components described as "electrically connected" are configured such that an electrical signal can be transferred from one component to another (although the strength of the electrical signal may decay as it is transferred and the electrical signal may be selectively transferred). Additionally, components that are "directly electrically connected" share a common electrical node through an electrical connection via one or more conductors such as, for example, wires, pads, internal wires, via components, etc. Thus, components that are directly electrically connected do not include components that are electrically connected through active elements such as transistors or diodes.

[0034] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for particular elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. Additionally, a term referred to by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or in another claim).

[0035] Terms such as "same", "equivalent", "in the same plane" or "coplanar" as used herein when referring to orientation, layout, position, shape, size, composition, quantity or other measures do not necessarily mean exactly the same orientation, layout, position, shape, size, composition, quantity or other measures, but are intended to include orientations, layouts, positions, shapes, sizes, compositions, quantities or other measures that are nearly identical within an acceptable range of variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equivalent" or "substantially in the same plane" may be exactly the same, equivalent or in the same plane, or may be the same, equivalent or in the same plane within an acceptable range of variations that may occur, for example, due to manufacturing processes.

[0036] It should be understood that "planarized", "coplanar", "in the same plane", etc. as used herein refer to structures that do not necessarily need to be geometrically in exactly the same plane, but may include an acceptable range of variations that may result from standard manufacturing processes.

[0037] Throughout the specification, when a component is described as "including" a particular element or a set of elements, it should be understood that the component is formed only by that element or that set of elements, or that element or that set of elements may be combined with additional elements to form the component, unless the context clearly and / or explicitly describes otherwise. On the other hand, the term "formed of" means that the component is formed only by the listed elements.

[0038] Figure 1 is a diagram schematically showing an electronic system including a semiconductor device according to some example embodiments of the present disclosure.

[0039] Referring to Figure 1 , an electronic system 1000 according to some example embodiments may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system in which at least one semiconductor device 1100 is provided.

[0040] The semiconductor device 1100 may be a non-volatile memory device (e.g., a NAND flash memory device). The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed beside the second structure 1100S.

[0041] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer circuit 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, an upper gate line UL1 and an upper gate line UL2, a lower gate line LL1 and a lower gate line LL2, and a memory cell string CSTR between the bit lines BL and the common source line CSL.

[0042] In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary differently according to embodiments.

[0043] In an embodiment, the upper transistors UT1 and UT2 may include at least one string selection transistor, and the lower transistors LT1 and LT2 may include at least one ground selection transistor. The lower gate lines LL1 and LL2 may serve as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may serve as a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may serve as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0044] The memory cell transistor MCT of each memory cell string CSTR may be controlled by a back gate line.

[0045] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer circuit 1120 through a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0046] In the first structure 1100F, the decoder circuit 1110 and the page buffer circuit 1120 may be configured to perform control operations on at least one of the selected memory cell transistors MCT. The decoder circuit 1110 and the page buffer circuit 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0047] Although Figure 1 not shown, the first structure 1100F may include a voltage generator (not shown). The voltage generator may generate a programming voltage, a read voltage, a pass voltage, and a verify voltage required for the operation of the memory cell string CSTR. Here, the programming voltage may be a relatively high voltage (e.g., 20V to 40V) compared to the read voltage, the pass voltage, and the verify voltage.

[0048] In an embodiment, the first structure 1100F may include high-voltage transistors and low-voltage transistors. The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high-voltage transistor that can withstand a high voltage such as the programming voltage applied to the word line WL during a programming operation. The page buffer circuit 1120 may also include high-voltage transistors that can withstand high voltages.

[0049] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in such a case, the controller 1200 may control the semiconductor devices 1100.

[0050] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on specific firmware and may control the NAND controller 1220 to access the semiconductor devices 1100. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor devices 1100. The NAND interface 1221 may be configured to send and receive control commands for controlling the semiconductor devices 1100, memory cell transistors MCT to be written to the semiconductor devices 1100, or data read from the memory cell transistors MCT of the semiconductor devices 1100, etc. The host interface 1230 may be configured to allow communication between the electronic system 1000 and an external host. When the processor 1210 receives a control command sent from the external host through the host interface 1230, the processor 1210 may control the semiconductor devices 1100 in response to the control command.

[0051] Figure 2 is a perspective view schematically showing an electronic system including semiconductor devices according to some example embodiments of the present disclosure.

[0052] Referring to Figure 2 FIG. 2, the electronic system 2000 according to some example embodiments may include a main substrate 2001 and a controller 2002, at least one semiconductor package 2003, and a DRAM 2004 mounted on the main substrate 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnect pattern 2005 formed in the main substrate 2001.

[0053] The main substrate 2001 may include a connector 2006 having a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the pins may vary according to the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with the external host according to interface standards such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI express), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS) M-Phy, etc. In an embodiment, the electronic system 2000 may be driven by electrical power supplied from the external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) configured to distribute the electrical power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0054] The controller 2002 can be configured to control write or read operations for the semiconductor package 2003 and improve the operation speed of the electronic system 2000.

[0055] The DRAM 2004 can be a buffer memory that alleviates technical difficulties caused by the speed difference between the semiconductor package 2003 used as a data storage device and an external host. The DRAM 2004 in the electronic system 2000 can be used as a cache memory and can be used as a storage space configured to temporarily store data during the control operation of the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 can further include a DRAM controller for controlling the DRAM 2004.

[0056] The semiconductor package 2003 can include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the respective bottom surfaces of the semiconductor chips 2200, a connection structure 2400 for electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 disposed on the package substrate 2100 to cover the semiconductor chips 2200 and the connection structure 2400.

[0057] The package substrate 2100 can be a printed circuit board including upper pads 2130. Each of the semiconductor chips 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to Figure 1 the input / output pads 1101. Each of the semiconductor chips 2200 can include a stacked structure 3210 and a vertical structure 3220. Each of the semiconductor chips 2200 can include a semiconductor device according to some example embodiments described below.

[0058] In an embodiment, the connection structure 2400 may be a bonding wire configured to electrically connect the input / output pad 2210 to the upper pad 2130. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the form of bonding wires and may be electrically connected to the upper pads 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, instead of or in addition to the connection structure 2400 configured in the form of bonding wires, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through-silicon via (TSV).

[0059] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on an additional insert substrate different from the main substrate 2001 and may be connected to each other through interconnect lines provided in the insert substrate.

[0060] Figure 3 and Figure 4 are cross-sectional views schematically showing semiconductor packages according to some example embodiments of the present disclosure. Figure 3 and Figure 4 are cross-sectional views taken along line I-I’ of Figure 2 and show two different examples of the semiconductor packages of Figure 2 .

[0061] Referring to Figure 3 , the package substrate 2100 of the semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate main body portion 2120, upper pads 2130 (e.g., see Figure 2 ) provided on the top surface of the package substrate main body portion 2120, lower pads 2125 provided on the bottom surface of the package substrate main body portion 2120 or exposed through the bottom surface of the package substrate main body portion 2120, and internal lines 2135 provided in the package substrate main body portion 2120 to electrically connect the upper pads 2130 to the lower pads 2125. The upper pads 2130 may be electrically connected to the connection structure 2400 (e.g., see Figure 2 ). The lower pads 2125 may be connected to the interconnect pattern 2005 of the main substrate 2001 of the electronic system 2000 shown in Figure 2 through the conductive connection portion 2800.

[0062] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having peripheral lines 3110. The second structure 3200 may include a source structure 3205, a stacked structure 3210 on the source structure 3205, a vertical structure 3220 passing through the stacked structure 3210 and a separation structure (not shown), a bit line 3240 electrically connected to the vertical structure 3220, and a cell contact plug 3235 electrically connected to the stacked structure 3210 and the word line WL (e.g., see Figure 1 ). Each of the first structure 3100 and the second structure 3200 and the semiconductor chip 2200 may also include a separation structure to be described below.

[0063] Each of the semiconductor chips 2200 may include a via line 3245 electrically connected to the peripheral lines 3110 of the first structure 3100 and extending to the second structure 3200. The via line 3245 may be disposed outside the stacked structure 3210, and the via line 3245 may be configured to further pass through the stacked structure 3210. Each of the semiconductor chips 2200 may also include an input / output pad 2210 electrically connected to the peripheral lines 3110 of the first structure 3100 (e.g., see Figure 2 ).

[0064] Referring to Figure 4 , in the semiconductor package 2003A, each of the semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner.

[0065] The first structure 4100 may include a peripheral circuit region having peripheral lines 4110 and a first bonding structure 4150. The second structure 4200 may include a source structure 4205, a stacked structure 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 passing through the stacked structure 4210 and a separation structure (not shown), and a second bonding structure 4250 electrically connected and respectively connected to the vertical structure 4220 and the word line WL (e.g., see Figure 1 ). For example, the second bonding structure 4250 may be electrically connected to the vertical structure 4220 and the word line WL (e.g., see Figure 1 ) respectively through a bit line 4240 electrically connected to the vertical structure 4220 and a cell contact plug 4235 electrically connected to the word line WL (e.g., see Figure 1)。The first engaging structure 4150 of the first structure 4100 may be in contact with the second engaging structure 4250 of the second structure 4200, and the first engaging structure 4150 of the first structure 4100 may be engaged to the second engaging structure 4250 of the second structure 4200. The engaging portion of the first engaging structure 4150 and the second engaging structure 4250 may be formed of and / or include, for example, copper (Cu).

[0066] Each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200a may further include a source structure according to an embodiment described below. Each of the semiconductor chips 2200a may further include an input / output pad 2210 electrically connected to the peripheral line 4110 of the first structure 4100 (e.g., see Figure 2 ).

[0067] Figure 3 The semiconductor chips 2200 and Figure 4 The semiconductor chips 2200a may be electrically connected to each other through a connection structure 2400 provided in the form of bonding wires (e.g., see Figure 2 ). However, in an embodiment, the semiconductor chips provided in each semiconductor package (e.g., Figure 3 The semiconductor chips 2200 and Figure 4 The semiconductor chips 2200a) may be electrically connected to each other through a connection structure including silicon through-vias (TSVs).

[0068] Figure 5 is a plan view of a semiconductor device according to some example embodiments of the present disclosure. Figure 6A , Figure 6B , Figure 6C and Figure 6D are cross-sectional views of the semiconductor device taken along lines A-A', B-B', C-C', and D-D' according to different some example embodiments of the present disclosure. Figure 5 Figure 7A is a plan view showing a ground selection gate pattern arranged in a stacked structure according to some example embodiments of the present disclosure. Figure 7B is a plan view showing a cell gate pattern arranged in a stacked structure according to some example embodiments of the present disclosure.

[0069] Referring to Figure 5 , Figure 6A , Figure 6B , Figure 6C and Figure 6D , a semiconductor device according to some example embodiments of the present disclosure may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0070] ​The peripheral circuit structure PS may include a peripheral circuit PTR integrated on the front surface of the semiconductor substrate 10 and a lower insulating layer 50 covering the peripheral circuit PTR. The semiconductor substrate 10 may be a silicon substrate. The semiconductor substrate 10 may include a cell array region CAR and a connection region CNR.

[0071] The peripheral circuit PTR may be a row decoder and a column decoder, a page buffer, and a control circuit. Specifically, the peripheral circuit PTR may include NMOS transistors and PMOS transistors. The peripheral circuit line PLP may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP.

[0072] The lower insulating layer 50 may be disposed on the entire surface of the semiconductor substrate 10. The lower insulating layer 50 may cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit line PLP on the semiconductor substrate 10. The peripheral contact plug PCP and the peripheral circuit line PLP may be electrically connected to the peripheral circuit PTR.

[0073] The lower insulating layer 50 may include insulating layers stacked in multiple layers. For example, the lower insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. As an example, the lower insulating layer 50 may include a first lower insulating layer 51, a second lower insulating layer 55, and an etch stop layer 53 between the first lower insulating layer 51 and the second lower insulating layer 55. The etch stop layer 53 may include an insulating material different from the first lower insulating layer 51 and the second lower insulating layer 55 and may cover the top surface of the uppermost peripheral circuit line PLP.

[0074] The cell array structure CS may be disposed on the lower insulating layer 50. The cell array structure CS may include a semiconductor layer 100, a source structure CST, a stacked structure ST, a vertical channel structure VS, a first dummy vertical structure DP1 and a second dummy vertical structure DP2, a through contact plug TPLG, a bit line BL, and a conductive line CL.

[0075] According to some embodiments, Figure 1 The illustrated cell string CSTR may be integrated on the semiconductor layer 100. The stacked structure ST and the vertical channel structure VS may form Figure 1 the illustrated cell string CSTR.

[0076] Specifically, the semiconductor layer 100 may be disposed at the top surface of the lower insulating layer 50. The semiconductor layer 100 may be formed of a semiconductor material, an insulating material, or a conductive material. The semiconductor layer 100 may include a semiconductor doped with a dopant of a first conductivity type (e.g., n-type) and / or an intrinsic semiconductor not doped with impurities. The semiconductor layer 100 may have a crystal structure including a single crystal structure, an amorphous structure, or a polycrystalline structure.

[0077] The source structure CST may be disposed between the semiconductor layer 100 and the stacked structure ST. The source structure CST may be parallel to the top surface of the semiconductor layer 100 and may extend in a first direction D1 parallel to the stacked structure ST in the cell array region CAR.

[0078] The source structure CST may include a source conductive pattern SC and a support conductive pattern SP on the source conductive pattern SC. The source conductive pattern SC may be disposed between the semiconductor layer 100 and the stacked structure ST in the cell array region CAR. The source conductive pattern SC may be formed of a semiconductor material doped with a dopant having a first conductivity type (e.g., phosphorus (P) or arsenic (As)). As an example, the source conductive pattern SC may be formed of a polysilicon layer doped with an n-type dopant.

[0079] According to some embodiments, the first insulating layer 101, the second insulating layer 103, and the third insulating layer 105 may be sequentially stacked and disposed between the semiconductor layer 100 and the stacked structure ST in the connection region CNR. The first insulating layer 101, the second insulating layer 103, and the third insulating layer 105 may be disposed at the same or substantially the same horizontal height as the source conductive pattern SC. The second insulating layer 103 may include an insulating material different from the first insulating layer 101 and the third insulating layer 105. The second insulating layer 103 may be thicker than the first insulating layer 101 and the third insulating layer 105. The first insulating layer 101, the second insulating layer 103, and the third insulating layer 105 may be at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, or a silicon germanium layer.

[0080] The support conductive pattern SP may cover the top surface of the source conductive pattern SC in the cell array region CAR and the top surface of the third insulating layer 105 in the connection region CNR. The support conductive pattern SP may include a semiconductor doped with a dopant having a first conductivity type (e.g., n-type) and / or an intrinsic semiconductor not doped with impurities.

[0081] The stacked structure ST may be disposed on the source structure CST. The stacked structure ST may extend from the cell array region CAR to the connection region CNR in the first direction D1 and may have a stepped structure in the connection region CNR.

[0082] The stacked structure ST may include gate patterns EGE, GSE1, GSE2, and CGE. The gate patterns EGE, GSE1, GSE2, and CGE may include at least one material selected from, for example, doped semiconductors (e.g., doped silicon, etc.), metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), or transition metals (e.g., titanium, tantalum, etc.). The stacked structure ST may include an interlayer insulating layer ILD interposed between the gate patterns EGE, GSE1, GSE2, and CGE. The interlayer insulating layer ILD may include a silicon oxide layer and / or a low dielectric layer.

[0083] Specifically, the gate pattern of the stacked structure ST may include an erase control gate pattern EGE, a first ground selection gate pattern GSE1, a second ground selection gate pattern GSE2, and a cell gate pattern CGE. The erase control gate pattern EGE may be sequentially stacked on the support conductive pattern SP. The first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be disposed between the erase control gate pattern EGE and the lowermost cell gate pattern CGE, and the cell gate pattern CGE may be vertically stacked on the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2.

[0084] The erase control gate pattern EGE may be adjacent to the source conductive pattern SC and may be used as the gate electrode of an erase control transistor that controls (e.g., Figure 1 in) the erase operation of the memory cell transistor MCT. The erase control gate pattern EGE may be used as the gate electrode of an erase control transistor ECT that generates gate-induced drain leakage (GIDL) (e.g., Figure 1 in).

[0085] According to an embodiment, the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be disposed at the same horizontal height with respect to the top surface of the substrate 10. As Figure 7A shown, the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. The first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be arranged to be mirror images (i.e., symmetric) of each other and may have uneven side surfaces in a part of the connection region CNR. The first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be used as the gate electrodes of ground selection transistors that control (e.g., Figure 1 in) the electrical connection between the common source line CSL and (e.g., Figure 1 in) a plurality of memory cell transistors MCT.

[0086] The plurality of cell gate patterns CGE may be disposed at different horizontal heights with respect to the top surface of the substrate 10. The cell gate pattern CGE may be used as a word line WL that is connected to (e.g., Figure 1 in) the gate electrodes of the memory cell transistors MCT (e.g., Figure 1 in). As Figure 7BAs shown, each of the cell gate patterns CGE may include a line portion LP extending side by side in a first direction D1 and a connection portion CNP connecting the line portions LP in a connection region CNR. Each cell gate pattern CGE may be formed of a single layer, and each cell gate pattern CGE may have at least one dummy hole DH1 in the connection portion CNP. When viewed in a plan view, the line portion LP of each cell gate pattern CGE may overlap with a first ground selection gate pattern GSE1 and a second ground selection gate pattern GSE2.

[0087] Although not shown in the figures, the stacked structure ST may further include a string selection gate pattern on the uppermost cell gate pattern CGE. The string selection gate pattern may be used as a gate electrode of string selection transistors SST1 and SST2 (e.g., Figure 1 in) that control the electrical connection between the bit line BL and the vertical channel structure VS.

[0088] According to some embodiments, as Figures 6A to 6D shown, each of the erase control gate pattern EGE and the cell gate pattern CGE may have a first thickness in a third direction D3. Each of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may have a second thickness greater than the first thickness.

[0089] The interlayer insulating layer ILD of the stacked structure ST may have the same or substantially the same thickness. That is, the distances between vertically adjacent gate patterns EGE, GSE1, GSE2, and CGE may all be consistent. The thickness of each of the interlayer insulating layers ILD may be less than the second thickness of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2.

[0090] The gate patterns EGE, GSE1, GSE2, and CGE of the stacked structure ST may extend from the cell array region CAR to the connection region CNR in the first direction D1. The lengths of the gate patterns EGE, GSE1, GSE2, and CGE of the stacked structure ST in the first direction D1 may decrease as the distance from the top surface of the substrate 10 increases.

[0091] Each of the gate patterns EGE, GSE1, GSE2, and CGE may include an electrode portion on the cell array region CAR and a pad portion PAD on the connection region CNR. The pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE of the stacked structure ST may be thicker than the electrode portions on the cell array region CAR.

[0092] A portion of the stacked structure ST may have a stepped arrangement structure in the connection region CNR. According to the stepped arrangement structure of the stacked structure ST, the pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE of the stacked structure ST may be horizontally and vertically arranged at different positions.

[0093] The planarized insulating layer 120 may cover the pad portion PAD of the stacked structure ST in the connection region CNR. The planarized insulating layer 120 may have a substantially flat upper surface. The planarized insulating layer 120 may include one insulating layer or a plurality of stacked insulating layers.

[0094] A plurality of vertical channel structures VS may pass through the stacked structure ST and the source structure SCT in the cell array region CAR. When viewed in a plan view, the vertical channel structures VS may be arranged in one direction or in a zigzag pattern.

[0095] Each of the vertical channel structures VS may include a first vertical extension portion extending through the lower portion of the stacked structure ST, a second vertical extension portion extending through the upper portion of the stacked structure ST, and a connection extension portion between the first vertical extension portion and the second vertical extension portion. The diameter of the vertical channel structure VS may rapidly increase in the connection extension portion.

[0096] Each of the vertical channel structures VS may include a vertical semiconductor pattern and a data storage pattern around the sidewall of the vertical semiconductor pattern.

[0097] The vertical semiconductor pattern may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern containing the semiconductor material may be used as a channel for the upper transistors UT1 and UT2, the memory cell transistor MCT, and the lower transistors LT1 and LT2 described above. A portion of the sidewall of the vertical semiconductor pattern may be in contact with the source conductive pattern SC. Figure 1 A portion of the sidewall of the vertical semiconductor pattern may be in contact with the source conductive pattern SC.

[0098] The data storage pattern may extend in a third direction D3 and may surround the sidewall of each vertical semiconductor pattern. The data storage pattern may be composed of one thin layer or a plurality of thin layers. In some exemplary embodiments of the present disclosure, the data storage pattern is a data storage layer of a NAND flash memory device and may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer sequentially stacked on the sidewall of the vertical semiconductor pattern. For example, the charge storage layer may be a trapping insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots.

[0099] The first interlayer insulating layer 130 may cover the upper surface of the vertical channel structures VS and may be disposed on the planarized insulating layer 120.

[0100] The first separation structure SS1 and the second separation structure SS2 can vertically penetrate the stacked structure ST on the semiconductor layer 100. Each of the first separation structure SS1 and the second separation structure SS2 can include an insulating layer covering the sidewalls of the stacked structure ST. Each of the first separation structure SS1 and the second separation structure SS2 can have a single-layer structure or a multi-layer structure. The top surfaces of the first separation structure SS1 and the second separation structure SS2 can be set at the same or substantially the same horizontal height.

[0101] The first separation structure SS1 can continuously extend from the cell array region CAR to the connection region CNR in the first direction D1 and can be spaced apart from each other in the second direction D2 intersecting the first direction D1. Some portions of the first separation structure SS1 can be in contact with the semiconductor layer 100 through the support conductive pattern SP and the source structure CST.

[0102] The second separation structure SS2 can be disposed between the first separation structures SS1 adjacent in the second direction D2. In the first direction D1, the length of the second separation structure SS2 can be less than the length of the first separation structure SS1.

[0103] The second separation structure SS2 can be disposed between the first ground select gate pattern GSE1 and the second ground select gate pattern GSE2 and can vertically penetrate the cell gate pattern CGE and the erase control gate pattern EGE.

[0104] The second separation structure SS2 can continuously extend in the first direction D1 in the cell array region CAR and can be arranged to be spaced apart from each other in the first direction D1 by a specific distance in the connection region CNR. That is, the second separation structures SS2 can be spaced apart from each other in the first direction D1 in the connection region CNR. As another example, a plurality of second separation structures SS2 can be disposed between the first separation structures SS1 and can be spaced apart from each other in the second direction D2.

[0105] The first dummy vertical structure DP1 and the second dummy vertical structure DP2 can penetrate the stacked structure ST in the connection region CNR. The top surfaces of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 can have various shapes such as circular, oval, or bar-shaped.

[0106] The first dummy vertical structure DP1 can be disposed between the first ground select gate pattern GSE1 and the second ground select gate pattern GSE2 in the connection region CNR and can be disposed between the second separation structures SS2 adjacent in the first direction D1. The second dummy vertical structure DP2 can penetrate the pad portions PAD of each of the gate patterns EGE, GSE1, GSE2, and CGE.

[0107] Each of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include an insulating layer covering the sidewall of the stacked structure ST. Each of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may have a single-layer structure or a multi-layer structure. The top surfaces of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may be disposed at the same or substantially the same horizontal height.

[0108] Each of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include vertical portions P1a and P1b vertically passing through the cell gate pattern CGE and the erase control gate pattern EGE, and extension portions P2a and P2b horizontally protruding from the vertical portions P1a and P1b at the same or substantially the same horizontal height as the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2. The first dummy vertical structure DP1 and the second dummy vertical structure DP2 may be formed of an insulating material, and the vertical portions P1a and P1b may have a cylindrical shape. The first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include air gaps therein. In the first dummy vertical structure DP1 and the second dummy vertical structure DP2, the top surfaces of the extension portions P2a and P2b may be in contact with the interlayer insulating layer ILD.

[0109] The extension portions P2a of the first dummy vertical structure DP1 may be connected to each other in the first direction D1. The extension portion P2a of the first dummy vertical structure DP1 adjacent to the second separation structure SS2 may be in contact with the second separation structure SS2. There may be no boundary between the extension portions P2a of the first dummy vertical structure DP1 connected to each other.

[0110] In some embodiments, the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be separated and spaced apart from each other in the second direction D2 by the first dummy vertical structure DP1 and the second separation structure SS2. That is, the sidewalls of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 facing each other may be in contact with the second separation structure SS2 formed of an insulating material and the extension portion P2a of the first dummy vertical structure DP1.

[0111] The extension portion P2a of the first dummy vertical structure DP1 may have the same or substantially the same thickness as the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2. The extension portion P2a of the first dummy vertical structure DP1 may overlap with the cell gate pattern CGE. That is, (for example, Figure 7B in) the connection region CNP of the cell gate pattern CGE may surround the vertical portion P1a of the first dummy vertical structure DP1 in the connection region CNR.

[0112] In some embodiments, the number of first dummy vertical structures DP1 disposed between second isolation structures SS2 adjacent in a first direction D1 may vary according to the diameters of the vertical portion P1a and the extending portion P2a and the distance between the second isolation structures SS2. As an example, three first dummy vertical structures DP1 are shown disposed between second isolation structures SS2 adjacent in the first direction D1, but the inventive concept is not limited thereto.

[0113] The distance S1 between the second isolation structures SS2 in the first direction D1 may be greater than the sum of the diameters r1 of the vertical portions P1a of the first dummy vertical structures DP1 disposed between the second isolation structures SS2 adjacent in the first direction D1.

[0114] The diameter r1 of the vertical portion P1a of the first dummy vertical structure DP1 may be the same as or substantially the same as the diameter of the vertical portion P1b of the second dummy vertical structure DP2. Here, the diameter may be the diameter at the top surface of each vertical portion. The diameter of the extending portion P2a of the first dummy vertical structure DP1 may be the same as or substantially the same as the diameter of the extending portion P2b of the second dummy vertical structure DP2. As another example, the diameter of the vertical portion P1a of the first dummy vertical structure DP1 may be different from the diameter of the vertical portion P1b of the second dummy vertical structure DP2, and the sizes and shapes may also be different. As another example, the second dummy vertical structure DP2 may be formed of a columnar vertical portion without an extending portion.

[0115] The second interlayer insulating layer 140 may cover the top surfaces of the first dummy vertical structure DP1 and the second dummy vertical structure DP2.

[0116] The through contact plug TPLG may vertically pass through the pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE in the connection region CNR and be connected to the peripheral circuit line PLP.

[0117] Sidewall patterns SSP formed of an insulating material may be disposed between the through contact plug TPLG and the gate patterns EGE, GSE1, GSE2, and CGE, and may be disposed under the pad portions PAD of the respective gate patterns EGE, GSE1, GSE2, and CGE. The sidewall patterns SSP may include an insulating material (e.g., silicon oxide).

[0118] Although the bit line is omitted when viewed in a plan view, refer to Figure 6D , the bit line BL may extend from the cell array region CAR across the stacked structure ST in a second direction D2. The bit line BL may be electrically connected to the vertical channel structure VS through a lower bit line contact plug BCTa and an upper bit line contact plug BCTb.

[0119] Figures 8A to 8Eis a cross-sectional view of a semiconductor device taken along line A-A' according to some different exemplary embodiments. In this embodiment, detailed descriptions of technical features that are substantially the same or identical to those described with reference to Figure 5 can be omitted, and the differences will be described in detail. Figure 5 , Figures 6A to 6D , Figure 7A and Figure 7B Referring to

[0120] , a first dummy vertical structure DP1 can be disposed between second isolation structures SS2 adjacent in a first direction D1, and each of the first dummy vertical structures DP1 can include a vertical portion P1a vertically passing through a cell gate pattern CGE and an erase control gate pattern EGE, a first extension portion P2a horizontally protruding from the vertical portion P1a at the same horizontal height as a first ground selection gate pattern GSE1 and a second ground selection gate pattern GSE2, and a second extension portion P3a, also referred to as a cell extension portion, located at the same position as the cell gate pattern CGE and the erase control gate pattern EGE and horizontally protruding from the vertical portion P1a. Figure 8A The thickness of the first extension portion P2a can be the same as or substantially the same as the thickness of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2. The thickness of the second extension portion P3a can be the same as or substantially the same as the thickness of the erase control gate pattern EGE and the cell gate pattern CGE and can be less than the thickness of the first extension portion P2a. Additionally, the horizontal distance from the sidewall of the vertical portion P1a to the sidewall of the first extension portion P2a can be greater than the horizontal distance from the sidewall of the vertical portion P1a to the sidewall of the second extension portion P3a. The sidewall of the second extension portion P3a can be spaced apart from the second isolation structure SS2.

[0121] Although

[0122] only the first dummy vertical structure DP1 is shown, a second dummy vertical structure DP2 can also have the same or substantially the same structure as the first dummy vertical structure DP1. Figure 8A Referring to

[0123] , a first dummy vertical structure DP1 can be disposed between second isolation structures SS2 adjacent in a first direction D1, and each of the first dummy vertical structures DP1 can include a vertical portion P1a and an extension portion P2a horizontally protruding from the vertical portion P1a, as described above with reference to Figure 8B . The extension portion P2a can be disposed at the same horizontal height as the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 and can have the same or substantially the same thickness as the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2. In Figures 6A to 6D Referring to Figure 8BIn the illustrated embodiment, the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may have the same or substantially the same thickness as the cell gate pattern CGE. That is, the thickness of the extension portion P2a may be the same or substantially the same as the thickness of each cell gate pattern CGE.

[0124] Referring Figure 8C , each of the first dummy vertical structures DP1 may include a vertical portion P1a and a first extension portion P2a and a second extension portion P3a that horizontally protrude from the vertical portion P1a, as described with reference to Figure 8A . Here, the first extension portion P2a may be disposed at the same horizontal height as the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2, and the second extension portion P3a may be disposed at the same horizontal height as the cell gate pattern CGE. In this embodiment, the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may have the same or substantially the same thickness as the cell gate pattern CGE, and the first extension portion P2a may have the same or substantially the same thickness as the second extension portion P3a. The first extension portions P2a of the first dummy vertical structures DP1 may be connected to each other in the first direction D1 and may contact the second separation structure SS2. The side walls of the second extension portions P3a of the first dummy vertical structures DP1 may be spaced apart from each other and from the second separation structure SS2.

[0125] Referring Figure 8D , each of the first dummy vertical structures DP1 may include a vertical portion P1a and an extension portion P2a that horizontally protrudes from the vertical portion P1a, as described above with reference to Figures 6A to 6D . Here, the thickness of the extension portion P2a may be less than the thickness of the cell gate pattern CGE. That is, the thicknesses of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 may be less than the thickness of each cell gate pattern CGE and may be the same or substantially the same as the thickness of the extension portion P2a.

[0126] Referring Figure 8E , each of the first dummy vertical structures DP1 may include a vertical portion P1a and a first extension portion P2a and a second extension portion P3a that horizontally protrude from the vertical portion P1a, as described with reference to Figure 8A . Here, the thickness of the first extension portion P2a may be the same or substantially the same as the thicknesses of the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2, and the thickness of the second extension portion P3a may be the same or substantially the same as the thickness of the cell gate pattern CGE. The thickness of the first extension portion P2a may be less than the thickness of the cell gate pattern CGE. That is, the thickness of the first extension portion P2a may be less than the thickness of each of the second extension portions P3a.

[0127] Figure 9A is a plan view of a semiconductor device according to some example embodiments of the present disclosure. Figure 9B is a plan view showing a cell gate pattern disposed in a stacked structure according to some example embodiments of the present disclosure. Figure 9C is a plan view showing a ground select gate pattern disposed in a stacked structure according to some example embodiments of the present disclosure. Figure 9D is according to some different example embodiments along Figure 9A a cross-sectional view of the semiconductor device taken along line D-D'. In this embodiment, detailed descriptions of technical features identical to those of the embodiments described with reference to Figure 5 , Figures 6A to 6D , Figure 7A and Figure 7B will be omitted, and differences will be described in detail.

[0128] Referring to Figures 9A to 9D , a first dummy vertical structure DP1 may be disposed between second separation structures SS2 adjacent to each other in a first direction D1 in a connection region CNR.

[0129] A through contact plug TPLG may be connected to and vertically penetrate pad portions PAD of gate patterns EGE, GSE1, GSE2, and CGE.

[0130] A second dummy vertical structure DP2 may be disposed around each through contact plug TPLG, and extension portions P2b of the second dummy vertical structure DP2 may be connected to each other around each through contact plug TPLG. A molding pattern MP may be disposed between the extension portion P2b of the second dummy vertical structure DP2 and each through contact plug TPLG. That is, the molding pattern MP may contact and surround the sidewall of the through contact plug TPLG at the same horizontal height as the first ground select gate pattern GSE1 and the second ground select gate pattern GSE2.

[0131] Referring to Figure 9B , the first ground select gate pattern GSE1 and the second ground select gate pattern GSE2 may be arranged to be mirror images (i.e., symmetric) of each other when viewed in a plan view. Referring to Figure 9C , as described above, each of the cell gate patterns CGE may be single-layer and may include a line portion LP and a connection portion CP connecting the line portions LP in a connection region CNR.

[0132] Figure 10A and Figure 10B are plan views of a semiconductor device according to various example embodiments of the present disclosure. In this embodiment, detailed descriptions of technical features identical to those of the embodiments described with reference to Figure 5 , Figures 6A to 6D , Figure 7A andFigure 7B a detailed description of the same technical features as those of the described embodiments, and the differences will be described in detail.

[0133] Referring to Figure 10A and Figure 10B , in the connection region CNR, the first dummy vertical structure DP1 may be disposed between second separation structures SS2 adjacent to each other in the first direction D1. Two dummy vertical structures DP2 may pass through the stacked structure ST in the connection region CNR. Here, each of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include the vertical portions P1a and P1b and the extension portions P2a and P2b as described above.

[0134] Referring to Figure 10A , the diameter of the vertical portion P1a in each first dummy vertical structure DP1 may be greater than the diameter of the vertical portion P1b in each second dummy vertical structure DP2. According to this embodiment, two first dummy vertical structures DP1 may be disposed between second separation structures SS2 adjacent to each other in the first direction D1.

[0135] Referring to Figure 10B , the first dummy vertical structures DP1 may be arranged in a matrix form between second separation structures SS2 adjacent to each other in the first direction D1. At least three or more extension portions P2a of the first dummy vertical structures DP1 may be connected to each other to form a circle or a polygon between the second separation structures SS2.

[0136] Figure 11 is a cross-sectional view of a semiconductor device according to some example embodiments of the present disclosure.

[0137] Referring to Figure 11 , a semiconductor device according to an embodiment of the present inventive concept may have a chip-to-chip (C2C) structure. The C2C structure may be formed by the following steps: manufacturing an upper chip including a cell array structure CS on a first wafer; manufacturing a lower chip including a peripheral circuit structure PS on a second wafer different from the first wafer; and connecting the upper chip and the lower chip to each other by bonding. As an example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the topmost metal layer of the upper chip to a bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum (Al) or tungsten (W).

[0138] The cell array structure CS may include a memory cell array including memory cells three-dimensionally arranged on a semiconductor layer 100. The memory cell array may be electrically connected to a first bonding pad BP1.

[0139] Specifically, the cell array structure CS may include a semiconductor layer 100, a source structure CST, a stacked structure ST, a vertical channel structure VS, a bit line BL, a cell contact plug CPLG, and an input / output contact plug IOPLG.

[0140] The cell array structure CS may include a cell array region CAR and a connection region CNR.

[0141] In the cell array region CAR and the connection region CNR, the semiconductor layer 100 of the cell array structure CS may be disposed on the top surface of the lower insulating layer 110. The semiconductor layer 100 may be formed of a semiconductor material, an insulating material, or a conductive material.

[0142] The source structure CST may be disposed on the semiconductor layer 100. The source structure CST may include a source conductive pattern SC and a support conductive pattern SP on the source conductive pattern SC. The source structure CST may be parallel to the top surface of the semiconductor layer 100 and may extend in a first direction D1 parallel to the stacked structure ST in the cell array region CAR and the connection region CNR.

[0143] The source conductive pattern SC may be formed of a semiconductor material doped with a dopant of a first conductivity type (e.g., phosphorus (P) or arsenic (As)). As an example, the source conductive pattern SC may be formed of the semiconductor layer 100 doped with an n-type dopant.

[0144] The support conductive pattern SP may cover the top surface of the source conductive pattern SC and may include a semiconductor doped with a dopant of a first conductivity type (e.g., n-type) and / or an intrinsic semiconductor in a state of being undoped with impurities. Some portions of the support conductive pattern SP in the cell array region CAR may pass through the source conductive pattern SC to contact the semiconductor layer 100.

[0145] The pad conductive pattern LP may be spaced apart from the sidewall of the semiconductor layer 100 and may be disposed in the connection region CNR. The pad conductive pattern LP may be connected to an input / output pad IOPAD disposed on the insulating layer 110.

[0146] The stacked structure ST may be disposed on the source structure CST. As described above, the stacked structure ST may include gate patterns EGE, CGE1, CGE2, and CGE and an interlayer insulating layer ILD alternately stacked in the vertical direction.

[0147] Each of the gate patterns EGE, GSE1, GSE2, and CGE may include an electrode portion on the cell array region CAR and a pad portion PAD on a first connection region CNR1, as referred to Figure 7ADescription. The gate patterns EGE, GSE1, GSE2, and CGE may be stacked on the source structure CST to have a stepped structure in the connection region CNR. The pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE may be horizontally and vertically arranged at different positions. The unit contact plugs CPLG may be respectively connected to the pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE.

[0148] Multiple vertical channel structures VS may pass through the stacked structure ST in the cell array region CAR. As described above, each of the vertical channel structures VS may include a vertical semiconductor pattern and a data storage pattern on the sidewalls surrounding the vertical semiconductor pattern. Each of the vertical channel structures VS may include a lower vertical structure passing through the lower region of the stacked structure ST and an upper vertical structure passing through the upper region of the stacked structure ST.

[0149] Although Figure 11 not shown, the first dummy vertical structure DP1 may be disposed between the first ground selection gate pattern GSE1 and the second ground selection gate pattern GSE2 at the same level. In addition, as described above, the second dummy vertical structure DP2 may pass through the pad portions PAD of the gate patterns EGE, GSE1, GSE2, and CGE in the connection region CNR.

[0150] The planarized insulating layer 120 may cover the stepped arrangement structure of the stacked structure ST. The planarized insulating layer 120 may have a substantially flat upper surface. The planarized insulating layer 120 may include one insulating layer or a plurality of stacked insulating layers. The interlayer insulating layers 130, 140, 150, 160, and 170 may be sequentially stacked on the planarized insulating layer 120. The interlayer insulating layers 130, 140, 150, 160, and 170 may include insulating materials such as silicon oxide or silicon nitride.

[0151] The unit contact plugs CPLG may pass through the first interlayer insulating layer 130 and the second interlayer insulating layer 140 and the planarized insulating layer 120, and are respectively connected to the pad portions of the gate patterns EGE, GSE1, GSE2, and CGE. The vertical lengths of the unit contact plugs CPLG may decrease as they become closer to the cell array region CAR. The top surfaces of the unit contact plugs CPLG may be substantially coplanar.

[0152] The input / output contact plugs IOPLG may pass through the first interlayer insulating layer 130 and the second interlayer insulating layer 140 and the planarized insulating layer 120, and are connected to the pad conductive pattern LP. The input / output contact plugs IOPLG may be electrically connected to the input / output pads IOPAD through the pad conductive pattern LP.

[0153] The bit line BL can be disposed on the second interlayer insulating layer 140 in the cell array region CAR and can extend across the stacked structure ST in the second direction D2. The bit line BL can be electrically connected to the vertical channel structure VS through the lower bit line contact plug BCTa.

[0154] The first upper conductive line UCLa and the second upper conductive line UCLb can be disposed in the fourth interlayer insulating layer 160. The first upper conductive line UCLa can be electrically connected to the bit line BL in the cell array region CAR. The second upper conductive line UCLb can be electrically connected to the lower conductive line in the connection region CNR.

[0155] The first bonding pad BP1 can be disposed in the uppermost interlayer insulating layer 170. The first bonding pad BP1 can be electrically connected to the first upper conductive line UCLa and the second upper conductive line UCLb. The first bonding pad BP1 can be formed of aluminum, copper, or tungsten.

[0156] The peripheral circuit structure PS can be formed on the semiconductor substrate 20 and can include a peripheral circuit PTR that controls the memory cell array, and peripheral interlayer insulating layers 210 and 220 that cover the peripheral circuit PTR. The peripheral circuit PTR can be integrated on the top surface of the semiconductor substrate 20. The surface insulating layer 201 can be disposed on the back surface of the semiconductor substrate 20.

[0157] The peripheral circuit PTR can be a row decoder and a column decoder, a page buffer, and a control circuit. Specifically, the peripheral circuit PTR can include NMOS transistors and PMOS transistors. The peripheral circuit line PLP can be electrically connected to the peripheral circuit PTR through the peripheral contact plug PCP.

[0158] The peripheral interlayer insulating layers 210 and 220 can be disposed on the top surface of the semiconductor substrate 20. The peripheral interlayer insulating layers 210 and 220 can cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit line PLP on the semiconductor substrate 20. The peripheral contact plug PCP and the peripheral circuit line PLP can be electrically connected to the peripheral circuit PTR. The peripheral interlayer insulating layers 210 and 220 can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer.

[0159] The second bonding pad BP2 can be disposed in the uppermost peripheral interlayer insulating layer 220 corresponding to the first bonding pad BP1. The second bonding pad BP2 can be electrically connected to the peripheral circuit PTR through the peripheral circuit line PLP and the peripheral contact plug PCP.

[0160] The second bonding pad BP2 can be electrically connected and physically connected to the first bonding pad BP1 by a bonding method. That is, the second bonding pad BP2 can directly contact the first bonding pad BP1.

[0161] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The second bonding pad BP2 may have the same or substantially the same shape, the same width, or the same area as the first bonding pad BP1.

[0162] The input / output pads IOPAD may be disposed on a lower surface of the insulating layer 110 of the cell array structure CS. The capping insulating layer 310 may be disposed on a lower surface of the lower insulating layer 110, and the capping insulating layer 310 may cover the input / output pads IOPAD.

[0163] The protective layer 320 and the passivation layer 330 may be sequentially formed on the entire surface of the capping insulating layer 310. For example, the protective layer 320 may be a silicon nitride layer or a silicon oxynitride layer. For example, the passivation layer 330 may be a polyimide-based material such as photosensitive polyimide (PSPI).

[0164] The protection layer 320 and the passivation layer 330 may have a pad opening OP exposing a portion of the input / output pad IOPAD.

[0165] Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A is a diagram for explaining a method of manufacturing a semiconductor device according to some example embodiments and shows a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line AA'. Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B is a diagram for explaining a method of manufacturing a semiconductor device according to some example embodiments, and shows a method of manufacturing a semiconductor device along the Figure 5 A cross section taken along line BB'. Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C and Figure 18C is a diagram for explaining a method of manufacturing a semiconductor device according to some example embodiments and shows a method of manufacturing a semiconductor device along the Figure 5 The cross section is taken along the line CC'.

[0166] Reference Figure 5 , Figure 12A , Figure 12B and Figure 12C , the peripheral circuit structure PS may be formed on the semiconductor substrate 10 .

[0167] The formation of the peripheral circuit structure PS may include: forming a peripheral circuit PTR on a semiconductor substrate 10; forming a peripheral interconnect structure PCP and PLP connected to the peripheral circuit PTR; and forming a lower insulating layer 50.

[0168] A row decoder, a column decoder, a page buffer, and a control circuit may be formed on the semiconductor substrate 10 as the peripheral circuit PTR. Here, the peripheral circuit PTR may include MOS transistors using the semiconductor substrate 10 as a channel.

[0169] The lower insulating layer 50 may include one insulating layer or a plurality of stacked insulating layers covering the peripheral circuit PTR. The lower insulating layer 50 may include a first lower insulating layer 51, a second lower insulating layer 55, and an etch stop layer 53 between the first lower insulating layer 51 and the second lower insulating layer 55. For example, the lower insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer.

[0170] The formation of the peripheral interconnect structure may include: forming a peripheral contact plug PCP passing through some portions of the lower insulating layer 50; and forming a peripheral circuit line PLP connected to the peripheral contact plug PCP.

[0171] A semiconductor layer 100 may be formed on the peripheral circuit structure PS. The semiconductor layer 100 may be formed by depositing a semiconductor material. The semiconductor layer 100 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The semiconductor layer 100 may include a doped semiconductor and / or an undoped intrinsic semiconductor. The semiconductor layer 100 may have a crystal structure including a single crystal structure, an amorphous structure, or a polycrystalline structure.

[0172] A first insulating layer 101, a second insulating layer 103, and a third insulating layer 105 may be sequentially stacked on the semiconductor layer 100. The first insulating layer 101 may be formed by thermally oxidizing the surface of the semiconductor layer 100 or by depositing a silicon oxide layer. The second insulating layer 103 may be formed of a material having an etching selectivity with respect to the first insulating layer 101 and the third insulating layer 105. As an example, the second insulating layer 103 may be at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, or a silicon germanium layer. The third insulating layer 105 may be formed by depositing a silicon oxide layer.

[0173] The support conductive pattern SP can be deposited on the third insulating layer 105 to have a uniform thickness. The support conductive pattern SP can fill the openings of the first insulating layer 101, the second insulating layer 103, and the third insulating layer 105 in the cell array region CAR. The support conductive pattern SP can be in direct contact with the semiconductor layer 100 in the opening. The support conductive pattern SP can be a polysilicon layer doped with an n-type dopant and / or carbon (C).

[0174] The molding structure ML can be formed on the support conductive pattern SP. The molding structure ML can include interlayer insulating layers ILD stacked vertically in an alternating manner, and a first sacrificial layer SL1 and a second sacrificial layer SL2.

[0175] In the molding structure ML, the first sacrificial layer SL1 and the second sacrificial layer SL2 can be formed of a material that can be etched with an etching selectivity relative to the insulating layer ILD. For example, the first sacrificial layer SL1 and the second sacrificial layer SL2 can be formed of an insulating material different from the interlayer insulating layer ILD. For example, the first sacrificial layer SL1 and the second sacrificial layer SL2 can be formed of a silicon nitride layer, and the interlayer insulating layer ILD can be formed of a silicon oxide layer. The second sacrificial layer SL2 is disposed vertically adjacent to the first sacrificial layer SL1 and is a layer that will be replaced by a first selected gate pattern and a second selected gate pattern in a subsequent manufacturing process.

[0176] For example, the first sacrificial layer SL1 and the second sacrificial layer SL2 can be formed of the same material, but the second sacrificial layer SL2 can be deposited thicker than the first sacrificial layer SL1. As another example, the second sacrificial layer SL2 can have the same or substantially the same thickness as the first sacrificial layer SL1, but can be formed of a material with a different etching selectivity. As another example, the thickness of the second sacrificial layer SL2 can be less than the thickness of each of the first sacrificial layer SL1. For example, in an isotropic etching process for removing the first sacrificial layer SL1 and the second sacrificial layer SL2, the etching rate of the second sacrificial layer SL2 can be greater than the etching rate of the first sacrificial layer SL1.

[0177] The interlayer insulating layer ILD, and the first sacrificial layer SL1 and the second sacrificial layer SL2 can be deposited by using a thermal chemical vapor deposition (thermal CVD), plasma enhanced chemical vapor deposition (CVD), physical chemical vapor deposition (physical CVD), or atomic layer deposition (ALD) process. The interlayer insulating layer ILD, and the first sacrificial layer SL1 and the second sacrificial layer SL2 can be deposited in-situ. In an embodiment, the interlayer insulating layer ILD has the same or substantially the same thickness and can be deposited alternately with the first sacrificial layer SL1 and the second sacrificial layer SL2.

[0178] After forming the molding structure ML, a vertical channel structure VS can be formed in the cell array region CAR (for example, see Figure 5 and Figure 6D), and after forming the vertical channel structure VS, a first interlayer insulating layer 130 may be formed to cover the upper surface of the vertical channel structure VS.

[0179] Referring to Figure 5 , Figure 12A , Figure 12B and Figure 12C , a first dummy hole DH1 and a second dummy hole DH2 may be formed in the connection region CNR.

[0180] The formation of the first dummy hole DH1 and the second dummy hole DH2 may include: forming a mask pattern (not shown) on the first interlayer insulating layer 130; and anisotropically etching the molded structure ML using the mask pattern (not shown) as an etching mask to expose the support conductive pattern SP.

[0181] The first dummy hole DH1 may be formed at regular intervals in the connection region CNR in the first direction D1. The second dummy hole DH2 may be formed to be spaced apart from the first dummy hole DH1 in the connection region CNR, and may be arranged in a zigzag pattern or in a honeycomb shape in the first direction D1 when viewed in a plan view.

[0182] Referring to Figure 5 , Figure 13A , Figure 13B and Figure 13C , some portions of the first sacrificial layer SL1 and the second sacrificial layer SL2 exposed to the first dummy hole DH1 and the second dummy hole DH2 may be isotropically etched. The isotropic etching process may use an etching recipe having an etching selectivity with respect to the interlayer insulating layer ILD. Accordingly, a part of the first sacrificial layer SL1 exposed to the first dummy hole DH1 and the second dummy hole DH2 may be etched to form a first recessed region R1, and a part of the second sacrificial layer SL2 exposed to the first dummy hole DH1 and the second dummy hole DH2 may be etched to form a second recessed region R2.

[0183] Since the thickness of the second sacrificial layer SL2 is greater than the thickness of the first sacrificial layer SL1, in the process of isotropically etching the first sacrificial layer SL1 and the second sacrificial layer SL2, the etching rate of the second sacrificial layer SL2 may be greater than the etching rate of the first sacrificial layer SC1. Accordingly, in the horizontal direction, the etching depth of the second recessed region R2 may be greater than the etching depth of the first recessed region R1. In addition, when the first sacrificial layer SL1 and the second sacrificial layer SL2 are isotropically etched, the second recessed regions R2 in the first dummy holes DH1 adjacent to each other in the first direction D1 may be connected to each other in the first direction D1.

[0184] As another example, when the thickness of the second sacrificial layer SL2 is less than the thickness of the first sacrificial layer SL1, the etching depth of the second recessed region R2 may be less than the etching depth of the first recessed region R1.

[0185] Referring to Figure 5 、 Figure 14A 、 Figure 14B and Figure 14C ,a third sacrificial layer 111 can be formed to cover the first recessed area R1, the second recessed area R2, the first dummy hole DH1, and the second dummy hole DH2 with a uniform thickness. The third sacrificial layer 111 can be formed of an insulating material having an etching selectivity with respect to the interlayer insulating layer ILD. The third sacrificial layer 111 can include the same material as the first sacrificial layer SL1 and the second sacrificial layer SL2. For example, the third sacrificial layer 111 can be a silicon nitride layer.

[0186] The thickness of the third sacrificial layer 111 can be less than half of the diameter of the first dummy hole DH1 and the second dummy hole DH2. The third sacrificial layer 111 can completely fill the first recessed area R1 and cover the inner wall of the second recessed area R2 with a substantially uniform thickness.

[0187] As another example, when the thickness of the second sacrificial layer SL2 is less than the thickness of the first sacrificial layer SL1, the third sacrificial layer 111 can be formed of the same insulating material as the interlayer insulating layer ILD (e.g., silicon oxide), and the third sacrificial layer 111 can completely fill the second recessed area R2 and cover the inner wall of the first recessed area R1 with a substantially uniform thickness.

[0188] Referring to Figure 5 、 Figure 15A 、 Figure 15B and Figure 15C ,an etching process is performed on the third sacrificial layer 111 to locally form a third sacrificial pattern 113 in the first recessed area R1.

[0189] The formation of the third sacrificial pattern 113 can include performing an isotropic etching process on the third sacrificial layer 111 to expose the sidewalls of the interlayer insulating layer ILD in the first dummy hole DH1 and the second dummy hole DH2. As the isotropic etching process is performed on the third sacrificial layer 111, the third sacrificial layer 111 can be removed from the second recessed area R2 and the sidewalls of the second sacrificial layer SL2 can be exposed again.

[0190] As another example, when the thickness of the second sacrificial layer SL2 is less than the thickness of the first sacrificial layer SL1, the third sacrificial layer 111 formed of silicon oxide can be removed from the first recessed area R1 to expose the sidewalls of the first sacrificial layer SL1 again, and then the third sacrificial pattern 113 can be locally formed in the first recessed area R1.

[0191] Referring to Figure 5 、 Figure 16A 、 Figure 16B and Figure 16C, after forming the third sacrificial pattern 113, a first dummy vertical structure DP1 and a second dummy vertical structure DP2 may be formed to fill the second recessed area R2 and the first dummy hole DH1 and the second dummy hole DH2.

[0192] The formation of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include: depositing an insulating material having an etching selectivity with respect to the first sacrificial layer SL1 and the third sacrificial pattern 113 in the second recessed area R2 and in the first dummy hole DH1 and the second dummy hole DH2; and performing a planarization process to expose the top surface of the first interlayer insulating layer 130. For example, the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer. An air gap may be formed while depositing the insulating material in the second recessed area R2 and the first dummy hole DH1 and the second dummy hole DH2. That is, the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may have an air gap in the first dummy hole DH1 and the second dummy hole DH2.

[0193] The first dummy vertical structure DP1 and the second dummy vertical structure DP2 may completely fill the second recessed area R2. The first dummy vertical structures DP1 adjacent to each other may be horizontally connected to each other at the same level as the second sacrificial layer SL. Each of the first dummy vertical structure DP1 and the second dummy vertical structure DP2 may include vertical portions P1a and P1b filled in the first dummy hole DH1 and the second dummy hole DH2 and extending portions P2a and P2b filled in the second recessed area R2.

[0194] Referring to Figure 5 、 Figure 17A 、 Figure 17B and Figure 17C , a first isolation trench T1 and a second isolation trench T2 may be formed through the molding structure to expose the support semiconductor pattern SP. The formation of the first isolation trench T1 and the second isolation trench T2 may include anisotropically etching the first interlayer insulating layer 130 and the molding structure ML, and the support semiconductor pattern SP may be used as an etch stop layer in the anisotropic etching process.

[0195] The first isolation trench T1 and the second isolation trench T2 may extend from the cell array region CAR to the connection region CNR in the first direction D1. The second isolation trench T2 may be shorter than the first isolation trench T1 in the first direction D1.

[0196] The first isolation trench T1 may continuously extend from the cell array region CAR to the connection region CNR in the first direction D1 and may be spaced apart from each other in the second direction D2.

[0197] The second isolation trench T2 may pass through the molded structure between the first isolation trenches T1 adjacent to each other in the second direction D2. The second isolation trench T2 may extend in the first direction D1 in the cell array region CAR and may be formed at a specific distance from the connection region CNR in the first direction D1.

[0198] The second isolation trench T2 may be formed in the first direction D1 while specific first dummy vertical structures DP1 are interposed between the second isolation trenches T2. The second isolation trench T2 may expose the extended portions P2a and P2b of the first dummy vertical structure DP1 and the second dummy vertical structure DP2.

[0199] Next, the first sacrificial layer SL1 and the second sacrificial layer SL2 and the third sacrificial pattern 113 exposed in the first isolation trench T1 and the second isolation trench T2 may be removed to form a first gate region G1 and a second gate region G2. The first gate region G1 and the second gate region G2 may be formed by isotropically etching the sacrificial layers using an etchant having an etching selectivity with respect to the interlayer insulating layer ILD, the vertical channel structure VS, and the first dummy vertical structure DP1 and the second dummy vertical structure DP2. Here, the first sacrificial layer SL1 and the second sacrificial layer SL2 and the third sacrificial pattern 113 may be completely removed through an isotropic etching process.

[0200] The first gate region G1 may expose the sidewalls of the vertical portions of the first dummy vertical structure DP1 and the second dummy vertical structure DP2, and the second gate region G2 may expose the sidewalls of the extended portions of the first dummy vertical structure DP1 and the second dummy vertical structure DP2. In the second direction D2, the extended portion of the first dummy vertical structure DP1 may be disposed between the second gate regions G2.

[0201] Refer to Figure 5 、 Figure 18A 、 Figure 18B and Figure 18C ,gate patterns EGE, GSE1, GSE2, and CGE may be formed in the first gate region G1 and the second gate region G2.

[0202] The formation of the gate patterns EGE, GSE1, GSE2, and CGE may include: filling the first gate region G1 and the second gate region G2; depositing a metal layer to conformally cover the inner walls of the first isolation trench T1 and the second isolation trench T2; and isotropically etching the metal layer to expose the sidewalls of the interlayer insulating layer ILD in the first isolation trench T1 and the second isolation trench T2. Accordingly, an erase control gate pattern EGE and a cell gate pattern CGE may be formed in the first gate region G1, and a first select gate pattern GSE1 and a second select gate pattern GSE2 may be formed in the second gate region G2.

[0203] Meanwhile, before forming the gate patterns EGE, GSE1, GSE2, and CGE, a process of replacing the first insulating layer 101, the second insulating layer 103, and the third insulating layer 105 with the source conductive pattern SC may be performed in the cell array region CAR.

[0204] After forming the gate patterns EGE, GSE1, GSE2, and CGE, referring to Figures 6A to 6D , insulating materials are buried in the first isolation trench T1 and the second isolation trench T2 to form the first separation structure SS1 and the second separation structure SS2. Then, the bit line BL and the through contact plug TPLG may be formed.

[0205] According to some example embodiments of the present disclosure, in a stacked structure including alternately stacked gate patterns and interlayer insulating layers, the ground select gate patterns may be separated from each other by dummy vertical structures and separation structures without horizontally patterning the ground select gate patterns.

[0206] The interlayer insulating layers in the stacked structure may be deposited to have substantially the same thickness, thereby simplifying the manufacturing process of the semiconductor device.

[0207] Although the embodiments have been described above, those skilled in the art will understand that many modifications and changes can be made without departing from the spirit and scope of the inventive concept defined in the claims. Therefore, the example embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, and the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a cell array region and a connection region; a plurality of ground selection gate patterns, wherein each of the ground selection gate patterns is spaced apart from each other and disposed at the same level as each other with respect to a top surface of the substrate; a plurality of unit gate patterns vertically stacked on the plurality of ground selection gate patterns; a plurality of separation structures, wherein each separation structure vertically extends into the plurality of unit gate patterns and is disposed between corresponding ground selection gate patterns among the plurality of ground selection gate patterns and is spaced apart from each other in the first direction in the connection region; as well as a plurality of dummy vertical structures disposed between first and second separation structures adjacent to each other along the first direction and between a first ground selection gate pattern of the plurality of ground selection gate patterns and a second ground selection gate pattern adjacent to the first ground selection gate pattern, Wherein, each of the plurality of dummy vertical structures comprises: a vertical portion vertically extending into the plurality of cell gate patterns; and an extending portion horizontally protruding from the vertical portion at the same level as the plurality of ground selection gate patterns, and The extending portion of each of the plurality of dummy vertical structures is connected to each other and in contact with the first and second separation structures.

2. The semiconductor device according to claim 1, wherein Each of the plurality of unit gate patterns has a first thickness in a vertical direction, and each of the plurality of ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness.

3. The semiconductor device according to claim 1, wherein Each of the plurality of unit gate patterns has a first thickness in a vertical direction, and each of the plurality of ground selection gate patterns has a second thickness in the vertical direction that is equal to the first thickness.

4. The semiconductor device according to claim 1, wherein A thickness of the extending portion of each of the plurality of dummy vertical structures in a vertical direction is equal to a thickness of the plurality of ground selection gate patterns in the vertical direction.

5. The semiconductor device according to claim 1, wherein A distance between a first cell gate pattern and a second cell gate pattern vertically adjacent to the first cell gate pattern is equal to a distance between the first cell gate pattern and a ground selection gate pattern vertically adjacent to the first cell gate pattern.

6. The semiconductor device according to claim 1, wherein A distance between the first separated structure and the second separated structure in the first direction is greater than a sum of diameters of the vertical portions of the plurality of dummy vertical structures.

7. The semiconductor device according to claim 1, wherein The plurality of cell gate patterns surround the vertical portion of the dummy vertical structure in the connection region.

8. The semiconductor device according to claim 1, wherein The plurality of unit gate patterns overlap the extending portion of each of the plurality of dummy vertical structures.

9. The semiconductor device according to claim 1, wherein: Sidewalls of the plurality of ground selection gate patterns contact the extending portion of each of the plurality of separation structures and the plurality of dummy vertical structures.

10. The semiconductor device according to claim 1, wherein The plurality of dummy vertical structures are formed of an insulating material.

11. The semiconductor device according to claim 1, wherein Each of the plurality of dummy vertical structures further includes a cell extension portion, wherein each cell extension portion horizontally protrudes from the vertical portion at the same level as a corresponding cell gate pattern, and Wherein, a diameter of the unit extension portion is smaller than a diameter of the extension portion of each of the plurality of dummy vertical structures.

12. A semiconductor device comprising: a substrate including a cell array region and a connection region; a first separation structure extending in a first direction parallel to a top surface of the substrate; a stacked structure disposed between first separation structures adjacent in a second direction perpendicular to the first direction, and comprising gate patterns and interlayer insulating layers vertically alternately stacked on the substrate, the gate patterns comprising a plurality of ground selection gate patterns and a plurality of unit gate patterns, wherein each of the ground selection gate patterns is spaced apart from each other at the same horizontal height from the top surface of the substrate, and the plurality of unit gate patterns are vertically stacked on the plurality of ground selection gate patterns; a second separation structure extending into the plurality of unit gate patterns and disposed between the plurality of ground selection gate patterns adjacent in the second direction and spaced apart from each other in the connection region in the first direction; a first dummy vertical structure disposed between the second separation structures adjacent to each other in the first direction and between the plurality of ground selection gate patterns adjacent to each other in the second direction; as well as a second dummy vertical structure extending into the stacked structure in the connection area, wherein each of the first dummy vertical structure and the second dummy vertical structure includes a vertical portion vertically extending into the plurality of unit gate patterns and an extending portion horizontally protruding from the vertical portion at the same level as the plurality of ground selection gate patterns, and Wherein, each extending portion of the first dummy vertical structure is connected to each other and contacts the second separation structures adjacent to each other in the first direction.

13. The semiconductor device according to claim 12, wherein: Each of the plurality of unit gate patterns has a first thickness in a vertical direction, and each of the plurality of ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness.

14. The semiconductor device according to claim 12, wherein: A thickness of each extending portion of the first dummy vertical structure in a vertical direction is the same as a thickness of the plurality of ground selection gate patterns in the vertical direction.

15. The semiconductor device according to claim 12, wherein: The plurality of unit gate patterns surround the vertical portions of the first and second dummy vertical structures.

16. The semiconductor device according to claim 12, wherein: The plurality of ground selection gate patterns surround each extending portion of the second dummy vertical structure.

17. The semiconductor device according to claim 12, wherein: A diameter of the vertical portion of the first dummy vertical structure is equal to a diameter of the vertical portion of the second dummy vertical structure.

18. The semiconductor device according to claim 12, wherein: The first dummy vertical structure and the second dummy vertical structure are formed of an insulating material.

19. The semiconductor device according to claim 12, further comprising: a through contact plug connected to pad portions of the plurality of cell gate patterns in the connection region, Each of the second dummy vertical structures is disposed around a corresponding through contact plug.

20. An electrical system comprising: A semiconductor device, comprising: a substrate having a cell array region and a connection region; a plurality of ground selection gate patterns, wherein each ground selection gate pattern is spaced apart from each other and disposed at the same horizontal height from a top surface of the substrate; a plurality of cell gate patterns vertically stacked on the plurality of ground selection gate patterns; a separation structure vertically extending into the plurality of cell gate patterns and disposed between adjacent ground selection gate patterns among the plurality of ground selection gate patterns and spaced apart from each other in the connection region in a first direction; and a dummy vertical structure between adjacent separation structures and between the adjacent ground selection gate patterns; and an input / output pad electrically connected to a peripheral circuit; and a controller which is electrically connected to the semiconductor device through the input / output pad and controls the semiconductor device, Wherein, each of the virtual vertical structures comprises: a vertical portion vertically extending into the plurality of cell gate patterns; and an extending portion horizontally protruding from the vertical portion at the same level as the plurality of ground selection gate patterns, and The extending portion of each of the dummy vertical structures is connected to each other and contacts the separation structure adjacent in the first direction.

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