Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device may include: a plurality of gate lines including a first gate line and a second gate line arranged over the first gate line; a plurality of insulating layers disposed between the plurality of gate lines, respectively; a plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to the upper surface of the substrate; and a separation pattern overlapping at least a portion of the plurality of channel structures in the vertical direction. The separation pattern may penetrate at least a portion of the second gate line and at least a portion of a first channel structure of the plurality of channel structures. The first channel structure may overlap the separation pattern in the vertical direction. The second gate line may be fully filled with a conductive material.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2023 - 0197641, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a semiconductor device and an electronic system including the semiconductor device. More particularly, the present inventive concept relates to a semiconductor device including a non - volatile vertical memory device and an electronic system including such a semiconductor device. Background art

[0004] Semiconductor devices capable of storing high - volume data have become increasingly important in electronic systems that require data storage. Accordingly, schemes for increasing the data storage capacity of semiconductor devices have been studied. For example, one method proposed for increasing the data storage capacity is a vertical memory device including memory cells arranged in a three - dimensional manner rather than a two - dimensional manner. Summary of the invention

[0005] The present inventive concept provides a semiconductor device having improved electrical characteristics and operational reliability, a method of forming the semiconductor device, and an electronic system including the semiconductor device.

[0006] According to some aspects of the present inventive concept, there is provided a semiconductor device including:

[0007] A plurality of gate lines including a first gate line disposed above a substrate and a second gate line disposed above the first gate line; a plurality of insulating layers respectively disposed between the plurality of gate lines;

[0008] A plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; and a separation pattern overlapping at least a portion of the plurality of channel structures in the vertical direction. The separation pattern may penetrate at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, and the first channel structure among the plurality of channel structures overlaps the separation pattern in the vertical direction. The second gate line may be completely filled with a conductive material.

[0009] According to some aspects of the inventive concept, there is provided a semiconductor device including: a peripheral circuit structure including a substrate, a peripheral circuit disposed above the substrate, and a peripheral circuit line structure connected to the peripheral circuit; a common source plate disposed above the peripheral circuit structure; a plurality of gate lines including a first gate line disposed above the common source plate and a second gate line disposed above the first gate line; a plurality of insulating layers respectively disposed between the plurality of gate lines; a plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; a first isolation pattern horizontally spaced apart from the plurality of channel structures and penetrating the plurality of gate lines in the vertical direction; and a second isolation pattern horizontally spaced apart from the first isolation pattern and overlapping at least a portion of the plurality of channel structures in the vertical direction. The second isolation pattern may penetrate at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, and the first channel structure overlaps the second isolation pattern in the vertical direction. The second gate line may be completely filled with a conductive material.

[0010] According to some aspects of the inventive concept, there is provided an electronic system including: a main board, a semiconductor device above the main board, and a controller electrically connected to the semiconductor device. The semiconductor device includes: a plurality of gate lines including a first gate line disposed above a substrate and a second gate line disposed above the first gate line; a plurality of insulating layers respectively disposed between the plurality of gate lines; a plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; and an isolation pattern overlapping at least a portion of the plurality of channel structures in the vertical direction. The isolation pattern may penetrate at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, and the first channel structure overlaps the isolation pattern in the vertical direction. The second gate line may be completely filled with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in the

[0012] drawings:

[0013] Figure 1 is a block diagram showing a semiconductor device according to some embodiments;

[0014] Figure 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to some embodiments;

[0015] Figure 3 is a perspective view schematically showing a semiconductor device according to some embodiments;

[0016] Figure 4 is a planar layout view schematically showing a semiconductor device according to some embodiments;

[0017] Figure 5 is a cross-sectional view of a semiconductor device taken along line A-A' of Figure 4 ;

[0018] Figure 6 is a cross-sectional view of a semiconductor device taken along line B-B' of Figure 4 ;

[0019] Figure 7 is an enlarged cross-sectional view of region EX1 of Figure 5 ;

[0020] Figure 8 is an enlarged cross-sectional view of region EX2 of Figure 6 ;

[0021] Figure 9 is an enlarged cross-sectional view of a region corresponding to region EX2 of Figure 6 ;

[0022] Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15 , Figure 16A , Figure 16B , Figure 17A and Figure 17B are cross-sectional views for describing a method of manufacturing a semiconductor device according to some embodiments;

[0023] Figure 18 is a diagram schematically showing an electronic system including a semiconductor device according to some embodiments;

[0024] Figure 19 is a perspective view schematically showing an electronic system including a semiconductor device according to some embodiments; and

[0025] Figure 20 is a cross-sectional view schematically showing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, some examples of embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In this document, like reference numerals will denote like elements, and redundant descriptions thereof may be omitted for simplicity.

[0027] Figure 1 is a block diagram showing a semiconductor device 10 according to some embodiments.

[0028] Referring to Figure 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 may include a plurality of memory cell blocks BLK1, BLK2, …, BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, …, BLKn may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, …, BLKn may be connected to the peripheral circuit 30 through a plurality of bit lines BL, a plurality of word lines WL, a plurality of string selection lines SSL, and a plurality of ground selection lines GSL.

[0029] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output circuit 36, and a control logic 38. Although Figure 1 not shown in , the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

[0030] The memory cell array 20 may be connected to the page buffer 34 through a plurality of bit lines BL, and may be connected to the row decoder 32 through a plurality of word lines WL, a plurality of string selection lines SSL, and a plurality of ground selection lines GSL. In the memory cell array 20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, …, BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of word lines WL vertically stacked above the substrate.

[0031] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from a device (not shown) external to the semiconductor device 10, and may transmit / receive data DATA to / from a device (or another device) external to the semiconductor device 10.

[0032] The row decoder 32 may select at least one of the plurality of memory cell blocks BLK1, BLK2, …, BLKn in response to an address ADDR from the outside, and select the word lines WL, string selection lines SSL, and ground selection lines GSL of the selected memory cell block. The row decoder 32 may send a voltage for performing a memory operation to the word lines WL of the selected memory cell block.

[0033] The page buffer 34 can be connected to the memory cell array 20 through a plurality of bit lines BL. The page buffer 34 can operate as a write driver in a programming operation to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit lines BL, and can operate as a sense amplifier in a read operation to read out the data DATA stored in the memory cell array 20.

[0034] The data input / output circuit 36 can be connected to the page buffer 34 through a plurality of data lines DLs. In a programming operation, the data input / output circuit 36 can receive the data DATA from a memory controller (not shown), and provide the programming data DATA to the page buffer 34 based on the column address C_ADDR received from the control logic 38. In a read operation, the data input / output circuit 36 can provide the read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR received from the control logic 38.

[0035] The data input / output circuit 36 can send an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0036] The control logic 38 can receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 can provide the row address R_ADDR to the row decoder 32, and can provide the column address C_ADDR to the data input / output circuit 36. The control logic 38 can generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, the control logic 38 can adjust the voltage levels provided to the plurality of word lines WL and the plurality of bit lines BL in a memory operation such as a programming operation or an erase operation.

[0037] Figure 2 is an equivalent circuit diagram of a memory cell array MCA of a semiconductor device according to some embodiments. Figure 2 The memory cell array MCA shown in Figure 1 can correspond to the memory cell array 20 described with reference to

[0038] With reference to Figure 2 the memory cell array MCA can include a plurality of memory cell strings MS. The memory cell array MCA can include a plurality of bit lines BL (BL1, BL2,..., BLm), a plurality of word lines WL (WL1, WL2,..., WLn-1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS can be formed between the plurality of bit lines BL (BL1, BL2,..., BLm) and the common source line CSL. Although Figure 2It is shown that each of the plurality of memory cell strings MS includes two string selection lines SSL, but the inventive concept of the present disclosure is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string selection line SSL.

[0039] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, …, MCn-1, MCn. The drain region of the string selection transistor SST may be connected to the bit lines BL (BL1, BL2, …, BLm), and the source region of the ground selection transistor GST may be connected to the common source line CSL. The common source line CSL may be a region to which the source regions of the plurality of ground selection transistors GST are commonly connected.

[0040] The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. The plurality of memory cell transistors MC1, MC2, …, MCn-1 and MCn may be respectively connected to a plurality of word lines WL (WL1, WL2, …, WLn-1, WLn).

[0041] Figure 3 is a perspective view schematically showing a semiconductor device 10 according to some embodiments.

[0042] The semiconductor device 10 may include a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction (Z direction). The cell array structure CS may include the memory cell array 20 described with reference to Figure 1 and the memory cell array MCA described with reference to Figure 2 and the peripheral circuit structure PS may include the peripheral circuit 30 described with reference to Figure 1 description.

[0043] The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, …, BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, …, BLKn may include three-dimensionally arranged memory cells.

[0044] Figure 4 is a plan layout view schematically showing a semiconductor device 100 according to some embodiments. Figure 5 is along Figure 4 The cross-sectional view taken along the line A-A' of.

[0045] Figure 6 is along Figure 4 The cross-sectional view taken along the line B-B' of. Figure 7 is Figure 5 The enlarged cross-sectional view of the region EX1 of. Figure 8 is Figure 6An enlarged cross-sectional view of the region EX2.

[0046] Referring to Figures 4 to 8 , the semiconductor device 100 may include a peripheral circuit structure PS and a cell array structure CS. The cell array structure CS is disposed above the peripheral circuit structure PS and overlaps the peripheral circuit structure PS in the vertical direction (Z direction).

[0047] The peripheral circuit structure PS may include a substrate 50, peripheral circuit transistors 60TR disposed on the substrate 50, and a peripheral circuit line structure 70 for connecting the peripheral circuit transistors 60TR to each other or connecting the peripheral circuit transistors 60TR to components in the cell array structure CS.

[0048] The substrate 50 may include a semiconductor material, for example, a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI oxide semiconductor. For example, the Group-IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate 50 may be provided as a bulk wafer or as an epitaxial layer. In some embodiments, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0049] A plurality of active regions AC may be defined in the substrate 50 by a device isolation layer 52. The device isolation layer 52 may be disposed in device isolation trenches (not shown) formed in the substrate 50. In some embodiments, the device isolation layer 52 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination of two or more of the above materials.

[0050] The peripheral circuit transistors 60TR may be formed above the plurality of active regions AC. The peripheral circuit transistors 60TR may include peripheral circuit gates 60G and source / drain regions 62 disposed in portions of the substrate on both sides of the peripheral circuit gates 60G. The peripheral circuit transistors 60TR may constitute a plurality of peripheral circuits included in the peripheral circuit structure PS. The plurality of peripheral circuits including the peripheral circuit transistors 60TR may include various circuits included in the peripheral circuit 30 described with reference to Figure 1 . For example, the plurality of peripheral circuits may include Figure 1 the row decoder 32, the page buffer 34, the data input / output circuit 36, and the control logic 38 shown in

[0051] The peripheral circuit line structure 70 may include a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit line layers 74. The plurality of peripheral circuit line layers 74 may have a multi-layer structure including a plurality of metal layers arranged at different vertical levels. At least some of the plurality of peripheral circuit line layers 74 may be configured to be electrically connected to the peripheral circuit transistors 60TR. The plurality of peripheral circuit contacts 72 may be configured to connect the peripheral circuit transistors 60TR to some of the plurality of peripheral circuit line layers 74 to each other.

[0052] The interlayer insulating layer 80 may be disposed on the substrate 50 and may cover the peripheral circuit transistors 60TR and the peripheral circuit line structure 70. The interlayer insulating layer 80 may include, for example, a silicon oxide layer, a silicon nitride layer, a SiON layer, a SiOCN layer, or any combination thereof.

[0053] The cell array structure CS may be disposed on the interlayer insulating layer 80. The cell array structure CS may include a memory cell region MEC and connection regions CON disposed on both sides of the memory cell region MEC in a first horizontal direction (X direction). A common source plate 110, a plurality of insulating layers 120, a plurality of gate lines 130, and a channel structure 140 may be disposed in the memory cell region MEC of the cell array structure CS, and a common source plate 110, a plurality of insulating layers 120, a plurality of gate lines 130, a plurality of gate pad portions PAD, and a first contact plug 170 may be disposed in the connection regions CON of the cell array structure CS.

[0054] The common source plate 110 may be used as a common source line CSL (see Figure 2 ), and may be configured to supply current to the vertical memory cells formed in the cell array structure CS. In some embodiments, the common source plate 110 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any mixture or combination thereof. In some embodiments, the common source plate 110 may include a semiconductor doped with a dopant. For example, the common source plate 110 may include polysilicon doped with an n-type dopant. In an embodiment, the common source plate 110 may have a crystal structure including at least one of a single crystal structure, an amorphous structure, and a polycrystalline structure.

[0055] The plurality of insulating layers 120 and the plurality of gate lines 130 may be alternately stacked on the common source plate 110 in a vertical direction (Z direction). Some of the plurality of insulating layers 120 may be disposed between the common source plate 110 and the bottommost gate line 130 and between adjacent gate lines 130 among the plurality of gate lines 130, and the uppermost insulating layer 120H among the plurality of insulating layers 120 may cover the uppermost gate line 130. Each of the plurality of insulating layers 120 may include, for example, silicon oxide.

[0056] A plurality of gate lines 130 may include a plurality of first gate lines 132 and a plurality of second gate lines 134. In this case, the first gate lines 132 may refer to the gate lines among the plurality of gate lines 130 that are not at least partially penetrated by the second isolation pattern SSLC, and the second gate lines 134 may refer to the gate lines among the plurality of gate lines 130 that are at least partially penetrated by the second isolation pattern SSLC. For example, as Figures 4 to 8 shown, when the second isolation pattern SSLC penetrates at least a portion of each of the two topmost gate lines among the plurality of gate lines 130, these two topmost gate lines may be referred to as the second gate lines 134, and the other gate lines except these two topmost gate lines may be referred to as the first gate lines 132.

[0057] As Figure 8 seen, the first gate line 132 may include a seam 132SM, which is an empty space and in which no conductive material exists. In the process of replacing a plurality of sacrificial layers 130S (see Figure 13C ) with a plurality of first gate lines 132 (see Figure 13C ) and a plurality of second gate lines 134S (see Figure 12A ), which will be described below with reference to Figure 13A , Figure 13B and Figure 13C , a seam 132SM in the first gate line 132 may be formed in the plurality of first gate lines 132. On the other hand, the second gate line 134 may not include a seam. That is, the second gate line 134 may be completely filled with a conductive material. This may be because, in the process described below with reference to Figure 14A , Figure 14B and Figure 15 , a seam 134SM (see Figure 14B ) formed in the plurality of second gate lines 134S (see Figure 14B ) is exposed through the second hole SSLCH, and the exposed seam 134SM may be filled with a conductive material.

[0058] In some embodiments, the first gate line 132 may include a single conductive material. The conductive material may include, for example, a metal (such as tungsten, nickel, cobalt, molybdenum, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, titanium nitride, tantalum nitride, tungsten nitride, or any combination of two or more thereof.

[0059] The second gate line 134 may include a first conductive material layer 134A and a second conductive material layer 134B. The first conductive material layer 134A may be a part of the second gate line 134 formed in the replacement process, which will be described below with reference to Figure 13A ,Figure 13B and Figure 13C described, and the second conductive material layer 134B may be other portions of the second gate line 134 formed in a process of filling seams 134SM (see Figure 14B ) exposed by the second hole SSLCH with a conductive material, which will be described below with reference to Figure 14A , Figure 14B and Figure 15 described. Accordingly, the interface where the first conductive material layer 134A and the second conductive material layer 134B contact each other may coincide with the surface of the seam 134SM (see Figure 14A , Figure 14B and Figure 15 ) exposed by the second hole SSLCH in the process described below with reference to Figure 14B . In some embodiments, the interface where the first conductive material layer 134A and the second conductive material layer 134B contact each other may have a shape that is rounded in a direction from the second conductive material layer 134B to the first conductive material layer 134A.

[0060] In some embodiments, the upper end portion of the second conductive material layer 134B may be located at a vertical level lower than the upper surface of the first conductive material layer 134A, and the lower end portion of the second conductive material layer 134B may be located at a vertical level higher than the lower surface of the first conductive material layer 134A. This may be because the second conductive material layer 134B can be formed by filling seams 134SM (see Figure 14A , Figure 14B and Figure 15 ) formed in the second gate line 134S (see Figure 14B ) with a conductive material in the process described below with reference to Figure 14B .

[0061] In some embodiments, each of the first conductive material layer 134A and the second conductive material layer 134B may include a metal (such as tungsten, nickel, cobalt, molybdenum, or tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide), doped polysilicon, titanium nitride, tantalum nitride, tungsten nitride, or any combination of two or more thereof.

[0062] In some embodiments, the first conductive material layer 134A may include the same material as the conductive material constituting the first gate line 132. For example, the first conductive material layer 134A and the first gate line 132 may include molybdenum.

[0063] In some embodiments, the first conductive material layer 134A and the second conductive material layer 134B may include the same conductive material. For example, each of the first conductive material layer 134A and the second conductive material layer 134B may include molybdenum.

[0064] In some embodiments, the first conductive material layer 134A and the second conductive material layer 134B may include different conductive materials. For example, the first conductive material layer 134A may include molybdenum, and the second conductive material layer 134B may include tungsten.

[0065] In some embodiments, a plurality of gate lines 130 may correspond to a ground selection line GSL (see Figure 2 ) that forms a memory cell string MS (see Figure 2 ), word lines WL (WL1, WL2, …, WLn-1, WLn) (see Figure 2 ), and at least one string selection line SSL (see Figure 2 ). For example, the bottommost gate line 130 may be used as the ground selection line GSL, the two topmost gate lines 130 may be used as the string selection lines SSL, and the other gate lines 130 (e.g., those between the bottommost and the two topmost gate lines 130) may be used as the word lines WL. Thus, a memory cell string MS in which a ground selection transistor GST (see Figure 2 ), a string selection transistor SST (see Figure 2 ), and memory cell transistors (MC1, MC2, …, MCn-1, MCn) (see Figure 2 ) therebetween are connected in series may be provided. In some embodiments, at least one of the gate lines 130 may be used as a pseudo word line; however, the inventive concept of the present disclosure is not limited thereto.

[0066] In some embodiments, the second gate line 134 may include the string selection line SSL (see Figure 2 ). For example, the two topmost second gate lines 134 may both be used as the string selection lines SSL, and a plurality of first gate lines 132 may be used as the word lines WL and the ground selection line GSL. In some embodiments, one of the two topmost second gate lines 134 may be used as the string selection line SSL, the other of the two topmost second gate lines 134 may be used as the word line WL, and a plurality of first gate lines 132 may be used as the word lines WL and the ground selection line GSL.

[0067] The first hole WLCH may extend in a vertical direction (Z direction) through the plurality of insulating layers 120 and the plurality of gate lines 130, and a plurality of first separation patterns WLC may be disposed in the first hole WLCH. The plurality of first separation patterns WLC may extend longitudinally or lengthwise in a first horizontal direction (X direction) in the memory cell region MEC and the connection region CON. The plurality of gate lines 130 between two adjacent first separation patterns WLC among the plurality of first separation patterns WLC may form a memory cell block BLK. The width of each of the plurality of gate lines 130 forming a memory cell block BLK in a second horizontal direction (Y direction) may be defined by the plurality of first separation patterns WLC.

[0068] Each of the plurality of first isolation patterns WLC may include an insulating structure. In some embodiments, the insulating structure may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. For example, the insulating structure may include a silicon oxide layer, a silicon nitride layer, a SiON layer, a SiOCN layer, a SiCN layer, or any combination of two or more thereof. In some embodiments, at least a portion of the insulating structure may include air gaps.

[0069] The second via SSLCH may extend in a vertical direction (Z direction) through at least a portion of the plurality of channel structures 140, at least a portion of the plurality of insulating layers 120, and the plurality of second gate lines 134 in a memory cell block BLK, and the second isolation pattern SSLC may be disposed in the second via SSLCH. The second isolation pattern SSLC may extend longitudinally or lengthwise in a first horizontal direction (X direction) in the memory cell region MEC. In another example, contrary to Figure 4 the illustration, the second isolation pattern SSLC may extend longitudinally or lengthwise in both the memory cell region MEC and the connection region CON in the first horizontal direction (X direction). The second isolation pattern SSLC may separate each of the plurality of second gate lines 134 in a second horizontal direction (Y direction). The second isolation pattern SSLC may overlap at least a portion of the plurality of channel structures 140 in the vertical direction (Z direction). Accordingly, at least a portion of the channel structures 140 among the plurality of channel structures 140 that overlap the second isolation pattern SSLC in the vertical direction (Z direction) may be removed by the second isolation pattern SSLC. A first sidewall of the second isolation pattern SSLC may contact the channel structure 140 penetrated by the second isolation pattern SSLC in the second horizontal direction (Y direction), and a second sidewall of the second isolation pattern SSLC opposite the first sidewall may contact the plurality of second gate lines 134 penetrated by the second isolation pattern SSLC.

[0070] Figures 4 to 8 The second isolation pattern SSLC is shown penetrating two topmost gate lines among the plurality of gate lines 130; however, the inventive concept of the present disclosure is not limited thereto. For example, the second isolation pattern SSLC may penetrate only one topmost gate line among the plurality of gate lines 130, or may penetrate three or more topmost gate lines among the plurality of gate lines 130. For example, when three topmost gate lines among the plurality of gate lines 130 are used as string select lines SSL, contrary to Figures 4 to 8Unlike the example in , the second isolation pattern SSLC may extend in the vertical direction (Z direction) to penetrate at least a portion of each of the three uppermost gate lines. In this case, the three uppermost gate lines penetrated by the second isolation pattern SSLC may be referred to as second gate lines 134, and the other gate lines except for the three uppermost gate lines may be referred to as first gate lines 132.

[0071] Figures 4 to 8 shows that the second isolation pattern SSLC has a linear shape extending in the first horizontal direction (X direction); however, the inventive concept of the present disclosure is not limited thereto. For example, unlike Figures 4 to 8 the illustration in , the second isolation pattern SSLC may have a zigzag shape extending in the first horizontal direction (X direction).

[0072] The second isolation pattern SSLC may be filled with an insulating layer. In some embodiments, the second isolation pattern SSLC may include an insulating layer including an oxide layer, a nitride layer, or a combination of two or more thereof. In some embodiments, at least a portion of the second isolation pattern SSLC may include an air gap.

[0073] Figures 4 to 8 shows that the upper surface of each of the first isolation pattern WLC and the second isolation pattern SSLC is located at the same vertical level as the upper surface of the uppermost insulating layer 120H; however, the inventive concept of the present disclosure is not limited thereto. For example, unlike Figures 4 to 8 the illustration in , the upper surface of each of the first isolation pattern WLC and the second isolation pattern SSLC may be located at the same vertical level as the upper surface of the first upper insulating layer 160. In this case, the second isolation pattern SSLC may extend in the vertical direction (Z direction) to the upper surface of the first upper insulating layer 160, and at least a portion of the bit line contact BLC disposed above the channel structure 140 penetrated by the second isolation pattern SSLC may be penetrated by the second isolation pattern SSLC.

[0074] A plurality of channel structures 140 may extend in the vertical direction (Z direction) from the upper surface of the common source electrode plate 110 through a plurality of insulating layers 120 and a plurality of gate lines 130. The plurality of channel structures 140 may be arranged such that they are spaced apart from each other at a certain distance in the first horizontal direction (X direction) and the second horizontal direction (Y direction). For example, the plurality of channel structures 140 may be arranged to be spaced apart from each other at a certain distance in the second horizontal direction (Y direction) between a pair of second isolation patterns SSLC spaced apart from each other in the second horizontal direction (Y direction). In this case, the number of channel structures 140 arranged in the second horizontal direction (Y direction) between a pair of second isolation patterns SSLC spaced apart from each other in the second horizontal direction (Y direction) may be 1, 2, or 4 or more.

[0075] Each of the plurality of channel structures 140 may include a gate insulating layer 142, a channel layer 144, a buried insulating layer 146, and a conductive plug 148 disposed in the channel hole 140T.

[0076] The gate insulating layer 142 and the channel layer 144 may be sequentially disposed on the sidewalls of the channel hole 140T. For example, the gate insulating layer 142 may be disposed on the sidewalls of the channel hole 140T and may be conformal therewith, and the channel layer 144 may be disposed on the sidewalls and the bottom surface of the channel hole 140T and may be conformal therewith.

[0077] As Figure 7 shown, the gate insulating layer 142 may include a tunneling dielectric layer 142A, a charge storage layer 142B, and a blocking dielectric layer 142C sequentially disposed on the outer wall of the channel layer 144. The relative thicknesses of the tunneling dielectric layer 142A, the charge storage layer 142B, and the blocking dielectric layer 142C that constitute the gate insulating layer 142 are not limited to Figure 7 those shown therein, and various modifications may be made.

[0078] The tunneling dielectric layer 142A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer 142B may be a region in which electrons that have passed through the tunneling dielectric layer 142A from the channel layer 144 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or doped polysilicon. The blocking dielectric layer 142C may include silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or any combination of two or more thereof.

[0079] The channel layer 144 may have a cylindrical shape. The channel layer 144 may include doped polysilicon or undoped polysilicon. In some embodiments, the channel layer 144 may be disposed to contact the upper surface of the common source electrode plate 110 at the bottom surface of the channel hole 140T. In an example, as Figure 7 shown, the bottom surface of the channel layer 144 may be disposed at a vertical level lower than the upper surface of the common source electrode plate 110; however, the inventive concept of the present disclosure is not limited thereto.

[0080] The buried insulating layer 146 may be in the internal space of the channel layer 144 (e.g., may fill the internal space). The buried insulating layer 146 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination of two or more thereof. In some embodiments, the buried insulating layer 146 may be omitted. In this case, the channel layer 144 may have a columnar shape without an internal space.

[0081] The conductive plug 148 may contact the channel layer 144 on the upper side of the channel hole 140T and may block the entrance of the channel hole 140T. The conductive plug 148 may include, for example, a doped polysilicon layer.

[0082] In some embodiments, the plurality of gate lines 130 may extend with a smaller length in the first horizontal direction X as they are farther from the upper surface of the common source electrode plate 110 (e.g., as the distance from the upper surface of the common source electrode plate 110 increases). That is, the plurality of gate lines 130 may have a stepped shape. In this case, the edge portions of the gate lines 130 arranged in a stepped shape may be referred to as gate pad portions PAD. However, the inventive concept of the present disclosure is not limited thereto; for example, Figure 5 different from the illustration in, each of the plurality of gate lines 130 may not have a gate pad portion PAD at its edge portion and may have a flat upper surface in the first horizontal direction (X direction). In this case, in the connection region CON, the first contact plug 170 may extend more in the vertical direction (Z direction) than Figure 5 the illustration in to contact the upper surface of one of the plurality of gate lines 130.

[0083] The covering insulating layer 150 may be disposed above the gate pad portion PAD, the first upper insulating layer 160 may be disposed above the uppermost insulating layer 120H and the covering insulating layer 150, and the second upper insulating layer 180 may be disposed above the first upper insulating layer 160. Each of the covering insulating layer 150, the first upper insulating layer 160, and the second upper insulating layer 180 may include an oxide layer, a nitride layer, or a combination thereof.

[0084] The first contact plug 170 penetrating the covering insulating layer 150 and the first upper insulating layer 160 in the vertical direction (Z direction) may be disposed in the connection region CON. The first contact plug 170 may be configured to be connected to one of the plurality of gate lines 130 selected. The first contact plug 170 may contact the gate pad portion PAD of the selected one of the gate lines 130 and may be connected to the selected one of the gate lines 130 through the gate pad portion PAD. The first contact plug 170 may include, for example, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or any combination of two or more thereof.

[0085] A second contact plug (not shown) that penetrates the cover insulating layer 150, the first upper insulating layer 160, and the common source electrode plate 110 in the vertical direction (Z direction) may be disposed in the connection region CON. The second contact plug may be configured to be connected to the peripheral circuit transistor 60TR through the peripheral circuit line layer 74. The second contact plug may include, for example, any one of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination of two or more thereof.

[0086] In the memory cell region MEC, the bit line contact BLC may penetrate the first upper insulating layer 160 and be connected to the channel structure 140. In the memory cell region MEC, the bit line BL may be disposed above the first upper insulating layer 160 and connected to the bit line contact BLC.

[0087] In the connection region CON, the first line ML may be disposed above the first upper insulating layer 160 and may be connected to the first contact plug 170. Further, in the connection region CON, a second line (not shown) connected to the second contact plug may be disposed above the first upper insulating layer 160.

[0088] The semiconductor device 100 according to an embodiment may include a first gate line 132 including a seam 132SM and a second gate line 134 not including a seam. In this case, in the manufacturing process of the semiconductor device 100, a part of the seam 134SM (see Figure 14B ) of the second gate line 134S (see Figure 14B ) may be removed by forming a second hole SSLCH, while other parts of the seam 134SM (see Figure 14B ) of the second gate line 134S (see Figure 14B ) that are not removed and remain may be filled with a conductive material via the second hole SSLCH without including a seam. Since the second gate line 134 does not include a seam, oxidation or loss of the conductive material constituting the second gate line 134 through the seam can be prevented in the subsequent manufacturing process of the semiconductor device 100. Therefore, the resistance of the second gate line 134 can be reduced, and a failure of the second gate line 134 can be prevented. Thus, the electrical characteristics and operation reliability of the semiconductor device 100 can be improved.

[0089] Figure 9 is an enlarged cross-sectional view showing a semiconductor device 100a according to some embodiments. In particular, Figure 9 is an enlarged cross-sectional view of a region of the semiconductor device 100a corresponding to the region EX2 of Figure 6 . Since the components of the semiconductor device 100a shown in Figure 9 are similar to the components of the semiconductor device 100 described with reference to Figures 4 to 8 , for the sake of brevity, the differences therebetween will be mainly described below.

[0090] Refer to Figure 9 , except that the second gate line 136 of the semiconductor device 100a may include an intermediate insulating layer 136L disposed between the first conductive material layer 136A and the second conductive material layer 136B, the semiconductor device 100a may have the same structure as Figures 4 to 8 the semiconductor device 100 shown in

[0091] The plurality of gate lines may include a first gate line 132 and a second gate line 136. The second gate line 136 of the semiconductor device 100a may include a first conductive material layer 136A, a second conductive material layer 136B, and an intermediate insulating layer 136L. Each of the first conductive material layer 136A and the second conductive material layer 136B of the second gate line 136 may be substantially the same as or similar to Figures 4 to 8 the first conductive material layer 134A and the second conductive material layer 134B of the second gate line 134 shown in

[0092] The intermediate insulating layer 136L may be disposed between the first conductive material layer 136A and the second conductive material layer 136B. The intermediate insulating layer 136L may be an oxide layer formed by an etching process for forming the second hole SSLCH (which will be described below with reference to Figure 14A and Figure 14B ) along the surface of the seam 134SM (see Figure 14B ), or may be a natural oxide layer formed along the surface of the seam 134SM (see Figure 14B ) after forming the second hole SSLCH and before forming the second conductive material layer 136B. Since the intermediate insulating layer 136L is formed along the surface of the seam 134SM (see Figure 14B ), the intermediate insulating layer 136L may have the same shape as the surface of the seam 134SM (see Figure 14B ). That is, the intermediate insulating layer 136L may have a rounded shape in the direction from the second conductive material layer 136B to the first conductive material layer 136A.

[0093] In some embodiments, the intermediate insulating layer 136L may be a metal oxide layer constituting the first conductive material layer 136A. For example, the first conductive material layer 136A may include molybdenum, and the intermediate insulating layer 136L may be a molybdenum oxide layer.

[0094] Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C ,Figure 14A , Figure 14B , Figure 15 , Figure 16A , Figure 16B , Figure 17A and Figure 17B are cross-sectional views for describing a method of manufacturing a semiconductor device (100) according to some embodiments. Specifically, Figure 10A , Figure 11 , Figure 12A , Figure 13A and Figure 17A are cross-sectional views taken along line A-A' of Figure 4 , Figure 10B , Figure 12B , Figure 13B , Figure 14A , Figure 16A and Figure 17B are cross-sectional views taken along line B-B' of Figure 4 , and Figure 13C , Figure 14B , Figure 15 and Figure 16B is an enlarged cross-sectional view of region EX2 of Figure 6 .

[0095] Referring to Figure 10A and Figure 10B , a peripheral circuit structure PS including a peripheral circuit transistor 60TR, a peripheral circuit line structure 70, and an interlayer insulating layer 80 disposed above a substrate 50 can be provided. Next, a common source plate 110 can be formed above the peripheral circuit structure PS, and a plurality of insulating layers 120 and a plurality of sacrificial layers 130S can be alternately formed one by one above the common source plate 110. For example, the plurality of insulating layers 120 can include silicon oxide layers, and the plurality of sacrificial layers 130S can include silicon nitride.

[0096] Referring to Figure 11 , in a connection region CON, by using a photolithography process to remove a part of each of the plurality of insulating layers 120 and the plurality of sacrificial layers 130S, each of the plurality of insulating layers 120 and the plurality of sacrificial layers 130S can have a stepped shape that extends in a first horizontal direction (X direction) with a smaller length as it is farther from the upper surface of the common source plate 110 (e.g., as the distance from the upper surface of the common source plate 110 increases). Next, a sacrificial pad portion PADS with an increased thickness can be formed at one end of each of the plurality of sacrificial layers 130S having the stepped shape.

[0097] In some embodiments, in order to form a sacrificial pad portion PADS on one end of each of the plurality of sacrificial layers 130S, a portion of the plurality of insulating layers 120 may be removed to expose one end of each of the plurality of sacrificial layers 130S. Then, an additional layer including a material the same as the constituent material of the plurality of sacrificial layers 130S may be deposited over the exposed one end of each of the plurality of sacrificial layers 130S, and the sacrificial pad portion PADS may be retained by patterning the additional layer.

[0098] In some embodiments, the process of forming the sacrificial pad portion PADS may be omitted. In this case, after performing the replacement process described below with reference to Figure 12A , Figure 12B , Figure 13A , Figure 13B and Figure 13C , each of the plurality of first gate lines 132 (see Figure 13A ) and the plurality of second gate lines 134S (see Figure 13A ) formed by replacing the plurality of sacrificial layers 130S may have a flat upper surface and no gate pad portion PAD (see Figure 13A ) at its edge portion.

[0099] Next, a covering insulating layer 150 covering the plurality of insulating layers 120 and the plurality of sacrificial layers 130S having a stepped shape may be formed, and the uppermost insulating layer 120H may be exposed by planarizing the covering insulating layer 150.

[0100] Referring to Figure 12A and Figure 12B , in the memory cell region MEC, a plurality of channel holes 140T may be formed. The plurality of channel holes 140T may penetrate through the plurality of insulating layers 120 and the plurality of sacrificial layers 130S stacked one on top of the other in an alternating manner, and the plurality of channel holes 140T may extend longitudinally in the vertical direction (Z direction). The bottom of each of the channel holes 140T may extend into the common source electrode plate 110. Next, a plurality of channel structures 140 including a gate insulating layer 142, a channel layer 144, a buried insulating layer 146, and a conductive plug 148 may be formed on the inner wall of each of the plurality of channel holes 140T.

[0101] Referring to Figure 13A , Figure 13B and Figure 13C , a mask pattern (not shown) may be formed over the uppermost insulating layer 120H and the covering insulating layer 150, and a first hole WLCH may be formed. The first hole WLCH may penetrate through the plurality of insulating layers 120 and the plurality of sacrificial layers 130S and may extend into the common source electrode plate 110. The first hole WLCH may be formed by performing an etching process using the mask pattern as an etching mask.

[0102] Next, in the memory cell region MEC and the connection region CON, a plurality of sacrificial layers 130S and sacrificial pad portions PADS can be replaced by a plurality of first gate lines 132 and a plurality of second gate lines 134S through the internal space of each of the first holes WLCH. In each of the plurality of first gate lines 132 and the plurality of second gate lines 134S, a relatively thick end portion obtained by replacing the sacrificial pad portion PADS can constitute a gate pad portion PAD.

[0103] In addition, each of the plurality of first gate lines 132 and the plurality of second gate lines 134S formed by the replacement process can include seams 132SM and 134SM as empty spaces.

[0104] Referring to Figure 14A and Figure 14B , a plurality of first separation patterns WLC filling the first holes WLCH can be formed. Next, a mask pattern (not shown) can be formed above the uppermost insulating layer 120H in the memory cell region MEC, and a second hole SSLCH can be formed. The second hole SSLCH can penetrate at least a part of each of the plurality of insulating layers 120 and the plurality of second gate lines 134S. The second hole SSLCH can be formed by performing an etching process using the mask pattern as an etching mask.

[0105] The second hole SSLCH can overlap at least a part of the plurality of channel structures 140 and each of the plurality of second gate lines 134S in the vertical direction (Z direction). Accordingly, at least a part of the channel structures 140 among the plurality of channel structures 140 that overlap the second separation pattern SSLC in the vertical direction (Z direction) can be removed through the second hole SSLCH. In addition, the plurality of second gate lines 134S can be separated from each other through the second hole SSLCH. In addition, a part of the seam 134SM of each of the plurality of second gate lines 134S that overlaps the second hole SSLCH in the vertical direction (Z direction) can be removed through the second hole SSLCH, and another part of the seam 134SM of each of the plurality of second gate lines 134S that is not removed by the second hole SSLCH and remains can be exposed by the second hole SSLCH and can communicate with the second hole SSLCH.

[0106] In some embodiments, after forming the plurality of channel structures 140 as described with reference to Figure 12A and Figure 12B , after forming a first upper insulating layer 160 above the uppermost insulating layer 120H and the covering insulating layer 150, and after performing the processes described with reference to Figure 13A and Figure 13B , the processes described with reference to Figure 14A andFigure 14B The process described above. In this case, each of the first hole WLCH and the second hole SSLCH may further extend in the vertical direction (Z direction) through the first upper insulating layer 160, and the first separation pattern WLC formed in the first hole WLCH and the second separation pattern SSLC formed in the second hole SSLCH may also further extend in the vertical direction (Z direction) through the first upper insulating layer 160.

[0107] Referring to Figure 15 , the seams 134SM (see Figure 14B ) of each of the plurality of second gate lines 134S (see Figure 14B ) may be filled with a conductive material through the second hole SSLCH. Accordingly, the plurality of second gate lines 134 may include a first conductive material layer 134A formed in the replacement process described in Figure 13A and Figure 13B and Figure 13C , and a second conductive material layer 134B formed in the process described in Figure 15 .

[0108] In some embodiments, an insulating layer (not shown) may be formed along the exposed surface of the remaining other portions of the seams 134SM (see Figure 14B ) of each of the plurality of second gate lines 134S (see Figure 14B ), and a conductive material may be formed through the second hole SSLCH above the insulating layer to fill the seams 134SM (see Figure 14B ). The insulating layer may be an oxide layer formed by the etching process for forming the second hole SSLCH described in Figure 14A and Figure 14B , or may be a natural oxide layer formed after forming the second hole SSLCH and before performing the process described in Figure 15 . Thereafter, by performing the subsequent processes described in Figure 16A , Figure 16B , Figure 17A and Figure 17B , the semiconductor device 100a shown in Figure 9 may be manufactured.

[0109] Referring to Figure 16A and Figure 16B , a second separation pattern SSLC may be formed in the second hole SSLCH, and the second separation pattern SSLC may fill the remaining portion of the second hole SSLCH. The second separation pattern SSLC may contact the channel structure 140 and the second gate line 134 on its first sidewall and second sidewall, respectively, in the second horizontal direction (Y direction).

[0110] Referring to Figure 17A andFigure 17B , a first upper insulating layer 160 may be formed above the uppermost insulating layer 120H and above the covering insulating layer 150. Subsequently, bit line contacts BLC penetrating the first upper insulating layer 160 may be formed in the memory cell region MEC, and first contact plugs 170 penetrating the first upper insulating layer 160 and the covering insulating layer 150 and second contact plugs (not shown) penetrating the covering insulating layer 150, the first upper insulating layer 160, and the common source plate 110 may be formed in the connection region CON.

[0111] The bit line contacts BLC may contact the conductive plugs 148 of the channel structure 140 at their bottom surfaces. The first contact plugs 170 may contact the gate pad portions PAD at their bottom surfaces. The second contact plugs may contact the peripheral circuit line layer 74 at their bottom surfaces. Subsequently, a second upper insulating layer 180 may be formed above the first upper insulating layer 160 in the memory cell region MEC and the connection region CON.

[0112] Next, in Figure 17A and Figure 17B in the final structure, bit lines BL penetrating the second upper insulating layer 180 and connected to the bit line contacts BLC may be formed in the memory cell region MEC, first lines ML penetrating the second upper insulating layer 180 and connected to the first contact plugs 170 and second lines (not shown) penetrating the second upper insulating layer 180 and connected to the second contact plugs (not shown) may be formed in the connection region CON, thereby manufacturing Figures 4 to 8 the semiconductor device 100 shown in

[0113] Figure 18 is a diagram schematically showing an electronic system 1000 including a semiconductor device 1100 according to some embodiments.

[0114] Referring to Figure 18 , the electronic system 1000 according to some embodiments may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a memory device including one or more semiconductor devices 1100, or may be an electronic device including a memory device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including at least one semiconductor device 1100.

[0115] The semiconductor device 1100 may be a non-volatile memory device. For example, the semiconductor device 1100 may be the one including the above-mentioned reference to Figures 4 to 9A NAND flash memory device with respect to at least one of the structures of semiconductor devices 100 and 100a. The semiconductor device may include a first structure 1100F and a second structure 1100S above the first structure 1100F. In some embodiments, the first structure 1100F may be arranged beside the second structure 1100S. The first structure 1100F may be a peripheral circuit structure that includes a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure that includes bit lines BL, a common source line CSL, a plurality of word lines WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a plurality of memory cell strings CSTR between the bit lines BL and the common source line CSL.

[0116] In the second structure 1100S, each of the plurality of memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be modified differently according to embodiments.

[0117] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The plurality of lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2 respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2.

[0118] The common source line CSL, the plurality of lower gate lines LL1 and LL2, the plurality of word lines WL, and the plurality of upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a plurality of first connection lines extending from the inside of the first structure 1100F to the second structure 1100S. The plurality of bit lines BL may be electrically connected to the page buffer 1120 through a plurality of second connection lines extending from the inside of the first structure 1100F to the second structure 1100S.

[0119] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform control operations on at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130.

[0120] The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connection line extending from the inside of the first structure 1100F to the second structure 1100S.

[0121] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some embodiments, the electronic system 1000 can include multiple semiconductor devices 1100, and in this case, the controller 1200 can control the multiple semiconductor devices 1100.

[0122] The processor 1210 can control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 can operate according to specific firmware and can access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 can include a NAND interface 1221 that handles communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the multiple memory cell transistors MCT of the semiconductor device 1100, data to be read from the multiple memory cell transistors MCT of the semiconductor device 1100, etc. can be transmitted through the NAND interface 1221. The host interface 1230 can provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0123] Figure 19 is a perspective view schematically showing an electronic system 2000 including a semiconductor device according to some embodiments.

[0124] Referring to Figure 19 , according to some embodiments, the electronic system 2000 can include a main board 2001, a controller 2002, one or more semiconductor packages 2003, and a DRAM 2004 mounted on the main board 2001. The semiconductor packages 2003 and the DRAM 2004 can be connected to the controller 2002 through multiple line patterns 2005 formed on the main board 2001.

[0125] The main board 2001 may include a connector 2006, which includes a plurality of pins coupled to or couplable to an external host (not shown). The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and Universal Flash Storage (UFS) M-Phy. In some embodiments, the electronic system 2000 may be operated by power supplied from the external host via the connector 2006. The electronic system 2000 may also include a Power Management Integrated Circuit (PMIC), which distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0126] The controller 2002 may write / read data to / from the semiconductor package 2003 and may increase the operation speed of the electronic system 2000.

[0127] The DRAM 2004 may be a buffer memory for reducing the speed difference between the external host and the semiconductor package 2003 serving as a data storage space. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide a space for temporarily storing data in the control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0128] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 disposed on or above the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 for electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the plurality of semiconductor chips 2200 and the connection structure 2400 above the package substrate 2100.

[0129] The encapsulation substrate 2100 may be a printed circuit board including a plurality of encapsulation upper pads 2130. Each of the plurality of semiconductor chips 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to Figure 18 the input / output pads 1101, and each of the plurality of semiconductor chips 2200 may include at least one of the structures described above with reference to Figures 4 to 9 the semiconductor devices 100 and 100a.

[0130] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 to the encapsulation upper pads 2130. Thus, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the encapsulation upper pads 2130 of the encapsulation substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including through-silicon vias (TSVs) instead of by the bonding wire type connection structure 2400.

[0131] In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main board 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other by lines formed on the interposer substrate.

[0132] Figure 20 is a cross-sectional view schematically showing a semiconductor package 2003 according to some embodiments. Figure 20 More specifically, it shows the structure of the cross-section taken along the line Figure 19 II-II' of.

[0133] Referring to Figure 20 , in the semiconductor package 2003, the encapsulation substrate 2100 may be a printed circuit board. The encapsulation substrate 2100 may include an encapsulation substrate body 2120, a plurality of encapsulation upper pads 2130 disposed on the upper surface of the encapsulation substrate body 2120 (see Figure 19 ), a plurality of lower pads 2125 disposed on the lower surface of the encapsulation substrate body 2120 or exposed through its lower surface, and a plurality of internal lines 2135 that electrically connect the plurality of encapsulation upper pads 2130 to the plurality of lower pads 2125 in the encapsulation substrate body 2120. The plurality of encapsulation upper pads 2130 may be electrically connected to the plurality of connection structures 2400. The plurality of lower pads 2125 may be connected toFigure 19 Multiple wire patterns 2005 on the main board 2001 of the electronic system 2000 shown in

[0134] In some embodiments, each of the multiple semiconductor chips 2200 may include at least one of the structures described above with reference to Figures 4 to 9 the structures described with respect to semiconductor devices 100 and 100a.

[0135] Although the inventive concept of the present disclosure has been specifically shown and described with reference to some examples of embodiments of the present disclosure, it will be understood that various changes may be made in form and detail without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: a plurality of gate lines, the plurality of gate lines comprising a first gate line arranged above the substrate and a second gate line arranged above the first gate line; A plurality of insulating layers, wherein the plurality of insulating layers are respectively arranged between the plurality of gate lines; a plurality of channel structures, the plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; as well as a separation pattern overlapping at least a portion of the plurality of channel structures in the vertical direction, wherein the separation pattern penetrates at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, the first channel structure overlaps the separation pattern in the vertical direction, and Wherein, the second gate line is completely filled with conductive material.

2. The semiconductor device according to claim 1, wherein The first gate line includes a seam in which no conductive material is present.

3. The semiconductor device according to claim 1, wherein The separation pattern includes a first side wall and a second side wall each extending longitudinally in a horizontal direction, and The first sidewall of the separation pattern contacts the first channel structure, and the second sidewall contacts the second gate line.

4. The semiconductor device according to claim 1, wherein The first gate line includes a single conductive material.

5. The semiconductor device according to claim 1, wherein The second gate line includes a first conductive material layer and a second conductive material layer surrounded by the first conductive material layer.

6. The semiconductor device according to claim 5, wherein: The first conductive material layer and the second conductive material layer include the same conductive material.

7. The semiconductor device according to claim 5, wherein: An upper end portion of the second conductive material layer is located at a lower vertical level than an upper surface of the first conductive material layer, and a lower end portion of the second conductive material layer is located at a higher vertical level than a lower surface of the first conductive material layer. 8 . The semiconductor device according to claim 5 , further comprising an intermediate insulating layer disposed between the first conductive material layer and the second conductive material layer.

9. The semiconductor device according to claim 8, wherein: The intermediate insulating layer includes an oxide layer of the conductive material of the first conductive material layer.

10. The semiconductor device according to claim 1, wherein The second gate line includes a string selection line.

11. A semiconductor device comprising: a peripheral circuit structure comprising a substrate, a peripheral circuit arranged above the substrate, and a peripheral circuit line structure connected to the peripheral circuit; A common source plate, which is arranged above the peripheral circuit structure; a plurality of gate lines, the plurality of gate lines comprising a first gate line arranged above the common source plate and a second gate line arranged above the first gate line; A plurality of insulating layers, wherein the plurality of insulating layers are respectively arranged between the plurality of gate lines; a plurality of channel structures, the plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; a first separation pattern horizontally spaced apart from the plurality of channel structures and penetrating the plurality of gate lines in the vertical direction; as well as a second separation pattern horizontally spaced apart from the first separation pattern and overlapping at least a portion of the plurality of channel structures in the vertical direction, wherein the second separation pattern penetrates at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, the first channel structure overlaps with the second separation pattern in the vertical direction, and Wherein, the second gate line is completely filled with conductive material.

12. The semiconductor device according to claim 11, wherein The first gate line includes a single conductive material and includes a seam where no conductive material exists.

13. The semiconductor device according to claim 11, wherein The second separation pattern includes a first sidewall and a second sidewall extending longitudinally in a horizontal direction, and The first sidewall of the second separation pattern contacts the first channel structure, and the second sidewall contacts the second gate line.

14. The semiconductor device according to claim 11, wherein The second gate line includes a first conductive material layer and a second conductive material layer surrounded by the first conductive material layer.

15. The semiconductor device according to claim 14, wherein: An upper end portion of the second conductive material layer is located at a lower vertical level than an upper surface of the first conductive material layer, and a lower end portion of the second conductive material layer is located at a higher vertical level than a lower surface of the first conductive material layer.

16. The semiconductor device according to claim 14, wherein: The first conductive material layer and the first gate line include the same conductive material.

17. The semiconductor device according to claim 14, further comprising an intermediate insulating layer disposed between the first conductive material layer and the second conductive material layer, wherein The intermediate insulating layer includes an oxide layer of the conductive material of the first conductive material layer.

18. The semiconductor device according to claim 11, wherein The second gate line includes a string selection line.

19. An electronic system comprising: Motherboard; a semiconductor device on the mainboard; as well as a controller electrically connected to the semiconductor device, Wherein, the semiconductor device comprises: a plurality of gate lines, the plurality of gate lines comprising a first gate line arranged above the substrate and a second gate line arranged above the first gate line; A plurality of insulating layers, wherein the plurality of insulating layers are respectively arranged between the plurality of gate lines; a plurality of channel structures penetrating the plurality of gate lines in a vertical direction perpendicular to an upper surface of the substrate; and a separation pattern overlapping at least a portion of the plurality of channel structures in the vertical direction, wherein the separation pattern penetrates at least a portion of the second gate line and at least a portion of a first channel structure among the plurality of channel structures, the first channel structure overlaps the separation pattern in the vertical direction, and Wherein, the second gate line is completely filled with conductive material.

20. The electronic system according to claim 19, wherein: The first gate line includes a single conductive material and includes a seam where no conductive material exists.

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