Techniques for stacks of components embedded in substrate core

Abstract

Techniques for components embedded in a substrate core are disclosed. In one embodiment, a power component, such as a deep trench capacitor, is disposed in a cavity defined in a substrate core of a circuit board for an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, for example, three or more power components. Through silicon vias in some or all of the power components may allow connections through one power component to another. Configuring the power component in this manner may provide mechanical stability to the power component and the substrate core, and provide power to the semiconductor die mounted on the circuit board.

Description

Background Art

[0001] High-power semiconductor die require a large amount of current at a stable voltage. To provide a stable voltage, capacitors are typically placed near the die, such as on the same package as the die. Capacitors near the die can suppress power delivery noise and improve power delivery performance. Deep trench capacitors can be used as some of these capacitors to provide more stable power. In deep trench capacitors, three-dimensional vertical capacitors are formed by etching deep trenches in a silicon substrate. Brief Description of the Drawings

[0002] Figure 1 is an isometric view of an embodiment of a system having integrated circuit components on a circuit board, where power components are embedded in a substrate core.

[0003] Figure 2 is Figure 1 a cross-sectional view of the system.

[0004] Figure 3 and Figure 4 is Figure 1 a flowchart of an embodiment of a method for creating an embodiment of the system.

[0005] Figure 5 is at Figure 3 and Figure 4 a cross-sectional view of an embodiment of a wafer for a deep trench capacitor at a stage of the flowchart.

[0006] Figure 6 is at Figure 3 and Figure 4 a cross-sectional view of an embodiment of a wafer for a deep trench capacitor at a stage of the flowchart.

[0007] Figure 7 is at Figure 3 and Figure 4 a cross-sectional view of an embodiment of a wafer for a deep trench capacitor at a stage of the flowchart.

[0008] Figure 8 is at Figure 3 and Figure 4 a cross-sectional view of an embodiment of the system at a stage of the flowchart.

[0009] Figure 9 is at Figure 3 and Figure 4 a cross-sectional view of an embodiment of the system at a stage of the flowchart.

[0010] Figure 10 is at Figure 3 and Figure 4Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0011] Figure 11 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0012] Figure 12 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0013] Figure 13 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0014] Figure 14 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0015] Figure 15 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0016] Figure 16 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0017] Figure 17 is at Figure 3 and Figure 4 Cross-sectional view of an embodiment of a system at a stage of a flowchart.

[0018] Figure 18 is Figure 1 Cross-sectional view of an embodiment of a variant of the system.

[0019] Figure 19 is Figure 1 Cross-sectional view of an embodiment of a variant of the system.

[0020] Figure 20 is Figure 1 Cross-sectional view of an embodiment of a variant of the system.

[0021] Figure 21 is Figure 1 Cross-sectional view of an embodiment of a variant of the system.

[0022] Figure 22 is Figure 1A cross-sectional view of an embodiment of a variation of a system.

[0023] Figure 23 yes Figure 1 A cross-sectional view of an embodiment of a variation of a system.

[0024] Figure 24 yes Figure 1 A cross-sectional view of an embodiment of a variation of a system.

[0025] Figure 25 yes Figure 1 A cross-sectional view of an embodiment of a variation of a system.

[0026] Figure 26 yes Figure 1 A cross-sectional view of an embodiment of a variation of a system.

[0027] Figure 27 is a top view of a wafer and die that can be included in a microelectronic assembly according to any embodiment disclosed herein.

[0028] Figure 28 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly according to any embodiment disclosed herein.

[0029] Figure 29A - 29D is a perspective view of an example planar transistor, a gate-all-around transistor, and a stacked gate-all-around transistor.

[0030] Figure 30 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any embodiment disclosed herein.

[0031] Figure 31 is a block diagram of an example electrical device that may include a microelectronic assembly according to any embodiment disclosed herein. DETAILED DESCRIPTION

[0032] In various embodiments disclosed herein, an integrated circuit component has a circuit board having a semiconductor die disposed on its surface. The circuit board has a substrate core having a cavity defined therein. Power components such as deep trench capacitors (DTCs) can be embedded in the cavity of the substrate core. The DTCs can provide improved power and voltage for the semiconductor die. The DTCs can include through-silicon vias to allow connection of one DTC in the DTC through another DTC in the DTC. Embedding several DTCs in the substrate core can provide several advantages, such as reducing the occupied space otherwise occupied by the DTCs and providing a short power delivery path to the semiconductor die.

[0033] As used herein, the phrase "communicatively coupled" refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send a signal to or receive a signal from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., a conductive trace, a conductive contact, air). Examples of communicatively coupled components include: integrated circuit dies located in the same package that communicate via an embedded bridge in the package substrate, and an integrated circuit component attached to a printed circuit board that sends a signal to or receives a signal from other integrated circuit components or electronic devices attached to the printed circuit board.

[0034] In the following description, specific details are set forth, but embodiments of the techniques described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this specification. Phrases such as "an embodiment", "various embodiments", "some embodiments" may include features, structures, or characteristics, but not every embodiment must include a particular feature, structure, or characteristic.

[0035] Some embodiments may have some, all, or none of the features described for other embodiments. Descriptions such as "first", "second", "third", etc. describe a common object and indicate that different instances of similar objects are being referenced. Such adjectives do not mean that the objects so described must be in a given sequence in time or space, in ranking, or in any other way. "Connected" may indicate that elements are in direct physical or electrical contact, and "coupled" may indicate that elements cooperate or interact, but they may or may not be in direct physical or electrical contact. Additionally, the terms "comprising", "including", "having", etc. used with respect to embodiments of the present disclosure are synonymous. A term modified by the word "substantially" includes an arrangement, orientation, spacing, or position that is slightly different in meaning from the unmodified term. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through-hole may deviate from the central axis of the through-hole by a few degrees. In another example, a substrate assembly feature (such as a through-width) described as substantially having a listed dimension may vary within a few percent of the listed dimension.

[0036] It should be understood that in the examples further shown and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, it should be understood that although some of the drawings show transistor designs in which source / drain regions, electrodes, etc. have orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees of orthogonality) due to the manufacturing methods used to create such devices or for other reasons.

[0037] Reference is now made to the accompanying drawings, which are not necessarily drawn to scale, where like or identical numerals may be used in different figures to represent like or identical parts. The use of like or identical numerals in different figures does not necessarily mean that all figures including those like or identical numerals constitute a single or identical embodiment. Like numerals with different alphabetic suffixes may represent different instances of like components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0038] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. However, it will be apparent that novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate their description. The intention is to cover all modifications, equivalents, and alternatives falling within the scope of the claims.

[0039] As used herein, in the context of a first layer or component being on a second layer or component, the phrase "on" means that the first layer or component is directly physically attached to the second part or component (with no layer or component between the first and second layers or components) or, in the case of having one or more intervening layers or components, physically attached to the second layer or component.

[0040] As used herein, the term "adjacent" means layers or components that are physically in contact with each other. That is, there is no layer or component between the adjacent layers or components. For example, layer X adjacent to layer Y means the layer that is physically in contact with layer Y.

[0041] Now refer to Figure 1 and Figure 2 , in one embodiment, the integrated circuit component 100 includes a circuit board 102, and one or more dies 104 are mounted on the circuit board 102. Figure 1 An isometric view of the integrated circuit component 100 is shown, and Figure 2 a cross-sectional view of the integrated circuit component 100 is shown. As Figure 1 shown, a die 104, such as a processor die 104, may be disposed on the top surface 108 of the circuit board 102. In an illustrative embodiment, additional components 106 (such as other semiconductor dies 106) are also disposed on the top surface 108 of the circuit board 102.

[0042] It should be understood that, as used herein, "top side", "bottom side", etc. are arbitrary designations used for clarity and do not denote a particular orientation required for manufacturing or use. Although the illustrative embodiments described have components 104, 106 placed on the "top" side of the circuit board 102, in some embodiments, these components may be placed on the "bottom" side of the circuit board 102.

[0043] The circuit board 102 includes a substrate core 202, a lower build layer 204, and an upper build layer 206. A cavity 214 is defined in the substrate core 202. A power component 208 is disposed within the cavity 214. In the illustrative embodiment, the power components 208 are arranged in a stack, as shown. The stack of power components 208 can include any suitable number of power components, such as from 1 to 6. In the illustrative embodiment, the top surface 228 of the upper power component 208 is substantially in the plane defined by the top surface 226 of the substrate core 202, and the bottom surface 232 of the lower power component 208 is substantially in the plane defined by the bottom surface 230 of the substrate core 202. For example, the top surface 228 of the upper power component 208 can be within 0 - 500 microns of the plane defined by the top surface 226 of the substrate core 202. In the illustrative embodiment, the top surface 228 of the upper power component 208 can be within (for example) 20 microns of the plane defined by the top surface 226 of the substrate core 202. The bottom surface 232 of the lower power component 208 can be similarly positioned relative to the plane defined by the bottom surface 230 of the substrate core 202.

[0044] The power component 208 can be any suitable power component. For example, in the illustrative embodiment, the power component 208 is a DTC. Additionally or alternatively, in some embodiments, one or both of the power components 208 can be another power component, such as a magnetic inductor array 208. Each DTC 208 can include one or more individual capacitors. The DTC 208 can have any suitable capacitance, such as a capacitance of 1 femtofarad - 10 microfarads and / or a capacitance density of 0.01 - 100 nanofarads per square millimeter. The DTC 208 can have the same capacitance or different capacitances. In some embodiments, the DTC 208 can be fabricated using different silicon nodes. Each DTC 208 can accommodate one capacitor, or one or two DTCs 208 each can accommodate more than one capacitor, such as from 2 to 1024. The power component 208 can form part of a voltage regulator or be connected to a voltage regulator, such as a fully integrated voltage regulator (FIVR).

[0045] In an illustrative embodiment, through-silicon vias (TSVs) 236 may be present in one or both of the power components 208. The TSVs 236 may permit connections through the upper power component 208 to the lower power component 208. The connection through the TSVs 236 to the lower power component 208 may be supplementary or alternative to the connection through the lower build layer 204. The TSVs 236 may be made of any suitable conductive material such as copper, tungsten, polysilicon, etc. The TSVs 236 may be connected to traces or pads 240 at the surface of the power components 208. The pads 240 may be any suitable conductor such as copper, aluminum, tungsten, etc. In some embodiments, conductors 238 may connect the TSVs 236 and / or pads 240 in the upper power component 208 to the lower power component 208. The conductors 238 may be copper, solder, etc. Additionally or alternatively, the lower power component 208 may be adhered to the upper power component 208 in a manner that does not require a separate layer of conductor 238 (e.g., hybrid bonding). The TSVs 236 may permit the capacitors in the power components 208 to be connected in series or in parallel. In some embodiments, some or all of the capacitors in the power components 208 may not be connected to each other. In some embodiments, the lower power component 208 may be oriented such that deep trench capacitors or other power circuitry is at the top of the lower power component 208, near the upper power component 208. In such embodiments, the shortest path length from the semiconductor die 104 to the capacitors or other power circuitry in the lower power component 208 may be through the through-silicon vias 236, rather than through the plated through-holes 216 and the lower build layer 204. In such embodiments, the lower power component 208 may not have any direct connection to the lower build layer 204. In an illustrative embodiment, the TSVs 236 are disposed towards the edge of the power component 208. In other embodiments, the TSVs 236 may be disposed in other locations, such as closer towards the middle of the power component 208.

[0046] In various embodiments, the power components 208 in the cavity 214 of the substrate core 202 may provide a series of possible advantages. For example, the power components 208 may otherwise be disposed on the bottom surface 234 of the circuit board 102, occupying space that could alternatively be used for signal routing, input / output pads, solder balls, land grid arrays, etc. The bottom surface 234 of the circuit board 102 may also be referred to as the land side or back side of the circuit board 102. The power components 208 may be directly below the semiconductor die 104 to which they supply power, thereby reducing the path length between the power components 208 and the semiconductor die 104.

[0047] Additionally, stacking power components 208 can provide advantages compared to positioning a single power component 208 in substrate core 202. In some cases, the height of power component 208 may be limited to, for example, 650 microns, while substrate core 202 can be higher, such as 1 millimeter. A single power component 208 disposed in cavity 214 of substrate core 202 may leave vertical space in cavity 214 that needs to be filled with, for example, a molding or other filler. The molding or other filler may cause structural or mechanical problems, such as displacement of power component 208 or other components due to, for example, a mismatch in coefficient of thermal expansion. However, in the case of two power components 208, the thickness of power component 208 can be reduced to, for example, 500 microns, such that the total height of power components 208 in cavity 214 matches the height of substrate core 202.

[0048] In an illustrative embodiment, circuit board 102 is a multi-layer circuit board 102 having build layers 204, 206 above and below substrate core 202. Build layers 204, 206 can have any suitable number of layers, such as 1 - 10 layers each. In other embodiments, circuit board 102 can be a single-layer circuit board 102. In an illustrative embodiment, substrate core 202 can be an organic core, such as a fiberglass board made of fiberglass and resin (e.g., FR-4). In some embodiments, substrate core 202 can be an inorganic core 202, such as a glass core 202. Glass core 202 can be silica glass. In other embodiments, glass core 202 can be made of any suitable material, which can be crystalline, non-crystalline, amorphous, etc., such as fused silica, borosilicate, sapphire, yttrium aluminum garnet, etc. Glass core 202 can be, for example, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silica. Glass core 202 can include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. Glass core 202 can include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. Glass core 202 can include at least 20% - 40% silicon by weight, at least 20% - 40% oxygen by weight, and at least 5% aluminum by weight. For example, some embodiments of glass core 202 can include, for example, at least 20% - 23% silicon and at least 20% - 26% oxygen by weight.

[0049] The thickness of the circuit board 102 can be any suitable thickness, such as 100 microns to 5 millimeters. The thickness of the substrate core 202 can be any suitable thickness, such as 50 microns to 1.7 millimeters. The circuit board 102 can have any suitable length and width, such as 5 - 500 millimeters. Although shown as rectangular, it should be understood that the circuit board 102 can be any suitable shape and can have protrusions, cutouts, etc. to accommodate, mate with, or contact other components of the device. In the illustrative embodiment, the circuit board 102 is planar. In other embodiments, the circuit board 102 can be non - planar. The cavity 214 can be any suitable size, such as a length and / or width of 1 - 20 millimeters.

[0050] In the illustrative embodiment, the die 104 above the power component 208 is a processor die, and the other die 106 can be a memory die communicatively coupled to the processor die 104. In other embodiments, the die 104 and / or the die 106 can be any suitable die, such as one or more processor dies, memory dies, central processing units (CPUs), graphics processing units (GPUs), any other suitable processing units (xPUs), accelerator circuits, field - programmable gate arrays (FPGAs), application - specific integrated circuits (ASICs), etc. The die 104, 106 can be connected to contact pads or vias 220 on the circuit board 102 by solder balls 222.

[0051] As described above, the power component 208 can be any suitable power component, such as the DTC 208 and / or the magnetic inductor array 208. In the illustrative embodiment, the DTC 208 is a silicon die including a trench array, such as trenches 0.1 - 100 microns deep. The trenches can have a pitch of, for example, 0.2 - 5 microns. The DTC 208 can include any suitable number of trenches, such as 1 - 10000. One electrode for the capacitor can be conformal with the trenches, with a dielectric material on top of the electrode, and the other electrode on top of the dielectric material. The electrodes for the capacitor can be coupled to traces 218 or pads 218 defined in the build layers 204, 206. The DTC 208 can be connected to the die 104, die 106, components connected to the circuit board 102, etc. through various connections in the integrated circuit component 100, such as traces 218, vias 220, through - holes 216, etc. The power component 208 can have any suitable size, such as a height of 25 microns to 650 microns and a length and / or width of 1 - 20 millimeters.

[0052] The power components 208 can be attached together in any suitable manner, such as by using an adhesive 212 (such as a die attach film 212). Additionally or alternatively, the power components 208 can be attached together using, for example, epoxy glue, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer - on - wafer bonding, wafer - on - wafer hybrid bonding, solder with underfill, etc.

[0053] The volume of the cavity 214 not occupied by the power components 208 can be filled with any suitable filler material 224. For example, the filler material 224 can be a prepreg, Ajinomoto build film (ABF), photo - imageable dielectric, inorganic dielectric material, organic dielectric material, oxide, nitride, silicon dioxide, silicon nitride, polymer, epoxy resin, polyimide, polymer composite with inorganic fillers, etc. The filler material 224 can be applied using any suitable method, such as compression molding, vacuum lamination, thermocompression, chemical vapor deposition, physical vapor deposition, etc.

[0054] In an illustrative embodiment, the plated vias 216 extend from the top surface 226 of the substrate core 202 to the bottom surface 230 of the substrate core 202. The vias 216 can transmit power and / or data signals through the substrate core 202.

[0055] The circuit board 102 includes traces 218 and vias 220. The traces 218 and vias 220 can be made of any suitable conductive material, such as copper or aluminum.

[0056] Now refer to Figure 3 and Figure 4, in one embodiment, a flowchart of a method 300 for creating an integrated circuit component 100 is shown. The method 300 can be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines can be programmed to perform some or all of the steps of the method 300. Such machines can include, for example, a memory, a processor, a data storage device, etc. The memory and / or the data storage device can store instructions that, when executed by the machine, cause the machine to perform some or all of the steps of the method 300. The method 300 can use any suitable set of techniques used in semiconductor processing or circuit board processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, lithography, ion implantation, dry etching, wet etching, selective laser etching, heat treatment, flip chip, layer transfer, magnetron sputtering deposition, pulsed laser deposition, laser processing, 3D lithography, screen printing, inkjet printing, etc. It should be understood that the method 300 is merely one embodiment of a method for creating one embodiment of a system, and other methods can be used to create any suitable embodiment of the system. In some embodiments, the steps of the method 300 can be performed in an order different from the order shown in the flowchart.

[0057] The method 300 begins at block 302, where one or more DTCs 208 are prepared. In an illustrative embodiment, a wafer 500 having a plurality of arrays of deep trenches 502 is fabricated. Figure 5 A cross-section of a portion of such a wafer 500 is shown. In some embodiments, as Figure 6 shown, wafer-level thinning can be performed in block 304 to obtain a thinner wafer 500. Additionally or alternatively, in other embodiments, the DTC 208 can be thinned after dicing or the DTC 208 can be left unthinned. In block 306, in some embodiments, electrodes 240 can be patterned on the DTC 208. Additionally or alternatively, in some embodiments, the electrodes can be patterned on the DTC 208 at another step in the manufacturing process, such as when forming the build layers 204, 206. In block 308, as Figure 7As shown, the wafer 500 is diced to form the DTC 208. In some embodiments, at block 310, the DTC 208 can be thinned after dicing. In some embodiments, through-silicon vias 236 can be formed on the DTC 208 at the wafer level. In other embodiments, as described below, the DTC 208 can have through-silicon vias 236 formed at a later time. At this stage, in some embodiments, the upper DTC 208 can be mounted on the lower DTC 208, such as by using a die attach film 212. In some embodiments, at block 312, the upper DTC 208 can be mounted on the lower DTC 208 at the wafer level, such as by wafer-on-wafer bonding. In other embodiments, as described below, the DTC 208 can be attached at a later time. In some embodiments, pre-fabricating a stack of power components 208 can allow testing of the stack of power components 208 before integration into the substrate core 202, thereby increasing yield and reducing cost.

[0058] At block 314, as Figure 8 shown, the substrate core 202 is prepared, such as by dicing, polishing, etc. In some embodiments, at block 316, as Figure 9 shown, through-holes 216 are formed in the substrate core 202.

[0059] At block 318, as Figure 10 shown, cavities 214 are formed in the substrate core 202. The cavities 214 can be formed in any suitable manner. For example, in some embodiments, the cavities 214 can be formed by drilling, such as by using mechanical or laser drilling, in block 320. In other embodiments, the cavities 214 can be etched in block 322. At block 324, as Figure 11 shown, the substrate core 202 is mounted on a carrier 1102. The carrier 1102 can be (for example) silicon or other substrate, glass substrate, tape material, etc.

[0060] Now referring Figure 4 , at block 326, as Figure 12 shown, the power components 208 are placed in the cavities 214. In some embodiments, the DTC 208 is placed at block 328. In other embodiments, the magnetic inductor array 208 can be placed at block 330. In some embodiments, after the power components 208 are placed in the cavities 214, through-silicon vias 236 and / or pads 240 can be added to the power components 208.

[0061] At block 332, if another power component is to be added, the method 300 proceeds to block 334, where, as Figure 13As shown, die attach film 212 is placed on DTC 208. In other embodiments, the power components 208 may be joined together in another manner, such as by using epoxy glue, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, etc. Method 300 then loops back to block 326, where another power component 208 is placed in cavity 214. Figure 14 Three power components 208 placed in cavity 214 are shown.

[0062] Returning to reference block 332, if no other power component 208 is added, method 300 proceeds to block 336, where cavity 214 is filled with a filler material 224, such as prepreg, ABF, photoimageable dielectric, etc. The filler material 224 can be applied using any suitable method, such as compression molding, vacuum lamination, thermocompression, chemical vapor deposition, physical vapor deposition, etc. In block 338, as Figure 15 shown, substrate core 202 is planarized. In block 340, as Figure 16 shown, substrate core 202 is removed from carrier 1102.

[0063] In block 342, as Figure 17 shown, build layers 204, 206 are built on substrate core 202. Any suitable set of techniques, such as electroplating, electroless plating, lithography, etching, etc., can be used to create build layers 204, 206. In block 344, one or more dies 104, 106 are mounted on the substrate, thus completing integrated circuit component 100 as Figure 2 shown.

[0064] It should be understood that the above embodiments are only some possible embodiments, and other embodiments with different features or different combinations of features disclosed herein are also contemplated. Illustrations of some but not all of the contemplated embodiments are described below.

[0065] Now referring to Figure 18 , in some embodiments, integrated circuit component 1800 may include two or more stacks of power components 208 in the same cavity 214. Additionally or alternatively, in some embodiments, as Figure 19 shown, integrated circuit component 1900 may include two or more stacks of power components 208 in different cavities 214.

[0066] In the embodiments described above with respect to Figure 2 , the power components 208 have approximately the same height. In other embodiments, the power components 208 may have different heights. For example, the upper power component 208 may have a height smaller than the height of the lower power component 208, as Figure 20as shown by the integrated circuit component 2000 therein. In some embodiments, fabricating the through-silicon vias 236 in the thinner power component 208 may be easier or less costly than fabricating the through-silicon vias 236 in the thicker power component 208. In such embodiments, the thinner power component 208 may have the through-silicon vias 236 while the thicker power component 208 may not have the through-silicon vias 236.

[0067] In the embodiments described above with respect to Figure 2 the power component stack includes a lower power component 208 and an upper power component 208. In another embodiment, a plurality of lower power components 208 and / or a plurality of upper power components 208 may be included in a stack. For example, as Figure 21 shown in, in one embodiment, two upper power components 208 of the integrated circuit component 2100 may be disposed on a lower power component 208.

[0068] In another possible embodiment, as Figure 22 shown, the integrated circuit component 2200 may include a die 104 mounted on the bottom side of the circuit board 102.

[0069] In another possible embodiment, as Figure 23 shown, the bridging die 2302 may be disposed on or within the circuit board 102 of the integrated circuit component 2300, such as within the upper build layer 206. The bridging die 2302 may provide interconnections between various components, such as interconnections between the dies 104, 106 of the integrated circuit component 100 or between the dies 104, 106 and connections external to the integrated circuit component 100. The bridging die 2302 may be embodied as (for example) an embedded multi-die interconnect bridge (EMIB) or an omnidirectional interconnect (ODI).

[0070] In another possible embodiment, the stack of power components 208 may include more than three power components 208, such as Figure 24 the four power components 208 in the integrated circuit component 2400 shown in.

[0071] In one possible embodiment, as Figure 25 shown, through-silicon vias (TSVs) 2402 may be present in the upper power component 208 of the integrated circuit component 2500. As shown, in the case where the lowermost power component 208 is arranged for connection to (for example) a capacitor and the capacitor is located on the top side, the capacitor in the lowermost power component 208 is accessible from the upper build layer 206 through the upper power component 208. In such a configuration, the lower build layer 204 may not have any direct electrical connection to the lowermost power component 208.

[0072] In another possible embodiment, spacers 2602 may be included in the stack of power components 208. The spacers 2602 may be on the bottom, on the top, or between the power components 208. The spacers 2602 may be any suitable material, such as an inorganic material, an organic material, a resin material with or without glass fibers, glass, a semiconductor such as silicon, etc. In the illustrative embodiment, the spacers 2602 are rigid. In some embodiments, the spacers 2602 may be a glass material similar to some embodiments of the substrate core 202 described above. The spacers 2602 may have any suitable dimensions, such as a height from 25 microns to 650 microns and a length and / or width from 1 - 20 millimeters.

[0073] It should be understood that the integrated circuit component 100 and other integrated circuit components described herein may have additional components not shown, such as additional semiconductor dies, active components, passive components, thermal management components (such as integrated heat sinks and heat spreaders), etc. In some embodiments, as shown in several of the figures above, the power component 208 may be embedded in the circuit board 102 below the die 104 in the integrated circuit component 100. In other embodiments, the power component 208 may be embedded in any suitable circuit board 102, such as a motherboard, daughter board, riser board, power distribution board, mezzanine board, auxiliary board, etc.

[0074] Figure 27 is a top view of a wafer 2700 and dies 2702 that may be included in any of the integrated circuit components 100 disclosed herein (e.g., any suitable power component or die such as the power component 208 or die 104). The wafer 2700 may be composed of a semiconductor material and may include one or more dies 2702 having an integrated circuit structure formed on the surface of the wafer 2700. The individual dies 2702 may be repeating units of an integrated circuit product including any suitable integrated circuit. After the fabrication of the semiconductor product is completed, the wafer 2700 may undergo a singulation process, where the dies 2702 are separated from each other to provide discrete "chips" of the integrated circuit product. The dies 2702 may be any of the power components 208 or dies 104 disclosed herein. The dies 2702 may include one or more transistors (e.g., as discussed below, Figure 28Some of the transistors 2840 in the transistor 2840), support circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 2700 or die 2702 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2702. For example, a memory array formed by multiple memory devices may be formed on the same die 2702 as a processor unit (e.g., Figure 31 processor unit 3102) or other logic unit configured to store information in the memory device or execute instructions stored in the memory array. The various integrated circuit components 100 in the integrated circuit component 100 disclosed herein may be fabricated using die-to-wafer assembly techniques, where some of the power components 208 or die 104 are attached to a wafer 2700 that includes other power components or die among the power components 208 or die 104, and the wafer 2700 is then singulated.

[0075] Figure 28 is a cross-sectional side view of an integrated circuit device 2800 that may be included in any of the integrated circuit components 100 disclosed herein (e.g., in any of the power components 208 or die 104). One or more of the integrated circuit devices 2800 may be included in one or more dies 2702 ( Figure 27 ). The integrated circuit device 2800 may be formed on a die substrate 2802 (e.g., Figure 27 wafer 2700) and may be included in a die (e.g., Figure 27into the die 2702). The die substrate 2802 can be a semiconductor substrate composed of a semiconductor material system including (e.g.) an n-type or p-type material system (or a combination of both). The die substrate 2802 can include (e.g.) a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials can be used to form the die substrate 2802, which can be combined with silicon or not combined with silicon, and the alternative materials include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as group II-VI, III-V, or IV can also be used to form the die substrate 2802. Although some examples of materials that can form the die substrate 2802 are described herein, any material that can serve as the basis of the integrated circuit device 2800 can be used. The die substrate 2802 can be an individualized die (e.g., Figure 27 the die 2702) or a portion of a wafer (e.g., Figure 27 the wafer 2700).

[0076] The integrated circuit device 2800 can include one or more device layers 2804 disposed on the die substrate 2802. The device layer 2804 can include features of one or more transistors 2840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 2802. The transistors 2840 can include (e.g.) one or more source and / or drain (S / D) regions 2820, a gate 2822 for controlling the current flow between the S / D regions 2820, and one or more S / D contact portions 2824 for routing electrical signals to / from the S / D regions 2820. The transistors 2840 can include additional features not shown for clarity, such as device isolation regions, gate contact portions, etc. The transistors 2840 are not limited to Figure 28 the types and configurations depicted therein, and can include a wide variety of other types and configurations, such as (e.g.) planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as double-gate or triple-gate transistors, and surround-gate or all-around-gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

[0077] Figure 29A - 29D are simplified perspective views of an example planar transistor, FinFET transistor, all-around gate transistor, and stacked all-around gate transistor. Figure 29A - 29D The transistors shown are formed on a substrate 2916 having a surface 2908. Isolation regions 2914 separate the source and drain regions of the transistors from other transistors and from the bulk region 2918 of the substrate 2916.

[0078] Figure 29Ais a perspective view of an example planar transistor 2900 that includes a gate 2902 that controls current flow between a source region 2904 and a drain region 2906. The transistor 2900 is planar because the source region 2904 and the drain region 2906 are planar relative to the substrate surface 2908.

[0079] Figure 29B is a perspective view of an example FinFET transistor 2920 that includes a gate 2922 that controls current flow between a source region 2924 and a drain region 2926. The transistor 2920 is non-planar because the source region 2924 and the drain region 2926 include "fins" that extend upward from the substrate surface 2928. Since the gate 2922 surrounds three sides of a semiconductor fin that extends from the source region 2924 to the drain region 2926, the transistor 2920 can be considered a triple-gate transistor. Figure 29B shows one S / D fin extending through the gate 2922, but multiple S / D fins can extend through the gate of a FinFET transistor.

[0080] Figure 29C is a perspective view of a gate-all-around (GAA) transistor 2940 that includes a gate 2942 that controls current flow between a source region 2944 and a drain region 2946. The transistor 2940 is non-planar because the source region 2944 and the drain region 2946 are elevated from the substrate surface 2928.

[0081] Figure 29D is a perspective view of a GAA transistor 2960 that includes a gate 2962 that controls current flow between a plurality of elevated source regions 2964 and a plurality of elevated drain regions 2966. The transistor 2960 is a stacked GAA transistor because the gate controls current flow between a plurality of elevated S / D regions stacked on top of each other. The transistors 2940 and 2960 are considered gate-all-around transistors because the gate surrounds all sides of a semiconductor portion that extends from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 2948 and 2968 for transistors 2940 and 2960, respectively), the transistors 2940 and 2960 can optionally be referred to as nanowire, nanosheet, or nanoribbon transistors.

[0082] Returning to Figure 28 , the transistor 2840 can include a gate 2822 formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric can include one layer, or a stack of layers. One or more layers can include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0083] High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process can be performed on the gate dielectric to improve its quality.

[0084] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2840 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode can be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers for other purposes, such as barrier layers, can be included.

[0085] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0086] In some embodiments, when viewing a cross-section of the transistor 2840 along the source-channel-drain direction, the gate electrode can be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the die substrate 2802 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 2802. In other embodiments, at least one of the metal layers forming the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the die substrate 2802 and does not include sidewall portions that are substantially perpendicular to the top surface of the die substrate 2802. In other embodiments, the gate electrode can be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0087] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to enclose the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0088] The S / D regions 2820 may be formed within the die substrate 2802 adjacent to the gates 2822 of individual transistors 2840. For example, the S / D regions 2820 may be formed using an implantation / diffusion process or an etch / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 2802 to form the S / D regions 2820. An annealing process to activate the dopants and cause them to diffuse further into the die substrate 2802 may follow the ion implantation process. In the latter process, the die substrate 2802 may first be etched to form a recess at the location of the S / D regions 2820. Then an epitaxial deposition process may be implemented to fill the recess with a material for making the S / D regions 2820. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide may be used to make the S / D regions 2820. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form the S / D regions 2820. In additional embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 2820.

[0089] Electrical signals such as power and / or input / output (I / O) signals may be routed to and / or from devices (e.g., transistors 2840) on the device layer 2804 through one or more interconnect layers (shown in Figure 28 as interconnect layers 2806 - 2810) disposed on the device layer 2804. For example, the conductive features (e.g., gates 2822 and S / D contacts 2824) on the device layer 2804 may be electrically coupled to the interconnect structures 2828 of the interconnect layers 2806 - 2810. One or more interconnect layers 2806 - 2810 may form the metallization stack (also referred to as the “ILD stack”) 2819 of the integrated circuit device 2800.

[0090] The interconnect structures 2828 may be arranged within the interconnect layers 2806 - 2810 according to a wide variety of designs to route electrical signals; in particular, the arrangement is not limited to Figure 28The specific configuration of the interconnect structure 2828 depicted in. Although a specific number of interconnect layers 2806-2810 are depicted in Figure 28 Integrated circuit devices having more or fewer interconnect layers than those depicted are included in embodiments of the present disclosure.

[0091] In some embodiments, the interconnect structure 2828 may include wires 2828a and / or vias 2828b filled with a conductive material such as metal. The wires 2828a may be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of the die substrate 2802 on which the device layer 2804 is formed. For example, the wires 2828a may route electrical signals in the in-and-out-of-page direction and / or in the cross-page direction. The vias 2828b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 2802 on which the device layer 2804 is formed. In some embodiments, the vias 2828b may electrically couple the wires 2828a of different interconnect layers 2806-2810 together.

[0092] As Figure 28 shown, the interconnect layers 2806-2810 may include a dielectric material 2826 disposed between the interconnect structures 2828. In some embodiments, the dielectric material 2826 between the interconnect structures 2828 in different interconnect layers disposed in the interconnect layers 2806-2810 may have different compositions; in other embodiments, the compositions of the dielectric material 2826 between the different interconnect layers 2806-2810 may be the same. The device layer 2804 may also include a dielectric material 2826 disposed between the transistors 2840 and the bottom layer of the metallization stack. The dielectric material 2826 included in the device layer 2804 may have a different composition from the dielectric material 2826 included in the interconnect layers 2806-2810; in other embodiments, the composition of the dielectric material 2826 in the device layer 2804 may be the same as the dielectric material 2826 in any of the interconnect layers included in the interconnect layers 2806-2810.

[0093] The first interconnect layer 2806 (referred to as metal 1 or "M1") may be directly formed on the device layer 2804. In some embodiments, as shown, the first interconnect layer 2806 may include wires 2828a and / or vias 2828b. The wires 2828a of the first interconnect layer 2806 may be coupled to the contacts (e.g., S / D contacts 2824) of the device layer 2804. The vias 2828b of the first interconnect layer 2806 may be coupled to the wires 2828a of the second interconnect layer 2808.

[0094] The second interconnect layer 2808 (referred to as Metal 2 or "M2") can be formed directly on the first interconnect layer 2806. In some embodiments, the second interconnect layer 2808 can include vias 2828b to couple the lines 2828 of the second interconnect layer 2808 to the lines 2828a of the third interconnect layer 2810. Although, for clarity, the lines 2828a and vias 2828b are structurally depicted with lines within the individual interconnect layers, in some embodiments, the lines 2828a and vias 2828b can be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0095] The third interconnect layer 2810 (referred to as Metal 3 or "M3") (and additional interconnect layers, as needed) can be successively formed on the second interconnect layer 2808 according to similar techniques and configurations described in connection with the second interconnect layer 2808 or the first interconnect layer 2806. In some embodiments, the interconnect layers that are "higher" (i.e., farther from the device layer 2804) in the metallization stack 2819 in the integrated circuit device 2800 can be thicker than the interconnect layers that are lower in the metallization stack 2819, where the lines 2828a and vias 2828b in the higher interconnect layers are thicker than the lines 2828a and vias 2828b in the lower interconnect layers.

[0096] The integrated circuit device 2800 can include a solder mask material 2834 (e.g., polyimide or a similar material) and one or more conductive contacts 2836 formed on the interconnect layers 2806 - 2810. In Figure 28 , the conductive contacts 2836 are shown in the form of bond pads. The conductive contacts 2836 can be electrically coupled to the interconnect structure 2828 and are configured to route the electrical signals of the (one or more) transistors 2840 to an external device. For example, solder joints can be formed on one or more of the conductive contacts 2836 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 2800 to another component (e.g., a printed circuit board). The integrated circuit device 2800 can include additional or alternative structures to route the electrical signals from the interconnect layers 2806 - 2810; for example, the conductive contacts 2836 can include other similar features (e.g., pillars) that route the electrical signals to external components.

[0097] In some embodiments where the integrated circuit device 2800 is a dual-sided die, the integrated circuit device 2800 may include another metallization stack (not shown) on opposite sides of the (one or more) device layers 2804. The metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 2806-2810 to provide a conductive path (e.g., including conductive lines and vias) between the (one or more) device layers 2804 and additional conductive contacts (not shown) on the side of the integrated circuit device 2800 opposite the conductive contact 2836.

[0098] In other embodiments where the integrated circuit device 2800 is a dual-sided die, the integrated circuit device 2800 may include one or more through-silicon vias (TSVs) that pass through the die substrate 2802; these TSVs may contact the (one or more) device layers 2804 and may provide a conductive path between the (one or more) device layers 2804 and additional conductive contacts (not shown) on the side of the integrated circuit device 2800 opposite the conductive contact 2836. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 2800 opposite the conductive contact 2836 to the transistors 2840 and any other components integrated into the die 2800, and the metallization stack 2819 may be used to route I / O signals from the conductive contact 2836 to the transistors 2840 and any other components integrated into the die 2800.

[0099] Multiple integrated circuit devices 2800 may be stacked, with one or more TSVs in the individual stacked devices, to provide connections between one device in the stack to any other device. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM dies may provide connections between the individual HBMs and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (micro-bumps).

[0100] Figure 30is a cross-sectional side view of an integrated circuit device assembly 3000 that can include any of the integrated circuit components 100, 2300, 2400, 2500, 2600, 2700, 2800, 2900 disclosed herein. In some embodiments, the integrated circuit device assembly 3000 can be an integrated circuit component 100, 2300, 2400, 2500, 2600, 2700, 2800, 2900. The integrated circuit device assembly 3000 includes a plurality of components disposed on a circuit board 3002, which can be a motherboard, a system board, a main board, etc. The integrated circuit device assembly 3000 includes components disposed on a first side 3040 of the circuit board 3002 and on an opposite second side 3042 of the circuit board 3002; generally, the components can be disposed on one or both of the sides 3040 and 3042. Any integrated circuit component discussed hereinafter with reference to the integrated circuit device assembly 3000 can take the form of any suitable embodiment of the integrated circuit components 100, 2300, 2400, 2500, 2600, 2700, 2800, 2900 disclosed herein.

[0101] In some embodiments, the circuit board 3002 can be a printed circuit board (PCB) that includes a plurality of metal (or interconnect) layers separated from each other by a dielectric material layer and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 3002. In other embodiments, the circuit board 3002 can be a non-PCB substrate. In some embodiments, the circuit board 3002 can be, for example, the circuit board 102. Figure 30 The integrated circuit device assembly 3000 shown in includes an on-interposer package structure 3036 coupled to the first side 3040 of the circuit board 3002 by a coupling component 3016. The coupling component 3016 can electrically and mechanically couple the on-interposer package structure 3036 to the circuit board 3002 and can include solder balls (as Figure 30 shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical coupling and / or mechanical coupling structure.

[0102] The on-interposer package structure 3036 can include an integrated circuit component 3020 coupled to an interposer 3004 by a coupling component 3018. The coupling component 3018 can take any suitable form for the application, such as the forms discussed above with reference to the coupling component 3016. Although Figure 30A single integrated circuit component 3020 is shown, but multiple integrated circuit components can be coupled to the interposer 3004; in fact, additional interposers can be coupled to the interposer 3004. The interposer 3004 can provide an intermediate substrate for bridging the circuit board 3002 and the integrated circuit component 3020.

[0103] The integrated circuit component 3020 can be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., Figure 27 die 2702 of Figure 28 integrated circuit device 2800) and / or one or more other suitable components. A packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, where the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 3020, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 3004. The integrated circuit component 3020 can include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit component 3020 can include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0104] In embodiments where the integrated circuit component 3020 includes multiple integrated circuit dies, the dies can be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0105] In addition to including one or more processor units, the integrated circuit component 3020 can include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components can be on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These individual integrated circuit dies can be referred to as "chiplets". In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnection between the dies can be through a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as provided by an Embedded Multi-Die Interconnect Bridge (EMIB) or a combination thereof.

[0106] Generally, the interposer 3004 can extend connections to a wider pitch or reroute connections to different connections. For example, the interposer 3004 can couple the integrated circuit component 3020 to a set of ball grid array (BGA) conductive contacts of the coupling component 3016 for coupling to the circuit board 3002. In Figure 30 the illustrated embodiment, the integrated circuit component 3020 and the circuit board 3002 are attached to opposite sides of the interposer 3004; in other embodiments, the integrated circuit component 3020 and the circuit board 3002 can be attached to the same side of the interposer 3004. In some embodiments, three or more components can be interconnected by means of the interposer 3004.

[0107] In some embodiments, the interposer 3004 can be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 3004 can be formed of epoxy resin, glass fiber-reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 3004 can be formed of alternating rigid or flexible materials, which can include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 3004 can include metal interconnects 3008 and vias 3010, including but not limited to through-hole vias 3010-1 (which extend from the first face 3050 of the interposer 3004 to the second face 3054 of the interposer 3004), blind vias 3010-2 (which extend from the first face 3050 or the second face 3054 of the interposer 3004 to an internal metal layer), and buried vias 3010-3 (which connect internal metal layers).

[0108] In some embodiments, the interposer 3004 can include a silicon interposer. Through-Silicon Vias (TSVs) extending through the silicon interposer can connect connections on the first face of the silicon interposer to the opposite second face of the silicon interposer. In some embodiments, the interposer 3004 including the silicon interposer can further include one or more wiring layers to route connections on the first face of the interposer 3004 to the opposite second face of the interposer 3004.

[0109] The interpolator 3004 may also include an embedded device 3014, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interpolator 3004. The on-interpolator package structure 3036 may take the form of any on-interpolator package structure known in the art.

[0110] The integrated circuit device assembly 3000 may include an integrated circuit component 3024 coupled to the first surface 3040 of the circuit board 3002 by a coupling component 3022. The coupling component 3022 may take the form of any of the embodiments discussed above with reference to the coupling component 3016, and the integrated circuit component 3024 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 3020.

[0111] Figure 30 The illustrated integrated circuit device assembly 3000 includes an on-package package structure 3034 coupled to the second surface 3042 of the circuit board 3002 by a coupling component 3028. The on-package package structure 3034 may include an integrated circuit component 3026 and an integrated circuit component 3032 coupled together by a coupling component 3030 such that the integrated circuit component 3026 is disposed between the circuit board 3002 and the integrated circuit component 3032. The coupling components 3028 and 3030 may take the form of any of the embodiments of the coupling component 3016 discussed above, and the integrated circuit components 3026 and 3032 may take the form of any of the embodiments of the integrated circuit component 3020 discussed above. The on-package package structure 3034 may be configured according to any on-package package structure known in the art.

[0112] Figure 31 is a block diagram of an example electrical device 3100 that may include one or more of the integrated circuit components 100, 2300, 2400, 2500, 2600, 2700, 2800, 2900 disclosed herein. For example, any suitable component of the components of the electrical device 3100 may include one or more of the integrated circuit device assemblies 3000, integrated circuit components 3020, integrated circuit devices 2800, or integrated circuit dies 2702 disclosed herein, and may be arranged in any of the integrated circuit components 100, 2300, 2400, 2500, 2600, 2700, 2800, 2900 disclosed herein. Figure 31Multiple components included in the electronic device 3100 are shown, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electronic device 3100 may be attached to one or more motherboards or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-chip (SoC) die.

[0113] Additionally, in various embodiments, the electronic device 3100 may not include Figure 31 one or more of the components shown, but the electronic device 3100 may include interface circuitry for coupling to one or more components. For example, the electronic device 3100 may not include the display device 3106, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 3106 may be coupled. In another set of examples, the electronic device 3100 may not include the audio input device 3124 or the audio output device 3108, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 3124 or the audio output device 3108 may be coupled.

[0114] The electronic device 3100 may include one or more processor units 3102 (e.g., one or more processing units). As used herein, the terms "processor unit", "processing unit", or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processor unit 3102 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller encryption processors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Thus, the processor unit may be referred to as an XPU (or xPU).

[0115] The electrical device 3100 may include a memory 3104, which itself may include one or more memory devices, such as volatile memories (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memories (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memories, and / or hard disk drives. In some embodiments, the memory 3104 may include a memory located on the same integrated circuit die as the processor unit 3102. This memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last-level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0116] In some embodiments, the electrical device 3100 may include one or more processor units 3102 that are heterogeneous or asymmetric with respect to another processor unit 3102 in the electrical device 3100. With respect to a series of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc., there may be various differences between the processing units 3102 in the system. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 3102 in the electrical device 3100.

[0117] In some embodiments, the electrical device 3100 may include a communication component 3112 (e.g., one or more communication components). For example, the communication component 3112 may manage wireless communication for transmitting data to and from the electrical device 3100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transfer data by using modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated device does not contain any wires, although in some embodiments they may not.

[0118] The communication component 3112 may implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) programs along with any of its amendments, updates, and / or revisions (e.g., LTE-Advanced program, Ultra Mobile Broadband (UMB) program (also known as “3GPP2”), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally known as WiMAX networks, and WiMAX is an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the IEEE 802.16 standards compliance and interoperability tests. The communication component 3112 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication component 3112 may operate according to Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 3112 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, the communication component 3112 may operate according to other wireless protocols. The electrical device 3100 may include an antenna 3122 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0119] In some embodiments, the communication component 3112 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 3112 may include multiple communication components. For example, a first communication component 3112 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 3112 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In some embodiments, the first communication component 3112 may be dedicated to wireless communications, and the second communication component 3112 may be dedicated to wired communications.

[0120] The electrical device 3100 may include a battery / power circuitry 3114. The battery / power circuitry 3114 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the electrical device 3100 to an energy source separate from the electrical device 3100 (e.g., an AC line power source).

[0121] The electrical device 3100 may include a display device 3106 (or corresponding interface circuitry, as discussed above). The display device 3106 may include one or more embedded or externally connected visual indicators, either wired or wirelessly, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0122] The electrical device 3100 may include an audio output device 3108 (or corresponding interface circuitry, as discussed above). The audio output device 3108 may include any embedded or externally connected device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0123] The electrical device 3100 may include an audio input device 3124 (or corresponding interface circuitry, as discussed above). The audio input device 3124 may include any embedded or externally connected device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output). The electrical device 3100 may include a Global Navigation Satellite System (GNSS) device 3118 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 3118 may communicate with a satellite-based system and may determine the geographical location of the electrical device 3100 based on information received from one or more GNSS satellites, which is known in the art.

[0124] The electrical device 3100 may include other output devices 3110 (or corresponding interface circuitry, as discussed above). Examples of other output devices 3110 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0125] The electrical device 3100 may include other input devices 3120 (or corresponding interface circuitry, as discussed above). Examples of other input devices 3120 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a single field-of-view or stereo camera), a trackball, a touchpad, a touch panel, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0126] The electrical device 3100 may have any desired form factor, such as a portable or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a notebook computer, a ultrabook computer, a personal digital assistant (PDA), a super mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart household appliance, a consumer electronics or equipment, a manufacturing equipment). In some embodiments, the electrical device 3100 may be any other electronic device that processes data. In some embodiments, the electrical device 3100 may include multiple discrete physical components. Given the range of devices that the electrical device 3100 may manifest as in various embodiments, in some embodiments, the electrical device 3100 may be referred to as a computing device or a computing system.

[0127] Examples

[0128] Illustrative examples of the techniques disclosed herein are provided below. Embodiments of the techniques may include any one or more of the examples described below, as well as any combination of the examples described below.

[0129] Example 1 includes a device that includes: a substrate core, wherein a cavity is defined in the substrate core; a first die disposed in the cavity, the first die including a capacitor; a second die disposed in the cavity, the second die including a capacitor, wherein the second die is disposed above the first die; and a third die disposed in the cavity, the third die including a capacitor, wherein the third die is disposed above the second die.

[0130] Example 2 includes the subject matter of Example 1, and wherein, the first die is a deep trench capacitor die, and wherein, the second die is a deep trench capacitor die.

[0131] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein, the first die includes a plurality of trenches, and wherein, an individual trench of the plurality of trenches extends from a surface of the first die to at least 10 micrometers below the surface of the first die.

[0132] Example 4 includes the subject matter of any of Examples 1 - 3, and wherein, the first die is a deep trench capacitor die, and wherein, the second die includes an array of magnetic inductors.

[0133] Example 5 includes the subject matter of any of Examples 1 - 4, and wherein, a bottom surface of the first die is within 100 micrometers of a plane defined by a bottom surface of the substrate core, and wherein a top surface of the second die is within 100 micrometers of a plane defined by a top surface of the substrate core.

[0134] Example 6 includes the subject matter of any of Examples 1 - 5, and wherein, the substrate core has a thickness of at least 800 micrometers.

[0135] Example 7 includes the subject matter of any of Examples 1 - 6, and wherein, a difference between a thickness of the first die and a thickness of the second die is less than 5 micrometers.

[0136] Example 8 includes the subject matter of any of Examples 1 - 7, and wherein, a difference between a thickness of the first die and a thickness of the second die is at least 20 micrometers.

[0137] Example 9 includes the subject matter of any of Examples 1 - 8, and wherein, the substrate core has a thickness of less than 200 micrometers.

[0138] Example 10 includes the subject matter of any of Examples 1 - 9, and further includes a spacer disposed in the cavity, and wherein, the spacer is disposed below the third die.

[0139] Example 11 includes the subject matter of any of Examples 1 - 10, and further includes a fourth die disposed on a surface of a circuit board of the device, and wherein, the fourth die is positioned to be at least partially above the first die and the second die.

[0140] Example 12 includes the subject matter of any of Examples 1 - 11, and further includes a fifth die disposed on a second surface of the circuit board, the second surface being opposite to the surface, and wherein, the fifth die is positioned to be at least partially below the first die and the second die.

[0141] Example 13 includes the subject matter of any of Examples 1-12 and further includes a fully integrated voltage regulator (FIVR), wherein the FIVR includes the first die and the second die.

[0142] Example 14 includes the subject matter of any of Examples 1-13 and further includes a fourth die disposed in the cavity; and a fifth die disposed in the cavity, wherein the fifth die is disposed above the fourth die.

[0143] Example 15 includes the subject matter of any of Examples 1-14 and wherein a second cavity is defined in the substrate core, the second cavity being separate from the cavity, and the device further includes: a fourth die disposed in the second cavity; and a fifth die disposed in the second cavity, wherein the fifth die is disposed above the fourth die.

[0144] Example 16 includes the subject matter of any of Examples 1-15 and further includes a plurality of build-up layers adjacent to the substrate core.

[0145] Example 17 includes a device comprising: a substrate core including a top surface and a bottom surface, wherein a cavity is defined in the substrate core, wherein the cavity extends from the top surface of the substrate core to the bottom surface of the substrate core; and a power component stack disposed in the cavity, wherein the power component stack extends at least from a top plane defined by the top surface of the substrate core to a bottom plane defined by the bottom surface of the substrate core, wherein the power component stack includes a first power component, a second power component, and a third power component.

[0146] Example 18 includes the subject matter of Example 17 and wherein the first power component is a deep trench capacitor and the second power component is a deep trench capacitor.

[0147] Example 19 includes the subject matter of any of Examples 17 and 18 and wherein the first power component includes a semiconductor die, wherein the semiconductor die includes a plurality of trenches, wherein an individual trench of the plurality of trenches extends from a surface of the semiconductor die to at least 10 micrometers below the surface of the semiconductor die.

[0148] Example 20 includes the subject matter of any of Examples 17-19 and wherein the first power component is a deep trench capacitor and the second power component is an array of magnetic inductors.

[0149] Example 21 includes the subject matter of any of Examples 17-20, and wherein a bottom surface of the first power component is within 100 microns of a plane defined by a bottom surface of the substrate core, and wherein a top surface of the second power component is within 100 microns of a plane defined by a top surface of the substrate core.

[0150] Example 22 includes the subject matter of any of Examples 17-21, and wherein the substrate core has a thickness of at least 800 microns.

[0151] Example 23 includes the subject matter of any of Examples 17-22, and wherein a difference between a thickness of the first power component and a thickness of the second power component is less than 5 microns.

[0152] Example 24 includes the subject matter of any of Examples 17-23, and wherein a difference between a thickness of the first power component and a thickness of the second power component is at least 20 microns.

[0153] Example 25 includes the subject matter of any of Examples 17-24, and wherein the substrate core has a thickness of less than 200 microns.

[0154] Example 26 includes the subject matter of any of Examples 17-25, and wherein the power component stack further includes a spacer.

[0155] Example 27 includes the subject matter of any of Examples 17-26, and further includes a semiconductor die disposed on a surface of a circuit board of the device, wherein the semiconductor die is positioned to be at least partially above the first power component and the second power component.

[0156] Example 28 includes the subject matter of any of Examples 17-27, and further includes a second semiconductor die disposed on a second surface of the circuit board, the second surface being opposite the surface, wherein the second semiconductor die is positioned to be at least partially below the first power component and the second power component.

[0157] Example 29 includes the subject matter of any of Examples 17-28, and further includes a fully integrated voltage regulator (FIVR), wherein the FIVR includes the first power component and the second power component.

[0158] Example 30 includes the subject matter of any of Examples 17-29, and further includes a fourth power component disposed in the cavity; and a fifth power component disposed in the cavity, wherein the fifth power component is disposed above the fourth power component.

[0159] Example 31 includes the subject matter of any of Examples 17 - 30, and wherein a second cavity is defined in the substrate core, the second cavity being separate from the cavity, the device further comprising: a fourth power component disposed in the second cavity; and a fifth power component disposed in the second cavity, wherein the fifth power component is disposed above the fourth power component.

[0160] Example 32 includes the subject matter of any of Examples 17 - 31, and further includes a plurality of build layers adjacent to the substrate core.

[0161] Example 33 includes a device comprising: a circuit board; a semiconductor die; and a stack of power components disposed in the circuit board, wherein the stack of power components supplies power to the semiconductor die, and wherein the stack of power components includes a first power component, a second power component, and a third power component.

[0162] Example 34 includes the subject matter of Example 33, and wherein the first power component is a deep trench capacitor, and wherein the second power component is a deep trench capacitor.

[0163] Example 35 includes the subject matter of any of Examples 33 and 34, and wherein the first power component includes a semiconductor die, and wherein the semiconductor die includes a plurality of trenches, and wherein an individual trench of the plurality of trenches extends from a surface of the semiconductor die to at least 10 microns below the surface of the semiconductor die.

[0164] Example 36 includes the subject matter of any of Examples 33 - 35, and wherein the first power component is a deep trench capacitor, and wherein the second power component is an array of magnetic inductors.

[0165] Example 37 includes the subject matter of any of Examples 33 - 36, and wherein a bottom surface of the first power component is within 100 microns of a plane defined by a bottom surface of a substrate core of the circuit board, and wherein a top surface of the second power component is within 100 microns of a plane defined by a top surface of the substrate core.

[0166] Example 38 includes the subject matter of any of Examples 33 - 37, and wherein the substrate core of the circuit board has a thickness of at least 800 microns.

[0167] Example 39 includes the subject matter of any of Examples 33 - 38, and wherein a difference between a thickness of the first power component and a thickness of the second power component is less than 5 microns.

[0168] Example 40 includes the subject matter of any of Examples 33 - 39, and wherein the difference between the thickness of the first power component and the thickness of the second power component is at least 20 microns.

[0169] Example 41 includes the subject matter of any of Examples 33 - 40, and wherein the substrate core of the circuit board has a thickness of less than 200 microns.

[0170] Example 42 includes the subject matter of any of Examples 33 - 41, and wherein the power component stack further includes a spacer.

[0171] Example 43 includes the subject matter of any of Examples 33 - 42, and wherein the semiconductor die is positioned at least partially over the first power component and the second power component.

[0172] Example 44 includes the subject matter of any of Examples 33 - 43, and further includes a second semiconductor die disposed on a second surface of the circuit board, the second surface being opposite the surface, wherein the second semiconductor die is positioned at least partially under the first power component and the second power component.

[0173] Example 45 includes the subject matter of any of Examples 33 - 44, and further includes a fully integrated voltage regulator (FIVR), wherein the FIVR includes the first power component and the second power component.

[0174] Example 46 includes the subject matter of any of Examples 33 - 45, and wherein a cavity is defined in the substrate core of the circuit board, wherein the first power component and the second power component are disposed in the cavity, the device further includes: a fourth power component disposed in the cavity; and a fifth power component disposed in the cavity, wherein the fifth power component is disposed over the fourth power component.

[0175] Example 47 includes the subject matter of any of Examples 33 - 46, and wherein a cavity is defined in the substrate core of the circuit board, wherein the first power component and the second power component are disposed in the cavity, wherein a second cavity is defined in the substrate core of the circuit board, the second cavity being separate from the cavity, the device further includes: a fourth power component disposed in the second cavity; and a fifth power component disposed in the second cavity, wherein the fifth power component is disposed over the fourth power component.

[0176] Example 48 includes the subject matter of any of Examples 33 - 47, and wherein the circuit board includes a substrate core and a plurality of build-up layers adjacent to the substrate core.

[0177] Example 49 includes an apparatus that includes: a substrate core, wherein a cavity is defined in the substrate core; and a stacked module device for providing power, wherein the stacked module device for providing power is disposed within the substrate core and includes at least three power components.

[0178] Example 50 includes the subject matter of Example 49, and wherein the stacked module device for providing power includes one or more deep trench capacitors.

[0179] Example 51 includes the subject matter of any of Examples 49 and 50, and wherein the stacked module device for providing power includes a semiconductor die, wherein the semiconductor die includes a plurality of trenches, and wherein an individual trench of the plurality of trenches extends from a surface of the semiconductor die to at least 10 micrometers below the surface of the semiconductor die.

[0180] Example 52 includes the subject matter of any of Examples 49 - 51, and wherein the stacked module device for providing power includes deep trench capacitors and a magnetic inductor array.

[0181] Example 53 includes the subject matter of any of Examples 49 - 52, and wherein a bottom surface of the stacked module device for providing power is within 100 micrometers of a plane defined by a bottom surface of the substrate core, and wherein a top surface of the stacked module device for providing power is within 100 micrometers of a plane defined by a top surface of the substrate core.

[0182] Example 54 includes the subject matter of any of Examples 49 - 53, and wherein the substrate core has a thickness of at least 800 micrometers.

[0183] Example 55 includes the subject matter of any of Examples 49 - 54, and wherein the substrate core has a thickness of less than 200 micrometers.

[0184] Example 56 includes the subject matter of any of Examples 49 - 55, and wherein the stacked module device for providing power further includes spacers.

[0185] Example 57 includes the subject matter of any of Examples 49 - 56, and further includes a semiconductor die disposed on a surface of a circuit board of the apparatus, wherein the semiconductor die is positioned to be at least partially above the stacked module device for providing power.

[0186] Example 58 includes the subject matter of any of Examples 49-57 and further includes a second semiconductor die disposed on a second surface of the circuit board, the second surface being opposite the surface, wherein the second semiconductor die is positioned at least partially under the stacked module device for providing power.

[0187] Example 59 includes the subject matter of any of Examples 49-58 and further includes a fully integrated voltage regulator (FIVR), wherein the FIVR includes the stacked module device for providing power.

[0188] Example 60 includes the subject matter of any of Examples 49-59 and further includes a plurality of build-up layers adjacent to the substrate core.

[0189] Example 61 includes a method that includes: forming a cavity in a substrate core; disposing a first power component, a second power component, and a third power component in the cavity, wherein the second power component is disposed above the first power component and the third power component is disposed above the second power component; and filling the cavity with a filler material.

[0190] Example 62 includes the subject matter of Example 61 and further includes: forming a plurality of power components on a semiconductor wafer; thinning the semiconductor wafer; and dicing the semiconductor wafer to form the first power component.

[0191] Example 63 includes the subject matter of any of Examples 61 and 62 and further includes: forming a plurality of power components on a semiconductor wafer; dicing the semiconductor wafer to form the first power component; and thinning the first power component after dicing the semiconductor wafer and before disposing the first power component in the cavity.

[0192] Example 64 includes the subject matter of any of Examples 61-63 and wherein disposing the first power component and the second power component in the cavity includes: disposing the first power component in the cavity; depositing a die attach film on the first power component in the cavity; and disposing the second power component on the die attach film.

[0193] Example 65 includes the subject matter of any of Examples 61 - 64 and further includes: forming a first plurality of power components on a first semiconductor wafer; forming a second plurality of power components on a second semiconductor wafer; bonding the first semiconductor wafer and the second semiconductor wafer, wherein bonding the first semiconductor wafer and the second semiconductor wafer includes bonding the first power components and the second power components; and dicing the first semiconductor wafer and the second semiconductor wafer, wherein disposing the first power components and the second power components in the cavity includes disposing the first power components and the second power components in the cavity while the first power components are bonded to the second power components.

[0194] Example 66 includes the subject matter of any of Examples 61 - 65 and wherein disposing the first power components and the second power components in the cavity includes: bonding the first power components and the second power components; and disposing the first power components and the second power components in the cavity while the first power components are bonded to the second power components.

[0195] Example 67 includes the subject matter of any of Examples 61 - 66 and wherein the first power component is a deep trench capacitor and wherein the second power component is a deep trench capacitor.

[0196] Example 68 includes the subject matter of any of Examples 61 - 67 and wherein the first power component includes a semiconductor die, wherein the semiconductor die includes a plurality of trenches, and wherein an individual trench of the plurality of trenches extends from a surface of the semiconductor die to at least 10 micrometers below the surface of the semiconductor die.

[0197] Example 69 includes the subject matter of any of Examples 61 - 68 and wherein the first power component is a deep trench capacitor and wherein the second power component is an array of magnetic inductors.

[0198] Example 70 includes the subject matter of any of Examples 61 - 69 and wherein a bottom surface of the first power component is within 100 micrometers of a plane defined by a bottom surface of the substrate core and wherein a top surface of the second power component is within 100 micrometers of a plane defined by a top surface of the substrate core.

[0199] Example 71 includes the subject matter of any of Examples 61 - 70 and wherein the substrate core has a thickness of at least 800 micrometers.

[0200] Example 72 includes the subject matter of any of Examples 61 - 71, and wherein, the difference between the thickness of the first power component and the thickness of the second power component is less than 5 micrometers.

[0201] Example 73 includes the subject matter of any of Examples 61 - 72, and wherein, the difference between the thickness of the first power component and the thickness of the second power component is at least 20 micrometers.

[0202] Example 74 includes the subject matter of any of Examples 61 - 73, and wherein, the substrate core has a thickness of less than 200 micrometers.

[0203] Example 75 includes the subject matter of any of Examples 61 - 74, and further includes: disposing spacers in the cavity.

[0204] Example 76 includes the subject matter of any of Examples 61 - 75, and further includes: disposing a semiconductor die on a surface of a circuit board including the substrate core, wherein the semiconductor die is positioned to be at least partially above the first power component and the second power component.

[0205] Example 77 includes the subject matter of any of Examples 61 - 76, and further includes: disposing a second semiconductor die on a second surface of the circuit board, the second surface being opposite to the surface, wherein the second semiconductor die is positioned to be at least partially below the first power component and the second power component.

[0206] Example 78 includes the subject matter of any of Examples 61 - 77, and wherein, the integrated circuit component including the circuit board and the semiconductor die further includes a fully integrated voltage regulator (FIVR), wherein the FIVR includes the first power component and the second power component.

[0207] Example 79 includes the subject matter of any of Examples 61 - 78, and further includes: disposing a fourth power component in the cavity; and disposing a fifth power component in the cavity, wherein the fifth power component is disposed above the fourth power component.

[0208] Example 80 includes the subject matter of any of Examples 61 - 79, and further includes: forming a second cavity in the substrate core, the second cavity being separated from the cavity; disposing a fourth power component in the second cavity; and disposing a fifth power component in the second cavity, wherein the fifth power component is disposed above the fourth power component.

[0209] Example 81 includes the subject matter of any of Examples 61 - 80, and further includes: forming a plurality of build layers adjacent to the substrate core.

Claims

1. A device comprising: a substrate core, wherein a cavity is defined in the substrate core; a first die disposed in the cavity, the first die comprising a capacitor; a second die disposed in the cavity, the second die comprising a capacitor, wherein the second die is disposed over the first die; and A third die is disposed in the cavity, the third die comprising a capacitor, wherein the third die is disposed over the second die.

2. The device according to claim 1, wherein: The first die is a deep trench capacitor die, wherein the second die is a deep trench capacitor die.

3. The device according to claim 2, wherein: The first die includes a plurality of trenches, wherein individual trenches of the plurality of trenches extend from a surface of the first die to at least 10 microns below the surface of the first die.

4. The device according to claim 1, wherein: The first die is a deep trench capacitor die, wherein the second die includes a magnetic inductor array.

5. The device according to claim 1, wherein: A bottom surface of the first die is within 100 microns of a plane defined by a bottom surface of the substrate core, wherein a top surface of the second die is within 100 microns of a plane defined by a top surface of the substrate core.

6. The device according to any one of claims 1 to 5, wherein: The substrate core has a thickness of at least 800 microns.

7. The device according to any one of claims 1 to 6, wherein: A difference between a thickness of the first die and a thickness of the second die is less than 5 microns.

8. The device according to any one of claims 1 to 6, wherein: The difference between the thickness of the first die and the thickness of the second die is at least 20 microns.

9. The device according to any one of claims 1 to 6, wherein: The substrate core has a thickness of less than 200 microns.

10. The apparatus of claim 1, further comprising a spacer disposed in the cavity, wherein: The spacer is disposed under the third die.

11. The device according to any one of claims 1 to 10, further comprising a fourth die disposed on a surface of a circuit board of the device, wherein The fourth die is positioned at least partially over the first die and the second die.

12. The apparatus of claim 11, further comprising a fully integrated voltage regulator (FIVR), wherein: The FIVR includes the first die and the second die.

13. A device comprising: Circuit boards; Semiconductor die; as well as A power component stack is disposed in the circuit board, wherein the power component stack provides power to the semiconductor die, wherein the power component stack includes a first power component, a second power component, and a third power component.

14. The device according to claim 13, wherein: The first power component is a deep trench capacitor, wherein the second power component is a deep trench capacitor.

15. The device according to claim 14, wherein: The first power component includes a semiconductor die, wherein the semiconductor die includes a plurality of trenches, wherein individual trenches of the plurality of trenches extend from a surface of the semiconductor die to at least 10 microns below the surface of the semiconductor die.

16. The apparatus according to claim 13, wherein: The first power component is a deep trench capacitor, wherein the second power component is a magnetic inductor array.

17. The apparatus according to claim 13, wherein: A bottom surface of the first power component is within 100 microns of a plane defined by a bottom surface of a substrate core of the circuit board, wherein a top surface of the second power component is within 100 microns of a plane defined by a top surface of the substrate core.

18. The apparatus according to any one of claims 13 to 17, wherein: The substrate core of the circuit board has a thickness of at least 800 microns.

19. The apparatus according to any one of claims 13 to 17, wherein: A difference between a thickness of the first power component and a thickness of the second power component is less than 5 micrometers.

20. The apparatus according to any one of claims 13 to 17, wherein: A difference between a thickness of the first power component and a thickness of the second power component is at least 20 micrometers.

21. The apparatus according to any one of claims 13 to 17, wherein: The substrate core of the circuit board has a thickness of less than 200 microns.

22. The apparatus according to any one of claims 13 to 17, wherein: The power component stack also includes a spacer.

23. A method comprising: forming a cavity in a substrate core; A first power component, a second power component, and a third power component are arranged in the cavity, wherein the second power component is arranged above the first power component, wherein the third power component is arranged above the second power component; and The cavity is filled with a filler material.

24. The method according to claim 23, further comprising: forming a plurality of power components on a semiconductor wafer; thinning the semiconductor wafer; as well as The thinned semiconductor wafer is cut to form the first power components.

25. The method of claim 23, further comprising: forming a plurality of power components on a semiconductor wafer; cutting the semiconductor wafer to form the first power component; as well as After dicing the semiconductor wafer and before arranging the first power component in the cavity, the first power component is thinned.

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