MOSFET device with super junction trench gate and manufacturing method thereof

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a super-junction trench gate. The MOSFET device comprises a substrate of a first conductive type; the epitaxial layer is formed on the substrate, and the doping concentration of the epitaxial layer is from shallow to deep from bottom to top; the body region of the second conduction type is formed on the surface of the epitaxial layer; the first gate groove is formed in the top of the body region, the first gate groove extends downwards from the upper surface of the epitaxial layer to penetrate through the body region, a second gate groove is formed in the epitaxial layer at the bottom of the first gate groove, and the width of the second gate groove is smaller than that of the first gate groove; an ion implantation region of a second conduction type, which assists in depletion of the drift region, is formed below the first gate trench, and the ion implantation region is located at the bottom and the side wall of the second gate trench; the insulating dielectric layer is located in the first gate groove and the second gate groove, and the first gate groove is not completely filled with the insulating dielectric layer. The breakdown voltage of the device is improved; and meanwhile, a new photomask is not added, and only the etching of the second gate groove is added.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a MOSFET device with a superjunction trench gate and a manufacturing method thereof. Background Art

[0002] Trench gate MOSFET devices are widely used in power conversion circuits and are often used as power switching devices. The on-resistance Rsp and breakdown voltage BV of the trench gate are important parameter indicators. Obtaining a higher breakdown voltage and a lower on-resistance of the trench gate can improve the competitiveness of products. To improve the on-resistance of medium-voltage (50 - 200V) trench gates, the concept of superjunction-trench gate achieved by implantation has been proposed, as Figure 1 shown.

[0003] Among them, the meanings of the reference numerals include: 101 is a highly doped N-type substrate, 102 is an N-type epitaxial layer / N-type drift region (5e15 - 1e17 cm^-3), 103 is a P-type implantation region (P-pillar, PPL) for assisting the depletion of the N-type drift region, 104 is a gate dielectric layer, 105 is a gate polysilicon, 106 is a P-type body region, 107 is a P-type heavily doped implantation, 108 is an N-type heavily doped implantation, 109 is a contact hole, 110 is an interlayer insulating dielectric layer, 211 is a source-terminal - body-region terminal metal layer, and 112 is a drain-terminal metal layer.

[0004] Taking the N-channel trench gate as an example, in order to improve the characteristics of the superjunction-trench gate device, the bottom end of the P-pillar 103 for assisting the depletion of the drift region will be as close as possible to the highly doped substrate 101 so that the depletable N-type drift region is long.

[0005] However, for the P-pillar formed by implantation, due to the limitation of the Boron (boron ion) implantation energy, the process conditions with Boron energy greater than 3500 KeV are restricted. Especially for the requirement of breakdown voltage > 80V (Epi thickness > 5um), Boron implantation energy needs to be greater than 2500 KeV to make the bottom end of 103 as close as possible to the highly doped substrate 101, but the high-energy Boron implantation brings great difficulties to process integration.

[0006] To solve the above problems, a new type of MOSFET device with a superjunction trench gate and a manufacturing method thereof need to be proposed. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a MOSFET device with a superjunction trench gate and a manufacturing method thereof, which are used to solve the problem that in the prior art, for the P-type implantation region that depletes the auxiliary N-type drift region formed by implantation, due to the limitation of the Boron (boron ion) implantation energy, the process conditions with a Boron energy greater than 3500 KeV are restricted, and the high-energy Boron implantation brings great difficulties to process integration.

[0008] To achieve the above object and other related objects, the present invention provides a MOSFET device with a superjunction trench gate, including:

[0009] A substrate of a first conduction type;

[0010] An epitaxial layer formed on the substrate, and the doping concentration of the epitaxial layer is gradually increased from shallow to deep from bottom to top;

[0011] A body region of a second conduction type formed on the surface of the epitaxial layer;

[0012] A first gate trench formed on the top of the body region, the first gate trench extends downward from the upper surface of the epitaxial layer through the body region, and a second gate trench is formed on the epitaxial layer at the bottom of the first gate trench, and the width of the second gate trench is smaller than that of the first gate trench;

[0013] A second conduction type ion implantation region for assisting in the depletion of the drift region is formed below the first gate trench, wherein the ion implantation region is located at the bottom and side walls of the second gate trench;

[0014] An insulating dielectric layer located in the first gate trench and the second gate trench, wherein the insulating dielectric layer does not completely fill the first gate trench;

[0015] A gate dielectric layer formed on the surface of the remaining first gate trench, and a gate polysilicon layer filling the remaining first gate trench, and the gate polysilicon layer is heavily doped with the first conduction type;

[0016] A source end heavily doped region is formed above the body region on both sides of the first gate trench, an interlayer dielectric layer is formed on the epitaxial layer, a contact hole is formed on the source end heavily doped region, and a second conduction type heavily doped region is formed on the body region below the contact hole;

[0017] A conductive metal filling the contact hole, and source end, body region end metal layers and drain end metal layers respectively located on the front and back surfaces of the substrate.

[0018] Preferably, the first conduction type is N-type; the second conduction type is P-type.

[0019] Preferably, the first conduction type is P-type; the second conduction type is N-type.

[0020] Preferably, the doping concentration of the epitaxial layer is 5e15 to 1e17 cm^-3.

[0021] Preferably, the distance between the bottom of the first gate trench and the bottom of the body region is greater than 1 um, and the distance between the bottom of the first gate trench and the top of the substrate is greater than 5 um.

[0022] Preferably, the distance between the bottom of the second gate trench and the top of the substrate is 3.5 to 4.5 um.

[0023] Preferably, the implanted ions in the ion implantation region are boron ions.

[0024] Preferably, the implantation dose of the boron ions is 1e12 to 1e13 cm^-2, and the implantation energy is 50 to 4000 KeV.

[0025] Preferably, the material of the gate dielectric layer is silicon dioxide.

[0026] Preferably, the gate dielectric layer includes: a first gate oxide layer formed by a low-temperature thermal oxidation method; a TEOS oxide layer deposited as a second gate oxide layer.

[0027] Preferably, the thickness of the first gate oxide layer is 100 to 400 angstroms.

[0028] Preferably, the doping concentration of the gate polysilicon layer is greater than 5e19 cm^-3.

[0029] The present invention also provides a manufacturing method of the above MOSFET device with a superjunction trench gate, including:

[0030] Step 1: Epitaxially form an epitaxial layer of the first conduction type on a substrate of the first conduction type, and the doping concentration of the epitaxial layer is gradually increased from bottom to top.

[0031] Step 2: Use an ion implantation method to form a body region of the second conduction type on the surface of the epitaxial layer, and then perform thermal diffusion and propulsion on the body region.

[0032] Step 3: Form a first gate trench on the top of the body region. The first gate trench extends downward from the upper surface of the epitaxial layer through the body region. Form sidewalls on the sidewalls of the first gate trench, and use the sidewalls as a mask to etch the epitaxial layer at the bottom of the first gate trench to form a second gate trench, and then remove the sidewalls.

[0033] Step 4: Form an ion implantation protection layer on the surfaces of the first gate trench and the second gate trench, and form an ion implantation region of the second conductivity type for assisting in the depletion of the drift region below the first gate trench, where the ion implantation region is located at the bottom and sidewalls of the second gate trench;

[0034] Step 5: Remove the ion implantation protection layer to form an insulating dielectric layer in the first gate trench and the second gate trench, where the insulating dielectric layer does not completely fill the first gate trench;

[0035] Step 6: Form a gate dielectric layer on the surface of the remaining first gate trench, and then form a gate polysilicon layer filling the remaining first gate trench, where the gate polysilicon layer is heavily doped with the first conductivity type;

[0036] Step 7: Form a source-end heavily doped region above the body regions on both sides of the first gate trench, form an interlayer dielectric layer on the epitaxial layer, form a contact hole on the source-end heavily doped region, perform a heavy doping implantation of the second conductivity type on the body region below the contact hole, and form a heavily doped region through thermal diffusion while activating the impurity implantation of the heavy doping implantation;

[0037] Step 8: Form a conductive metal filling the contact hole, and then form a source-end, body-region end metal layer and a drain-end metal layer.

[0038] Preferably, in Step 1, the first conductivity type is N-type; the second conductivity type is P-type.

[0039] Preferably, in Step 1, the first conductivity type is P-type; the second conductivity type is N-type.

[0040] Preferably, the doping concentration of the epitaxial layer in Step 1 is 5e15 - 1e17 cm^-3.

[0041] Preferably, the epitaxial layer in Step 1 is formed by at least two epitaxial growths.

[0042] Preferably, the method for forming the first gate trench in Step 3 includes: forming an etching stop layer, a hard mask layer and a photoresist layer stacked from bottom to top on the body region; opening the photoresist layer by photolithography to define the formation position of the first gate trench, and then forming an opening on the hard mask layer to the etching stop layer by etching; removing the photoresist layer, and etching the etching stop layer and the epitaxial layer at the bottom of the opening with the hard mask layer as a mask to form the first gate trench.

[0043] Preferably, the material of the etching stop layer in Step 3 is silicon nitride.

[0044] Preferably, the material of the hard mask layer in step three is silicon dioxide.

[0045] Preferably, the distance between the bottom of the first gate trench and the bottom of the body region in step three is greater than 1 μm, and the distance between the bottom of the first gate trench and the top of the substrate is greater than 5 μm.

[0046] Preferably, the distance between the bottom of the second gate trench and the top of the substrate in step three is 3.5 to 4.5 μm.

[0047] Preferably, the sidewall is formed by deposition and etch-back in step three.

[0048] Preferably, in step four, a sacrificial oxide layer is formed by thermal oxidation while retaining the hard mask layer and the etch stop layer, and the defects formed by the gate trench etching are repaired by thermal oxidation. The sacrificial oxide layer serves as an ion implantation protection layer.

[0049] Preferably, boron ions are used for ion implantation in step four to form the ion implantation region.

[0050] Preferably, the ion implantation region in step four is formed by multiple ion implantations.

[0051] Preferably, the implantation dose of the boron ions in step four is 1e12 - 1e13 cm^-2, and the implantation energy is 50 - 4000 keV.

[0052] Preferably, the ion implantation region is formed by ion implantation at an angle less than 7° and greater than or equal to 0° in step four.

[0053] Preferably, the remaining hard mask layer is used as the mask for ion implantation, and the sacrificial oxide layer is used as the ion implantation protection layer, and the ion implantation region is formed by self-aligned implantation in step four.

[0054] Preferably, the sacrificial oxide layer and the hard mask layer are removed in the same wet etching in step five, and then the etch stop layer is removed.

[0055] Preferably, the material of the gate dielectric layer in step six is silicon dioxide.

[0056] Preferably, the formation method of the gate dielectric layer in step six includes: forming a first gate oxide layer of 100 to 400 angstroms by low-temperature thermal oxidation; depositing a TEOS oxide layer as the second gate oxide layer, and then performing rapid annealing to densify the TEOS oxide layer.

[0057] Preferably, the temperature of the low-temperature thermal oxidation in step six is 800 to 930 degrees Celsius, and the processing time is less than 30 minutes.

[0058] Preferably, the thickness of the first gate oxide layer in step six is 100 to 400 angstroms.

[0059] Preferably, the doping concentration of the gate polycrystalline layer in step six is greater than 5e19 cm^-3.

[0060] Preferably, the contact holes in step seven are formed by photolithography and etching.

[0061] Preferably, after the contact holes are formed by photolithography and etching in step seven, the remaining photoresist is subjected to resist-implantation to form the source-side heavily doped region.

[0062] As described above, the MOSFET device with a superjunction trench gate and its manufacturing method according to the present invention have the following beneficial effects:

[0063] The structure of the superjunction-trench gate MOSFET device of the present invention increases the length of the drift region, and the bottom drift region is assisted in depletion by the ion implantation region, so the breakdown voltage is improved; at the same time, no new mask is added, and only the etching of the second gate trench is increased. Description of the Drawings

[0064] Figure 1 Schematic diagram of the junction of a MOSFET device with a superjunction trench gate shown as the prior art;

[0065] Figure 2 Schematic diagram of the process flow of the present invention;

[0066] Figure 3 Schematic diagram of forming a body region on an epitaxial layer according to the present invention;

[0067] Figure 4 Schematic diagram of the patterned hard mask layer according to the present invention;

[0068] Figure 5 Schematic diagram of forming the first gate trench according to the present invention;

[0069] Figure 6 Schematic diagram of forming a sidewall according to the present invention;

[0070] Figure 7 Schematic diagram of forming the second gate trench according to the present invention;

[0071] Figure 8 Schematic diagram of forming an ion implantation protection layer according to the present invention;

[0072] Figure 9 Schematic diagram of forming an ion implantation region according to the present invention;

[0073] Figure 10 Schematic diagram of forming an insulating dielectric layer according to the present invention;

[0074] Figure 11 Schematic diagram showing the height of the insulating dielectric layer in the control trench of the present invention;

[0075] Figure 12 Schematic diagram showing the formation of the gate dielectric layer and the gate polysilicon layer of the present invention;

[0076] Figure 13 Schematic diagram showing the formation of the contact hole of the present invention;

[0077] Figure 14 Schematic diagram showing the formation of the source end, the body region end metal layer, and the drain end metal layer of the present invention;

[0078] Figure 15 Schematic diagram showing the id-vd relationship curve of the trench-gate MOS of the present invention;

[0079] Figure 16 Schematic diagram showing the impact ionization of the trench-gate MOS of the present invention. Detailed implementation manners

[0080] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0081] Please refer to Figure 14 , the present invention provides a MOSFET device with a superjunction trench gate, including:

[0082] A substrate 101 of the first conduction type;

[0083] In some embodiments, the first conduction type is N-type; the second conduction type is P-type.

[0084] In some embodiments, the first conduction type is P-type; the second conduction type is N-type.

[0085] An epitaxial layer 102 formed on the substrate 101, the doping concentration of the epitaxial layer 102 is from shallow to deep from bottom to top, and the epitaxial layer 102 serves as the drift region of the device;

[0086] In some embodiments, the doping concentration of the epitaxial layer 102 is 5e15 - 1e17 cm^-3.

[0087] A body region 106 of the second conduction type formed on the surface of the epitaxial layer 102;

[0088] A first gate trench is formed at the top of the body region 106. The depth of the first gate trench is about 4 μm. The first gate trench extends downward from the upper surface of the epitaxial layer 102 through the body region 106. A second gate trench is formed on the epitaxial layer 102 at the bottom of the first gate trench. The depth of the second gate trench is about 2 μm, and the width of the second gate trench is smaller than that of the first gate trench.

[0089] In some embodiments, the distance between the bottom of the first gate trench and the bottom of the body region 106 is greater than 1 μm, and the distance between the bottom of the first gate trench and the top of the substrate 101 is greater than 5 μm.

[0090] In some embodiments, the distance between the bottom of the second gate trench and the top of the substrate 101 is 3.5 to 4.5 μm.

[0091] A second-conductivity-type ion implantation region 103 for assisting the depletion of the drift region is formed below the first gate trench. Among them, the ion implantation region 103 is located at the bottom and side walls of the second gate trench.

[0092] In some embodiments, the implanted ions in the ion implantation region 103 are boron ions.

[0093] In some embodiments, the implantation dose of boron ions is 1e12 to 1e13 cm^-2, and the implantation energy is 50 to 4000 keV.

[0094] An insulating dielectric layer 204 is located in the first gate trench and the second gate trench. The insulating dielectric layer 204 does not completely fill the first gate trench.

[0095] A gate dielectric layer 104 is formed on the surface of the remaining first gate trench, and a gate polysilicon layer 105 that fills the remaining first gate trench. The gate polysilicon layer 105 is heavily doped with the first conductivity type.

[0096] In some embodiments, the material of the gate dielectric layer 104 is silicon dioxide.

[0097] In some embodiments, the gate dielectric layer 104 includes: a first gate oxide layer formed by a low-temperature thermal oxidation method; depositing a TEOS oxide layer as the second gate oxide layer. The growth method of the gate dielectric layer 104 adopts the method of low-temperature oxidation + deposition, which can reduce the thermal process introduced by thermal growth and prevent the lateral diffusion of the ion implantation region 103.

[0098] In some embodiments, the thickness of the first gate oxide layer is 100 to 400 angstroms.

[0099] In some embodiments, the doping concentration of the gate polysilicon layer is greater than 5e19 cm^-3.

[0100] A source-end heavily doped region 108 is formed above the body regions 106 on both sides of the first gate trench. An interlayer dielectric layer 110 is formed on the epitaxial layer 102. A contact hole 109 is formed on the source-end heavily doped region 108. A heavily doped region 107 of the second conductivity type is formed on the body region 106 below the contact hole 109;

[0101] The conductive metal filling the contact hole 109, the source-end and body-region end metal layers 211 and the drain-end metal layer 112 located on the front and back surfaces of the substrate 101 respectively.

[0102] Please refer to Figure 15 , which shows the current-voltage characteristic curve of the superjunction-trench gate MOSFET device of the present invention. Please refer to Figure 16 The ionization collision diagram of the superjunction-trench gate MOSFET device of the present invention. When the total depth of the first and second gate trenches is about 6 μm, the breakdown voltage of the superjunction-trench gate MOSFET device can reach 198 V, and Rsp (parasitic capacitance) is 98.5 mOhm*mm2.

[0103] The structure of the superjunction-trench gate MOSFET device of the present invention increases the length of the drift region. The bottom drift region is assisted in depletion by the ion implantation region 103, thus improving the breakdown voltage. At the same time, no new mask is added, only the etching of the second gate trench is increased.

[0104] Please refer to Figure 2 , the present invention also provides a manufacturing method of the above MOSFET device with a superjunction trench gate, including:

[0105] Step 1: Epitaxially form an epitaxial layer 102 of the first conductivity type on a substrate 101 of the first conductivity type. The doping concentration of the epitaxial layer 102 is from shallow to deep from bottom to top. The epitaxial layer 102 serves as the drift region of the device;

[0106] In some embodiments, the first conductivity type in Step 1 is N-type; the second conductivity type is P-type.

[0107] In some embodiments, the first conductivity type in Step 1 is P-type; the second conductivity type is N-type.

[0108] In some embodiments, the doping concentration of the epitaxial layer 102 in Step 1 is 5e15 - 1e17 cm^-3.

[0109] In some embodiments, the epitaxial layer 102 in Step 1 is formed by at least two epitaxial growths.

[0110] Step 2: Use the ion implantation method to form a body region 106 of the second conductivity type on the surface of the epitaxial layer 102, and then perform thermal diffusion and push on the body region 106 to form as Figure 3The structure shown; place the thermal diffusion promotion process of the body region 106 before the formation of the trench gate structure and the ion implantation region 103 to prevent excessive lateral diffusion of the column region 106 under the thermal promotion process of the ion implantation region 103;

[0111] Step three: form a first gate trench on the top of the body region 106. The depth of the first gate trench is about 4 μm. The first gate trench extends downward from the upper surface of the epitaxial layer 102 through the body region 106. Form a sidewall 202 on the sidewall of the first gate trench to form a structure as shown in Figure 6 the figure; use the sidewall 202 as a mask to etch the epitaxial layer 102 at the bottom of the first gate trench to form a second gate trench, forming a structure as shown in Figure 7 the figure. The depth of the second gate trench is about 2 μm. Then remove the sidewall 202;

[0112] In some embodiments, the method of forming the first gate trench in step three includes: forming an etch stop layer 201, a hard mask layer 502, and a photoresist layer 501 stacked from bottom to top on the body region 106; opening the photoresist layer 501 by photolithography to define the formation position of the first gate trench. Then, use the etching method to form an opening on the hard mask layer 502 to the etch stop layer 201, forming a structure as shown in Figure 4 the figure; remove the photoresist layer 501, and use the hard mask layer 502 as a mask to etch the etch stop layer 201 and the epitaxial layer 102 at the bottom of the opening to form the first gate trench, forming a structure as shown in Figure 5 the figure.

[0113] In some embodiments, the material of the etch stop layer 201 in step three is silicon nitride.

[0114] In some embodiments, the material of the hard mask layer 502 in step three is silicon dioxide.

[0115] In some embodiments, the distance between the bottom of the first gate trench and the bottom of the body region 106 is greater than 1 μm, and the distance between the bottom of the first gate trench and the top of the substrate 101 is greater than 5 μm.

[0116] In some embodiments, the distance between the bottom of the second gate trench and the top of the substrate 101 is 3.5 to 4.5 μm.

[0117] In some embodiments, the sidewall 202 is formed by deposition and etch-back methods in step three.

[0118] Step four: form an ion implantation protection layer 203 on the surfaces of the first gate trench and the second gate trench to form a structure as shown in Figure 8For the structure shown, an ion implantation region 103 of the second conductivity type for assisting in the depletion of the drift region is formed below the first gate trench. Among them, the ion implantation region 103 is located at the bottom and sidewalls of the second gate trench, forming a structure as shown in Figure 9 the structure shown;

[0119] In some embodiments, in step four, while retaining the hard mask layer 502 and the etch stop layer 201, a sacrificial oxide layer is formed by thermal oxidation to repair the defects formed during the gate trench etching. The sacrificial oxide layer serves as the ion implantation protection layer 203.

[0120] In some embodiments, in step four, boron ions are used for ion implantation to form the ion implantation region 103.

[0121] In some embodiments, the ion implantation region 103 in step four is formed by multiple ion implantations.

[0122] In some embodiments, the implantation dose of the boron ions in step four is 1e12 - 1e13 cm^-2, and the implantation energy is 50 - 4000 KeV.

[0123] In some embodiments, in step four, ion implantation at an angle less than 7° and greater than or equal to 0° is used to form the ion implantation region 103.

[0124] In some embodiments, in step four, the retained hard mask layer 502 is used as the mask for ion implantation, and the sacrificial oxide layer is used as the ion implantation protection layer 203. Self-aligned implantation is used to form the ion implantation region 103.

[0125] Step five: Remove the ion implantation protection layer 203, which can further save manufacturing costs, and form an insulating dielectric layer 204 in the first gate trench and the second gate trench. The insulating dielectric layer 204 does not completely fill the first gate trench. For example, the insulating dielectric layer 204 can be formed by deposition, forming a structure as shown in Figure 10 the structure shown, and then methods such as chemical mechanical planarization polishing and etching are used to control the height of the insulating dielectric layer 204 in the gate trench, forming a structure as shown in Figure 11 the structure shown;

[0126] In some embodiments, in step five, the sacrificial oxide layer and the hard mask layer 502 are removed in the same wet etching, and then the etch stop layer 201 is removed.

[0127] Step six: A gate dielectric layer 104 is formed on the surface of the remaining first gate trench, and then a gate polysilicon layer 105 filling the remaining first gate trench is formed. The gate polysilicon layer 105 is heavily doped with the first conductivity type, forming a structure as shown in Figure 12 the structure shown;

[0128] In some embodiments, the material of the gate dielectric layer 104 in step six is silicon dioxide.

[0129] In some embodiments, the method for forming the gate dielectric layer 104 in step six includes: forming a first gate oxide silicon layer with a thickness of 100 to 400 angstroms by using a low-temperature thermal oxidation method; depositing a TEOS oxide silicon layer as the second gate oxide layer, and then performing rapid annealing to densify the TEOS oxide silicon layer. The growth mode of the gate dielectric layer 104 adopts the mode of low-temperature oxidation + deposition, which can reduce the thermal process introduced by thermal growth and prevent the lateral diffusion of the ion implantation region 103.

[0130] In some embodiments, the temperature of the low-temperature thermal oxidation in step six is 800 to 930 degrees Celsius, and the processing time is less than 30 minutes.

[0131] In some embodiments, the thickness of the first gate oxide silicon layer in step six is 100 to 400 angstroms.

[0132] In some embodiments, the doping concentration of the gate polycrystalline layer in step six is greater than 5e19 cm^-3.

[0133] Step seven: Form source-end heavily doped regions 108 above the body regions 106 on both sides of the first gate trench, form an interlayer dielectric layer 110 on the epitaxial layer 102, form contact holes 109 on the source-end heavily doped regions 108, perform a heavy doping implantation of the second conductivity type on the body regions 106 below the contact holes 109, and form heavily doped regions 107 through thermal diffusion, while activating the impurity implantation of the heavy doping implantation.

[0134] In some embodiments, the contact holes 109 in step seven are formed by using photolithography and etching methods.

[0135] In some embodiments, after forming the contact holes 109 by photolithography and etching in step seven, the remaining photoresist is subjected to resist-implantation to form the source-end heavily doped regions 108.

[0136] Step eight: Form a conductive metal to fill the contact holes 109, form the structure as shown in Figure 13 After that, form a source-end, body-region-end metal layer 211 and a drain-end metal layer 112, and form the structure as shown in Figure 14 Shown.

[0137] Please refer to Figure 15 which shows the current-voltage characteristic curve of the superjunction-trench gate MOSFET device of the present invention. Please refer to Figure 16 The ionization collision diagram of the superjunction-trench gate MOSFET device of the present invention. When the total depth of the first and second gate trenches is about 6 um, the breakdown voltage of the superjunction-trench gate MOSFET device can reach 198 V, and the Rsp (parasitic capacitance) is 98.5 mOhm*mm2.

[0138] The superjunction-trench gate MOSFET device structure of the present invention increases the length of the drift region, and the drift region at the bottom is assisted in depletion by the ion implantation region 103, thus improving the breakdown voltage. At the same time, no new mask is added, and only the etching of the second gate trench is increased.

[0139] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0140] In summary, the superjunction-trench gate MOSFET device structure of the present invention increases the length of the drift region, and the drift region at the bottom is assisted in depletion by the ion implantation region, thus improving the breakdown voltage; at the same time, no new mask is added, and only the etching of the second gate trench is increased. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0141] The above embodiments are only used to illustrate the principle and its effects of the present invention by way of example, rather than to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A MOSFET device with a superjunction trench gate, characterized in that: include: a substrate of a first conductivity type; An epitaxial layer formed on the substrate, wherein the doping concentration of the epitaxial layer increases from shallow to deep from bottom to top; a body region of a second conductivity type formed on a surface of the epitaxial layer; a first gate trench formed on the top of the body region, the first gate trench extending downward from the upper surface of the epitaxial layer through the body region, a second gate trench formed on the epitaxial layer at the bottom of the first gate trench, the second gate trench having a width smaller than the first gate trench; An ion implantation region of the second conductivity type for assisting depletion of the drift region is formed below the first gate trench, wherein the ion implantation region is located at the bottom and sidewalls of the second gate trench; an insulating dielectric layer located in the first gate trench and the second gate trench, wherein the insulating dielectric layer does not completely fill the first gate trench; a gate dielectric layer formed on the surface of the remaining first gate trench, and a gate polysilicon layer filling the remaining first gate trench, wherein the gate polysilicon layer is heavily doped with a first conductivity type; A source end heavily doped region is formed above the body region on both sides of the first gate trench, an interlayer dielectric layer is formed on the epitaxial layer, a contact hole is formed on the source end heavily doped region, and a heavily doped region of the second conductivity type is formed on the body region below the contact hole; The conductive metal filling the contact hole is respectively located at the source end, the body region end metal layer and the drain end metal layer on the front side and the back side of the substrate.

2. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The first conductivity type is N type; the second conductivity type is P type.

3. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The first conductivity type is P type; the second conductivity type is N type.

4. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The doping concentration of the epitaxial layer is 5e15 to 1e17 cm^-3.

5. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The distance between the bottom of the first gate trench and the bottom of the body region is greater than 1 um, and the distance between the bottom of the first gate trench and the top of the substrate is greater than 5 um.

6. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The distance between the bottom of the second gate trench and the top of the substrate is 3.5 to 4.5 um.

7. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The implanted ions in the ion implantation region are boron ions.

8. The MOSFET device with super junction trench gate according to claim 7, characterized in that: The implantation dose of the boron ions is 1e12-1e13 cm^-2, and the implantation energy is 50-4000 KeV.

9. The MOSFET device with super junction trench gate according to claim 9, characterized in that: The material of the gate dielectric layer is silicon dioxide.

10. The MOSFET device with super junction trench gate according to claim 11, characterized in that: The gate dielectric layer comprises: a first gate silicon oxide layer formed by a low-temperature thermal oxidation method; and a TEOS silicon oxide layer deposited as a second gate oxide layer.

11. The MOSFET device with super junction trench gate according to claim 12, characterized in that: The thickness of the first gate silicon oxide layer is 100 to 400 angstroms.

12. The MOSFET device with super junction trench gate according to claim 1, characterized in that: The doping concentration of the gate polycrystalline layer is greater than 5e19 cm^-3.

13. A method for manufacturing a MOSFET device having a superjunction trench gate, characterized in that: At least: Step 1: epitaxially forming an epitaxial layer of the first conductivity type on a substrate of the first conductivity type, wherein the doping concentration of the epitaxial layer increases from shallow to deep from bottom to top; Step 2: forming a body region of the second conductivity type on the surface of the epitaxial layer by an ion implantation method, and then thermally diffusing the body region; Step 3, forming a first gate trench on the top of the body region, wherein the first gate trench extends downward from the upper surface of the epitaxial layer through the body region, forming a sidewall on the sidewall of the first gate trench, etching the epitaxial layer at the bottom of the first gate trench using the sidewall as a mask to form a second gate trench, and then removing the sidewall; Step 4: forming an ion implantation protection layer on the surfaces of the first gate trench and the second gate trench, and forming an ion implantation region of the second conductivity type for auxiliary drift region depletion below the first gate trench, wherein the ion implantation region is located at the bottom and sidewalls of the second gate trench; Step 5: removing the ion implantation protection layer to form an insulating dielectric layer located in the first gate trench and the second gate trench, wherein the insulating dielectric layer does not completely fill the first gate trench; Step 6: forming a gate dielectric layer on the surface of the remaining first gate trench, and then forming a gate polysilicon layer filling the remaining first gate trench, wherein the gate polysilicon layer is heavily doped with the first conductivity type; Step 7: forming a source end heavily doped region above the body region on both sides of the first gate trench, forming an interlayer dielectric layer on the epitaxial layer, forming a contact hole on the source end heavily doped region, performing a heavily doped implant of a second conductivity type on the body region below the contact hole, forming a heavily doped region through thermal diffusion, and activating the impurity implantation of the heavily doped implant; Step eight: forming a conductive metal to fill the contact hole, and then forming a source terminal, a body terminal metal layer and a drain terminal metal layer.

14. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The first conductivity type in step 1 is N type; the second conductivity type is P type.

15. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The first conductivity type in step 1 is P type; the second conductivity type is N type.

16. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The doping concentration of the epitaxial layer in step 1 is 5e15 to 1e17 cm^-3.

17. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The epitaxial layer in step 1 is formed by at least two epitaxy operations.

18. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The method for forming the first gate trench in step three includes: forming an etch stop layer, a hard mask layer and a photoresist layer stacked in sequence from bottom to top on the body region; photolithographically opening the photoresist layer to define the formation position of the first gate trench, and then using an etching method to form an opening on the hard mask layer to the etch stop layer; removing the photoresist layer, and etching the etch stop layer and the epitaxial layer at the bottom of the opening using the hard mask layer as a mask to form the first gate trench.

19. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 18, characterized in that: The material of the etching stop layer in step three is silicon nitride.

20. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 18, characterized in that: The material of the hard mask layer in step three is silicon dioxide.

21. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step three, the distance between the bottom of the first gate trench and the bottom of the body region is greater than 1 um, and the distance between the bottom of the first gate trench and the top of the substrate is greater than 5 um.

22. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step three, the distance between the bottom of the second gate trench and the top of the substrate is 3.5 to 4.5 um.

23. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step three, the sidewalls are formed by deposition and back etching.

24. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step 4, a sacrificial oxide layer is formed by thermal oxidation while retaining the hard mask layer and the etch stop layer, and defects formed by etching the gate trench are repaired by thermal oxidation. The sacrificial oxide layer serves as an ion implantation protection layer.

25. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step 4, boron ions are used for ion implantation to form the ion implantation area.

26. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The ion implantation region in step 4 is formed by multiple ion implantations.

27. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 25, characterized in that: The implantation dose of the boron ions in step 4 is 1e12-1e13 cm^-2, and the implantation energy is 50-4000 KeV.

28. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: In step 4, ion implantation at an angle less than 7° and greater than or equal to 0° is used to form the ion implantation area.

29. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 18, characterized in that: In step 4, the retained hard mask layer is used as the mask for ion implantation, the sacrificial oxide layer is used as the ion implantation protection layer, and the ion implantation region is formed by self-aligned implantation.

30. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 29, characterized in that: In step five, the sacrificial oxide layer and the hard mask layer are removed in the same wet etching process, and then the etch stop layer is removed.

31. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The material of the gate dielectric layer in step six is ​​silicon dioxide.

32. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 31, characterized in that: The method for forming the gate dielectric layer in step six includes: forming a first gate silicon oxide layer of 100 to 400 angstroms by a low-temperature thermal oxidation method; depositing a TEOS silicon oxide layer as a second gate oxide layer, and then performing rapid annealing to densify the TEOS silicon oxide layer.

33. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 32, characterized in that: The temperature of the low temperature thermal oxidation in step six is ​​800 to 930 degrees Celsius, and the processing time is less than 30 minutes.

34. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 32, characterized in that: The thickness of the first gate silicon oxide layer in step six is ​​100 to 400 angstroms.

35. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The doping concentration of the gate polycrystalline layer in step six is ​​greater than 5e19 cm^-3.

36. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 13, characterized in that: The contact hole in step seven is formed by photolithography and etching.

37. The method for manufacturing a MOSFET device with a super junction trench gate according to claim 36, characterized in that: In step seven, the remaining photoresist after the contact hole is formed by photolithography and etching is injected with adhesive to form the heavily doped source end region.

Images