Method for suppressing voltage overshoot

Abstract

The invention relates to a method for suppressing voltage overshoot. Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for electric vehicles. The disclosed techniques may minimize the impact on turn-on and turn-off losses while reducing gate and drain voltage spikes during device switching. A fast / slow cell design including a shield gate MOSFET controls gate-drain capacitance and gate resistance to optimize suppression of voltage overshoot.

Description

Technical Field

[0001] This specification relates to high-power integrated circuit modules. More specifically, this specification relates to the suppression of voltage spikes in high-power integrated circuit modules. Background Art

[0002] Semiconductor device assemblies (such as chip assemblies) including high-power semiconductor devices can be used in various applications, including electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications. High-power modules can operate at voltages, for example, in excess of 100V and can carry large currents (e.g., 200A), as opposed to computer applications that operate at voltages in the range of about 1V to about 15V, for example. Power transistors can include, for example, insulated gate bipolar transistors (IGBTs), shield-gate metal-oxide-semiconductor field-effect transistors (shield-gate MOSFETs), and double-diffused metal-oxide-semiconductor (DMOS) devices. Some shield-gate MOSFETs can be formed in a silicon carbide (SiC) substrate. Summary of the Invention

[0003] In some aspects, the techniques described herein relate to an apparatus that includes: a first four-terminal device having a first source, a first gate, a first drain, and a first shield; a second four-terminal device having a second source, a second gate, a second drain, and a second shield, wherein: the first drain is coupled to the second drain; the first gate is coupled to the second gate; and the first shield and the first source are coupled to the second source; and a gate resistor coupled between the first gate and the second gate, the gate resistor being configured to reduce voltage overshoot during a switching event.

[0004] In some aspects, the techniques described herein relate to a circuit that includes: a plurality of first units, each first unit including a first transistor having a first source, a first gate, and a first drain, the first transistor being further configured with a first shield terminal coupled to the first source; and a plurality of second units, each second unit including a second transistor having a second source, a second gate, and a second drain, the second transistor being further configured with a second shield terminal.

[0005] In some aspects, the techniques described herein relate to a method that includes: forming a plurality of first transistors and a plurality of second transistors in a die; configuring the plurality of first transistors to have a lower power loss than the plurality of second transistors; and configuring the plurality of second transistors to have a larger RC time constant than the plurality of first transistors. Brief Description of the Drawings

[0006] Figure 1Schematic diagram of a unit including a fast-switching device and a slow-switching device according to a first specific implementation of the present disclosure.

[0007] Figure 2 Schematic diagram of a unit including a fast-switching device and a slow-switching device according to a second specific implementation of the present disclosure.

[0008] Figure 3 Top plan view of a die showing the connection to the active area according to a specific implementation of the present disclosure.

[0009] Figure 4 According to a specific implementation of the present disclosure Figure 3 Top plan view of fast and slow cells within the active area shown.

[0010] Figure 5 According to a specific implementation of the present disclosure along Figure 4 Cross-sectional view along the cut line A-A' of the active area shown.

[0011] Figure 6 According to a specific implementation of the present disclosure along Figure 4 Cross-sectional view along the cut line B-B' of the active area shown.

[0012] Figure 7 Schematic diagram of a unit including a fast-switching device and a slow-switching device according to a second specific implementation of the present disclosure.

[0013] Figure 8A Plot showing the simulated behavior of a first switching unit during an on-event according to a specific implementation of the present disclosure.

[0014] Figure 8B Plot showing the simulated behavior of a first switching unit during an off-event according to a specific implementation of the present disclosure.

[0015] Figure 9A Plot showing the simulated behavior of a second switching unit during an on-event according to a specific implementation of the present disclosure.

[0016] Figure 9B Plot showing the simulated behavior of a second switching unit during an off-event according to a specific implementation of the present disclosure.

[0017] Figure 10 Flowchart showing a method of configuring fast and slow cells for a die to suppress voltage oscillation according to a specific implementation of the present disclosure.

[0018] Figure 11 Series of bar charts showing the simulated behavior of a switching unit as a function of area ratio according to a specific implementation of the present disclosure.

[0019] Figure 12A and Figure 12B and Figure 12C are plots showing the simulated behavior of the switching unit during an on-event for three different area ratios, according to specific embodiments of the present disclosure.

[0020] When read in conjunction with the Figure 1 accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. Note that, in accordance with industry practice, the various feature portions are not necessarily drawn to scale. For the sake of clarity in discussion, the dimensions of the various features may be arbitrarily increased or decreased. In the drawings, the same reference symbols may indicate the same and / or similar components (elements, structures, etc.) in different views. The drawings generally illustrate, by way of example and not limitation, the various specific embodiments discussed in the present disclosure. The reference symbols shown in one drawing may not be repeated for the same and / or similar elements in the associated views. The reference symbols repeated in multiple drawings may not be specifically discussed with respect to each of these drawings, but rather provide context between the associated views. Additionally, not all similar elements in the drawings are specifically referenced with reference symbols when showing multiple instances of the element. Detailed Description

[0021] When the power to a shield gate MOSFET switches between an on state (low voltage, high current) and an off state (high voltage, low current), there may be a brief time interval during the transition when high voltage and high current coexist. This situation results in power losses associated with the high voltage (according to P = V 2 / R), and power losses associated with the high current (according to P = I 2 R). Faster switching results in less power loss. However, voltage spikes may also occur during power switching, exceeding the rated voltage of the device. Voltage spikes can be caused, for example, by parasitic inductance. A voltage overshoot event manifests as a voltage spike, followed by ringing (e.g., voltage oscillations) or fluctuations, which decrease in amplitude over a short period of time. Faster switching can exacerbate the voltage spike, resulting in a higher amplitude, which may also take longer to decay.

[0022] Voltage overshoot can be suppressed by introducing a resistor-capacitor (RC) buffer to slow down the switching and thereby reduce the initial voltage spike. However, slower switching increases power loss and reduces efficiency. Another problem with this method is that the buffer can be designed as an external component applied to the entire die, which further increases component cost and power loss within the entire high-power module.

[0023] The present disclosure presents a new method for solving voltage overshoot while minimizing power loss, without relying on the use of RC buffers or buffer capacitors that reduce the switching speed of various high-power semiconductor devices. In some specific implementations, suppressing or preventing voltage overshoot is necessary, while minimizing power loss, although desirable, may be relatively less of a concern. Using the new method described herein, voltage overshoot can be suppressed without slowing down the overall high-power switching operation. Instead, a dedicated portion of the high-power module can be slowed down by various other means to suppress voltage overshoot. At the same time, other portions of the high-power module can remain configured for fast switching. The techniques described below can be applied to any type of power switch, such as, for example, silicon-based MOSFETs, IGBTs, and SiC MOSFETs, as well as shield-gate MOSFETs.

[0024] Figure 1 A first specific implementation of unit 100 for preventing voltage overshoot according to some specific implementations of the present disclosure is shown. Unit 100 may have a high gate RC time constant that slows down the switching speed of unit 100. Externally, unit 100 appears as a single three-terminal device with an external source terminal S1, an external drain terminal D1, and an external gate terminal G1. Internally, unit 100 includes a slow transistor 102 coupled in parallel with a fast transistor 104. The fast transistor 104 may be implemented as any fast-switching device, and the slow transistor 102 may be implemented as any slow-switching device. In some specific implementations, the components (e.g., transistors, resistors) of unit 100 may be discrete devices. In some specific implementations, such components of unit 100 may be integrated circuit devices or monolithic implementations.

[0025] In some examples, both the slow transistor 102 and the fast transistor 104 may be implemented using shield-gate MOSFETs. Each shield-gate MOSFET in unit 100 is a four-terminal device including a source terminal s, a drain terminal d, a gate terminal g, and a shield terminal h. In unit 100, the corresponding source terminals of the slow transistor 102 and the fast transistor 104 are coupled together at a common source connection S1, and the corresponding drain terminals are coupled together at a common drain connection D1. Additionally, in unit 100, the shield terminal h of the slow transistor 102 is coupled to the gate terminal g, and the shield terminal h of the fast transistor 104 is coupled to the source terminal s. The gate resistor r G may optionally be coupled between the corresponding gate terminals of the slow transistor 102 and the fast transistor 104, which are coupled together at a common gate connection G1. The shield-gate connection increases the gate-drain capacitance. Both the shield-gate connection and the increase in the gate resistor r G contribute to slowing down unit 100 by increasing the gate RC time constant. In some specific implementations, rG It can be set to 10 ohms, for example, in the range of about 4 ohms to about 20 ohms. In some specific embodiments, r G can be omitted. By making the r value of one cell different from that of another cell within the die, different cells 100 can have different gate RC time constants, such that some of the cells 100 are fast cells and other cells are slow cells. G Value different, different units 100 can have different gate RC time constants, so that some of the units 100 are fast units and other units are slow units.

[0026] Figure 2 A second specific embodiment of the unit 200 for preventing voltage overshoot according to some specific embodiments of the present disclosure is shown. The unit 200 is similar to the unit 100 in some aspects, but it will become apparent that the internal connections between the two types of units are different. Similar to the unit 100, the unit 200 can have a high gate RC time constant that slows down the switching speed of the unit 200. Externally, the unit 200 appears as a three-terminal device with an external source terminal S2, an external drain terminal D2, and an external gate terminal G2. Internally, the unit 200 includes a slow transistor 202 coupled in parallel with a fast transistor 204. The fast transistor 204 can be implemented as any fast-switching device, while the slow transistor 202 can be implemented as any slow-switching device. In some specific embodiments, the components (e.g., transistors, resistors) of the unit 200 can be discrete devices. In some specific embodiments, such components of the unit 200 can be integrated circuit devices.

[0027] In some examples, both the slow transistor 202 and the fast transistor 204 can be implemented using shield-gate MOSFETs. Each shield-gate MOSFET in the unit 200 is a four-terminal device including a source terminal s, a drain terminal d, a gate terminal g, and a shield terminal h. In the unit 200, the corresponding source terminals of the slow transistor 202 and the fast transistor 204 are coupled together at the external source terminal S2, and the corresponding drain terminals are coupled together at the external drain terminal D2. In addition, in the unit 200, the shield terminals of the slow transistor 202 and the fast transistor 204 are coupled to the respective source terminals s. The shield-source connection differentiates the unit 200 from the unit 100, which is characterized by a shield-gate connection. The gate resistor R G can be coupled between the gate terminal g of the slow transistor 202 and the gate terminal g of the fast transistor 204, and these gate terminals are coupled together at the external gate terminal G2. The addition of the gate resistor R G helps to slow down the speed of the unit 200. The value of the gate resistor is another difference between the unit 200 and the unit 100. In some specific embodiments, the R in the unit 200 G can be set to about 160 ohms, for example, in the range of about 50 ohms to about 400 ohms, such that R G >rG 。

[0028] In other examples, the slow transistor 202 and the fast transistor 204 may not be implemented as shield-gate MOSFETs. Instead, the slow transistor 202 and the fast transistor 204 may be planar or simple trench MOSFETs formed on a silicon or SiC substrate. When using a planar or simple trench MOSFET, the configuration shown is modified by omitting the shield terminal h. Figure 2 In this configuration, the difference between the slow transistor and the fast transistor can be determined by adding the gate resistor R G .

[0029] Thus, a fast / slow cell design (such as cell 100 or cell 200) can reduce gate voltage spikes and drain voltage spikes by adjusting the gate-drain capacitance (C gd ), the gate resistor (R g ), or both. By adjusting the gate RC time constant in this way, cell 100 and / or cell 200 can be configured as fast cells or slow cells and replicated on the die. In some specific implementations, due to differences in the shield connection, cell 200 can be faster than cell 100. However, depending on the values of R G and r G , in some specific implementations, cell 100 can be faster than cell 200. In some specific embodiments, R G and r G can be set differently for different cell groups such that the statistical speed distribution of cell 100 overlaps with the statistical speed distribution of cell 200. This multi-cell design introduces flexibility within the die and thus avoids having to correct the entire die, which might otherwise be limited to a single cell design.

[0030] In some specific implementations, most of the cells in a semiconductor die can be fast cells optimized for fast switching and minimal power loss, while a minority of the cells in the semiconductor die are slow cells with a high gate RC time constant or a high gate drive resistance. Additionally, or as an alternative to varying the gate resistance between fast cells and slow cells, the fast cells can be coupled to a gate bus separate from the gate bus of the slow cells. The gate bus can be connected to a single input control signal to introduce a dedicated gate resistance to control the switching speed, thereby separating the speed of the fast cells from the speed of the slow cells.

[0031] In one example, a silicon MOSFET coupled in series with a silicon carbide JFET as part of a cascode circuit can exhibit a drain voltage overshoot. Instead of adding an RC buffer to the cascode circuit, the silicon MOSFET can be implemented as a pair of fast and slow shield-gate MOSFETs coupled in parallel, with a shield-gate connection on the slow device to increase the gate-drain capacitance, as in cell 100. A gate resistor can be introduced to further increase the gate RC time constant. Alternatively, both of the pair of shield-gate MOSFETs can have a shield-source connection as in cell 200, with a gate resistance R G higher than the gate resistance r G .

[0032] Figure 3 FIG. shows a layout of die 300 according to some embodiments of the present disclosure. Die 300 includes metal lines that provide connections to, for example, cell 100 or cell 200. The metal lines surround an active area 302 in which transistors are formed. In some embodiments, die 300 encompasses an active area 302 of from about 1.5 square millimeters to 5.0 square millimeters. In some embodiments, the metal lines include two gate metal feeders - an internal "fast" gate metal feeder 304 and an external "slow" gate metal feeder 306. The fast gate metal feeder 304 and the slow gate metal feeder 306 can couple several portions of the active area 302 to a gate pad 308 shown in the lower left corner of die 300. In some embodiments, a resistor block disposed under or adjacent to the gate pad 308 includes an array of shield trenches outside the active area 302. In some embodiments, the internal fast gate metal feeder 304 is directly connected to the gate pad 308 and to an active cell (e.g., cell 200), where a shield terminal h is coupled to a source terminal s. In some embodiments, the external slow gate metal feeder 306 is connected to the gate pad 308 through a resistor block and to an active cell (e.g., cell 100), where a shield terminal h is coupled to a gate terminal g.

[0033] Figure 4 FIG. shows a top plan view of a layout of an active cell region 400 according to some embodiments of the present disclosure. The active cell region 400 can be located in the active area 302. In one example, the active cell region 400 is sized from about 20 mm 2 to about 30 mm 2Within a range. In some specific embodiments, the active cell region 400 includes slow cells distributed among fast cells. The slow cells can be identified by slow cell gate structures 402 (four are shown), which are disposed between groups of fast cells identified by fast cell gate structures 404 (eight groups are shown). The slow cell gate structures 402 can extend across the entire active cell region 400, while the fast cell gate structures 404 can be shorter and extend less than half of the active cell region 400. In the example shown, each group of four fast cell gate structures 404 is coupled to a gate contact 406 (eight are shown). A metal gate bus 408 can be formed on each of the gate contacts 406 and can be coupled to each gate contact. The polysilicon gate bus 410 can be directly coupled to each of the slow cell gate structures 402. The materials used to fabricate the metal gate bus 408 and the polysilicon gate bus 410 can further control the speed of the devices coupled to the buses. For example, the polysilicon gate bus 410 can provide a higher resistance connectivity for the slow cells than the metal gate bus 408 coupled to the fast cells. To further control the speed of the cells, the fast cell gate resistor 412 can be coupled to the fast cell gate structures 404 via the metal gate bus 408; and the slow cell gate resistor 414 can be coupled to the slow cell gate structures 402 via the polysilicon gate bus 410.

[0034] Figure 5 FIG. 500 is a cross-sectional view of the active cell region 400 along the Figure 4 cutting line A-A' shown in accordance with some specific embodiments of the present disclosure. In this example, the cutting line A-A' intersects approximately 2-1 / 2 groups of fast cells and two slow cells. Figure 5It is shown that the active cell region 400 is constructed on a substrate 502 (e.g., a silicon substrate or other semiconductor substrate, e.g., a silicon carbide (SiC) substrate). In some specific implementations, non-semiconductor substrate materials such as sapphire, glass, polymers, etc. can be used. Transistor source and drain regions are formed in the substrate 502 but are not shown here to focus on the gate structure. The slow cell gate structure 402 and the fast cell gate structure 404 can be formed together in the substrate 502 in the following manner: for example, by etching to form trenches, and then lining the trenches with an insulator (e.g., oxide), and filling the trenches with a conductive material (e.g., polysilicon or metal). In some specific implementations, the trenches can be equally spaced and of equal size. Then, a polysilicon surface layer 504 can be formed on the filled trenches and patterned to contact only the fast cell gate structure 404 and not the slow cell gate structure 402. The polysilicon surface layer 504 thus forms the gate contact 406. In some specific implementations, the central portion 506 of the polysilicon surface layer 504 can be recessed relative to the end portions 508. Then, a thin interlayer dielectric (ILD) 510 can be grown conformally with the polysilicon surface layer 504. Then, openings can be formed in the ILD 510 while the remaining ILD 510 covers the end portions 508 of the polysilicon surface layer 504 and the slow cell gate structure 402. Finally, a gate metal layer forming the metal gate bus 408 can be conformally deposited on the gate contact 406 to reach the fast cell gate structure 404. The recessed pattern of the polysilicon surface layer 504 replicated in the upper surface of the metal gate bus 408 can be removed in a subsequent planarization operation.

[0035] Figure 6 A cross-sectional view 600 of the active cell region 400 along the Figure 4 cutting line B-B' shown in accordance with some specific implementations of the present disclosure is shown. The cutting line B-B' intersects two of the slow cell gate structures 402. Since the cutting line B-B' is located in the region between the rows of the gate contacts 406, the cutting line B-B' does not intersect any of the fast cell gate structures 404. Thus, the cross-sectional view 600 shows the substrate 502 and two filled trenches formed in the substrate 502, and the two filled trenches are the slow cell gate structures 402. A blanket polysilicon surface layer 504, a blanket ILD layer 510, and the metal gate bus 408 are formed on the slow cell gate structures 402.

[0036] Figure 7 A schematic diagram of a cascode circuit 700 for preventing voltage overshoot in accordance with some specific implementations of the present disclosure is shown. In some specific implementations, the cascode circuit 700 can be implemented as a JFET-based cascode circuit. As Figure 7As shown, the cascode circuit 700 may include a high-voltage JFET chip 702 formed on a SiC substrate and a low-voltage MOSFET chip 704 formed on a silicon substrate. The high-voltage JFET chip 702 and the low-voltage MOSFET chip 704 are three-terminal devices each including a source terminal s, a drain terminal d, and a gate terminal g. The cascode circuit 700 may further include a packaged sub-circuit chip 706. In some specific embodiments, the packaged sub-circuit chip 706 includes a source terminal s, a drain terminal d, a gate terminal g, and a Kelvin return terminal k of the gate, and these terminals serve as external terminals of the cascode circuit 700. The packaged sub-circuit chip 706 may further include internal components, for example, parasitic passive components such as resistors, inductors, and capacitors. Figure 7 Additional resistors and inductors coupled between the respective chips are clearly shown. In some specific embodiments, the components (e.g., transistors, resistors) of the cascode circuit 700 may be discrete devices. In some specific embodiments, such components of the cascode circuit 700 may be integrated circuit devices.

[0037] Figure 8A and Figure 8B show simulation results of the cascode circuit described above with reference to Figure 7 and Figure 1 in accordance with some specific embodiments of the present disclosure. In Figure 8A and Figure 8B the low-voltage MOSFET chip 704 of the high-power cascode circuit 700 is implemented together with the cell 100. That is, the low-voltage MOSFET chip 704 includes a fast transistor 104 and a slow transistor 102 in parallel, where the fast device dominates the turn-on, and the slow device dominates the turn-off. Figure 8A shows a plot 800 of voltage and current as a function of time during turn-on. In the simulation, the drain current I D is set to 50 A. During the turn-on event, as the switching voltage V SW decreases, the drain current I D suddenly turns on and experiences a current overshoot 802. Figure 8A indicates that the cell 100 will effectively attenuate the overshoot 802 in about 0.025 μs.

[0038] Figure 8B shows a plot 810 of voltage and current as a function of time during turn-off of the cascode circuit 700 implemented together with the cell 100. During the turn-off event, as the drain current I D decreases to zero, the switching voltage V SW increases and experiences a voltage overshoot 812. Figure 8BIt is shown that unit 100 will effectively cause the voltage overshoot 812 to decay within about 0.05 μs. The overshoot in the turn-off current is attenuated within about the same time interval.

[0039] Figure 9A and Figure 9B shows simulation results of the cascode circuit described above with reference to some specific implementations of the present disclosure. Figure 7 and Figure 2 In Figure 9A and Figure 9B a low-voltage MOSFET chip 704 of the high-power cascode circuit 700 is implemented together with unit 200. That is, the low-voltage MOSFET chip 704 includes a fast transistor 204 and a slow transistor 202 in parallel, where the fast device dominates the turn-on and the slow device dominates the turn-off. Figure 9A shows a plot 900 of voltage and current as a function of time in microseconds during the turn-on of the high-power cascode circuit implemented together with unit 200. In the simulation, the drain current is set to 50 A. During the turn-on event, as the switching voltage V SW decreases, the drain current I D suddenly turns on and experiences a current overshoot 902. Figure 9A It is shown that unit 200 will effectively attenuate the overshoot 902 within about 0.01 μs.

[0040] Figure 9B shows a plot 910 of voltage and current as a function of time in microseconds during the turn-off of the cascode circuit 700 implemented together with unit 200. During the turn-off event, as the drain current I D drops to zero, the switching voltage V SW increases and experiences a voltage overshoot 912. Figure 9B It is shown that unit 200 will effectively cause the voltage overshoot 912 to decay within about 0.06 μs. The overshoot in the turn-off current is attenuated within about the same time interval.

[0041] Figure 10 is a flowchart of a method 1000 for configuring a fast unit and a slow unit to reduce voltage overshoot for a die (e.g., die 300) according to some specific implementations of the present disclosure. According to some specific implementations described above with reference to Figures 1 to 6 the operations 1002 - 1008 of method 1000 can be performed to configure die 300. The operations of method 1000 can be performed in a different order or not performed, depending on the specific application. It should be noted that method 1000 may not configure die 300 exactly as desired. Therefore, it should be understood that additional processes may be provided before, during, or after method 1000, and some of these additional processes may be briefly described herein.

[0042] At 1002, method 1000 includes arranging a plurality of fast cells and slow cells on die 300. A single semiconductor die 300 for use in high power applications can be configured to have various arrangements of fast cells and slow cells. In some embodiments, slow cells can be disposed between fast cells. For example, several slow cell gate structures 402 can be interleaved with fast cell gate structures 404 to intersperse fast cells and slow cells as shown. In some embodiments, the die can be segmented. For example, fast cells and slow cells can each be arranged in blocks such that slow cells are isolated in a particular region of the die, separate from the area where fast cells are concentrated. Figure 4 At 1004, method 1000 includes configuring a high gate RC time constant for the slow cells. Increasing the gate RC time constant can be achieved by increasing the gate resistance r or R, or by increasing the gate-drain capacitance C via a shield-gate connection. In some embodiments, both the gate resistance and the gate-drain capacitance can be increased to slow down the switching rate. At the same time, there is no need to down-tune the speed of the fast cells because the fast cells can be configured and controlled separately from the slow cells.

[0043] At 1006, method 1000 includes configuring the fast cells to achieve low power loss. For example, the speed of the fast cells can be increased by adjusting the gate resistance. During a switching event, the current will then decrease quickly enough such that there is little overlap between high current values and high voltage values, which will limit power dissipation in the form of I²R losses. G or R G or by increasing the gate-drain capacitance C via a shield-gate connection. GD At 1008, method 1000 includes allocating portions of die 300 to include a specified area ratio of fast cells to slow cells. The area ratio can be defined as the ratio of the die area containing fast cells to the die area containing slow cells. The area ratio can be configured in different portions of die 300 as needed to balance high switching speed and low power loss during switching events within each die. In some embodiments, changing the area ratio can achieve a target capacitance. In some embodiments, the ratio of fast cells to slow cells can be equal, for example, a 50 / 50 or 1:1 ratio. In some embodiments, the ratio can be closer to 10:1 such that the percentage of slow cells can be from about 10% to about 15%. In some embodiments, the size of the fast cells can be different from the size of the slow cells. For example, the fast cells can be about 10% to about 50% larger than the slow cells. In some embodiments, the fast cells can be about 25% larger than the slow cells.

[0044] At 1006, method 1000 includes configuring the fast cells to achieve low power loss. For example, the speed of the fast cells can be increased by adjusting the gate resistance. During a switching event, the current will then decrease quickly enough such that there is little overlap between high current values and high voltage values, which will limit power dissipation in the form of I²R losses. 2 R losses form of power dissipation.

[0045] At 1008, method 1000 includes allocating portions of die 300 to include a specified area ratio of fast cells to slow cells. The area ratio can be defined as the ratio of the die area containing fast cells to the die area containing slow cells. The area ratio can be configured in different portions of die 300 as needed to balance high switching speed and low power loss during switching events within each die. In some embodiments, changing the area ratio can achieve a target capacitance. In some embodiments, the ratio of fast cells to slow cells can be equal, for example, a 50 / 50 or 1:1 ratio. In some embodiments, the ratio can be closer to 10:1 such that the percentage of slow cells can be from about 10% to about 15%. In some embodiments, the size of the fast cells can be different from the size of the slow cells. For example, the fast cells can be about 10% to about 50% larger than the slow cells. In some embodiments, the fast cells can be about 25% larger than the slow cells.

[0046] Figure 11 A series of simulated bar graphs 1100 showing peak drain and gate voltage spikes and power loss or energy loss E as a function of the area ratio of slow cells according to some specific implementations of the present disclosure. The area ratio on the horizontal axis represents the percentage of slow cells contained within a die (e.g., die 300), ranging from 0% to 30%. Thus, the main body of the active area 302 contains lower gate RC time constant cells that turn on and off first to minimize power loss, while the slow cells with larger gate RC time constants experience delayed switching to reduce voltage overshoot.

[0047] The three bottom bar graphs show the energy losses calculated during turn-on, turn-off, and the total energy loss as a function of the percentage of slow cells. The two top bar graphs show the simulated peak gate voltage overshoot V g and drain voltage overshoot V d . The leftmost bar 1110 corresponds to 0% slow cells (i.e., all fast cells), and the adjacent bar 1010 corresponds to 100% slow cells (i.e., no fast cells). These two extreme cases represent a comparison of a single-cell die with a die containing a mixture of fast and slow cells.

[0048] Comparing bar 1110 with bar 1120, it is clear that in the absence of any slow cells (e.g., for bar 1110), neither the gate voltage overshoot nor the drain voltage overshoot is suppressed, so both voltages are at their maximum values. For 0% slow cells, the energy loss is normalized to 100. For 100% slow cells (e.g., for bar 1120), the gate voltage overshoot has been reduced by approximately 50%, and the drain voltage overshoot experiences the maximum suppression, dropping by approximately 22%. At the same time, for 100% slow cells, the energy loss increases by approximately 24%. This represents the most unfavorable (e.g., less desirable) switching loss scenario.

[0049] The best (e.g., desirable) scenario occurs at 15% slow cells, where the gate voltage overshoot experiences the maximum suppression of 77% and the drain voltage overshoot drops by approximately 19%, while the power loss only increases slightly (by approximately 4%). Thus, compared to a single-cell die, a die with a mixture of approximately 15% slow cells and 85% fast cells can more effectively suppress V g and V d overshoot with less power loss.

[0050] Figure 11 An asymmetric effect is also shown when comparing turn-on with turn-off. While the power loss during turn-on is flat as a function of the area ratio, Figure 11 it shows that the energy loss during turn-off continuously increases as the ratio of slow cells increases. That is, Figure 10Shows the benefits of the fast device during turn - on and the benefits of the slow device during turn - off.

[0051] Figure 12A 、 Figure 12B and Figure 12C Show the voltage and current as a function of time in microseconds during a turn - off event, according to some specific implementations of the present disclosure. Figure 12A Corresponds to Figure 11 the left - most bar 1110 in, where a single - unit die includes only fast cells (0% slow cells). Figure 12B Corresponds to Figure 11 the adjacent bar 1120 in, where a single - unit die includes only slow cells (100% slow cells). Figure 12C Corresponds to Figure 11 the best - case scenario in, where the die 300 combines both fast and slow cells (e.g., about 15% slow cells). Figure 12A Shows that during turn - off, as the drain current I D decreases and the drain voltage increases, the gate voltage experiences a large negative voltage overshoot and the drain voltage experiences a large positive voltage overshoot. The large negative spike in the gate voltage is particularly undesirable because it may potentially damage the gate oxide of the transistor. In Figure 12B for 100% slow cells, the voltage spikes and oscillations are suppressed. In Figure 12C for 15% slow cells, the overshoots in V G and V D are mostly suppressed, and the two voltages only exhibit small ripples that decay rapidly, such that the gate voltage remains above - 30V and the drain voltage remains well below 500V. Figure 12B and Figure 12C The comparison shows that having 15% slow cells is almost as beneficial as having 100% slow cells.

[0052] As described above, various specific implementations of switching units suitable for use in high - power applications can suppress voltage spikes and oscillations while limiting power losses during switching events. The trade - off between power losses and attenuating the gate - voltage and drain - voltage signals can be addressed by adjusting the ratio of slow cells to fast cells within the same die. The placement of the cells within the die and the gate - resistance value are additional variables that can be adjusted to balance the need for voltage - spike suppression with the desire for power savings.

[0053] It should be understood that in the foregoing description, when an element such as a layer, region, or substrate is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected or coupled to the other element, or there can be one or more intermediate elements. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intermediate elements or layers. Although the terms directly on..., directly connected to..., or directly coupled to... may not be used throughout the detailed description, elements shown as being directly on an element, directly connected, or directly coupled can be referred to in such a manner. The claims of the present application can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0054] As used in this specification, unless specifically indicated otherwise by context, the singular forms may include the plural forms. Except for the orientations shown in the drawings, the spatial relative terms (e.g., above, on, over, below, under, beneath, at the top of, at the bottom of, etc.) are intended to cover different orientations of the device during use or operation. In some specific implementations, the relative terms above and below may respectively include vertically above and vertically below. In some specific implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

[0055] Some specific implementations can be realized using various semiconductor processing and / or packaging technologies. Some specific implementations can be realized using various types of semiconductor device processing technologies associated with a semiconductor substrate, which includes but is not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0056] Although certain features of the described specific implementations have been illustrated as described herein, many modifications, alternative forms, variations, and equivalent forms will now occur to those skilled in the art. For example, the features shown with respect to one specific implementation can also be included in other specific implementations, where appropriate. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the specific implementations. It should be understood that these modifications and variations are presented by way of example only and not by way of limitation, and various changes in form and detail can be made. Except for mutually exclusive combinations, any part of the devices and / or methods described herein can be combined in any combination. The specific implementations described herein can include various combinations and / or sub - combinations of the functions, components, and / or features of the different specific implementations described.

Claims

1. A device, comprising: a first multi-terminal device having a first source, a first gate, and a first drain; a second multi-terminal device having a second source, a second gate, and a second drain, wherein: The first drain is coupled to the second drain; The first gate is coupled to the second gate; and The first source is coupled to the second source; and A gate resistor is coupled between the first gate and the second gate, the gate resistor being configured to reduce voltage overshoot during a switching event. 2 . The apparatus of claim 1 , wherein the first multi-terminal device has a first shield, the second multi-terminal device has a second shield, and the first shield is coupled to the first source. The apparatus of claim 2 , wherein the second shield is coupled to the second gate.

4. The apparatus of claim 3, wherein the gate transistor has a value in the range of about 4 ohms to about 20 ohms.

5. The apparatus of claim 2, wherein the second shield is coupled to the second source.

6. The apparatus of claim 5, wherein the gate transistor has a value in the range of about 50 ohms to about 400 ohms.

7. A circuit, comprising: a plurality of first cells, each first cell comprising a first transistor having a first source, a first gate and a first drain, the first transistor further configured with a first shield terminal coupled to the first source; and A plurality of second cells, each second cell comprises a second transistor having a second source, a second gate and a second drain, the second transistor further being configured with a second shielding terminal.

8. The circuit of claim 7, wherein the second shield terminal is coupled to the second gate.

9. The circuit of claim 7, wherein the second shield terminal is coupled to the second source. 10 . The circuit of claim 7 , wherein a ratio of the plurality of first cells to the plurality of second cells is approximately 1:

1. 11 . The circuit of claim 7 , wherein a ratio of the plurality of first cells to the plurality of second cells is approximately 10:

1.

12. The circuit of claim 7, wherein an active area of ​​the plurality of first cells is approximately 10% to approximately 25% greater than an active area of ​​the plurality of second cells. 13 . The circuit according to claim 7 , wherein the circuit is divided into a first block including the plurality of first cells and a second block including the plurality of second cells.

14. The circuit of claim 13, further comprising a first gate bus coupled to the first block and a second gate bus coupled to the second block.

15. The circuit of claim 14, wherein the first gate bus is connected to a first input control signal having a first gate resistance, and the second gate bus is connected to a second input control signal having a second gate resistance.

16. The circuit of claim 7, wherein the plurality of first cells are configured to switch faster with lower power loss than the plurality of second cells.

17. The circuit of claim 7, wherein the plurality of first cells are interleaved with the plurality of second cells.

18. The circuit of claim 7, wherein the second plurality of cells have a higher gate RC time constant than the first plurality of cells.

19. A method comprising: forming a plurality of first transistors and a plurality of second transistors in the die; configuring the plurality of first transistors to have lower power loss than the plurality of second transistors; as well as The second plurality of transistors are configured to have a gate RC time constant greater than that of the first plurality of transistors. 20 . The method of claim 19 , wherein an area of ​​the die including the plurality of first transistors is larger than an area of ​​the plurality of second transistors to achieve a target capacitance.

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