N-type finger-shaped polysilicon passivation structure and preparation method thereof

Abstract

The application relates to an N-type finger-shaped polycrystalline silicon passivation structure and a preparation method thereof. The structure comprises non-contact areas and contact areas staggered along the length direction of a silicon wafer substrate, and a side wall between the non-contact areas and the contact areas; the contact area comprises, from the side close to the silicon wafer substrate to the side away from the silicon wafer substrate, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer and an electrode grid line; the thickness of the tunneling oxide layer is 1-5 nm, and the thickness of the phosphorus-doped polycrystalline silicon layer is 50-200 nm; the non-contact areas, the contact areas and the side wall are all deposited with an aluminum oxide / silicon nitride stack; the aluminum oxide / silicon nitride stack of the contact area is located on the outside of the phosphorus-doped polycrystalline silicon layer, and the aluminum oxide / silicon nitride stack of the non-contact area is located on the silicon wafer substrate; the side wall is gradually inclined upward from the non-contact area to the contact area, and the inclination angle alpha of the side wall is 40-90 degrees. The application has the effects of good passivation effect and low production cost.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and in particular to an N-type finger-shaped polycrystalline silicon passivation structure and its preparation method. Background Technology

[0002] With the development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells has been continuously improving. In recent years, N-type tunneling oxide passivated contact (TOPCon) cells have gradually become the mainstream in the market, with a conversion efficiency exceeding 25%. As the core structure of this type of cell, the ultrathin silicon oxide / doped polycrystalline silicon stack has both passivation and contact functions, and can be used as a passivation film layer on the cell surface, especially the N-type surface and contact area.

[0003] However, polycrystalline silicon films exhibit strong parasitic absorption, which severely impacts the photocurrent generated by the battery. Therefore, TOPCon stacked structures are generally only used on the back surface of the battery. Even so, the polycrystalline silicon layer on the back surface still adversely affects the battery's long-wavelength response, thereby reducing the battery's short-circuit current density (Jsc).

[0004] The main function of the TOPCon structure is to reduce the minority carrier recombination rate in the electrode contact area and decrease the thickness of the polysilicon layer in the non-contact area on the back side, which can, to some extent, solve the problem of poor long-wavelength response in TOPCon cells. Currently, the main technological routes can be roughly divided into three categories: 1. Using laser oxidation, silicon oxide is prepared as a barrier layer in the back contact area, and the polysilicon layer in the non-contact area is etched with an alkaline solution. Finally, hydrofluoric acid (HF) is used to remove the silicon oxide in the contact area. 2. An alkaline-resistant mask layer is used to protect the contact area, combined with alkaline etching, to achieve thinning of the polysilicon layer in the non-contact area. 3. Laser ablation is used to directly erode the non-contact area, achieving thinning of the polysilicon layer in that area.

[0005] like Figure 1 As shown, the polycrystalline silicon passivation structure fabricated using the relevant technical process includes a silicon wafer substrate 1, a tunneling oxide layer 2 deposited on the back side of the silicon wafer substrate 1, a phosphorus-doped polycrystalline silicon layer 3 deposited on the side of the tunneling oxide layer 2 away from the silicon wafer substrate 1, and a silicon nitride layer 4 deposited on the side of the phosphorus-doped polycrystalline silicon layer 3 away from the tunneling oxide layer 2. The polycrystalline silicon passivation structure also includes multiple spaced electrode grid lines 5, which form ohmic contacts with the polycrystalline silicon layer. The areas that do not contact the electrode grid lines 5 are non-contact areas. By thinning the polycrystalline silicon layer in the non-contact areas, the thickness of the polycrystalline silicon layer in the non-contact areas is made smaller than that in the contact areas, thereby improving the long-wavelength response of the TOPCon cell and reducing the short-circuit current density (Jsc) of the cell.

[0006] The aforementioned technologies have the following drawbacks: When preparing polycrystalline silicon passivation structures using related technical processes, it is necessary to increase the initial thickness of the polycrystalline silicon layer and then thin the polycrystalline silicon layer in the non-contact area. This can lead to the introduction of additional parasitic absorption in the contact area. Moreover, a thicker polycrystalline silicon layer means that the deposition time or temperature needs to be increased, which increases the production cost. Summary of the Invention

[0007] The BSG mentioned in this application refers to Borosilicate Glass.

[0008] The PSG mentioned in this application refers to Phosphosilicate glass.

[0009] In order to optimize the passivation structure of the non-contact area without affecting the passivation level of the battery back surface and electrode contact area, thereby improving the battery short-circuit current density and minimizing the impact on process cost, this application provides an N-type finger polycrystalline silicon passivation structure and its preparation method.

[0010] In a first aspect, this application provides an N-type finger-shaped polycrystalline silicon passivation structure, employing the following technical solution:

[0011] An N-type finger polycrystalline silicon passivation structure includes a silicon wafer substrate. The back side of the silicon wafer substrate includes non-contact regions and contact regions that are staggered along the length direction of the silicon wafer substrate, and the non-contact regions and contact regions are separated by sidewalls.

[0012] The contact area includes a tunneling oxide layer, a phosphorus-doped polysilicon layer, and an electrode gate line sequentially disposed from the side closest to the silicon substrate to the side furthest from the silicon substrate; the thickness of the tunneling oxide layer is 1nm-5nm, and the thickness of the phosphorus-doped polysilicon layer is 50nm-200nm; wherein, the thickness of the tunneling oxide layer can be 1nm, 2nm, 3nm, 4nm, 5nm, etc., and the thickness of the phosphorus-doped polysilicon layer can be 50nm, 60nm, 70nm, 80nm, 100nm, 130nm, 150nm, 180nm, 200nm, etc.

[0013] Alumina / silicon nitride stacks are deposited on the non-contact area, the contact area, and the sidewalls. The alumina / silicon nitride stacks in the contact area are located outside the phosphorus-doped polycrystalline silicon layer, and the alumina / silicon nitride stacks in the non-contact area are located on the silicon wafer substrate.

[0014] The sidewall is gradually inclined upwards from the non-contact area towards the contact area, and the inclination angle α of the sidewall is 40°-90°. Specifically, the inclination angle α of the sidewall can be 40°, 50°, 60°, 70°, 80°, or 90°.

[0015] By adopting the above technical solution, the deposition thickness of the phosphorus-doped polycrystalline silicon layer in existing processes needs to reach more than 200 nm to ensure that a certain thickness of polycrystalline silicon is retained in the non-contact area after laser or etching, thereby ensuring that the passivation structure has a good passivation effect. Moreover, under the existing process route, the thinner the initial thickness of the phosphorus-doped polycrystalline silicon layer, the narrower the process window for laser or etching, and the greater the difficulty in controlling the process fabrication. However, the phosphorus-doped polycrystalline silicon layer of this application has a relatively thin thickness, not exceeding 200 nm. Therefore, when depositing the phosphorus-doped polycrystalline silicon layer, only a shorter deposition time or a lower temperature is required to complete the deposition. The silicon layer deposition process helps reduce production costs. The thinner phosphorus-doped polycrystalline silicon layer prevents the introduction of additional parasitic absorption in the contact area. At the same time, the process route of this application helps to completely remove the phosphorus-doped polycrystalline silicon layer and tunnel oxide layer in the non-contact area. In order to overcome the impact of the complete removal of the phosphorus-doped polycrystalline silicon layer in the non-contact area, both the contact area and the non-contact area are encapsulated by a polycrystalline silicon passivation structure formed by aluminum oxide / silicon nitride stack. This can ensure the improvement of battery Jsc without affecting the passivation level of the battery back surface and electrode contact area, and minimize the impact on process cost.

[0016] Optionally, the alumina / silicon nitride stack includes an alumina film, a first antireflective film, and a second antireflective film. The alumina film is located on the side closer to the silicon substrate, and the first and second antireflective films are located on the side of the alumina film away from the silicon substrate. The thickness of the alumina film is 2nm-10nm. The first and second antireflective films are one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide. The total thickness of the first and second antireflective films is 60nm-100nm.

[0017] Optionally, the thickness of the alumina film can be 2nm, 5nm, 8nm, 10nm, etc., and the total thickness of the first antireflection film and the second antiemissivity film can be 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.

[0018] By adopting the above technical solution, by depositing aluminum oxide / silicon nitride stacks on the non-contact area, the contact area and the sidewall, it is possible to ensure that the non-contact area still has a good passivation effect after the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer are completely removed. Alumina / silicon nitride has a good passivation effect on the N-type silicon surface. The resulting back structure can improve the long-wavelength response of the battery and increase Jsc, while achieving a better back surface passivation level.

[0019] Optionally, the inclination angle α of the sidewall is 62°-88°.

[0020] Optionally, the inclination angle α of the sidewall can be 62°, 65°, 68°, 70°, 75°, 80°, 85°, 88°, etc.

[0021] By adopting the above technical solution, a sidewall inclination angle of 62°-88° between the non-contact area and the contact area is more conducive to the subsequent deposition of alumina and silicon nitride stacks, resulting in uniform stack thickness and thus ensuring the passivation effect in this area. If the sidewall inclination angle between the non-contact area and the contact area is close to a right angle, the subsequently deposited alumina and silicon nitride stacks are prone to detachment, which is detrimental to improving the passivation effect in this area.

[0022] Optionally, the contact area further includes a grid line region for printing electrode grid lines, wherein the width of the electrode grid lines is smaller than the width of the grid line region, the width of the grid line region is 40μm-300μm, and the width difference between the electrode grid lines and the grid line region on one side is 20μm-100μm.

[0023] Optionally, the width of the contact area is 20μm, 50μm, 80μm, 100μm, 150μm, 180μm, 200μm, 250μm, 280μm, 300μm, etc., and the width difference between the electrode grid line and the grid line area can be 20μm, 40μm, 60μm, 80μm, 100μm, etc.

[0024] By adopting the above technical solution, and controlling the width of the grid line area to be within the range of 40μm-300μm, and the width difference between the electrode grid line and the grid line area on one side to be 20μm-100μm, the misalignment during the printing of the electrode grid line is reduced, while ensuring that the battery has a good passivation effect. When the width of the grid line area is too narrow, it is easy for the width of the grid line area and the electrode grid line to be very close, which is not conducive to printing alignment and has the risk of misalignment. When the width of the grid line area is too wide, it is easy to have an adverse effect on the passivation effect of the battery.

[0025] Optionally, the height difference H between the non-contact area and the contact area is 1μm-5μm. Specifically, the height difference H between the non-contact area and the contact area can be 1μm, 2μm, 3μm, 4μm, or 5μm.

[0026] Optionally, the boundary between the contact area and the non-contact area is wavy, with a wave amplitude of ±5μm.

[0027] By adopting the above technical solution, the height difference between the non-contact and contact areas can easily lead to uneven passivation film and weak deposition when passivating simultaneously. By controlling the synergistic effect of height difference, wave amplitude, and tilt angle, the passivation layer deposition effect is improved. The non-contact area is directly passivated by an alumina / silicon nitride stack, which not only has lower surface recombination compared to the existing TOPCon structure, but is also free from the parasitic absorption of polycrystalline silicon, and has better long-wavelength response when used as a back passivation layer.

[0028] Secondly, this application provides a method for preparing an N-type finger-shaped polycrystalline silicon passivation structure, employing the following technical solution:

[0029] A method for preparing an N-type finger-shaped polycrystalline silicon passivation structure includes the following steps:

[0030] S1. A tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, and a protective layer are deposited sequentially from the back side of the silicon wafer substrate outwards, wherein the protective layer contains silicon dioxide.

[0031] S2, Laser Process: Laser scanning of the non-contact area on the back of the silicon wafer substrate;

[0032] S3, Alkaline Etching: Using an alkaline solution with a concentration of 5-50%, the protective layer and polysilicon layer of the non-contact area on the back surface that have been treated by laser are completely removed, and the underlying silicon layer is also etched to form a pit structure with a depth of 1-5μm. Then, the protective layer of the contact area is removed with HF.

[0033] S4. Backside passivation: Alumina / silicon nitride stacks are sequentially deposited on the back surface of the silicon wafer substrate to form a complete passivation structure;

[0034] S5. Screen printing: The electrode grid lines are aligned with the grid line area for printing.

[0035] By adopting the above technical solution, this application eliminates the need to increase the initial thickness of the polysilicon. The polysilicon layer in the non-contact areas is completely removed using laser and alkaline etching, followed by passivation of the back surface using a stack of alumina and silicon nitride. Except for the laser process, which is an additional step, alkaline etching is a necessary step for removing the polysilicon wrapping on the front surface. The alumina on the back surface is naturally formed during atomic layer deposition (ALD) of alumina on the front surface; neither introduces additional process steps. Since alumina / silicon nitride provides good passivation for N-type silicon surfaces, the back structure formed by this method improves the long-wavelength response of the battery, increases Jsc, and achieves a superior level of back surface passivation.

[0036] Optionally, the laser process parameters in S1 are: spot size 100μm-500μm, wavelength 300 nm-1100nm, frequency 500 kHz-100000kHz, and scanning speed 10 m / s-200m / s. The spot size can be 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, or 500μm; the wavelength can be 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, or 1100 nm; the frequency can be 500 kHz, 1000 kHz, 2000 kHz, 3000 kHz, 4000 kHz, 5000 kHz, 6000 kHz, 7000 kHz, 8000 kHz, 9000 kHz, 10000 kHz, 50000 kHz, or 100000 kHz; and the scanning speed can be 10 m / s, 20 m / s, 30 m / s, 40 m / s, 50 m / s, 60 m / s, or 70 m / s. m / s, 80 m / s, 90 m / s, 100 m / s, 150 m / s, 180 m / s, 200m / s, etc.

[0037] By employing the above technical solution, laser scanning is performed on the back side of the silicon wafer substrate, which thins or makes the phosphorus-silicon glass and phosphorus-doped polysilicon layer thinner, making it easier to completely remove the phosphorus-doped polysilicon layer and tunneling oxide layer in the non-contact area.

[0038] In summary, this application has the following beneficial effects:

[0039] 1. When depositing a phosphorus-doped polysilicon layer, only a thin layer needs to be deposited, which helps to reduce the preparation time or temperature of the phosphorus-doped polysilicon layer, reduce production costs, and avoid introducing additional parasitic absorption in the contact area. At the same time, it helps to completely remove the phosphorus-doped polysilicon layer and tunneling oxide layer in the non-contact area. The polysilicon passivation structure formed by the alumina / silicon nitride stack can ensure the improvement of the battery Jsc without affecting the passivation level of the battery back surface and electrode contact area, and minimize the impact on process costs.

[0040] 2. This application eliminates the need to increase the initial thickness of the polysilicon. It completely removes the polysilicon layer in non-contact areas using laser and alkaline etching, and then passivates the back surface using a stack of alumina and silicon nitride. Except for the laser process, which is an additional step, alkaline etching is a necessary step to remove the polysilicon wrapping on the front surface. The alumina on the back surface is naturally formed during atomic layer deposition (ALD) of alumina on the front surface; neither introduces additional process steps. Since alumina / silicon nitride provides good passivation for N-type silicon surfaces, the back structure formed by this method improves the long-wavelength response of the battery, increases Jsc, and achieves a superior level of back surface passivation. Attached Figure Description

[0041] Figure 1 A side view of the passivation structure of the related technology and Comparative Example 1.

[0042] Figure 2 This is a side view of the N-type finger polycrystalline silicon passivation structure of Embodiment 1 of this application.

[0043] Figure 3 This is a top view of the N-type finger polycrystalline silicon passivation structure of Embodiment 1 of this application.

[0044] Explanation of reference numerals in the attached figures:

[0045] Figure 1 In the middle: 1. Silicon wafer substrate; 2. Tunneling oxide layer; 3. Phosphorus-doped polycrystalline silicon layer; 4. Silicon nitride layer; 5. Electrode gate line.

[0046] Figures 2-3 In the middle: 1. Silicon substrate; 2. Tunneling oxide layer; 3. Phosphorus-doped polycrystalline silicon layer; 4. Alumina / silicon nitride stack; 5. Electrode gate line; 6. Gate line region; 7. Sidewall. Detailed Implementation

[0047] Unless otherwise specified, the experimental methods described in the following embodiments of the present invention are generally performed under conventional conditions or as recommended by the manufacturer. All commonly used chemical reagents used in the embodiments are commercially available products.

[0048] Example 1

[0049] like Figure 2As shown, an N-type finger polycrystalline silicon passivation structure includes a silicon wafer substrate 1. The back side of the silicon wafer substrate 1 includes non-contact regions and contact regions that are staggered along the length of the silicon wafer substrate 1. There is a sidewall 7 between the non-contact regions and the contact regions, which is gradually inclined upward from the non-contact regions to the contact regions. The inclination angle α of the sidewall 7 is 75°. The contact regions include a tunneling oxide layer 2, a phosphorus-doped polycrystalline silicon layer 3, and an electrode gate line 5 that are sequentially arranged from the side close to the silicon wafer substrate 1 to the side away from the silicon wafer substrate 1. The thickness of the tunneling oxide layer 2 is 1.5 nm, and the thickness of the phosphorus-doped polycrystalline silicon layer 3 is 150 nm.

[0050] Alumina / silicon nitride stack 4 is deposited on the non-contact area, the contact area, and the sidewall 7. The alumina / silicon nitride stack 4 in the contact area is located outside the phosphorus-doped polycrystalline silicon layer 3, and the alumina / silicon nitride stack 4 in the non-contact area is located on the silicon wafer substrate 1.

[0051] The alumina / silicon nitride stack 4 includes an alumina film, a first antireflective film, and a second antireflective film. The thickness of the alumina film is 5 nm, and both the first and second antireflective films are silicon nitride. The total thickness of the first and second antireflective films is 80 nm.

[0052] Reference Figure 3 The width of electrode grid line 5 is smaller than the width of grid line region 6. The width of grid line region 6 is 150 μm, and the difference in width between one side of electrode grid line 5 and grid line region 6 is 60 μm.

[0053] The height difference H between the non-contact area and the contact area is 3μm, and the boundary between the contact area and the non-contact area is wavy with a wave amplitude of ±5μm.

[0054] A method for preparing an N-type finger-shaped polycrystalline silicon passivation structure includes the following steps:

[0055] S1, Texturing of silicon wafers;

[0056] S2, front boron diffusion, forming a boron diffusion layer and borosilicate glass, while back diffusion is formed;

[0057] S3. Single-sided wet removal of borosilicate glass on the back side;

[0058] S4. Alkali polishing removes back-side wrapping, and the front is protected by borosilicate glass.

[0059] S5. LPCVD is used to deposit tunnel oxide layer 2 and intrinsic polysilicon on the back side, while a wrap-around expansion is formed on the front side.

[0060] S6. Phosphorus diffusion on the back side forms a phosphorus-doped polycrystalline silicon layer 3 and a protective layer. The protective layer is phosphorosilicate glass (PSG). A wrap-around diffusion area is formed on the front side.

[0061] S7. Backside laser removal of non-contact area of ​​phosphorus silicate glass (PSG): The non-contact area of ​​the back surface is scanned by laser to make the phosphorus silicate glass (PSG) and phosphorus-doped polycrystalline silicon layer 3 thinner or more porous. The laser spot size is 300μm, wavelength is 532nm, frequency is 10000kHz, and scanning speed is 60m / s.

[0062] S8. Single-sided wet removal of the phosphor silicate glass (PSG) in the front-side wrap-around area, while ensuring that the front-side BSG is not damaged;

[0063] S9. Alkali etching: Remove the polysilicon winding plating on the front side and etch the non-contact area on the back side to remove the polysilicon layer and tunneling oxide layer 2. During the alkaline etching of the non-contact area on the back side, three different concentrations of alkaline solutions are used for cleaning. The concentrations of the three alkaline solutions are set from high to low as 30%, 25%, and 20%, respectively, so that the alkaline etching results in... Figure 2 The pit structure shown has a depth of 3μm (i.e., the height difference H between the non-contact area and the contact area is 3μm).

[0064] S10, RCA cleaning and front BSG and back PSG removal, use hydrofluoric acid solution to remove PSG in contact areas;

[0065] S11. Deposition of passivation and antireflection layers on the front and back surfaces: Alumina film, first antireflection film, and second antireflection film are deposited sequentially on the front and back surfaces of silicon substrate 1 to form aluminum oxide / silicon nitride stack 4, thereby forming a complete passivation structure.

[0066] S12. Screen printing and sintering are performed to form electrode grid lines 5 and grid line regions 6. The width of electrode grid lines 5 is smaller than the width of grid line regions 6 to ensure that electrode grid lines 5 are aligned with grid line regions 6 during printing.

[0067] Example 2

[0068] An N-type finger polycrystalline silicon passivation structure differs from Example 1 in that the thickness of the tunneling oxide layer 2 is 3 nm, the thickness of the phosphorus-doped polycrystalline silicon layer is 100 nm, the tilt angle α of the sidewall 7 is 62°, the width of the contact area is 20 μm, the difference in width between the electrode gate line 5 and the gate line region 6 on one side is 100 μm, and the height difference H between the non-contact area and the contact area is 1 μm.

[0069] Example 3

[0070] An N-type finger polycrystalline silicon passivation structure differs from Example 1 in that the thickness of the tunneling oxide layer 2 is 5 nm, the thickness of the phosphorus-doped polycrystalline silicon layer is 200 nm, the tilt angle α of the sidewall 7 is 88°, the width of the contact area is 300 μm, the width difference between the electrode gate line 5 and the gate line region 6 on one side is 20 μm, and the height difference H between the non-contact area and the contact area is 5 μm.

[0071] Example 4

[0072] An N-type finger polysilicon passivation structure differs from Example 1 in that the width difference between one side of the electrode gate line 5 and the gate line region 6 is 10 μm.

[0073] Example 5

[0074] An N-type finger polysilicon passivation structure differs from Example 1 in that the width difference between one side of the electrode gate line 5 and the gate line region 6 is 120 μm.

[0075] Example 6

[0076] An N-type finger polycrystalline silicon passivation structure differs from Example 1 in that the inclination angle α of the sidewall 7 between the non-contact region and the contact region is 90°.

[0077] Example 7

[0078] An N-type finger polycrystalline silicon passivation structure differs from Example 1 in that the inclination angle α of the sidewall 7 between the non-contact region and the contact region is 45°.

[0079] Comparative Example 1

[0080] like Figure 1 As shown, a polycrystalline silicon passivation structure differs from that in Example 1 in that it includes a silicon wafer substrate 1, a tunneling oxide layer 2 deposited on the back side of the silicon wafer substrate 1, the thickness of the tunneling oxide layer 2 being 2 nm, a phosphorus-doped polycrystalline silicon layer 3 deposited on the side of the tunneling oxide layer 2 away from the silicon wafer substrate 1, the thickness of the phosphorus-doped polycrystalline silicon layer 3 being 300 nm, and a silicon nitride layer 4 deposited on the side of the phosphorus-doped polycrystalline silicon layer 3 away from the tunneling oxide layer 2. The polycrystalline silicon passivation structure also includes a plurality of spaced electrode gate lines 5, the electrode gate lines 5 forming ohmic contacts with the polycrystalline silicon layer.

[0081] Comparative Example 2

[0082] A method for preparing a polycrystalline silicon passivation structure includes the following steps:

[0083] S1, Texturing of silicon wafers;

[0084] S2, front boron diffusion, forming a boron diffusion layer and borosilicate glass (BSG), while back diffusion is formed;

[0085] S3. Single-sided wet removal of borosilicate glass on the back side;

[0086] S4. Alkali polishing removes back-side wrapping, and the front is protected by borosilicate glass.

[0087] S5, LPCVD deposits a tunneling oxide layer and intrinsic polysilicon on the back side, while forming a wraparound on the front side;

[0088] S6. Phosphorus diffusion on the back side forms phosphorus-doped polycrystalline silicon and phosphorus silicon glass (PSG), while a wrap-around region is formed on the front side.

[0089] S7. Single-sided wet removal of the phosphor silicate glass (PSG) in the front-side wrap-around area, while ensuring that the front-side BSG is not damaged;

[0090] S8. Alkali etching to remove the polysilicon wrapping on the front side.

[0091] S9, RCA cleaning and front BSG and back PSG removal;

[0092] S10, front and back passivation and antireflection layer deposition;

[0093] S11, screen printing, sintering, forming electrode grid lines and contact areas.

[0094] The difference between Comparative Example 2 and Example 1 is that ① the back-side laser removal of the non-contact area of ​​the phosphosilicate glass (PSG) was not performed; ② the back-side alkaline etching was not performed and the sloped sidewalls were not formed.

[0095] Comparative Example 3

[0096] A polycrystalline silicon passivation structure differs from Example 1 in that only silicon nitride layers are deposited on the non-contact region, the contact region, and the sidewalls.

[0097] Performance testing

[0098] The passivation structures of the batteries in Examples 1-7 and Comparative Examples 1-3 were subjected to IV electrical performance tests under the same test conditions. The test results are shown in Table 1.

[0099] Table 1. Test results of Examples 1-7 and Comparative Examples 1-3.

[0100]

[0101] The process times of Example 1 and Comparative Examples 1-2 were compared and tested, and the test times are shown in Table 2.

[0102] Table 2. Process times for Example 1 and Comparative Examples 1-2.

[0103]

[0104] Based on Example 1 and Comparative Examples 1-2, and the test results in Table 1-2, it can be seen that the N-type finger polycrystalline silicon passivation structure of this application has a thinner polycrystalline silicon layer, which greatly shortens the time for depositing the polycrystalline silicon layer. At the same time, the open-circuit voltage of the fabricated battery structure is 733.3mV, the short-circuit current is 14.005A, the fill factor is 84.31%, and the conversion efficiency is 25.87%, which has the advantages of short process time and high battery conversion efficiency.

[0105] Combining Example 1 and Comparative Example 3 with the test results in Table 1, it can be seen that by depositing aluminum oxide / silicon nitride stacks on the non-contact area, the contact area, and the sidewalls, the non-contact area can still have a good passivation effect after the phosphorus-doped polycrystalline silicon layer and the tunneling oxide layer are completely removed. Alumina / silicon nitride provides good passivation for the N-type silicon surface. The resulting back surface structure improves the long-wavelength response of the battery and increases Jsc, while achieving a better level of back surface passivation.

[0106] Combining Examples 1-3 and Examples 4-5 with Table 1, it can be seen that Examples 1-3 are superior to Examples 4-5. The reason for this is that when the width difference between one side of the electrode grid line and the grid line region is small (i.e., Example 4), it is easy to cause misalignment during the printing of the electrode grid line, which has an adverse effect on the battery structure. When the width difference between one side of the electrode grid line and the grid line region is large (i.e., Example 5), the area of ​​the polycrystalline silicon layer in the removed non-contact region becomes smaller, resulting in insufficient improvement on the long-wavelength response of the battery and little improvement in Jsc. By controlling the width of the contact region to be within the range of 40μm-300μm and the width difference between one side of the electrode grid line and the grid line region to be 20μm-100μm, the misalignment during the printing of the electrode grid line is reduced, while ensuring that the battery has a good passivation effect.

[0107] Combining Examples 1 and 6-7 with Table 1, it can be seen that Example 1 is superior to Examples 6-7. This is because a sidewall inclination angle of 62°-88° between the non-contact area and the contact area is more conducive to the subsequent deposition of alumina and silicon nitride stacks, resulting in uniform stack thickness and thus ensuring the passivation effect in that area. If the sidewall inclination angle between the non-contact area and the contact area is close to a right angle, the subsequently deposited alumina and silicon nitride stacks are prone to detachment, which is detrimental to improving the passivation effect in that area.

[0108] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An N-type finger-shaped polycrystalline silicon passivation structure, characterized in that: The silicon wafer substrate (1) includes a back surface of a non-contact area and a contact area that are staggered along the length of the silicon wafer substrate (1), and a sidewall (7) is provided between the non-contact area and the contact area. The contact area includes a tunneling oxide layer (2), a phosphorus-doped polysilicon layer (3), and an electrode gate line (5) arranged sequentially from the side closest to the silicon substrate (1) to the side furthest from the silicon substrate (1); the thickness of the tunneling oxide layer (2) is 1nm-5nm, and the thickness of the phosphorus-doped polysilicon layer (3) is 50nm-200nm. Alumina / silicon nitride stack (4) is deposited on the non-contact area, the contact area and the sidewall (7). The alumina / silicon nitride stack (4) in the contact area is located outside the phosphorus-doped polycrystalline silicon layer (3), and the alumina / silicon nitride stack (4) in the non-contact area is located on the silicon wafer substrate (1). The sidewall (7) is gradually inclined upward from the non-contact area to the contact area, and the inclination angle α of the sidewall (7) is 62°-88°. The height difference H between the non-contact area and the contact area is 1μm-5μm; The N-type finger-shaped polycrystalline silicon passivation structure is prepared by the following steps: S1. A tunneling oxide layer (2), a phosphorus-doped polycrystalline silicon layer (3) and a protective layer are deposited sequentially from the back side of a silicon wafer substrate (1) outwards, wherein the protective layer contains silicon dioxide; S2, Laser process: Laser scanning is performed on the non-contact area on the back side of the silicon wafer substrate (1); S3, Alkaline Etching: Using an alkaline solution with a concentration of 5-50%, the protective layer and polysilicon layer of the non-contact area on the back surface that have been treated by laser are completely removed, and the underlying silicon layer is also etched to form a pit structure with a depth of 1-5μm. Then, the protective layer of the contact area is removed with HF. S4, Backside passivation: Alumina / silicon nitride stack (4) is sequentially deposited on the back surface of the silicon substrate (1) to form a complete passivation structure; S5, Screen printing: The electrode grid lines (5) are aligned with the grid line area (6) for printing; During the alkaline etching process on the non-contact area on the back side, three different concentrations of alkaline solution were used for cleaning. The concentrations of the alkaline solution in the three alkaline solution tanks were set from high to low as 30%, 25%, and 20%, respectively, so that a pit structure was formed after alkaline etching.

2. The N-type finger-shaped polycrystalline silicon passivation structure according to claim 1, characterized in that: The alumina / silicon nitride stack (4) includes an alumina film, a first antireflective film, and a second antireflective film. The alumina film is located on the side close to the silicon substrate (1), and the first and second antireflective films are located on the side of the alumina film away from the silicon substrate (1). The thickness of the alumina film is 2nm-10nm. The first and second antireflective films are one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide. The total thickness of the first and second antireflective films is 60nm-100nm.

3. The N-type finger-shaped polycrystalline silicon passivation structure according to claim 1, characterized in that: The contact area also includes a grid area (6) for printing electrode grid lines (5), the width of the electrode grid lines (5) is smaller than the width of the grid area (6), the width of the grid area (6) is 40μm-300μm, and the width difference between the electrode grid lines (5) and the grid area (6) on one side is 20μm-100μm.

4. The N-type finger-shaped polycrystalline silicon passivation structure according to claim 1, characterized in that: The boundary between the contact area and the non-contact area is wavy, with a wave amplitude of ±5μm.

5. The N-type finger polycrystalline silicon passivation structure according to claim 1, characterized in that: The laser process parameters in S2 are: spot size 100μm - 500μm, wavelength 300 nm - 1100nm, frequency 500 kHz - 100000kHz, and scanning speed 10 m / s - 200m / s.

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