Display panel and display device including the same

Abstract

The embodiment of the invention discloses a display panel and a display device comprising the display panel. The display panel comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with a display area and a non-display area located on the periphery of the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads disposed in the first area, a driver IC being attached to the plurality of driving pads in the non-display area, and the plurality of driving pads being connected to the plurality of signal lines; and a dummy pad disposed in the first region, in which a positive voltage is applied to the dummy pad.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0197393, filed on December 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display panel and a display device including the display panel. Background art

[0004] In modern information society, display devices are becoming more important as visual information delivery media. To occupy an important position in the future, they must meet the requirements of low power consumption, light weight, thinness, and high definition.

[0005] Display devices can be classified into self - emissive types and non - self - emissive types. Self - emissive types such as electroluminescence (EL), light - emitting diodes (LEDs), and field - emission displays (FEDs) emit light by themselves, and non - self - emissive types such as liquid - crystal displays (LCDs) do not emit light by themselves.

[0006] By extending signal lines from a display area to a non - display area, a display device can be electrically connected to a driver IC. In this case, the signal lines and pads are corroded by external moisture brought about by an operating environment of high temperature and high humidity. Such a bad state often occurs in the pads located at the edge of the driver IC, resulting in poor driving. Summary of the invention

[0007] Embodiments of the present disclosure provide a display panel and a display device including the display panel, which can prevent driving pads from being corroded by negative charges.

[0008] The problems to be solved by the embodiments are not limited to the problems mentioned above, and those skilled in the art will clearly understand other problems not mentioned herein from the following description.

[0009] A display panel according to an embodiment of the present disclosure includes: a substrate having a display area and a non - display area surrounding the display area; a plurality of signal lines extending from the display area to the non - display area; a plurality of driving pads disposed in a first area of the non - display area where a driver IC is disposed and connected to the plurality of signal lines; and dummy pads disposed in the first area. A positive voltage is applied to the dummy pads.

[0010] A display device according to an embodiment of the present disclosure includes: a substrate having a display area and a non-display area around the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads disposed in a first area of the non-display area and connected to the plurality of signal lines; dummy pads disposed in the first area; and a driver IC disposed in the first area. The plurality of dummy pads include a plurality of dummy signal lines extending toward the display area.

[0011] According to one or more embodiments of the present disclosure, reaction of the driving pads with negative charges present in the area where the driver IC is mounted can be prevented or delayed, thereby improving defective driving pads. This can achieve low-voltage driving and improve the reliability of the display device.

[0012] The effects of the present disclosure are not limited to the above effects, and for those of ordinary skill in the art to which the technical concept of the present disclosure pertains, other effects not mentioned will be obvious through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features, and advantages of the present disclosure will become apparent to those of ordinary skill in the art by referring to the accompanying drawings and describing its exemplary embodiments in detail, in which:

[0014] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure;

[0015] Figure 2 is a schematic diagram showing signal lines and driving pads in a display device according to an embodiment of the present disclosure;

[0016] Figure 3 is a cross-sectional view showing a display device bent according to an embodiment of the present disclosure;

[0017] Figure 4 and 5 is a circuit diagram showing various pixel circuits in a display device according to an embodiment of the present disclosure;

[0018] Figure 6 is showing applied to Figure 5 the driving signal waveforms of the pixel circuits shown in;

[0019] Figure 7 is a cross-sectional view showing a cross-sectional structure of a display area according to an embodiment of the present disclosure;

[0020] Figure 8 is a cross-sectional view showing a cross-sectional structure of a display area according to another embodiment of the present disclosure;

[0021] Figure 9is a schematic diagram showing a cross-sectional structure of a display area according to another embodiment of the present disclosure;

[0022] Figure 10 is a schematic diagram showing signal lines and pads in a display device according to another embodiment of the present disclosure;

[0023] Figure 11 is a schematic diagram showing Figure 10 the region EA of

[0024] Figure 12 is a cross-sectional view of a driving pad and a dummy pad according to an embodiment of the present disclosure;

[0025] Figure 13 is a schematic diagram showing Figure 10 the potential level of the region EA of

[0026] Figure 14 is a schematic diagram showing that negative charges are concentrated at the edge of the first region where the driver IC is provided;

[0027] FIGS. 15A - 15D are schematic diagrams showing electrolytic corrosion in the driving pads due to negative charges on the edge;

[0028] Figure 16 is a graph measuring the number of defects occurring in each driving pad;

[0029] Figures 17 - 19 is a schematic diagram showing various connection relationships of dummy pads in a display device according to an embodiment of the present disclosure;

[0030] Figure 20 is a schematic diagram showing the operation timing of a pixel circuit in a display device according to an embodiment of the present disclosure;

[0031] Figure 21 is a block diagram of a driver IC according to an embodiment of the present disclosure;

[0032] Figure 22 is a schematic diagram showing that a plurality of dummy pads are electrically connected by a gate line in a display device according to an embodiment of the present disclosure;

[0033] Figure 23 is a schematic diagram showing that dummy pads are electrically connected by a sensor electrode line in a display device according to an embodiment of the present disclosure;

[0034] Figure 24 is a schematic diagram showing that adjacent dummy pads are electrically connected by a data line in a display device according to an embodiment of the present disclosure;

[0035] Figure 25is a schematic diagram showing the fixing of negative charges by connecting gate electrodes in a display device according to an embodiment of the present disclosure; and

[0036] Figure 26 is a schematic diagram of a display device according to another embodiment of the present disclosure. Detailed implementation manners

[0037] Advantages and features of the present disclosure and methods for realizing them will be apparent by referring in detail to the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the following embodiments disclosed herein, but can be implemented in various different forms; on the contrary, these embodiments are provided to make the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure.

[0038] The shapes, sizes, proportions, angles, numbers, etc. of the elements shown in the drawings for illustrating embodiments of the present disclosure are merely illustrative and are not intended to be limiting. The same reference numerals can indicate the same components throughout the specification. In addition, when describing the present disclosure, detailed descriptions of related known technologies can be omitted to avoid obscuring the essence of the present disclosure. Terms such as "including", "comprising", "having", or "consisting of" used herein generally intend to allow the addition of other components, unless the term is used together with the term "only". Components referred to by a singular noun include the plural of that noun, unless specifically stated otherwise.

[0039] In the interpretation of components, they are understood to include a margin of error, even if this is not explicitly stated.

[0040] When describing positional relationships, for example, "on top of", "above", "below", or "adjacent to" describe the positional relationship between two components, and there can be one or more other components between the two components, unless "tight" or "direct" is used.

[0041] When describing temporal relationships, "after", "subsequent to", "thereafter", or "before" describe a relationship of precedence or succession in time, and may not be continuous, unless "tight" or "direct" is used.

[0042] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can be the second component within the technical spirit of the present disclosure.

[0043] Terms such as first, second, A, B, (a), or (b) may be used to describe elements of embodiments of the present disclosure. Such terms are merely intended to distinguish one component from another and are not intended to define the nature, sequence, order, or quantity of such components. When a component is described as "connected", "coupled", or "attached" to another component, it should be understood that the component can be directly connected or attached to the other component, but other components may also be "interposed" between the corresponding components, and the corresponding components can be indirectly connected or attached, unless otherwise explicitly stated.

[0044] It should be understood that the term "at least one" includes all possible combinations of one or more related components. For example, the meaning of "at least one of the first, second, and third components" can be understood to include not only the first, second, or third component, but also any combination of two or more of the first, second, and third components.

[0045] According to one or more embodiments of the present disclosure, when the display panel is a liquid crystal display panel, it may include a plurality of gate lines and data lines, and pixels formed at intersections between the gate lines and the data lines. Additionally, it may include a first substrate, a second substrate, and a liquid crystal layer between the first substrate and the second substrate. The first substrate includes thin film transistors as switching elements for controlling the light transmittance ratio in each pixel, and the second substrate includes color filters and / or black matrices.

[0046] When the display panel is an organic light emitting display panel, it may include a plurality of gate lines and data lines, and pixels formed at intersections between the gate lines and the data lines. Additionally, it may include a substrate, an organic light emitting element layer on the substrate, and a packaging layer (or packaging substrate) disposed on the substrate to cover the organic light emitting element layer. The substrate includes thin film transistors as elements for selectively applying voltage to each pixel. The packaging substrate can protect the thin film transistors and the organic light emitting element layer from external impacts and prevent moisture or oxygen from invading the organic light emitting element layer. The organic light emitting element layer may also include an inorganic light emitting layer (e.g., a material layer of nanoscale size) and / or a quantum dot light emitting layer. In another example, the organic light emitting element layer can be made into a micro light emitting diode.

[0047] The pixel circuits and gate drivers formed on the display panel of the present disclosure may include a plurality of transistors. The transistors can be implemented as oxide TFTs (thin film transistors) including oxide semiconductors, LTPS TFTs including low temperature polycrystalline silicon (LTPS), etc. Each transistor can be implemented as a p-channel TFT or an n-channel TFT.

[0048] A transistor is a three - electrode device including a gate, a source, and a drain. Here, the source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow out from the source. Additionally, the drain is the electrode through which carriers leave the TFT. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor (NMOS transistor), since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In this case, in an n - channel transistor, the current direction is from the drain to the source. In the case of a p - channel transistor (PMOS transistor), since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p - channel transistor, the current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0049] The gate signal can swing between a gate - on voltage and a gate - off voltage. The gate - on voltage can be set to a voltage higher than the transistor threshold voltage, and the gate - off voltage can be set to a voltage lower than the transistor threshold voltage. The transistor can conduct in response to the gate - on voltage and can be turned off in response to the gate - off voltage. For an n - channel transistor, the gate - on voltage can be the gate high voltage VGH / VEH, and the gate - off voltage can be the gate low voltage VGL / VEL. For a p - channel transistor, the gate - on voltage can be the gate low voltage VGL / VEL, and the gate - off voltage can be the gate high voltage VGH / VEH.

[0050] Each feature of the embodiments described herein can be coupled or combined with each other in whole or in part, and can be technically interlocked and operate in various ways, and each embodiment can be executed independently or in combination with each other.

[0051] Hereinafter, embodiments of the present disclosure are illustrated with reference to the drawings and examples. The scales of the components shown in the drawings are only proportional for illustrative purposes and are not proportional to the actual components shown in the figures.

[0052] Figure 1 is a plan view of a display device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram showing signal lines and driving pads in a display device according to an embodiment of the present disclosure. Figure 3 is a cross - sectional view of a bent display device according to an embodiment of the present disclosure.

[0053] Reference Figure 1 and 2, a display device according to an embodiment of the present disclosure may include a display panel 100, a plurality of signal lines 210, a plurality of driving pads 220, and dummy pads 230.

[0054] The display panel 100 may include a display area DA and a non-display area NA. The non-display area NA may be located around the display area DA. For example, the invisible area NA may be adjacent to the display area DA.

[0055] The plurality of signal lines 210 may extend from the display area DA to the non-display area NA. The plurality of signal lines 210 may include a plurality of data lines 211 and a plurality of gate lines 212.

[0056] The plurality of data lines 211, the plurality of gate lines 212, and a plurality of pixels P may be disposed in the display area DA of the display panel 100. For example, the plurality of gate lines 212 may be disposed intersecting the plurality of data lines 211. The plurality of pixels P may be disposed in an area defined by the plurality of data lines 211 and / or the plurality of gate lines 212. For example, the plurality of pixels P may be arranged in a matrix form, but the embodiments of the present disclosure are not limited thereto. Additionally, the display panel 100 may include a border area BZ and a bending area BA, which are located on the non-display area NA outside the display area DA.

[0057] Each of the pixels P may include sub-pixels of different colors. The sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. Each of the pixels P may further include white sub-pixels. Hereinafter, a pixel may be understood as a sub-pixel unless otherwise defined. Additionally, each of the sub-pixels may include a pixel circuit.

[0058] The pixel circuit may include a light-emitting element, a driving element for supplying current to the light-emitting element, one or more switching elements for switching the current path of the driving element and the light-emitting element, and a capacitor for maintaining the voltage Vgs between the gate and the source of the driving element.

[0059] The light-emitting element may be implemented as an organic light-emitting diode (OLED). The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), an electron transport layer (ETL), a hole blocking layer (HBL), and an electron injection layer (EIL), but is not limited thereto. Alternatively, the organic compound layer may further include a charge generation layer (CGL), such as a P-type charge generation layer and an N-type charge generation layer. When a voltage is applied to the anode electrode and the cathode electrode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons, resulting in the emission of visible light from the light-emitting layer (EML).

[0060] The display panel driver can write pixel data of an input image to the pixel P. The display panel driver can include a data driver and a gate driver 110. The data driver can supply a data voltage of pixel data to the data line 211. The gate driver 110 can sequentially supply gate pulses to the gate line 212. The data driver can be integrated into the driver IC 300. The driver IC 300 can be attached to the display panel 100.

[0061] The driver IC 300 can be connected to the data line 211 through a data output channel to supply a voltage of a data signal to the display area DA. The driver IC 300 can include a timing controller. The timing controller can send pixel data of an input image received from the host system to the data driver and control the operation timing of the data driver and the gate driver 110.

[0062] The data driver of the driving IC 300 can convert pixel data into a gamma compensation voltage through a digital-to-analog converter (DAC) and output a data voltage.

[0063] The gate driver 110 can include a shift register formed in a circuit layer of the display panel 100 together with a pixel array. The shift register of the gate driver 110 can sequentially supply gate signals to the gate line 212 under the control of the timing controller. The gate signals can include a scan pulse and a light emission control pulse. The shift register can include a scan driver that outputs a scan pulse and an EM driver that outputs an EM pulse.

[0064] The host system SYS can be implemented by an application processor (hereinafter referred to as AP). The host system SYS can send pixel data of an input image to the driver IC 300. The host system SYS can be connected to the driver IC 300 through a flexible printed circuit, such as an FPC (flexible printed circuit), but the embodiments of the present disclosure are not limited thereto.

[0065] The driver IC 300 is illustrated as being provided on the display panel 100, but is not necessarily limited thereto. For example, the driver IC 300 mounted on a flexible printed circuit board can be electrically connected to the display panel 100. The flexible circuit board can also be bonded to the display panel 100 through a bonding process in a state where an anisotropic conductive film (ACF) is aligned in an area where the flexible circuit board FCB will be bonded to the display panel 100.

[0066] In the display panel 100, a part of the area including the driver IC 300 can be bent toward the rear of the display panel 100 by using a bending area BA. For example, for a smaller device, bending may be necessary to reduce the size. However, it is not necessarily limited thereto.

[0067] According to an embodiment of the present disclosure, the driver IC 300 may have a chip-on-panel (COP) structure disposed on the display panel 300. In the COP structure, a plurality of driving pads 220 may be disposed in the non-display area NA. The plurality of driving pads 220 may be disposed at the ends (or one side) of the plurality of signal lines 210 to be connected to the driver IC 300. The plurality of driving pads 220 may be disposed in the first area SA where the driver IC 300 is disposed.

[0068] According to an embodiment of the present disclosure, it may further include dummy pads 230 disposed adjacent to the driving pads 220.

[0069] The plurality of dummy pads 230 may be disposed in the first area SA where the driver IC 300 is attached. The driving pads 220 are vulnerable to electrolytic corrosion because moisture introduced from the outside in a high-temperature and high-humidity environment can cause hydroxyl groups (OH-). For example, during driving, the intensity of hydroxyl groups (OH-) in the floating area of the driver IC 300 may increase, thereby introducing negative charges into the adjacent driving pads 220 supplied with a positive voltage, resulting in electrolytic corrosion of the driving pads 220.

[0070] The dummy pads 230 may prevent or inhibit the reaction of negative charges with the driving pads 220 by attracting negative charges. For example, the dummy pads 230 may prevent the driving pads 220 supplied with a positive voltage from reacting with negative charges caused by the introduction of external moisture. As a result, electrolytic corrosion in the driving pads 220 can be prevented.

[0071] Electrolytic corrosion may be a phenomenon in which current flows in a conductor and corrodes the conductor. Corrosion occurs regardless of whether current is applied, while electrolytic corrosion occurs when current flows through a conductor such as a wire, causing the conductor to corrode through a redox reaction.

[0072] The dummy pads 230 may be disposed in the first area SA. The dummy pads 230 may be disposed at the edge of the first area SA. The edge or floating area of the driver IC 300 may be an area where the intensity of hydroxyl OH- increases during driving, thereby causing a large amount of negative charges to be introduced into the adjacent driving pads 220 supplied with a positive voltage. Therefore, the dummy pads 230 may be disposed in the edge of the driver IC 300.

[0073] Dummy pads 230 may be provided to match the number of bumps on the driver IC 300 in terms of the number of pads. The number of bumps on the driver IC 300 may be arbitrarily set to allow connection to various display panels. Thus, when some of the driving pads in a given panel are unnecessary, they may be formed as dummy pads 230. For example, the required number of lines may vary depending on the type of the display panel or the driver IC 300, and thus the number of dummy pads 230 may also vary, but embodiments of the present disclosure are not limited thereto.

[0074] According to an embodiment of the present disclosure, a positive voltage may be applied to the dummy pad 230 to attract the negative charges accumulated at both edges of the first region SA, thereby preventing the negative charges from moving toward the central portion where the driving pads 220 are provided. This can prevent or delay the reaction between the positive voltage applied to the driving pads and the negative charges and cause electrolytic corrosion.

[0075] Due to process deviations and device characteristic deviations caused by the manufacturing process of the display panel 100, there may be differences in the electrical characteristics of the driving elements for each sub-pixel, and such differences may increase as the pixel driving time elapses. To compensate for the deviations in the electrical characteristics of the driving elements for each pixel, an internal compensation technique or an external compensation technique may be applied to the organic light emitting display device.

[0076] The internal compensation technique may sense the threshold voltage of the driving element for each sub-pixel by using an internal compensation circuit implemented in each pixel circuit, and compensate the gate-source voltage Vgs of the driving element through the threshold voltage.

[0077] The external compensation technique may sense the current or voltage that varies according to the electrical characteristics of the driving element in real time by using an external compensation circuit. The external compensation technique may modulate the pixel data (or digital data) of the input image through the deviation (or difference) in the electrical characteristics of the driving element sensed for each pixel, thereby compensating for the deviation (or difference) in the electrical characteristics of the driving element in each pixel in real time.

[0078] Figure 4 and 5 are circuit diagrams showing various pixel circuits of a display area of a display device according to an embodiment of the present disclosure. Figure 6 is a waveform diagram showing the driving signals applied to Figure 5 the pixel circuit shown in

[0079] Referring to Figure 4 , the pixel circuit may include a light emitting element EL, a driving element DT, a switching element M01, and a capacitor Cst, but embodiments of the present disclosure are not limited thereto. In the pixel circuit, the driving element DT and the switching element M01 may be implemented as but not limited to n-channel transistors.

[0080] The switching element M01 can connect the data line DL in response to the scan pulse SCAN. For example, the switching element M01 can be turned on in response to the gate conduction voltage of the scan pulse SCAN to connect the data line DL to the gate electrode of the driving element DT.

[0081] The driving element DT can supply current to the light-emitting element EL. The driving element DT can include a first electrode, a gate electrode, and a second electrode.

[0082] The first electrode can be connected to the VDD line PL to which the pixel driving voltage ELVDD is applied. The gate electrode can be connected to the switching element M01 and the capacitor Cst. The second electrode can be connected to the light-emitting element EL. And the driving element DT drives the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage Vgs. Here, when the forward voltage between the anode electrode and the cathode electrode of the light-emitting element EL is greater than or equal to the threshold voltage, the light-emitting element can be turned on to emit light.

[0083] The capacitor Cst can be connected to the gate electrode of the driving element DT. The capacitor Cst can be connected between the gate electrode and the second electrode of the driving element DT to store the gate-source voltage Vgs of the driving element DT.

[0084] Figure 5 The pixel circuit shown can also include an EM switching element. The EM switching element can switch the current path of the light-emitting element EL in response to the EM pulse. The EM switching element can be connected between the pixel driving voltage ELVDD and the driving element DT or between the driving element DT and the light-emitting element EL.

[0085] Reference Figure 5 and 6 , the pixel circuit includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, and a switching circuit.

[0086] The switching circuit can switch the voltages applied to the light-emitting element EL and the driving element DT. The switching circuit is connected to the power supply lines PL1, PL2, and PL3 to which the pixel driving voltage ELVDD, the low-potential voltage ELVSS, and the initialization voltage Vini are applied, the data line DL, and the gate lines GL1, GL2, and GL3. The switching circuit can switch the voltages applied to the light-emitting element EL and the driving element DT in response to the scan pulses [SCAN(N - 1) and SCAN(N)] and the EM pulse [EM(N)].

[0087] The switching circuit can sample the threshold voltage Vth of the driving element DT using a plurality of switching elements M1 to M6, store the sampled threshold voltage Vth in the capacitor Cst, and compensate the gate voltage of the driving element DT with the threshold voltage Vth of the driving element DT. The driving element DT and the switching elements M1 to M6 can be implemented as, but not limited to, p-channel transistors.

[0088] The driving period of the pixel circuit can be divided into an initialization period Tini, a sampling period Tsam, and an emission period Tem, as Figure 6 shown.

[0089] The Nth scan pulse [SCAN(N)] can be generated as a gate-on voltage VGL during the sampling period Tsam and applied to the first gate line GL1. The (N - 1)th scan pulse [SCAN(N - 1)] can be generated and applied to the second gate line GL2 before the Nth scan pulse [SCAN(N)]. The (N - 1)th scan pulse [SCAN(N - 1)] can include the initialization period Tini. The EM pulse [EM(N)] can be generated as a gate-off voltage VEH during the initialization period Tini and the sampling period Tsam and applied to the third gate line GL3.

[0090] During the initialization period Tini, the (N - 1)th scan pulse [SCAN(N - 1)] can be generated as a gate-on voltage VGL and applied to the second gate line GL2. During the initialization period Tini, the voltages of the first gate line GL1 and the third gate line GL3 can be the gate-off voltages VGH and VEH, respectively.

[0091] The Nth scan pulse [SCAN(N)] can be generated as a pulse of the gate-on voltage VGL during the sampling period Tsam and applied to the first gate line GL1. During the sampling period Tsam, the voltages of the second gate line GL2 and the third gate line GL3 are the gate-off voltage VGH.

[0092] The EM pulse [EM(N)] can be generated as a gate-on voltage VEL during at least a part of the emission period Tem and applied to the third gate line GL3. During the emission period Tem, the voltages of the first gate line GL1 and the second gate line GL2 can be the gate-off voltage VGH.

[0093] The anode electrode of the light-emitting element EL can be connected to the fourth node n4 between the fourth switching transistor M4 and the sixth switching transistor M6. The fourth node n4 can be connected to the anode electrode of the light-emitting element EL, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode electrode of the light-emitting element EL can be connected to the ELVSS line PL3 to which a low-potential power supply voltage ELVSS is applied. The light-emitting element EL can emit light by a current flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the light-emitting element EL can be switched by the second switching element M2 and the fourth switching element M4.

[0094] The capacitor Cst can be connected between the ELVDD line PL1 and the second node n2. The capacitor Cst can include a first electrode connected to the ELVDD line PL1 and a second electrode connected to the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT can be charged to the capacitor Cst. In each sub-pixel, the data voltage Vdata is compensated by the threshold voltage Vth of the driving element DT, thereby compensating for the characteristic deviation (or difference) of the driving element DT in the sub-pixel.

[0095] The first switching element M1 can be turned on according to the gate-on voltage VGL of the Nth scan pulse [SCAN(N)] to connect the second node n2 and the third node n3. The second node n2 can be connected to the gate electrode of the driving element DT, the second electrode of the capacitor Cst, and the first electrode of the first switching element M1. The third node n3 can be connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. The gate electrode of the first switching element M1 can be connected to the first gate line GL1 to receive the Nth scan pulse [SCAN(N)]. The first electrode of the first switching element M1 can be connected to the second node n2, and the second electrode of the first switching element M1 can be connected to the third node n3.

[0096] Since the first switching element M1 is turned on for a duration of one horizontal period 1H, and the Nth scan pulse [SCAN(N)] is generated as the gate-on voltage VGL in one frame period during the one horizontal period, a leakage current can be generated in its off state. To suppress the leakage current of the first switching element M1, the first switching element M1 can be implemented by a transistor having a double-gate structure, in which two transistors are connected in series, but the embodiments of the present disclosure are not limited thereto.

[0097] The second switching element M2 can be turned on according to the gate conduction voltage VGL of the N-th scan pulse [SCAN(N)] to supply the data voltage Vdata to the first node n1. The gate electrode of the second switching element M2 can be connected to the first gate line GL1 to receive the N-th scan pulse [SCAN(N)]. The first electrode of the second switching element M2 can be connected to the first node n1. The second electrode of the second switching element M2 can be connected to the data line DL to which the data voltage Vdata is applied. The first node n1 can be connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0098] The third switching element M3 can be turned on according to the gate conduction voltage VGL of the EM pulse [EM(N)] to connect the ELVDD line PL1 to the first node n1. The gate electrode of the third switching element M3 can be connected to the third gate line GL3 to which the EM pulse [EM(N)] is to be supplied. The first electrode of the third switching element M3 can be connected to the ELVDD line PL1. The second electrode of the third switching element M3 can be connected to the first node n1.

[0099] The fourth switching element M4 can be turned on according to the gate conduction voltage VEL of the EM pulse [EM(N)] to connect the third node n3 to the fourth node n4. The gate electrode of the fourth switching element M4 can be connected to the third gate line GL3 to which the EM pulse [EM(N)] is to be supplied. The first electrode of the fourth switching element M4 can be connected to the third node n3, and its second electrode can be connected to the fourth node n4.

[0100] The fifth switching element M5 can be turned on according to the gate conduction voltage VGL of the (N-1)-th scan pulse [SCAN(N-1)] to connect the second node n2 to the Vini line PL2. The gate electrode of the fifth switching element M5 can be connected to the second gate line GL2 to which the (N-1)-th scan pulse [SCAN(N-1)] is to be supplied. The first electrode of the fifth switching element M5 can be connected to the second node n2, and its second electrode can be connected to the Vini line PL2 to which the initialization voltage Vini is applied. In order to suppress the leakage current of the fifth switching element M5, the fifth switching element M5 can be implemented by a transistor having a structure in which two transistors are connected in series, but the embodiments of the present disclosure are not limited thereto.

[0101] The sixth switching element M6 can be turned on by the gate conduction voltage VGL of the N-th scan pulse [SCAN(N)] to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 can be connected to the second gate line GL2 to which the N-th scan pulse [SCAN(N)] is to be supplied. The first electrode of the sixth switching element M6 can be connected to the Vini line PL2, and its second electrode can be connected to the fourth node n4. In another embodiment, the gate electrodes of the fifth switching element M5 and the sixth switching element M6 can be commonly connected to the second gate line GL2 to which the (N - 1)-th scan pulse [SCAN(N - 1)] is applied. In this case, the fifth switching element M5 and the sixth switching element M6 can be turned on simultaneously in response to the (N - 1)-th scan pulse [SCAN(N - 1)] during the initialization period Tini.

[0102] The driving element DT can drive the light-emitting element EL by modulating the current flowing to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT can include a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0103] During the initialization period Tini, the (N - 1)-th scan pulse [SCAN(N - 1)] can be generated as the gate conduction voltage VGL. The N-th scan pulse [SCAN(N)] and the EM pulse [EM(N)] can maintain the gate high and the gate cut-off voltages VGH and VEH during the initialization period Tini. Therefore, during the initialization period Tini, the fifth switching element M5 can be turned on, so that the second node n2 can be initialized to the initialization voltage Vini. When the fifth switching element M5 and the sixth switching element M6 are turned on during the initialization period Tini, the second node n2 and the fourth node n4 can be initialized to the initialization voltage Vini.

[0104] The holding period Th can be set between the initialization period Tini and the sampling period Tsam and between the sampling period Tsam and the emission period Tem. During the holding period, the scan pulses [SCAN(N - 1) and [SCAN(N)] and the EM pulse [EM(N)] are at the gate cut-off voltage VGH, and the main nodes n1 to n4 of the pixel circuit can be floating.

[0105] During the sampling period Tsam, the N-th scan pulse [SCAN(N)] can be generated as the gate-on voltage VGL. The pulse of the N-th scan pulse [SCAN(N)] can be synchronized with the data voltage Vdata of the pixel data to be written to the sub-pixels of the N-th pixel line. The (N-1)-th scan pulse [SCAN(N-1)] and the EM pulse [EM(N)] can be at the gate-off voltages VGH and VEH, respectively, during the sampling period Tsam. Therefore, the first switching element M1 and the second switching element M2 can be turned on during the sampling period Tsam. At this time, the sixth switching element M6 can also be turned on to supply the initialization voltage Vini to the fourth node n4, thereby preventing the light-emitting element EL from emitting light.

[0106] During the sampling period Tsam, the gate voltage DTG of the driving element DT can be boosted by the current flowing through the first switching element M1 and the second switching element M2. During the sampling period Tsam, the threshold voltage Vth of the driving element DT can be sampled in the capacitor Cst.

[0107] During the emission period Tem, the EM pulse [EM(N)] can be generated as the gate-on voltage VGL. During the emission period Tem, the voltage of the EM pulse [EM(N)] can be inverted to a predetermined duty ratio. Therefore, the EM pulse [EM(N)] can be generated as the gate-on voltage VGL during at least a part of the emission period Tem.

[0108] When the EM pulse [EM(N)] is at the gate-on voltage VEL, a current flows between the pixel driving voltage ELVDD and the light-emitting element EL, causing the light-emitting element EL to emit light. During the emission period Tem, the (N-1)-th scan pulse [SCAN(N-1)] and the N-th scan pulse [SCAN(N)] can be at the gate-off voltage VGH. During the emission period Tem, the third switching element M3 and the fourth switching element M4 can be turned on according to the gate-on voltage VEL of the EM pulse [EM(N)]. When the EM pulse [EM(N)] is at the gate-on voltage VEL, the third switching element M3 and the fourth switching element M4 are turned on, causing a current to flow to the light-emitting element EL. During the emission period Tem, the current flowing through the light-emitting element EL is as follows: K(ELVDD - Vdata)2. Here, K is a constant value determined by the charge mobility, parasitic capacitance, and channel capacitance of the driving element DT.

[0109] According to an embodiment of the present disclosure, since the EM pulse emits light at a low brightness, the width of the gate-on voltage VGL can be narrowed, and the interval between the gate-high voltages VGH and VEH can be increased. Therefore, when the dummy pad is connected to the driving pad that supplies the EM pulse, the gate-high voltage can be applied to the dummy pad.

[0110] Figure 7 is a cross-sectional view showing a cross-sectional structure of a display region according to an embodiment of the present disclosure. Figure 8 is a cross-sectional view showing a cross-sectional structure of a display region according to another embodiment of the present disclosure. Figure 9 is a schematic view showing a cross-sectional structure of a display region according to another embodiment of the present disclosure.

[0111] Referring Figure 7 , the display panel 100 may include a circuit layer 12, an emission element layer 14, and a encapsulation layer 16 stacked on a substrate 10.

[0112] The substrate 10 may be formed of an insulating material or a flexible material. For example, the substrate 10 may be made of glass, metal, or plastic, but is not limited thereto. When the substrate 10 is made of plate-shaped non-alkali glass or non-alkali glass, it may be more resistant to impact and less deformed than a plastic substrate.

[0113] The circuit layer 12 may include a pixel circuit connected to lines such as data lines, gate lines, and power lines, and a gate driver connected to the gate lines. In addition, the circuit elements and lines in the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by the insulating layers therebetween, and an active layer containing a semiconductor material.

[0114] The emission element layer 14 may include a light-emitting element EL driven by the pixel circuit. The light-emitting element EL may include a plurality of red light-emitting elements R, a plurality of green light-emitting elements G, and a plurality of blue light-emitting elements B. In another embodiment, the emission element layer 14 may further include a white light-emitting element and a color filter. The light-emitting element EL of the emission element layer 14 may be covered with an encapsulation layer including an organic film and an inorganic film.

[0115] The encapsulation layer 16 may cover the emission element layer 14 to seal the circuit layer 12 and the emission element layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which organic films and inorganic films are stacked alternately, but embodiments of the present disclosure are not limited thereto. The inorganic film may block the intrusion of moisture and oxygen. The organic film may flatten the surface of the inorganic film. When the organic layer and the inorganic layer are stacked in multiple layers, the moving path of moisture or oxygen introduced from the outside becomes longer compared to an encapsulation composed of a single layer, thereby effectively blocking the intrusion of moisture / oxygen affecting the emission element layer 14.

[0116] Referring Figure 8, the display panel 100 may further include a touch sensor layer 18 formed on the encapsulation layer 16. The touch sensor layer 18 may be implemented by a capacitive touch sensor, which senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer 18 may include sensor electrodes TE1 that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the sensor electrodes TE1. The touch sensor layer 18 may include an organic film that covers the sensor electrodes TE1 of the touch sensor.

[0117] Reference Figure 9 , a plurality of pixel circuits and lines connected to the pixel circuits may be disposed in the display area DA of the display panel 100. The pixel circuits in the display area DA may include pixel circuits for driving red sub-pixels of red light-emitting elements, pixel circuits for driving green sub-pixels of green light-emitting elements, and pixel circuits for driving blue sub-pixels of blue light-emitting elements. And a plurality of circuit regions are separated along the X-axis direction of the display panel 100 within the display area DA.

[0118] The substrate PI may include a first substrate PI1 and a second substrate PI2. An inorganic film IPD may be formed between the first substrate PI1 and the second substrate PI2. The inorganic film IPD may block moisture from invading from the outside.

[0119] A first buffer layer BUF1 may be formed on the second substrate PI2. The first buffer layer BUF1 may be formed of a multilayer insulating film in which two or more oxide films (SiO2) and nitride films (SiNx) are stacked. A first semiconductor layer may be formed on the first buffer layer BUF1. The first semiconductor layer may include a polysilicon semiconductor layer. The first semiconductor layer may include a polysilicon active layer ACT1 that forms a semiconductor channel in the first TFT TFT1.

[0120] A first gate insulating layer GI1 may be formed on the first buffer layer BUF1 to cover the active layer ACT1 of the first semiconductor layer.

[0121] The first gate insulating layer GI1 may include a single layer of inorganic insulating material. A first metal layer may be formed on the first gate insulating layer GI1.

[0122] The first metal layer may be insulated from the first semiconductor layer through the first gate insulating layer GI1.

[0123] The first metal layer may include a single layer of metal or a multilayer of metals in which two or more metal layers are stacked on each other. The first metal layer may include a gate electrode GE1 of the first TFT TFT1 and a light-shielding layer BSM under the second TFT TFT2.

[0124] The first interlayer insulating layer ILD1 may be formed on the first gate insulating layer GI1. The first interlayer insulating layer ILD1 may cover the first metal layer. The first interlayer insulating layer ILD1 may include an inorganic insulating material. The second buffer layer BUF2 may be formed on the first interlayer insulating layer ILD1. The second buffer layer BUF2 may include a single layer or multiple layers of inorganic insulating materials, but embodiments of the present disclosure are not limited thereto.

[0125] The second semiconductor layer may include an oxide semiconductor layer ACT2 that forms a semiconductor channel in the second TFT TFT2. The second gate insulating layer GI2 may be formed or deposited on the second buffer layer BUF2 to cover the active layer ACT2 of the second semiconductor layer. The second gate insulating layer GI2 may include a single layer or multiple layers of inorganic insulating materials. The second metal layer may be formed on the second gate insulating layer GI2. The second metal layer may be insulated from the second semiconductor layer by the second gate insulating layer GI2.

[0126] The second metal layer may include a single metal layer or multiple metal layers, and in the case of multiple metal layers, two or more metal layers are stacked on top of each other. The second metal layer may include the gate electrode GE2 of the second TFT TFT2 and the lower capacitor electrode CE1.

[0127] The second interlayer insulating layer ILD2 may be formed on the second gate insulating layer GI2. The second interlayer insulating layer ILD2 may cover the second metal layer. The second interlayer insulating layer ILD2 may include a single layer or multiple layers of inorganic insulating materials. The third metal layer may be formed on the second interlayer insulating layer ILD2. The third metal layer may be insulated from the second metal layer by the second interlayer insulating layer ILD2.

[0128] The third metal layer may include a single metal layer or multiple metal layers, and in the case of multiple metal layers, two or more metal layers are stacked on top of each other. The third metal layer may include the upper capacitor electrode CE2. The capacitor Cst of the pixel circuit may include the upper capacitor electrode CE2, the lower capacitor electrode CE1, and a dielectric layer between the upper capacitor electrode CE2 and the lower capacitor electrode CE1, for example, the second interlayer insulating layer ILD2.

[0129] The third interlayer insulating layer ILD3 may be formed on the second interlayer insulating layer ILD2. The third interlayer insulating layer ILD3 may cover the third metal layer. The third interlayer insulating layer ILD3 may include a single layer or multiple layers of inorganic insulating materials. The fourth metal layer SD1 may be formed on the third interlayer insulating layer ILD3. The fourth metal layer may be insulated from the second semiconductor layer by the second gate insulating layer GI2.

[0130] The fourth metal layer SD1 may include a single metal layer or multiple metal layers. In the case of multiple metal layers, two or more metal layers are stacked on top of each other. The fourth metal layer SD1 may include the first electrode E11 and the second electrode E12 of the first TFT TFT1, and the first electrode E21 and the second electrode E22 of the second TFT TFT2. The fourth metal layer SD1 may be the first signal line.

[0131] The first electrode E11 and the second electrode E12 of the first TFT TFT1 may be connected to the first active layer ACT1 through a first contact hole that passes through the insulating layers GI1, ILD1, BUF2, GI2, ILD2, and ILD3. The first electrode E21 and the second electrode E22 of the second TFT TFT2 may be connected to the second active layer ACT2 through a second contact hole that passes through the insulating layers GI2, ILD2, and ILD3. The first electrode E21 of the second TFT TFT2 may be connected to the light-shielding layer BSM through a third contact hole that passes through the insulating layers ILD1, BUF2, GI2, ILD2, and ILD3. Due to the voltage swing between the gate-on voltage and the gate-off voltage with a large voltage difference, high-intensity fields may be generated in the fourth metal layers E11 to E22, but embodiments of the present disclosure are not limited thereto.

[0132] The first planarization layer PLN1 may cover the fourth metal layers E11 to E22. The first planarization layer PLN1 may be made of an organic insulating material. The first planarization layer PLN1 may cover the display area DA of the circuit layer 12. When coating (or forming)

[0133] the first planarization layer PLN1, the organic insulating material may flow to the edge of the display panel 100 to cover the side surfaces of the circuit layer 12 in the border area BZ.

[0134] The fifth metal layer may be formed on the first planarization layer PLN1. The fifth metal layer may be insulated from the fourth metal layer through the first planarization layer PLN1. The fifth metal layer may include a single metal layer or multiple metal layers. In the case of multiple metal layers, two or more metal layers are stacked on top of each other. The fifth metal layer may include a metal layer SD2 that connects the light-emitting element EL to the second TFT TFT2. The metal layer SD2 may be connected to the second electrode E22 of the second TFT TFT2 through a fourth contact hole that passes through the first planarization layer PLN1.

[0135] The second planarization layer PLN2 may be formed on the first planarization layer PLN1 to cover the metal layer of the fifth metal layer. The second planarization layer PLN2 may be made of an organic insulating material. The second planarization layer PLN2 may cover the display area DA of the circuit layer 12. The sixth metal layer may be formed on the second planarization layer PLN2. The second planarization layer PLN2 may planarize the surface on which the sixth metal layer is formed.

[0136] The sixth metal layer may include a single metal layer or multiple metal layers. In the case of multiple metal layers, two or more metal layers are stacked on top of each other. The sixth metal layer may include the anode electrode AND of the light-emitting element EL. The anode electrode AND may be in contact with the metal layer SD2, which is connected to the second TFT TFT2 of the pixel circuit through a fifth contact hole passing through the second planarization layer PLN2.

[0137] In the light-emitting element layer 14, a bank BNK may be formed on the second planarization layer PLN2 to cover the edge of the anode electrode AND. The bank BNK may be formed by a pattern that separates the light-emitting regions (or aperture regions), and light is transmitted from the corresponding pixel to the outside through the light-emitting regions. The bank BNK may be patterned during a photolithography process by including an organic insulating material having photosensitive characteristics, but embodiments of the present disclosure are not limited thereto.

[0138] A spacer SPC having a predetermined height may be formed on the bank BNK. The bank BNK and the spacer SPC may be integrated with the same organic insulating material. The spacer SPC may fix the gap between the fine metal mask (FMM) and the anode electrode AND, such that the FMM does not contact the anode electrode AND during the deposition process of the light-emitting element EL formed of an organic compound.

[0139] The seventh metal layer used as the cathode electrode CAT of the light-emitting element EL may be formed on the light-emitting element EL implemented by the bank BNK and the organic compound layer. The seventh metal layer may be connected between sub-pixels in the display area DA.

[0140] The encapsulation layer 16 may include one or more insulating layers covering the cathode electrode CAT of the light-emitting element EL. The one or more insulating layers may include a first inorganic insulating layer PAS1 covering the cathode electrode CAT, an organic insulating layer PCL covering the first inorganic insulating layer PAS1, and a second inorganic insulating layer PAS2 covering the organic insulating layer PCL.

[0141] The touch sensor layer 18 may include a third buffer layer BUF3 covering the second inorganic insulating layer PAS2, a sensor electrode TE1 formed on the third buffer layer BUF3, and an organic insulating layer PAC covering the sensor electrode TE1.

[0142] Figure 10 is a schematic diagram showing signal lines and pads in a display device according to another embodiment of the present disclosure. Figure 11 is a schematic diagram showing Figure 10 the region EA of Figure 12 is a cross-sectional view of a driving pad and a dummy pad according to an embodiment of the present disclosure.

[0143] Refer toFigure 10 and 11 In the first region SA, the outer portion EA and the central portion CA may be included. The outer portion EA may be on one side and the other side of the first region SA. The outer portion EA may be on both sides of the central portion CA.

[0144] A plurality of signal lines 210 may extend from the display area DA to the first region SA. A plurality of driving pads 220 connected to the signal lines 210 may be provided in the first region SA.

[0145] Some of the plurality of driving pads 220 may be provided in the central portion CA of the first region SA, and the remaining driving pads may be provided in the outer portion EA of the first region SA. The dummy pads 230 may be provided in the outer portion EA of the first region SA. For example, the remaining ones of the plurality of driving pads 220 and the dummy pads 230 may be provided in the outer portion EA of the first region SA.

[0146] Each of the driving pads 220 may be provided in the direction from the display area DA toward the first region SA. The driving pads 220 may include a plurality of sub-driving pads 220a, 220b, and 220c. The plurality of sub-driving pads 220a, 220b, and 220c may be provided in the outer portion EA and the central portion CA of the first region SA. The plurality of sub-driving pads 220a, 220b, and 220c may be provided in the direction from the display area DA toward the first region SA. The plurality of sub-driving pads 220a, 220b, and 220c may be electrically connected through the signal lines 210. Therefore, even if there is a contact failure between any one of the sub-driving pads 220a, 220b, and 220c and the bumps on the driver IC 300, the signal lines 210 can be connected to the driver IC 300 through the other sub-driving pads 220a, 220b, and 220c.

[0147] Each of the driving pads 220 may include, but is not limited to, three sub-driving pads 220a, 220b, and 220c. The number of the plurality of sub-driving pads 220a, 220b, and 220c may be changed according to the bump structure or design of the driver IC 300.

[0148] The dummy pad 230 may be disposed in a direction from the display area DA toward the first area SA. The dummy pad 230 may include a plurality of sub-dummy pads 230a, 230b, and 230c. The plurality of sub-dummy pads 230a, 230b, and 230c may be disposed in a direction from the display area DA toward the first area SA. For example, some of the plurality of sub-dummy pads 230a, 230b, and 230c and some of the plurality of driving pads 220 may be disposed on each of the outer portions EA of the first area SA. The number of the plurality of sub-dummy pads 230a, 230b, and 230c may be changed according to the bump structure or design specifications of the driver IC 300.

[0149] Reference Figure 11 , the outer portion EA of the first area SA may include a first outer portion DPA, a second outer portion GPA, and a third outer portion SPA.

[0150] The first outer portion DPA may be one side of the first area SA. A plurality of dummy pads 230 may be disposed on the first outer portion DPA. For example, the plurality of sub-dummy pads 230a, 230b, and 230c may be disposed on the first outer portion DPA.

[0151] The second outer portion GPA may be disposed adjacent to the first outer portion DPA. The driving pads 220 connected to the gate lines may be disposed in the second outer portion GPA.

[0152] The third outer portion SPA may be disposed adjacent to the second outer portion GPA. The second outer portion GPA may be located between the first outer portion DPA and the third outer portion SPA. The driving pads 220 connected to the gate lines may be disposed in the third outer portion SPA.

[0153] The driving pads 220 and the dummy pads 230 may be disposed to extend in an inclined direction with respect to the vertical line. The driving pads 220 and the dummy pads 230 may have a parallelogram shape. However, the shapes of the driving pads 220 and the dummy pads 230 are not limited thereto.

[0154] The driving pad 220 may include a plurality of sub-driving pads 220a, 220b, and 220c spaced apart in the inclined direction. The dummy pad 230 may include a plurality of sub-dummy pads 230a, 230b, and 230c spaced apart in the inclined direction. In addition, the signal line 210 connecting the plurality of sub-driving pads 220a, 220b, and 220c may extend in the inclined direction.

[0155] Dummy pad 230 may include a first dummy pad 231 and a second dummy pad 232. The first dummy pad 231 may be disposed outside the first region SA. The second dummy pad 232 may be disposed between the plurality of driving pads 220. The second dummy pad 232 and the sub-dummy pads 230a, 230b, and 230c may not be connected to each other, but this is not necessarily limited thereto.

[0156] A plurality of first dummy pads 231 may be disposed on the outside, such that the number thereof may be greater than that of the second dummy pad 232. However, the embodiments are not limited thereto, and the number of the second dummy pads 232 may be greater according to the type of the display panel.

[0157] The size of the dummy pad 230 may be the same as or greater than that of the driving pad 220. The sizes of the plurality of dummy pads 230 may be the same as each other, but some of the dummy pads 230 may have different sizes. The plurality of sub-dummy pads 230a, 230b, and 230c may be connected to each other through the signal line 210, or may be electrically isolated from each other.

[0158] According to an embodiment of the present disclosure, since the dummy pad 230 is disposed outside or at the edge of the first region SA, it may capture negative charges at the driver IC to prevent electrolytic corrosion in the driving pad 220 and optimize the region where the driver IC is disposed.

[0159] Reference Figure 12 , the driving pad 220 may include a substrate PI, a buffer layer BUF, a gate electrode GE, a first line electrode SD1, a second line electrode SD2, and a sensor electrode TE1.

[0160] The buffer layer BUF may be disposed on the substrate PI.

[0161] The gate electrode GE may be disposed on the buffer layer BUF. The gate electrode GE may be electrically connected to the signal line 210. For example, the gate electrode GE may be connected to the signal line 210, and the signal line will be electrically connected to the display area.

[0162] The interlayer insulating film ILD may be disposed on the gate electrode GE. The first line electrode SD1 may be disposed on the interlayer insulating film ILD. The second line electrode SD2 may be disposed on the interlayer dielectric film ILD. The second line electrode SD2 may be disposed on the first line electrode SD1.

[0163] The first line electrode SD1 may be electrically connected to the gate electrode GE by passing through the interlayer insulating layer ILD. The second line electrode SD2 may be disposed on the first line electrode SD1 and electrically connected to the first line electrode SD1. However, this is not necessarily limited thereto, and only either the first line electrode SD1 or the second line electrode SD2 may be provided.

[0164] The third buffer layer BUF3 can be disposed on the second line electrode SD2.

[0165] The sensor electrode TE1 can be disposed on the third buffer layer BUF3 and electrically connected to the second line electrode SD2. The sensor electrode TE1 can be fabricated wide enough to cover the second line electrode SD2. Thus, the drive pad 220 of the driver IC 300 and the bump 300a can be stably connected to each other.

[0166] The anisotropic conductive film ACF can be disposed between the drive pad 220 of the driver IC 300 and the bump 300a. Thus, the drive pad 220 of the driver IC 300 and the bump 300a can be electrically connected through the conductive particles CB.

[0167] According to an embodiment of the present disclosure, the drive pad 220 can be configured using the gate electrode GE, the first line electrode SD1, the second line electrode SD2, and the sensor electrode TE1 in the display area.

[0168] The drive pad 220 can be structurally modified in various ways. For example, it can be constituted by one or more of the first line electrode SD1, the second line electrode SD2, and the sensor electrode TE1 disposed on the gate electrode GE. For example, the sensor electrode can be omitted, and the second line electrode SD2 can be connected to the bump 300a of the driver IC 300. For example, the drive pad 220 can use a metal layer disposed in the display area to form a structurally different drive pad 220.

[0169] The dummy pad 230 can have the same structure as the drive pad 220. For example, the dummy pad 230 can be different from the drive pad 220 in that it is not connected to the signal line 210, and the configuration of the pad itself can be the same. Thus, since the drive pad 220 and the dummy pad 230 have the same height, the flatness of the driver IC 300 can be maintained to improve the driving reliability.

[0170] Figure 13 is a schematic diagram showing Figure 10 the potential level of the region EA. Figure 14 is a schematic diagram showing that negative charges are concentrated at the edge of the first region where the driver IC is disposed.

[0171] Referring to Figure 13 , the outer portion EA of the first region SA can include a first outer portion DPA on which a plurality of dummy pads 230 are disposed, a second outer portion GPA on which drive pads 220 connected to the gate line are disposed, and a third outer portion SPA on which drive pads 220 connected to the data line are disposed. Figure 13It is a schematic diagram showing that the driving pad 220 and the dummy pad 230 are provided on the substrate PI and the anisotropic conductive film ACF is provided thereon.

[0172] Some of the data lines provided on the third outer side portion SPA can be supplied with a positive voltage of a high level, while other data lines can be supplied with a positive or negative voltage of a lower level. Therefore, some portions of the third outer side portion SPA can have a potential level as high as 6V, and some other portions thereof can have a potential level as low as -3V. For example, the initialization voltage or the reset voltage applied to the pixel circuit can be set to a low negative voltage, for example, -5V or -3.3V.

[0173] A clock signal, a scan signal, or a light emission control signal can be applied to the driving pad 220 provided on the second outer side portion GPA, and the clock signal, the scan signal, or the light emission control signal can swing between a gate high voltage and a gate low voltage.

[0174] A negative voltage can be applied to the driving pad 220 closest to the first outer side portion DPA. Therefore, as the driving pad gets closer and closer to the first outer side portion DPA, the concentration (or intensity) of negative charges such as OH- increases at the first outer side portion DPA, thereby forming a low potential level.

[0175] It can be seen that the dummy pad 230 provided on the first outer side portion DPA is floating, so that the externally introduced negative charges gradually accumulate at the first outer side portion DPA, resulting in the formation of a very low potential of -9V. The concentration (or intensity) of negative charges on the first outer side portion DPA can gradually increase each time a voltage is applied to the driving pad 220.

[0176] Reference Figure 14 , when the display panel is driven, the negative charges concentrated at the edge of the first region SA can be moved (indicated by the arrow) to the driving pad 220 to which a positive voltage is applied, resulting in electrolytic corrosion occurring in the driving pad 220. As a result, there is a problem that the electrical connection becomes unstable.

[0177] If the negative charges concentrated at the edge of the first region SA are controlled so as not to move to the driving pad 220 to which a positive voltage is applied, the electrolytic corrosion in the driving pad 220 to which a positive voltage is applied can be prohibited or delayed.

[0178] Figures 15a to 15d It is a schematic diagram showing the electrolytic corrosion in the driving pad due to the negative charges accumulated at the edge of the first region. Figure 16 It is a graph measuring the number of defects occurring in each driving pad.

[0179] Reference Figure 15a, the anisotropic conductive film ACF can be disposed on the dummy pad 230 and the driving pad 220 of the bump 300a that is to be electrically connected to the driver IC 300 through the conductive particles CB. However, the anisotropic conductive film ACF is susceptible to moisture, which may cause a gap SG1 to form between it and the driving pad 220. Therefore, the intrusion of external moisture (H2O) into the gap SG1 may be accelerated, as Figure 15b shown.

[0180] Refer to Figure 15c , when a positive voltage is applied while the intrusion of moisture is accelerated, negative charges may be introduced into the driving pad 220, resulting in electrolytic corrosion. Additionally, metal components of the driving pad 220, such as aluminum ions (Al 3+ ), nickel ions (Ni 2 + ) and oxygen ions (Ox) may migrate. During this process, a short circuit line AIM that is electrically connected to an adjacent driving pad 220 is formed, as Figure 15d shown, thus causing an electrical failure.

[0181] Refer to Figure 16 , it has been observed that among the driving pads 220 disposed on the outermost side, the driving pad 220 to which a negative voltage is applied does not experience any electrolytic corrosion, while the driving pad 220 to which a relatively high positive voltage is applied experiences a large amount of electrolytic corrosion.

[0182] For example, for the second driving pad 222, one defect was detected in the second test, and two and five defects were detected in the third and fourth tests respectively. The second driving pad 222, the third driving pad 223, the fourth driving pad 224, and the fifth driving pad 225 are all driving pads to which a high voltage is applied. On the other hand, the first driving pad 220 to which a negative voltage is applied did not show any defects in all four tests. Therefore, it can be seen that defects mainly occur in the driving pads to which a positive voltage is applied.

[0183] Figures 17 to 19 is a schematic diagram showing various connection relationships of the dummy pads in the display device according to an embodiment of the present disclosure.

[0184] Refer to Figure 17 , when a positive voltage is applied to multiple dummy pads 230, they can attract and concentrate the negative charges at the edge of the first region SA. Therefore, the negative charges do not move to the driving pad 220 to which a positive voltage is applied, thereby suppressing or preventing electrolytic corrosion in the driving pad 220.

[0185] A plurality of dummy pads 230 may be connected in parallel with each other to form an equipotential. At least one of the plurality of dummy pads 230 may be electrically connected to a driving pad 220 to which a positive voltage is applied by a connection line CB1. Therefore, when a positive voltage is applied to the driving pad 220, a positive voltage of the same level may be applied to the plurality of dummy pads 230.

[0186] According to an embodiment of the present disclosure, a dummy pad 230 to which a positive voltage having a high voltage level is applied may be connected to a driving pad 220 to strongly constrain negative charges. Therefore, the voltage applied to the plurality of dummy pads 230 may be equal to the highest value of the positive voltage applied to the plurality of driving pads 220.

[0187] However, this is not necessarily limited thereto, and the voltage applied to the plurality of dummy pads 230 may be lower than the highest value of the positive voltage applied to the plurality of driving pads 220. In a case where it is difficult for the dummy pad 230 to be connected to a driving pad 220 to which a high-level positive voltage is applied (because it is separated from the driving pad 220), among the driving pads 220 adjacent to and capable of being connected to the dummy pad 230, the dummy pad 230 may be connected to another driving pad 220 to which the highest voltage is applied.

[0188] Reference Figure 18 , the voltage to be applied to the dummy pad 230 may be directly applied through a driver IC 300. For example, the dummy pad 230 and the driving pad 220 may be electrically isolated, and the voltage applied to the dummy pad 230 may be provided by the driver IC300 or a power management integrated circuit (PMIC). The plurality of dummy pads 230 may be connected in parallel by a connection line CB2 to form an equipotential.

[0189] In this way, the positive voltage applied to the dummy pad 230 may be set to be higher than the voltage applied to the driving pad 220, thereby increasing the binding force on negative charges. In addition, a positive voltage may be applied to the dummy pad 230 at a time different from the time when the driving pad 220 is driven. Therefore, even when the display device is turned off, negative charge movement can be prevented by periodically applying a positive voltage to the dummy pad 230.

[0190] However, this is not necessarily limited thereto, some of the dummy pads 230 may be electrically connected to the driving pads 220, and a positive voltage may be directly supplied to some of them through the driver IC 300.

[0191] Reference Figure 19 , the plurality of dummy pads 230 may include a first dummy pad 231 provided at an edge of a first region SA and a second dummy pad 232 provided between the plurality of driving pads 220. The plurality of first dummy pads 231 and the second dummy pad 232 may be connected by a connection line CB3 to form an equipotential.

[0192] In this way, it is possible to prevent the negative charges concentrated at the edge of the first region SA and the negative charges around the driving pad 220 to which a positive voltage is applied from reacting with the driving pad 220.

[0193] The positive voltage applied to the first dummy pad 231 and the positive voltage applied to the second dummy pad 232 may have different voltage levels. For example, the first dummy pad 231 may be coupled to the driving pad 220 to which a clock voltage of 2V is applied. For example, the second dummy pad 232 may be coupled to the driving pad 220 to which a gate high voltage of 6V is applied.

[0194] In another example, a positive voltage may be directly applied to the first dummy pad 231 from the driver IC, and the second dummy pad 232 may be connected to the surrounding driving pads 220. In this case, the first dummy pad 231 receives a high positive voltage, which can strongly constrain the negative charges concentrated at the edge of the first region, while the second dummy pad 232 may have the same voltage as the surrounding driving pads 220, which can minimize the parasitic capacitance.

[0195] Figure 20 is a schematic diagram showing the operation timing of a pixel circuit in a display device according to an embodiment of the present disclosure.

[0196] Reference Figure 20 , the gate driving signal SCAN2 can be applied as the gate high voltage during the holding period after the refresh period. Therefore, when the dummy pad 230 is connected to the driving pad 220 to which the gate high voltage is applied, a positive voltage can be applied to the dummy pad 230 during the holding period. For example, a positive voltage can be applied to the dummy pad 230 around the driving pad 220 of the driving signal SCAN2 to which the gate high voltage is applied during the holding period. When driving at a low speed of 1Hz, the holding period can be 119 times longer than the refresh period. Therefore, a high voltage can be applied to the dummy pad 230 for a longer period of time.

[0197] In addition, when the light-emitting transistor is a p-channel transistor and is driven by pulse width modulation (PWM), when driving at low brightness, the width of the gate low voltage VGL of the emission signal EM may become smaller, and the width W1 of the gate high voltage VGH may become larger. Therefore, when the dummy pad 230 is connected to the driving pad 220 to which the light emission control signal is applied, a high voltage can be applied to the dummy pad 230 when driving at low brightness.

[0198] However, this is not necessarily limited thereto. In a case where the dummy pad 230 is independently powered by the driver IC 300 or the power management integrated circuit (PMIC), a positive voltage can be applied to the dummy pad 230 synchronously with an input signal derived from the first frame by the driver IC 300 or the power management integrated circuit (PMIC). Alternatively, even when the display device is turned off, a positive voltage can be applied to the dummy pad 230 by periodically operating the driver IC 300 or the PMIC in a wake-up mode.

[0199] Figure 21 is a block diagram of a driver IC according to an embodiment of the present disclosure.

[0200] Reference Figure 21 , the driver IC 300 can be coupled to the host system SYS, the first memory 301, and the display panel. The driver IC 300 can include a data reception and calculation section 308, a timing controller 303, a data driver 306, a gamma compensation voltage generator 305, a power supply 304, a second memory 302, etc., but the embodiments of the present disclosure are not limited thereto.

[0201] The data reception and calculation section 308 can include a reception section and a data calculation section. The reception section can receive pixel data input as a digital signal from the host system SYS. The data calculation section can process the pixel data input through the reception section to improve the image quality.

[0202] The data calculation section can include a data recovery section and an optical compensation section. The data recovery section can decode and recover the pixel data in a compressed state. The optical compensation section can add a preset optical compensation value to the pixel data. The optical compensation value can be set to a value for correcting the brightness of each pixel data based on the screen brightness of the display panel, and the screen brightness is measured based on a camera image taken during the manufacturing process.

[0203] The timing controller 303 can provide the pixel data of the input image received from the host system SYS to the data driver 306. The timing controller 303 can generate a gate timing signal for controlling the gate driver and a source timing signal for controlling the data driver 306 to control the operation timing of the gate driver and the data driver 306.

[0204] The data driver 306 can convert the digital data including pixel data received from the timing controller 303 into a gamma compensation voltage using a digital-to-analog converter (DAC) and output a data voltage. The data voltages DATA1 to DATA6 output from the data driver 306 can be supplied to the data lines of the pixel array through an output buffer connected to the data channels in the driver IC 300.

[0205] The gamma compensation voltage generator 305 can generate gamma compensation voltages for each gray level by dividing the gamma reference voltage from the power supply 304 with a voltage divider circuit. The gamma compensation voltage can be an analog voltage set for each gray level of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 can be provided to the data driver 306.

[0206] The power supply 304 can use a DC-to-DC converter to generate the power required to drive the pixel array, the gate driver, and the driver IC 300 of the display panel. The DC-to-DC converter can include, but is not limited to, a charge pump, a voltage regulator, a buck converter, a boost converter, etc.

[0207] The power supply 304 can generate DC power by adjusting the DC input voltage from the host system SYS, such as a gamma reference voltage, a gate-off voltage VGL, a gate-on voltage VGH, a pixel drive voltage VDD, a low-potential power supply voltage VSS, and an initialization voltage Vini. The power supply 304 can also generate a positive voltage to be applied to the dummy pad.

[0208] The positive voltage applied to the dummy pad can be equal to or greater than the maximum value of the voltage applied to the driving pad. The power supply 304 can be provided within the driver IC 300 or can be provided independently. The power supply 304 can include a power management integrated circuit (PMIC).

[0209] The gamma reference voltage can be supplied to the data driver 305. The gate-off voltage VGL and the gate-on voltage VGH can be supplied to the level shifter 307. The level shifter 307 can output clock signals GCLK and ECLK and start signals GVST and EVST. Pixel power, such as the pixel drive voltage VDD, the low-potential power supply voltage VSS, and the initialization voltage Vini can be commonly supplied to the pixel P.

[0210] Figure 22 is a schematic diagram showing a plurality of dummy pads electrically connected by a gate line in a display device according to an embodiment of the present disclosure. Figure 23 is a schematic diagram showing a dummy pad electrically connected by a sensor electrode line in a display device according to an embodiment of the present disclosure. Figure 24 is a schematic diagram showing adjacent dummy pads electrically connected by a data line in a display device according to an embodiment of the present disclosure. Figure 25 is a schematic diagram showing fixing negative charges by connecting gate electrodes in a display device according to an embodiment of the present disclosure.

[0211] Reference Figure 22, among the third dummy pad 230A and the fourth dummy pad 230B adjacent to each other, the buffer layer BUF and the gate electrode GE can be disposed on the substrate PI, and the first line electrode SD1 and the second line electrode SD2 can be disposed on the interlayer insulating layer ILD. In addition, a third buffer layer BUF can be disposed on the second line electrode SD2, and the sensor electrode TE1 can be disposed on the third buffer layer BUF.

[0212] The gate electrode GE of the third dummy pad 230A and the gate electrode GE of the fourth dummy pad 230B can be electrically connected. Therefore, the first line electrode SD1 of the third dummy pad 230A is connected to the gate electrode GE, and the first line electrode SD1 of the fourth dummy pad 230B is connected to the second gate electrode GE, so that the third dummy pad 230A and the fourth dummy pad 230B can be electrically connected.

[0213] Reference Figure 23 , the sensor electrode TE1 of the third dummy pad 230A and the sensor electrode TE1 of the fourth dummy pad 230B can be connected. For example, the sensor electrode TE1 of the third dummy pad 230A and the sensor electrode TE1 of the fourth dummy pad 230B can be directly connected. Therefore, the area of the dummy pad 230 can be larger than the area of the driving pad 220.

[0214] Reference Figure 24 , the first line electrode SD1 can be used to form a jumper. Therefore, in the case where there is a gate electrode GE connected to the signal line between the dummy pads, the jumper can jump over the gate electrode and connect to other adjacent gate electrodes GE.

[0215] Reference Figure 25 , the gate electrode GE or the light-shielding layer ( Figure 9 BSM) can be disposed above the substrate PI, and the first line electrodes SD1 of the plurality of dummy pads 230A, 230B, and 230C on the light-shielding layer can be connected to the gate electrode GE. In this way, all the plurality of dummy pads 230 can be formed to have the same electric potential, and a positive voltage is applied to the gate electrode GE, and the effect of this is to restrict the movement of negative charges within a wide range.

[0216] Figure 26 is a schematic diagram showing a display device according to another embodiment of the present disclosure.

[0217] Reference Figure 26 , a display device according to another embodiment of the present disclosure may include a display panel 100, a plurality of signal lines 210, a plurality of driving pads 220, and dummy pads 230.

[0218] The display panel 100 may include a display area DA and a non-display area NA. The non-display area NA may be located around the display area DA.

[0219] A plurality of signal lines 210 may be configured to extend from a display area DA to a non-display area NA. A plurality of driving pads 220 may be disposed at ends (or one side) of the plurality of signal lines 210. The plurality of driving pads 220 may be connected to a driver IC.

[0220] Dummy pads 230 may be provided adjacent to the plurality of driving pads 220. The dummy pads 230 may further include dummy signal lines 233 extending toward the display area DA. Negative charges may be concentrated in an outermost area of the non-display area NA between the first area SA and the display area DA. Accordingly, the negative charges may be coupled to the signal lines 210 to which a positive voltage is applied, resulting in electrolytic corrosion. The non-display area NA between the first area SA and the display area DA may be a bending area BA. The bending area BA may be between the first area SA and the display area DA. Due to stress during bending, the bending area BA may be subject to accelerated electrolytic corrosion of the signal lines 210.

[0221] According to an embodiment of the present disclosure, a high voltage may be applied to the dummy signal lines 233 extending from the dummy pads 230 to prohibit movement of negative charges concentrated outside the driver IC. Accordingly, the problem of electrolytic corrosion occurring due to coupling of negative charges to the signal lines 210 to which a positive voltage is applied can be solved.

[0222] The dummy pads 230 may include a first dummy pad 231 and a second dummy pad 232. The first dummy pad 231 may be disposed outside the signal lines 210. The second dummy pad 232 may be disposed between the plurality of signal lines 210. The same voltage or different voltages may be applied to the first dummy pad 231 and the second dummy pad 232, or different voltages may be applied. Accordingly, the same voltage or different voltages may be applied to the dummy signal lines 233 connected to the first dummy pad 231 and the dummy signal lines 233 connected to the second dummy pad 232.

[0223] A display panel and a display device including the display panel according to an embodiment of the present disclosure may be described as follows.

[0224] A display panel according to an embodiment of the present disclosure may include: a substrate having a display area and a non-display area surrounding the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads disposed in a first area in the non-display area where a driver IC is attached and connected to the plurality of signal lines; and dummy pads disposed in the first area. A positive voltage may be applied to the dummy pads.

[0225] According to one or more embodiments of the present disclosure, the plurality of driving pads may be disposed in a central portion of the first region, and the dummy pads may be disposed at two edges of the first region.

[0226] According to one or more embodiments of the present disclosure, the dummy pads may include a first dummy pad disposed at an edge of the first region and a second dummy pad disposed between the plurality of driving pads.

[0227] According to one or more embodiments of the present disclosure, the number of the first dummy pads may be greater than the number of the second dummy pads.

[0228] According to one or more embodiments of the present disclosure, the positive voltage applied to the dummy pads may be a voltage equal to the highest value of the positive voltage applied to the plurality of driving pads.

[0229] According to one or more embodiments of the present disclosure, the positive voltage applied to the dummy pads may be a voltage higher than the highest value of the positive voltage applied to the plurality of driving pads.

[0230] According to one or more embodiments of the present disclosure, the dummy pads may further include a plurality of sub-dummy pads spaced apart from each other in a direction from the display region toward the first region.

[0231] According to one or more embodiments of the present disclosure, the plurality of sub-dummy pads may be electrically connected to each other.

[0232] According to one or more embodiments of the present disclosure, the plurality of sub-dummy pads may be electrically isolated from each other.

[0233] According to one or more embodiments of the present disclosure, each of the plurality of driving pads may further include a plurality of sub-driving pads spaced apart from each other in a direction from the display region toward the first region. The plurality of sub-driving pads may be electrically connected by the signal lines.

[0234] According to one or more embodiments of the present disclosure, the plurality of driving pads and the dummy pads may have the same structure.

[0235] According to one or more embodiments of the present disclosure, the plurality of driving pads and the dummy pads may each include a gate electrode disposed on a substrate, a first line electrode disposed on the gate electrode, a second line electrode disposed on the first line electrode, and a sensing electrode disposed on the second line electrode.

[0236] According to one or more embodiments of the present disclosure, the dummy pads may be configured to be multiple. At least some of the multiple dummy pads may be connected to any one of the gate electrode, the first line electrode, the second line electrode, and the sensing electrode.

[0237] According to one or more embodiments of the present disclosure, the gate electrode of the first dummy pad and the gate electrode of the second dummy pad may be electrically connected.

[0238] According to one or more embodiments of the present disclosure, the levels of the voltages applied to the first dummy pad and the second dummy pad may be different.

[0239] According to one or more embodiments of the present disclosure, the level of the voltage applied to the first dummy pad may be higher than the level of the voltage applied to the second dummy pad.

[0240] A display device according to one or more embodiments of the present disclosure may include: a substrate having a display area and a non-display area surrounding the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads disposed in a first area of the non-display area and connected to the plurality of signal lines; a plurality of dummy pads disposed in the first area; and a driver IC disposed in the first area. The plurality of dummy pads may include a plurality of dummy signal lines extending toward the display area.

[0241] According to one or more embodiments of the present disclosure, the driver IC may include a plurality of bumps electrically connected to the plurality of driving pads and the plurality of dummy pads.

[0242] According to one or more embodiments of the present disclosure, the driver IC may be implemented to apply a positive voltage to the plurality of dummy pads through the plurality of bumps.

[0243] According to one or more embodiments of the present disclosure, the positive voltage may be applied to the plurality of dummy pads even during a shutdown period of the display device.

[0244] The display device according to the embodiment of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, electronic books, portable multimedia players (PMP), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, notebook computers, workstations, navigation devices, in-vehicle navigation devices, in-vehicle display devices, in-vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, video recorders, and home appliances.

[0245] The disclosure described above is not limited to the aforementioned embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications and variations can be made within the scope of the disclosure without departing from its technical essence. Therefore, the scope of the disclosure is represented by the appended claims, and it should be understood that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the disclosure.

[0246] [Description of Reference Signs]

[0247] 100: display panel 210: signal line

[0248] 211: Data line 212: Gate line

[0249] 220: driving pad 230: dummy pad

[0250] 300: Driver IC

Claims

1. A display panel, comprising: A substrate, the substrate having a display area and a non-display area located around the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads disposed in a first region where a driver IC is disposed in the non-display region and connected to the plurality of signal lines; and a dummy pad disposed in the first region, Wherein, a positive voltage is applied to the dummy pad.

2. The display panel according to claim 1, wherein: The plurality of driving pads are disposed in a central portion of the first region, and Wherein, the dummy pads are arranged at two edges of the first area.

3. The display panel according to claim 1, wherein: The dummy pad comprises: a first dummy pad disposed at the edge of the first region; and A second dummy pad is disposed between the plurality of driving pads.

4. The display panel according to claim 3, wherein: The number of the first dummy pads is greater than the number of the second dummy pads.

5. The display panel according to claim 1, wherein: The positive voltage applied to the dummy pad is a voltage equal to a highest value of the positive voltages applied to the plurality of driving pads.

6. The display panel according to claim 1, wherein: The positive voltage applied to the dummy pad is a voltage higher than a highest value of the positive voltages applied to the plurality of driving pads.

7. The display panel according to claim 1, wherein: The dummy pad further includes a plurality of sub-dummy pads spaced apart from each other in a direction from the display area toward the first area.

8. The display panel according to claim 7, wherein: The plurality of sub-dummy pads are electrically connected to each other.

9. The display panel according to claim 7, wherein: The plurality of sub-dummy pads are electrically isolated from each other.

10. The display panel according to claim 1, wherein: Each of the plurality of driving pads further includes a plurality of sub-driving pads spaced apart from each other in a direction from the display area toward the first area, and Wherein, the plurality of sub-driving pads are electrically connected by the signal line.

11. The display panel according to claim 1, wherein: The plurality of driving pads and the dummy pads have the same structure.

12. The display panel according to claim 11, wherein: The plurality of driving pads and the dummy pads each include: A gate electrode disposed on the substrate; a first line electrode disposed on the gate electrode; a second line electrode disposed on the first line electrode; and A sensing electrode is disposed on the second line electrode.

13. The display panel according to claim 12, wherein: The dummy pads are arranged in plural numbers, and, At least some of the plurality of dummy pads are connected to any one of the gate electrode, the first wire electrode, the second wire electrode, and the sensing electrode.

14. The display panel according to claim 3, wherein: The gate electrode of the first dummy pad and the gate electrode of the second dummy pad are electrically connected.

15. The display panel according to claim 3, wherein: Levels of the voltage applied to the first dummy pad and the second dummy pad are different.

16. The display panel according to claim 3, wherein: The level of the voltage applied to the first dummy pad is higher than the level of the voltage applied to the second dummy pad.

17. A display device comprising: A substrate, the substrate having a display area and a non-display area located around the display area; a plurality of signal lines extending from the display area to the non-display area; a plurality of driving pads, the plurality of driving pads being disposed in a first area of ​​the non-display area and connected to the plurality of signal lines; A plurality of dummy pads disposed in the first region; and a driver IC disposed in the first area, The plurality of dummy pads include a plurality of dummy signal lines extending toward the display area.

18. The display device according to claim 17, wherein: The driver IC includes a plurality of bumps electrically connected to the plurality of driving pads and the plurality of dummy pads.

19. The display device according to claim 18, wherein: The driver IC is configured to apply a positive voltage to the plurality of dummy pads through the plurality of bumps.

20. The display device according to claim 17, wherein: Even during power-off of the display device, the positive voltage is applied to the plurality of dummy pads.

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