Transparent display device

Abstract

A transparent display device includes: a display area including a plurality of pixel blocks disposed therein and displaying an image; a bezel region disposed at at least one side of the display region; and a plurality of mesh blocks disposed in the bezel region, each of the plurality of mesh blocks including mesh power lines having a mesh shape. Each of the plurality of pixel blocks includes a first transmissive region that transmits external light, and each of the plurality of mesh blocks includes a second transmissive region that transmits external light.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195616, filed on December 28, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a transparent display device. Background art

[0004] With the development of an information - oriented society, the demand for display devices for displaying images has increased in various forms. Various types of display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, quantum dot light - emitting displays (QLEDs), and organic light - emitting display (OLED) devices, have been widely used.

[0005] In recent years, active research has been conducted on display devices that allow users to view objects or images located on the rear surface of the display device. A transparent display device may include a display area for displaying an image, and the display area may include a transmissive area that can transmit external light. In a transparent display device, a high light transmittance can be achieved in the display area through the transmissive area. Summary of the invention

[0006] The present disclosure aims to provide a transparent display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0007] One aspect of the present disclosure relates to providing a transparent display device capable of improving light transmittance.

[0008] Another aspect of the present disclosure relates to providing a transparent display device capable of stably supplying power.

[0009] The additional advantages and features of the present disclosure will be partially described in the following description, and will be partially apparent to those of ordinary skill in the art after reviewing the following, or may be learned from the practice of the present disclosure. The objectives and other advantages of the present disclosure can be achieved and obtained by the structures particularly pointed out in the written description and claims of the present disclosure and the drawings.

[0010] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a transparent display device is provided that has: a display area including a plurality of pixel blocks disposed therein and configured to display an image; a border area disposed on one or more sides of the display area; and a plurality of grid blocks disposed in the border area, wherein each of the plurality of grid blocks includes grid power lines having a grid shape. Each of the plurality of pixel blocks includes a first transmissive area configured to transmit external light, and each of the plurality of grid blocks includes a second transmissive area configured to transmit external light. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0012] Figure 1 is a plan view schematically showing a transparent display device according to one or more embodiments of the present disclosure.

[0013] Figure 2 is Figure 1 an enlarged view of region A of

[0014] Figure 3 is a view showing Figure 2 an example of the pixel block shown in

[0015] Figure 4 is a view showing Figure 3 a circuit diagram of an example of the sub-pixels included in the pixel block shown in

[0016] Figure 5 is a cross-sectional view showing an example of the elements disposed in the Figure 3 transmissive area and non-transmissive area of

[0017] Figure 6 is a view showing Figure 2 an example of the grid block shown in

[0018] Figure 7 is a cross-sectional view showing an example taken along line I-I' of Figure 6

[0019] Figure 8 is a cross-sectional view showing an example taken along line II-II' of Figure 6

[0020] Figure 9 is a cross-sectional view showing an example taken along line III-III' of Figure 6 ​​​

[0021] Figure 10 is a cross-sectional view showing an example taken along line IV-IV' Figure 6 .

[0022] Figure 11 is a diagram showing an example in which a grid block according to an embodiment of the present disclosure is provided in a transparent display panel

[0023] Figure 12 is a diagram showing an example of a first column line and a second column line provided in area B Figure 11 .

[0024] Figure 13 is a diagram showing the relationship between the number of pixel blocks included in the first column line and the number of grid blocks included in the second column line

[0025] Figure 14 is a diagram showing an example in which a transparent display device according to an embodiment of the present disclosure is applied to a vehicle DETAILED DESCRIPTION

[0026] Advantages and features of the present disclosure and methods for realizing them will be clarified by the embodiments described below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by the scope of the claims

[0027] The shapes, dimensions, ratios, angles, and numbers disclosed in the accompanying drawings for describing the embodiments of the present disclosure are only examples, and thus the present disclosure is not limited to the details shown. Like reference numerals always refer to like elements. In the following description, when a detailed description of related known technologies is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. In cases where "comprising", "having", and "including" described in the present disclosure are used, other parts may be added unless "only" is used. Singular terms may include plural forms unless stated otherwise. Further, the term "able to" fully encompasses all meanings and scopes of the term "may"

[0028] When interpreting an element, although not explicitly described, the element is interpreted as including an error range

[0029] When describing positional relationships, for example, when the positional relationship between two parts is described as "on...", "above...", "below...", and "next to...", one or more other parts may be disposed between these two parts, unless "exactly" or "directly" is used.

[0030] When describing temporal relationships, for example, when describing temporal precedence relationships such as "after", "then", "next", "before", etc., it may include discontinuous cases, unless "immediately" or "directly" is used.

[0031] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from other elements and may not necessarily define an order or sequence. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0032] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more items selected from the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0033] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other, and various interoperations and drivings may be performed technically. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0034] Hereinafter, with reference to the drawings, an example of a display device according to the present disclosure will be described. When assigning reference numerals to components in each drawing, the same components may preferably have the same numerals, even if they are shown in different drawings. Additionally, when the detailed description of related known technologies is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. All components of each display device / equipment according to all embodiments of the present disclosure are operably coupled and configured.

[0036] Figure 1 is a plan view schematically showing a transparent display device 100 according to an embodiment of the present disclosure, and Figure 2 is Figure 1 an enlarged view of region A of

[0037] In this document, the X-axis may represent a direction parallel to the scanning line, the Y-axis may represent a direction parallel to the data line, and the Z-axis may represent the height of the transparent display device 100.

[0038] The transparent display device 100 according to an embodiment of the present disclosure may be mainly described as being implemented as an organic light emitting display, but is not limited thereto, and may be implemented as a liquid crystal display (LCD), a plasma display panel (PDP), a quantum dot light emitting display (QLED), or an electrophoretic display.

[0039] Referring to Figure 1 and Figure 2 , the transparent display device 100 according to an embodiment of the present disclosure may include a transparent display panel 110. The transparent display panel 110 may be divided into a display area DA where pixels are provided to display an image and a border area BA where no image is displayed.

[0040] A plurality of pixel blocks PB may be provided in the display area DA.

[0041] Figure 3 is a diagram showing Figure 2 an example of the pixel block shown. Figure 4 is a circuit diagram showing Figure 3 an example of sub-pixels included in the pixel block shown. Figure 5 is a cross-sectional view showing Figure 3 an example of elements provided in the transmissive area and non-transmissive area of

[0042] Referring to Figures 3 to 5 , as Figure 3 shown, each of the plurality of pixel blocks PB may include a first area NTA1 where a plurality of sub-pixels SP1 to SP3 are provided and a second area TA1 where the plurality of sub-pixels SP1 to SP3 are not provided. The first area NTA1 may be a first non-transmissive area that does not transmit most of the light incident from the outside, and the second area TA1 may be a first transmissive area that transmits most of the light incident from the outside.

[0043] For example, the first transmissive area TA1 may be an area where the light transmittance is greater than α%, and the first non-transmissive area NTA1 may be an area where the light transmittance is less than β%. Here, α may be a value greater than β. The transparent display panel 110 may enable an object or background provided at the rear surface of the transparent display panel 110 to be seen based on the plurality of first transmissive areas TA1.

[0044] The plurality of sub-pixels SP1 to SP3, the plurality of circuit devices, and the plurality of signal lines SL1 and SL2 may be provided in the first non-transmissive area NTA1 and may not transmit the light incident from the outside.

[0045] A plurality of signal lines may include a first signal line SL1 and a second signal line SL2. The first signal line SL1 may extend in a first direction (e.g., the Y-axis direction) in a first non-transmissive region NTA1. The first signal line SL1 may have a straight shape. The first signal line SL1 may include a pixel power line VDDL, a data line, and a common power line VSSL. In one embodiment, the first signal line SL1 may further include a reference line.

[0046] The pixel power line VDDL may transmit a first power to a driving transistor of each of the plurality of sub-pixels SP1 to SP3. The common power line VSSL may transmit a second power to a cathode electrode of each of the plurality of sub-pixels SP1 to SP3. In this case, the second power may be a common power commonly supplied to the plurality of sub-pixels SP1 to SP3. Further, the common power line VSSL may be spaced apart from the pixel power line VDDL by a transmissive region TA therebetween. One pixel power line VDDL or one common power line VSSL may be provided between transmissive regions TA adjacent to each other in a second direction (e.g., the X-axis direction).

[0047] The reference line may transmit an initialization voltage (or a reference voltage) to a driving transistor of each of the plurality of sub-pixels SP1 to SP3. The data lines may respectively transmit data voltages to the plurality of sub-pixels SP1 to SP3.

[0048] The second signal line SL2 may extend in a second direction (e.g., the X-axis direction) in the first non-transmissive region NTA1. The second signal line SL2 may include a scan line SCANL. The scan line SCANL may be provided as one or more between transmissive regions TA adjacent to each other in the first direction (e.g., the Y-axis direction). The scan line SCANL may include a first scan line and a second scan line. The second signal line SL2 may further include an emission control line. The scan line SCANL may transmit a scan signal to the sub-pixels SP1 to SP3.

[0049] Each of the sub-pixels SP1 to SP3 may be included in the first non-transmissive region NTA1 and may emit light to display an image. An emission region EA may correspond to a light-emitting region of each of the sub-pixels SP1 to SP3.

[0050] The sub-pixels SP1 to SP3 can each be one of a first sub-pixel SP1 that emits light of a first color, a second sub-pixel SP2 that emits light of a second color, and a third sub-pixel SP3 that emits light of a third color, but is not limited thereto. The unit pixel P can include two or more sub-pixels SP1 to SP3. For example, the unit pixel P can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. As another example, one unit pixel P can include a first sub-pixel SP1 and a second sub-pixel SP2, and another unit pixel P can include a second sub-pixel SP2 and a third sub-pixel SP3. Each pixel P can also include a fourth sub-pixel SP4 that emits white light.

[0051] The first sub-pixel SP1 can include a first emission region EA1 that emits light of a first color, the second sub-pixel SP2 can include a second emission region EA2 that emits light of a second color, and the third sub-pixel SP3 can include a third emission region EA3 that emits light of a third color. However, the embodiments of the present disclosure are not limited thereto. Each pixel P can also include a fourth sub-pixel SP4 that emits white light.

[0052] For example, the first emission region EA1 to the third emission region EA3 can emit light of different colors. For example, the first emission region EA1 can emit blue light, the second emission region EA2 can emit red light, and the third emission region EA3 can emit green light. The arrangement order of the sub-pixels SP1 to SP3 can be changed differently.

[0053] The sub-pixels SP1 to SP3 can be set to overlap at least one of the first signal line SL1 and the second signal line SL2. The first sub-pixel SP1 to the third sub-pixel SP3 can be disposed in a region where the first signal line SL1 and the second signal line SL2 overlap.

[0054] Specifically, each of the first sub-pixel SP1 and the third sub-pixel SP3 can be disposed in a region where one of the pixel power line VDDL and the common power line VSSL overlaps with the second signal line SL2. For example, the first sub-pixel SP1 can be disposed in a region where the pixel power line VDDL overlaps with the second signal line SL2, and the third sub-pixel SP3 can be disposed in a region where the common power line VSSL overlaps with the second signal line SL2.

[0055] The first sub-pixel SP1 and the third sub-pixel SP3 may be alternately arranged along the pixel power line VDDL and may be alternately arranged along the common power line VSSL. In this case, in the first horizontal line, the third sub-pixel SP3 may be disposed in a region where the common power line VSSL overlaps with the second signal line SL2, and the first sub-pixel SP1 may be disposed in a region where the pixel power line VDDL overlaps with the second signal line SL2. Further, in the second horizontal line disposed adjacent thereto, the third sub-pixel SP3 may be disposed in a region where the pixel power line VDDL overlaps with the second signal line SL2, and the first sub-pixel SP1 may be disposed in a region where the common power line VSSL overlaps with the second signal line SL2.

[0056] The second sub-pixel SP2 may be disposed between the first sub-pixel SP1 and the third sub-pixel SP3. The second sub-pixel SP2 may be disposed in a region where the second signal line SL2 is provided, between the adjacent first signal lines SL1. The second sub-pixel SP2 may be disposed in a region where the second signal line SL2 is provided, between the pixel power line VDDL and the common power line VSSL which are arranged adjacent to each other.

[0057] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a circuit device and a light-emitting device. Referring to Figure 4 , each of the sub-pixels SP1 to SP3 may include a pixel circuit including a plurality of transistors DT and T1 to T5 and a light-emitting device ED.

[0058] Figure 4 The pixel circuit shown may include five switching transistors T1 to T5, a driving transistor DT, a storage capacitor Cst, and a light-emitting device ED, but is not limited thereto.

[0059] Each of the transistors DT and T1 to T5 in each of the sub-pixels SP1 to SP3 may include a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode cannot be fixed and may be changed based on the voltage applied to the gate electrode and the direction of the current. Therefore, one of the source electrode and the drain electrode may be referred to as the first electrode, and the other may be referred to as the second electrode. Each of the transistors DT and T1 to T5 in each of the sub-pixels SP1 to SP3 may use at least one of polycrystalline silicon semiconductors, amorphous silicon semiconductors, and oxide semiconductors. The transistors may be P-type or N-type, or may be a combination of P-type and N-type.

[0060] The first electrode of the driving transistor DT may be connected to the pixel power line VDDL that transmits the first source voltage EVDD. The second electrode of the driving transistor DT may drive the light-emitting device ED through the fourth switching transistor T4. The driving transistor DT may control the driving current based on the driving voltage of the storage capacitor Cst. Therefore, the driving transistor DT may control the light-emitting intensity of the light-emitting device ED.

[0061] The storage capacitor Cst may be charged with a driving voltage corresponding to the data voltage Vdata. The storage capacitor Cst may supply the charged driving voltage to the driving transistor DT.

[0062] The first switching transistor T1 may be turned on or off in response to the first scan signal Scan1 supplied to the first scan line SCANL1. The first switching transistor T1 may supply the data voltage Vdata supplied through the data line DL to the first electrode of the storage capacitor Cst in response to the gate conduction voltage of the first scan signal Scan1.

[0063] The second switching transistor T2 and the fifth switching transistor T5 may be turned on or off in response to the second scan signal Scan2 supplied to the second scan line SCANL2. The second switching transistor T2 may connect the gate electrode and the second electrode of the driving transistor DT to each other in response to the gate conduction voltage of the second scan signal Scan2 to connect the driving transistor DT in a diode structure. The second switching transistor T2 may charge the threshold voltage Vth of the driving transistor DT into the storage capacitor Cst to compensate for the driving transistor DT. Therefore, the storage capacitor Cst may be charged with the data voltage "Vdata + Vth" obtained by compensating the threshold voltage Vth of the driving transistor DT.

[0064] The fifth switching transistor T5 may supply the initialization voltage Vref (or reference voltage) supplied through the initialization voltage line VREFL to the anode electrode of the light-emitting device ED in response to the gate conduction voltage of the second scan signal Scan2.

[0065] The third switching transistor T3 and the fourth switching transistor T4 may be turned on or off in response to the emission control signal EM supplied to the emission control line EML. The third switching transistor T3 may supply the initialization voltage Vref (or reference voltage) supplied through the initialization voltage line VREFL to the first electrode of the storage capacitor Cst in response to the gate conduction voltage of the emission control signal EM.

[0066] The fourth switching transistor T4 can connect the driving transistor DT to the light-emitting device ED in response to the gate conduction voltage of the emission control signal EM. The light-emitting device ED can include an anode electrode, a cathode electrode supplied with a second source voltage EVSS through a common power line VSSL, and a light-emitting layer between the anode electrode and the cathode electrode. When a driving current is supplied from the driving transistor DT through the fourth switching transistor T4, electrons from the cathode electrode can be injected into the light-emitting layer, holes from the anode electrode can be injected into the organic light-emitting layer, and a fluorescent or phosphorescent material can emit light based on the recombination of electrons and holes in the light-emitting layer. Thus, the light-emitting device ED can emit light having a brightness proportional to the current value of the driving current.

[0067] Hereinafter, elements provided in the first non-transmissive region NTA1 and the first transmissive region TA1 will be described in more detail with reference to Figure 5 FIGs.

[0068] Referring to Figure 5 , a transparent display panel 110 according to an embodiment of the present disclosure may include a first substrate 111 and a second substrate 112 facing each other, and circuit devices, a light-emitting device ED, a packaging layer 180, a color filter CF, and a black matrix BM may be provided between the first substrate 111 and the second substrate 112.

[0069] The circuit devices may include various signal lines, thin film transistors (TFTs), and capacitors. The signal lines may include pixel power lines, common power lines, scan lines, and data lines, and the TFTs may include switching transistors and a driving transistor DT. The switching transistor may be turned on based on a scan signal supplied to the scan line and may charge a data voltage supplied through the data line into the capacitor.

[0070] The driving transistor DT may be turned on based on the data voltage charged in the storage capacitor Cst (see Figure 4 ) and may generate a data current according to the power supplied through the pixel power line VDDL (see Figure 4 ) to supply the data current to the first electrode E1 of each of the sub-pixels SP1 to SP3. The driving transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0071] Specifically, a light-blocking layer LS may be provided on the first substrate 111. The light-blocking layer LS may be provided to overlap with the region where the driving transistor DT is formed and may block external light incident on the active layer ACT of the driving transistor DT. In addition, the light-blocking layer LS may be provided to overlap with the regions where other transistors (e.g., switching transistors T1 to T5 (see Figure 4)) overlap in area and can block external light incident on the active layers of each of the switching transistors T1 to T5 (see Figure 4 ).

[0072] The transparent display panel 110 may be used extensively in an external environment rather than inside. The time that the transparent display panel 110 is exposed to external light may increase, and thus the characteristics of circuit devices such as transistors DT and T1 to T5 may be changed. Due to the change in the characteristics of the circuit devices, the brightness of the transparent display panel 110 may be reduced, and the screen may become dark.

[0073] In the transparent display panel 110 according to an embodiment of the present disclosure, the light blocking layer LS may be disposed under the transistors DT and T1 to T5, and thus external light incident on the transistors DT and T1 to T5 may be prevented. The transparent display panel 110 according to an embodiment of the present disclosure may prevent the characteristics of the transistors DT and T1 to T5 from being changed, and the sub-pixels may maintain high brightness.

[0074] The light blocking layer LS may be formed of a single layer or multiple layers including one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0075] The buffer layer 120 may be disposed on the light blocking layer LS. The buffer layer 120 may protect the transistor DT from water permeating into the first substrate 111 vulnerable to water transmission. For this purpose, the buffer layer 120 may be included in the non-transmissive region NTA and the transmissive region TA. The buffer layer 120 may be formed of an inorganic layer, and for example, may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer thereof.

[0076] The active layer ACT of the driving transistor DT may be disposed on the buffer layer 120. The active layer ACT of the driving transistor DT may include a silicon-based semiconductor material or an oxide-based semiconductor material.

[0077] The gate insulating layer 130 may be disposed on the active layer ACT of the driving transistor DT. The gate insulating layer 130 may be included in the non-transmissive region NTA and the transmissive region TA. The gate insulating layer 130 may be formed of an inorganic layer, and for example, may be formed of SiOx, SiNx, or a multi-layer thereof.

[0078] The gate electrode GE of the driving transistor DT may be disposed on the gate insulating layer 130. The gate electrode GE of the driving transistor DT may be formed of a single layer or multiple layers including one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu.

[0079] The first interlayer insulating layer 140 and the second interlayer insulating layer 145 may be disposed on the gate electrode GE of the driving transistor DT. In order to improve the light transmittance of the first transmissive region TA1, the first interlayer insulating layer 140 and the second interlayer insulating layer 145 may be included only in the first non-transmissive region NTA1 and not included in the first transmissive region TA1. Each of the first interlayer insulating layer 140 and the second interlayer insulating layer 145 may be formed of an inorganic layer and may be formed of, for example, SiOx, SiNx, or a multilayer thereof.

[0080] The source electrode SE and the drain electrode DE of the driving transistor DT may be disposed on the second interlayer insulating layer 145. Each of the source electrode SE and the drain electrode DE of the driving transistor DT may be connected to the active layer ACT of the driving transistor DT through a first contact hole CH1 passing through the first interlayer insulating layer 140 and the second interlayer insulating layer 145. The source electrode SE and the drain electrode DE of the driving transistor DT may be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0081] The first planarization layer 150 may be disposed on the source electrode SE and the drain electrode DE of the driving transistor DT to planarize the step height caused by the driving transistor DT. The first planarization layer 150 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0082] The auxiliary electrode AE may be disposed on the first planarization layer 150. The auxiliary electrode AE may be connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through a second contact hole CH2 passing through the first planarization layer 150. The auxiliary electrode AE may be formed of a single layer or a multilayer including one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0083] The second planarization layer 155 may be disposed on the auxiliary electrode AE. The second planarization layer (PLN2) 155 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0084] At least one of the first planarization layer 150 and the second planarization layer 155 may be disposed in the first non-transmissive region NTA1 and not disposed in at least a part of the first transmissive region TA1.

[0085] In the transparent display panel 110 according to an embodiment of the present disclosure, at least one of the first planarization layer 150 and the second planarization layer 155 is not disposed in the first transmissive region TA1, and thus the light transmittance of the first transmissive region TA1 can be improved.

[0086] A light-emitting device ED including a first electrode E1, a light-emitting layer EL, and a second electrode E2, and a bank 160 may be disposed on the second planarization layer 155.

[0087] The first electrode E1 may be disposed on the second planarization layer 155 and may be electrically connected to the driving transistor DT. Specifically, the first electrode E1 may be connected to the auxiliary electrode AE through a third contact hole CH3 penetrating the second planarization layer 155. In addition, the auxiliary electrode AE may be connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through a second contact hole CH2, and the first electrode E1 may be connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through the auxiliary electrode AE.

[0088] The first electrode E1 may be included in each of the sub-pixels SP1 to SP3 and may not be included in the transmissive region TA. The bank 160 may be disposed between adjacent first electrodes E1, and thus adjacent first electrodes E1 may be electrically insulated from each other.

[0089] The first electrode E1 may include a metal material having a high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag alloy, a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a stacked structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy may be an alloy of Ag, palladium (Pd), and Cu. The MoTi alloy may be an alloy of Mo and Ti. The first electrode E1 may be an anode electrode.

[0090] The bank 160 may be disposed on the second planarization layer 155. In addition, the bank 160 may be formed to cover the edge of the first electrode E1 and expose a part of the first electrode E1. Therefore, the bank 160 may solve the problem of reduced emission efficiency due to current concentration at the end of the first electrode E1.

[0091] The bank 160 may define the emission areas (EA) EA1 to EA3 of the sub-pixels SP1 to SP3. Each of the emission areas (EA) EA1 to EA3 of the sub-pixels SP1 to SP3 may represent an area where the first electrode E1, the light-emitting layer EL, and the second electrode E2 are sequentially stacked. Thus, holes from the first electrode E1 and electrons from the second electrode E2 may combine with each other in the light-emitting layer EL to emit light. In this case, the area where the bank 160 is formed cannot emit light and may thus be a non-emission area NEA, and the area where the bank 160 is not formed and the first electrode E1 is exposed may be the emission areas (EA) EA1 to EA3. The bank 160 may be disposed in the first non-transmissive area NTA1 and may not be disposed in at least a part of the first transmissive area TA1.

[0092] The bank 160 may be formed of an organic layer such as an acrylic-based material, an epoxy-based material, a phenolic-based material, a polyamide-based material, or a polyimide-based material.

[0093] The light-emitting layer EL may be disposed on the first electrode E1. The light-emitting layer EL may include a light-emitting material layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. The light-emitting layer EL may have a multi-layer structure. For example, the light-emitting layer EL may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In this case, when a voltage is applied to the first electrode E1 and the second electrode E2, holes and electrons may move to the light-emitting material layer through the hole transport layer and the electron transport layer, respectively, and may combine with each other in the light-emitting material layer to emit light.

[0094] In an embodiment, the light-emitting layer EL may be a common layer formed in the sub-pixels SP1 to SP3. In this case, the light-emitting layer EL may be a white light-emitting layer that emits white light. Here, in addition to the sub-pixels SP1 to SP3, the light-emitting layer EL may also be formed in the non-emission area NEA between the sub-pixels SP1 to SP3. The light-emitting layer EL may be continuously formed in the sub-pixels SP1 to SP3 and between the sub-pixels SP1 to SP3. In addition, the light-emitting layer EL may be disposed in the first transmissive area TA1 and the first non-transmissive area NTA1 including the emission areas EA1 to EA3 and the non-emission area NEA, but is not limited thereto. The light-emitting layer EL may be patterned and formed only in the first non-transmissive area NTA1 including the emission areas EA1 to EA3 and the non-emission area NEA.

[0095] In another embodiment, as Figure 5As shown, in the light-emitting layer EL, a light-emitting material layer can be formed in each of the sub-pixels SP1 to SP3. For example, a green light-emitting layer that emits green light can be formed in the first sub-pixel SP1, a red light-emitting layer that emits red light can be formed in the second sub-pixel SP2, and a blue light-emitting layer that emits blue light can be formed in the third sub-pixel SP3. In this case, the light-emitting material layer of the light-emitting layer EL cannot be formed in the first transmission region TA1. In addition to the light-emitting material layer, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) can be commonly formed in the sub-pixels SP1 to SP3 and can also be formed in the first transmission region TA1.

[0096] The second electrode E2 can be disposed on the light-emitting layer EL. The second electrode E2 can be a common layer that is commonly formed in the sub-pixels SP1 to SP3. In addition to the emission regions (EA) EA1 to EA3, the second electrode E2 can also be formed in the non-emission region NEA between the sub-pixels SP1 to SP3. In this case, the light-emitting layer EL can be a white light-emitting layer that emits white light. The second electrode E2 can be continuously formed in the sub-pixels SP1 to SP3 and between the sub-pixels SP1 to SP3.

[0097] The second electrode E2 can include a transparent conductive material (TCO) such as ITO or indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), Ag, or an alloy of Mg and Ag. In the case where the second electrode E2 includes a semi-transmissive conductive material, the emission efficiency can be improved by a microcavity. The second electrode E2 can be a cathode electrode.

[0098] The encapsulation layer 180 can be disposed on the light-emitting device ED. The encapsulation layer 180 can be formed on the second electrode E2 to cover the second electrode E2. The encapsulation layer 180 can prevent oxygen or water from penetrating into the light-emitting layer EL and the second electrode E2. For this purpose, the encapsulation layer 180 can include at least one inorganic layer and at least one organic layer. The encapsulation layer 180 can be formed in a structure in which the inorganic layer and the organic layer are alternately stacked, but is not limited thereto.

[0099] The color filter CF can be disposed on the encapsulation layer 180. The color filter CF can be patterned and formed in each of the sub-pixels SP1 to SP3. Specifically, the color filter CF can include a first color filter, a second color filter, and a third color filter. The first color filter can be disposed to correspond to the emission region EA1 of the first sub-pixel SP1, and can be a blue color filter that transmits blue light. The second color filter can be disposed to correspond to the emission region EA2 of the second sub-pixel SP2, and can be a red color filter that transmits red light. The third color filter can be disposed to correspond to the emission region EA3 of the third sub-pixel SP3, and can be a green color filter that transmits green light.

[0100] The black matrix BM can be disposed between the color filters CF, and the color filters CF are patterned and formed in each of the sub-pixels SP1 to SP3. The black matrix BM can be disposed between the sub-pixels SP1 to SP3, and can prevent color mixing from occurring between adjacent sub-pixels SP1 to SP3. In addition, the black matrix BM can prevent light incident from the outside from being reflected by the plurality of signal lines disposed between the sub-pixels SP1 to SP3.

[0101] In addition, the black matrix BM can be disposed between the first transmission region TA1 and the plurality of sub-pixels SP1 to SP3, and can prevent light emitted from each of the plurality of sub-pixels SP1 to SP3 from traveling to the first transmission region TA1. The black matrix BM can include a light-absorbing material, and for example, can include a black dye that absorbs all light in the visible light wavelength band.

[0102] The first substrate 111 including the color filter CF and the black matrix BM can be bonded to the second substrate 112 through a separate adhesive layer 190. In this case, the adhesive layer 190 can be an optically transparent resin layer (OCR) or an optically transparent adhesive film (OCA).

[0103] Referring again to Figure 2 , a plurality of dummy blocks DB, a plurality of grid blocks MB, and at least one scan driver 205 can be disposed in the border area BA. The scan driver 205 can be disposed outside the plurality of dummy blocks DB and the plurality of grid blocks MB. The scan driver 205 can supply a scan signal to the scan lines SCANL included in the pixel block PB (see Figure 3 ).

[0104] Each of the plurality of grid blocks MB can include grid power lines having a grid shape.

[0105] Figure 6 is a diagram showing Figure 2 an example of the grid block shown. Figure 7 is a cross-sectional view showing an example taken along the line I-I' of Figure 6 .Figure 8 is a cross-sectional view showing an example taken along line II-II' Figure 6 as shown. Figure 9 is a cross-sectional view showing an example taken along line III-III' Figure 6 as shown. Figure 10 is a cross-sectional view showing an example taken along line IV-IV' Figure 6 as shown.

[0106] Referring to Figures 6 to 10 as shown in Figure 6 , each of the plurality of grid blocks MB may include a first region NTA2 provided with grid power lines and a second region TA2 not provided with grid power lines. The first region NTA2 may be a second non-transmissive region that does not transmit most of the light incident from the outside, and the second region TA2 may be a second transmissive region that transmits most of the light incident from the outside.

[0107] For example, the second transmissive region TA2 may be a region having a light transmittance greater than α%, and the second non-transmissive region NTA2 may be a region having a light transmittance less than β%. Here, α may be a value greater than β. The transparent display panel 110 may enable an object or background provided at the rear surface of the transparent display panel 110 to be seen based on the plurality of second transmissive regions TA2.

[0108] The grid block MB may have the same size as the pixel block PB. In addition, the ratio of the size of the second transmissive region TA2 in each grid block MB to the size of the area of each grid block MB may be equal to the ratio of the size of the first transmissive region TA1 in each pixel block PB to the size of the area of each pixel block PB. Therefore, the transmissive display panel 110 according to an embodiment of the present disclosure may have the same light transmittance in the region where the pixel block PB is provided and the region where the grid block MB is provided. The transmissive display panel 110 according to an embodiment of the present disclosure may increase the light transmittance of the entire panel and may prevent a sense of difference from occurring between the region where the pixel block PB is provided and the region where the grid block MB is provided. For example, the transmissive display panel 110 according to an embodiment of the present disclosure may prevent a sense of difference from occurring between the display region DA and the border region BA.

[0109] The grid pixel power line MVDDL and the grid common power line MVSSL may be provided in the second non-transmissive region NTA2 and may not transmit the light incident from the outside.

[0110] The grid pixel power line MVDDL may include a first grid pixel power line MVDDL1 and a second grid pixel power line MVDDL2. The first grid pixel power line MVDDL1 may extend in a first direction (e.g., the Y-axis direction). As Figure 7As shown, the first grid pixel power line MVDDL1 may be configured with multiple layers. The first grid pixel power line MVDDL1 may include a first layer MVDDL1a and a second layer MVDDL1b. The first layer MVDDL1a may be formed of the same material in the same layer as the source electrode SE (see Figure 5 ) and the drain electrode DE (see Figure 5 ) of the driving transistor DT (see Figure 5 ) provided in the display area DA. The second layer MVDDL1b may be provided on the first layer MVDDL1a and may be formed of the same material in the same layer as the auxiliary electrode AE (see Figure 5 ) provided in the display area DA. However, embodiments of the present disclosure are not limited thereto. When the first layer MVDDL1a and the second layer MVDDL1b are provided in different layers with an insulating layer therebetween, the first layer MVDDL1a and the second layer MVDDL1b may be provided in any layer.

[0111] The second layer MVDDL1b of the first grid pixel power line MVDDL1 may be connected to the first layer MVDDL1a through the fourth contact hole CH4. The first layer MVDDL1a and the second layer MVDDL1b of the first grid pixel power line MVDDL1 may be electrically connected to each other. The second layer MVDDL1b may be connected to the first layer MVDDL1a through a plurality of fourth contact holes CH4. Therefore, in the transmissive display panel 110 according to an embodiment of the present disclosure, the first layer MVDDL1a and the second layer MVDDL1b of the first grid pixel power line MVDDL1 may be stably connected to each other without contact defects.

[0112] In addition, the first grid pixel power line MVDDL1 may overlap the grid common power line MVSSL in at least some regions. The first grid pixel power line MVDDL1 may overlap the second grid common power line MVSSL2 in at least some regions. Therefore, the first grid pixel power line MVDDL1 may be formed of a single layer so that a short circuit with the second grid common power line MVSSL2 does not occur in the region overlapping the second grid common power line MVSSL2. As Figure 7 shown, the first grid pixel power line MVDDL1 may be formed of a double layer including the first layer MVDDL1a and the second layer MVDDL1b in a region not overlapping the second grid common power line MVSSL2, and may be formed of a single layer as the first layer MVDDL1a in a region overlapping the second grid common power line MVSSL2.

[0113] The second grid pixel power line MVDDL2 may extend in a second direction (e.g., the X-axis direction). As Figure 8As shown, the second grid pixel power line MVDDL2 can be formed of a single layer. The second grid pixel power line MVDDL2 can be formed of the same material in the same layer as the auxiliary electrode AE (see Figure 5 ) provided in the display area DA, but is not limited thereto.

[0114] The second grid pixel power line MVDDL2 can be connected to the second layer MVDDL1b of the first grid pixel power line MVDDL1. The second grid pixel power line MVDDL2 can be electrically connected to the first grid pixel power line MVDDL1.

[0115] In an embodiment, the second grid pixel power line MVDDL2 can be disposed along a plurality of first holes H1. A plurality of contact holes can be provided in the area of the display area DA where the second sub-pixel SP2 is provided. Accordingly, a plurality of first holes H1 can be formed in the area corresponding to the second sub-pixel SP2. Accordingly, the border area BA can have visibility similar to that of the display area DA.

[0116] The grid common power line MVSSL can include a first grid common power line MVSSL1 and a second grid common power line MVSSL2. The first grid common power line MVSSL1 can extend in a first direction (e.g., the Y-axis direction). The first grid common power line MVSSL1 can be separately provided from the first grid pixel power line MVDDL1, with a second transmission area TA2 therebetween.

[0117] As Figure 9 shown, the first grid common power line MVSSL1 can be configured with multiple layers. The first grid common power line MVSSL1 can include a first layer MVSSL1a and a second layer MVSSL1b. The first layer MVSSL1a can be formed of the same material in the same layer as the source electrode SE (see Figure 5 ) and the drain electrode DE (see Figure 5 ) of the driving transistor DT (see Figure 5 ) provided in the display area DA. The second layer MVSSL1b can be provided on the first layer MVSSL1a and can be formed of the same material in the same layer as the auxiliary electrode AE (see Figure 5 ) provided in the display area DA. However, embodiments of the present disclosure are not limited thereto. In the case where the first layer MVSSL1a and the second layer MVSSL1b are provided in different layers with an insulating layer therebetween, the first layer MVSSL1a and the second layer MVSSL1b can be provided in any layer.

[0118] The second layer MVSSL1b of the first grid common power line MVSSL1 can be connected to the first layer MVSSL1a through the fifth contact hole CH5. The first layer MVSSL1a and the second layer MVSSL1b of the first grid common power line MVSSL1 can be electrically connected to each other. The second layer MVSSL1b can be connected to the first layer MVSSL1a through a plurality of fifth contact holes CH5. Therefore, in the transmissive display panel 110 according to an embodiment of the present disclosure, the first layer MVSSL1a and the second layer MVSSL1b of the first grid common power line MVSSL1 can be stably connected to each other without contact defects.

[0119] In addition, the first grid common power line MVSSL1 can overlap with the grid pixel power line MVDDL in at least some regions. The first grid common power line MVSSL1 can overlap with the second grid pixel power line MVDDL2 in at least some regions. Therefore, the first grid common power line MVSSL1 can be formed of a single layer, so that no short circuit occurs with the second grid pixel power line MVDDL2 in the overlapping region with the second grid pixel power line MVDDL2. As Figure 9 shown, the first grid common power line MVSSL1 can be formed of a double layer including the first layer MVSSL1a and the second layer MVSSL1b in the region where it does not overlap with the second grid pixel power line MVDDL2, and can be formed of a single layer as the first layer MVSSL1a in the region where it overlaps with the second grid pixel power line MVDDL2.

[0120] The second grid common power line MVSSL2 can extend in the second direction (e.g., the X-axis direction). The second grid common power line MVSSL2 can be separately arranged from the second grid pixel power line MVDDL2, with a second transmissive region TA2 therebetween.

[0121] As Figure 10 shown, the second grid common power line MVSSL2 can be configured with a single layer. The second grid common power line MVSSL2 can be formed of the same material as the auxiliary electrode AE (see Figure 5 ) provided in the display area DA in the same layer, but is not limited thereto.

[0122] The second grid common power line MVSSL2 can be connected to the second layer MVSSL1b of the first grid common power line MVSSL1. The second grid common power line MVSSL2 can be electrically connected to the first grid common power line MVSSL1.

[0123] In an embodiment, the second grid common power line MVSSL2 may be disposed along a plurality of first holes H1. A plurality of contact holes may be disposed in a region of the display area DA where the second sub-pixels SP2 are provided. Accordingly, the plurality of first holes H1 may be formed in a region corresponding to the second sub-pixels SP2. Accordingly, the bezel area BA may have a visibility similar to that of the display area DA.

[0124] The grid pixel power line MVDDL of the grid block MB may be electrically connected to the pixel power line VDDL of the pixel block PB. The grid pixel power line MVDDL may be directly connected to the pixel power line VDDL of the pixel block PB. Alternatively, the grid pixel power line MVDDL may be connected to the pixel power line VDDL of the pixel block PB through a dummy block DB.

[0125] Among the grid pixel power lines MVDDL, the first grid pixel power line MVDDL1 may extend toward the display area DA in a first direction (e.g., the Y-axis direction) and may be connected to the pixel power line VDDL of the pixel block PB at one of its ends. In this case, the pixel power line VDDL of the pixel block PB may not have a grid structure, and thus, among the grid pixel power lines MVDDL, only the second layer MVDDL1b of the first grid pixel power line MVDDL1 may extend. The pixel power line VDDL of the pixel block PB may be formed of a single layer and may be formed in the same layer as the second layer MVDDL1b of the first grid pixel power line MVDDL1, but is not limited thereto. The pixel power line VDDL of the pixel block PB may be formed of a double layer like the first grid pixel power line MVDDL1.

[0126] The grid common power line MVSSL of the grid block MB may be electrically connected to the common power line VSSL of the pixel block PB. The grid common power line MVSSL may be directly connected to the common power line VSSL of the pixel block PB. Alternatively, the grid common power line MVSSL may be connected to the common power line VSSL of the pixel block PB through a dummy block DB.

[0127] In the grid common power line MVSSL, the first grid common power line MVSSL1 can extend toward the display area DA in a first direction (e.g., the Y-axis direction), and can be connected to the common power line VSSL of the pixel block PB at one of its ends. In this case, the common power line VSSL of the pixel block PB may not have a grid structure, and thus, in the grid common power line MVSSL, only the second layer MVSSL1b of the first grid common power line MVSSL1 can extend. The common power line VSSL of the pixel block PB can be formed of a single layer and can be formed in the same layer as the second layer MVSSL1b of the first grid common power line MVSSL1, but is not limited thereto. The common power line VSSL of the pixel block PB can be formed of two layers like the first grid common power line MVSSL1.

[0128] In addition, the grid block MB can further include scan lines extending in a second direction (e.g., the X-axis direction) in the second non-transmissive area NTA2. The scan lines can include a first scan line SCANL1 and a second scan line SCANL2. The grid block MB can further include an emission control line EML extending in the second direction (e.g., the X-axis direction) in the second non-transmissive area NTA2. Each of the first scan line SCANL1, the second scan line SCANL2, and the emission control line EML can extend from the gate driver 205 and can extend up to the pixel block PB of the display area DA.

[0129] As Figures 7 to 10 shown, in the grid block MB, the color filter CF can be disposed on the encapsulation layer 180. Similar to the pixel block PB, in the color filter CF, each of the first color filter, the second color filter, and the third color filter can be patterned and formed. The first color filter can be disposed at a position corresponding to the first sub-pixel SP1 of the pixel block PB (see Figure 3 ), and can be a blue color filter that transmits blue light. The second color filter can be disposed at a position corresponding to the second sub-pixel SP2 of the pixel block PB (see Figure 3 ), and can be a red color filter that transmits red light. The third color filter can be disposed at a position corresponding to the third sub-pixel SP3 of the pixel block PB (see Figure 3 ), and can be a green color filter that transmits green light.

[0130] In addition, a black matrix BM can be disposed between the color filters CF and between the second transmissive area TA2 and the color filter CF.

[0131] In the transparent display panel 110 according to an embodiment of the present disclosure, the color filter CF and the black matrix BM may be included in the grid block MB, and thus, the display area DA provided with the pixel block PB and the border area BA provided with the grid block MB may have similar visibility.

[0132] Referring again to Figure 2 , a plurality of dummy blocks DB and a plurality of grid blocks MB may be provided between the display area DA and the grid block MB. A plurality of dummy blocks DB may be provided between the pixel block PB and the grid block MB. Each of the plurality of dummy blocks DB may include a third non-transmissive area provided with a plurality of dummy pixels and a third transmissive area not provided with the plurality of dummy pixels.

[0133] The dummy block DB may have the same size as the pixel block PB. In addition, the ratio of the size of the third transmissive area in each dummy block DB to the size of the area of each dummy block DB may be equal to the ratio of the size of the first transmissive area TA1 in each pixel block PB to the size of the area of each pixel block PB. Therefore, the transmissive display panel 110 according to an embodiment of the present disclosure may have the same light transmittance in the area provided with the pixel block PB, the area provided with the dummy block DB, and the area provided with the grid block MB. The transmissive display panel 110 according to an embodiment of the present disclosure may increase the light transmittance of the entire panel and may prevent a sense of difference from occurring between the area provided with the pixel block PB, the area provided with the dummy block DB, and the area provided with the grid block MB. For example, the transmissive display panel 110 according to an embodiment of the present disclosure may prevent a sense of difference from occurring between the display area DA and the border area BA.

[0134] A plurality of dummy pixels may be provided in the third non-transmissive area and may not transmit light incident from the outside. The pixel block PB may include a plurality of sub-pixels SP1 to SP3 (see Figure 3 ) that emit light of a specific color, while the dummy block DB may include a plurality of dummy pixels that do not emit light.

[0135] Similar to the sub-pixels, the dummy pixels may include electrode patterns configuring circuit devices, electrode patterns and a light-emitting layer configuring a light-emitting device, but contact holes for electrical connection between the electrode patterns may not be formed. For example, the first electrode E1 (see Figure 3 ), the light-emitting layer EL (see Figure 5 ), and the second electrode E2 (see Figure 5 ) of the light-emitting device ED (see Figure 5 ) included in the sub-pixels SP1 to SP3 (see Figure 5 ) may be patterned and formed in the dummy pixels. However, since contact holes are not formed in the dummy pixels, the first electrode E1 (see Figure 5) cannot be electrically connected to the driving transistor DT. Thus, in the dummy pixel, the light-emitting layer EL (see Figure 5 ) provided between the first electrode E1 and the second electrode E2 (see Figure 5 ) cannot emit light. Figure 5 )

[0136] Similar to the pixel block PB, in the dummy block DB, the first signal line and the second signal line can also be provided in the third non-transmissive region. The first signal line can extend in the first direction (e.g., the Y-axis direction) in the third non-transmissive region. The first signal line can include a pixel power line VDDL, a data line, and a common power line VSSL. In an embodiment, the first signal line can further include a reference line.

[0137] The pixel power line VDDL and the common power line VSSL can be provided separately from each other with a third transmissive region therebetween. The pixel power line VDDL included in the dummy block DB can extend from the pixel power line VDDL included in the pixel block PB, and one end thereof can be connected to the mesh pixel power line MVDDL included in the mesh block MB. The pixel power line VDDL included in the dummy block DB cannot transmit power to the dummy pixel.

[0138] The common power line VSSL included in the dummy block DB can extend from the common power line VSSL included in the pixel block PB, and one end thereof can be connected to the mesh common power line MVSSL included in the mesh block MB. The common power line VSSL included in the dummy block DB cannot transmit the second power to the dummy pixel.

[0139] The second signal line can extend in the second direction (e.g., the X-axis direction) in the third non-transmissive region. The second signal line can include a scan line SCANL. The scan line SCANL can include a first scan line and a second scan line. The second signal line SL2 can further include an emission control line. The scan line SCANL and the emission control line included in the dummy block DB can extend from the scan line SCANL and the emission control line included in the pixel block PB, and one end thereof can be connected to each line of the scan line SCANL and the emission control line included in the mesh block MB. The scan line SCANL and the emission control line included in the dummy block DB cannot transmit a scan signal and an emission control signal.

[0140] Similar to the pixel block PB, the dummy block DB can include a color filter CF and a black matrix BM. Thus, in the transparent display panel 110 according to an embodiment of the present disclosure, the display area DA provided with the pixel block PB and the border area BA provided with the dummy block DB and the mesh block MB can have similar visibility.

[0141] Figure 11It is a diagram showing an example in which a grid block according to an embodiment of the present disclosure is provided in a transparent display panel 110. Figure 12 It is a diagram showing Figure 11 an example of a first column line and a second column line provided in region B of

[0142] Referring to Figure 11 , the transparent display panel 110 according to an embodiment of the present disclosure may include a display area DA and a border area BA. The display area DA may include a first side S1 facing a pad area PA where power pads are provided, a second side S2 facing the first side S1, and third and fourth sides S3 and S4 connecting the first side S1 to the second side S2.

[0143] In the display area DA, the width W1 of the first side S1 may be different from the width W2 of the second side S2. In an embodiment, as Figure 11 shown, in the display area DA, the width W1 of the first side S1 may be greater than the width W2 of the second side S2. As described above, in the display area DA, since the width W1 of the first side S1 is different from the width W2 of the second side S2, at least one of the third side S3 and the fourth side S4 may be inclined. When the width W1 of the first side S1 is greater than the width W2 of the second side S2, at least one of the third side S3 and the fourth side S4 may be inclined toward the first side S1. Alternatively, when the width W1 of the first side S1 is less than the width W2 of the second side S2, at least one of the third side S3 and the fourth side S4 may be inclined toward the second side S2. Hereinafter, for ease of description, an example in which the third side S3 and the fourth side S4 are inclined toward the first side S1 will be described, but the embodiments of the present disclosure are not limited thereto. Only one of the third side S3 and the fourth side S4 may be inclined toward the first side S1.

[0144] The slope of each of the third side S3 and the fourth side S4 may not be constant between the first side S1 and the second side S2. For example, the slope of each of the third side S3 and the fourth side S4 may change from the first side S1 toward the second side S2.

[0145] The slope may change based on the number of pixel blocks PB provided in the column lines. Specifically, the display area DA may include a plurality of first column lines CL1 configured with pixel blocks PB arranged in a second direction (e.g., the X-axis direction). The first column lines CL1 among the plurality of first column lines CL1 provided between the first side S1 and the second side S2 of the display area DA may include the same number of pixel blocks PB.

[0146] However, the first column lines CL1 among multiple first column lines CL1, which are set between the first side S1 and the third side S3 of the display area DA and between the first side S1 and the fourth side S4 of the display area DA, may include different numbers of pixel blocks PB. The number of pixel blocks PB of the first column lines CL1 set between the first side S1 and the third side S3 of the display area DA may gradually increase toward the central area of the display area DA. The first column lines CL1 set between the first side S1 and the third side S3 of the display area DA may be different in terms of the change in the number of pixel blocks PB toward the central area of the display area DA. In the first column lines CL1 set between the first side S1 and the third side S3 of the display area DA, the change in the number of pixel blocks PB may gradually decrease toward the central area of the display area DA.

[0147] In addition, the number of pixel blocks PB of the first column lines CL1 set between the first side S1 and the fourth side S4 of the display area DA may gradually increase toward the central area of the display area DA. The first column lines CL1 set between the first side S1 and the fourth side S4 of the display area DA may be different in terms of the change in the number of pixel blocks PB toward the central area of the display area DA. In the first column lines CL1 set between the first side S1 and the fourth side S4 of the display area DA, the change in the number of pixel blocks PB may gradually decrease toward the central area of the display area DA.

[0148] The slope can be determined based on the change in the number of pixel blocks PB between adjacent first column lines CL1. When the change in the number of pixel blocks PB between adjacent first column lines CL1 is large, the slope of the third side S3 and the fourth side S4 can be large. On the other hand, when the change in the number of pixel blocks PB between adjacent first column lines CL1 is small, the slope of the third side S3 and the fourth side S4 can be small.

[0149] In the third side S3 of the display area DA, the change in the number of pixel blocks PB set in the first column lines CL1 may gradually decrease toward the central area of the display area DA, and thus, the slope may gradually decrease toward the central area of the display area DA. In addition, in the fourth side S4 of the display area DA, the change in the number of pixel blocks PB set in the first column lines CL1 may gradually decrease toward the central area of the display area DA, and thus, the slope may gradually decrease toward the central area of the display area DA.

[0150] On the other hand, in the third side S3 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually increase in the direction away from the central area of the display area DA, and thus, the slope can gradually increase in the direction away from the central area of the display area DA. In addition, in the fourth side S4 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually increase in the direction away from the central area of the display area DA, and thus, the slope can gradually increase in the direction away from the central area of the display area DA.

[0151] In addition, the border area BA may include: a first border area BA1 provided at the first side S1 of the display area DA and including a pad area PA, a second border area BA2 provided at the second side S2 of the display area DA, a third border area BA3 provided at the third side S3 of the display area DA, and a fourth border area BA4 provided at the fourth side S4 of the display area DA.

[0152] A power pad, a first auxiliary common power electrode VSS1, a first auxiliary pixel power electrode VDD1, and an auxiliary reference power electrode VREF may be provided in the first border area BA1. Each of the first auxiliary common power electrode VSS1, the first auxiliary pixel power electrode VDD1, and the auxiliary reference power electrode VREF may extend along the first side S1 of the display area DA and may be spaced apart from each other in the first border area BA1.

[0153] A second auxiliary common power electrode VSS2 and a second auxiliary pixel power electrode VDD2 may be provided in the second border area BA2. Each of the second auxiliary common power electrode VSS2 and the second auxiliary pixel power electrode VDD2 may extend along the second side S2 of the display area DA and may be spaced apart from each other in the second border area BA2.

[0154] The first auxiliary pixel power electrode VDD1 may be connected to a pixel power pad provided in the pad area PA, and a first source voltage may be supplied to the first auxiliary pixel power electrode VDD1 through the pixel power pad from a circuit film (chip on film (COF)). The first auxiliary pixel power electrode VDD1 may be connected to a pixel power line included in the display area DA, and the first source voltage may be supplied to the pixel power line. One end of each of the plurality of pixel power lines included in the display area DA may be connected to the first auxiliary pixel power electrode VDD1, and the other end may be connected to the second auxiliary pixel power electrode VDD2. As described above, each of the plurality of pixel power lines may be connected to the first auxiliary pixel power electrode VDD1 and the second auxiliary pixel power electrode VDD2, and thus, the first source voltage may be transmitted more uniformly and stably.

[0155] The first auxiliary common power electrode VSS1 may be connected to a common power pad provided in the pad area PA, and may be supplied with a second source voltage from a circuit on film (COF) through the common power pad. The first auxiliary common power electrode VSS1 may be connected to a common power line included in the display area DA, and may supply the second source voltage to the common power line. One end of each of a plurality of common power lines included in the display area DA may be connected to the first auxiliary common power electrode VSS1, and the other end may be connected to the second auxiliary common power electrode VSS2. As described above, each of the plurality of common power lines may be connected to the first auxiliary common power electrode VSS1 and the second auxiliary common power electrode VSS2, and thus the second source voltage may be transmitted more uniformly and stably.

[0156] In addition, in the transparent display panel 110 according to an embodiment of the present disclosure, the width W1 of the first side S1 of the display area DA may be formed to be greater than the width W2 of the second side S2, and thus, the pixel power lines and the common power lines provided between the first side S1 and the third side S3 and provided between the first side S1 and the fourth side S4 may not extend up to the second border area BA2. Accordingly, the pixel power lines and the common power lines provided between the first side S1 and the third side S3 and provided between the first side S1 and the fourth side S4 may not be connected to the second auxiliary pixel power electrode VDD2 and the second auxiliary common power electrode VSS2 provided in the second border area BA2. In addition, the pixel power lines and the common power lines provided between the first side S1 and the third side S3 and provided between the first side S1 and the fourth side S4 may have lengths shorter than those of each of the pixel power lines and the common power lines provided between the first side S1 and the second side S2. Accordingly, the pixel power lines and the common power lines provided between the first side S1 and the third side S3 and provided between the first side S1 and the fourth side S4 may be smaller in terms of resistance than the pixel power lines and the common power lines provided between the first side S1 and the second side S2. In particular, the number of pixel blocks PB included in the first column line CL1 may be greatly reduced in the direction away from the central area of the display area DA, and thus, the length of each of the pixel power lines and the common power lines may be very short. Due to this, the voltage deviation between the pixel power lines included in the display area DA may increase, and the voltage deviation between the common power lines may increase, and thus the luminance deviation may increase.

[0157] In the transparent display panel 110 according to an embodiment of the present disclosure, a plurality of grid blocks MB may be provided in the third border area BA3 and the fourth border area BA4, thereby reducing the length difference between pixel power lines and the length difference between common power lines in the display area DA that occur due to the width difference between the first side S1 and the second side S2 of the display area DA. For example, in the transparent display panel 110 according to an embodiment of the present disclosure, pixel power lines and common power lines may extend from the display area DA to the third border area BA3 and the fourth border area BA4, and thus, the length of each of the pixel power lines and common power lines provided between the first side S1 and the third side S3 and provided between the first side S1 and the fourth side S4 may be increased.

[0158] In addition, in the transparent display panel 110 according to an embodiment of the present disclosure, pixel power lines and common power lines provided in the third border area BA3 and the fourth border area BA4 may be connected to each other in a grid form to form grid pixel power lines and grid common power lines, and thus, the voltage deviation between pixel power lines provided in the display area DA may be reduced, and the voltage deviation between common power lines may be reduced. Therefore, the transparent display panel 110 according to an embodiment of the present disclosure may reduce the brightness deviation of the display area DA and may have uniform brightness.

[0159] In addition, in the transparent display panel 110 according to an embodiment of the present disclosure, the number of grid blocks MB provided in the column lines may vary based on the slope of each of the third side S3 and the fourth side S4 of the display area DA. Specifically, the third border area BA3 and the fourth border area BA4 may include a plurality of second column lines CL2 in which grid blocks MB are arranged in the second direction (e.g., the X-axis direction).

[0160] The second column lines CL2 provided at the third side S3 of the display area DA may respectively correspond to the first column lines CL1 provided between the first side S1 and the third side S3 of the display area DA. For example, as Figure 12 shown, the nth first column line CL1n may correspond to the nth second column line CL2n. A plurality of grid blocks MB included in the nth second column line CL2n may be provided on a plurality of pixel blocks PB included in the nth first column line CL1n.

[0161] When the slope of each of the third side S3 and the fourth side S4 of the display area DA is large, the number of grid blocks MB included in the second column line CL2 may increase. On the other hand, when the slope of each of the third side S3 and the fourth side S4 of the display area DA is small, the number of grid blocks MB included in the second column line CL2 may be small.

[0162] In the third side S3 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually decrease toward the central area of the display area DA, and thus, the slope can gradually decrease toward the central area of the display area DA. Therefore, in the second column line CL2 provided in the third border area BA3, the number of grid blocks MB can gradually decrease toward the central area of the display area DA.

[0163] For example, the first column line CL1 provided between the first side S1 and the third side S3 of the display area DA may include: one first column line CL1 having a first change in the number of pixel blocks PB and another first column line CL1 having a second change in the number of pixel blocks PB, the second change being smaller than the first change. In this case, the second column line CL2 corresponding to the another first column line CL1 may be smaller than the second column line CL2 corresponding to the one first column line CL1 in terms of the number of grid blocks MB.

[0164] In addition, in the fourth side S4 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually decrease toward the central area of the display area DA, and thus, the slope can gradually decrease toward the central area of the display area DA. Therefore, in the second column line CL2 provided in the fourth border area BA4, the number of grid blocks MB can gradually decrease toward the central area of the display area DA.

[0165] On the other hand, in the third side S3 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually increase toward the central area of the display area DA, and thus, the slope can gradually increase toward the central area of the display area DA. Therefore, in the second column line CL2 provided in the third border area BA3, the number of grid blocks MB can gradually increase toward the central area of the display area DA.

[0166] In addition, in the fourth side S4 of the display area DA, the change in the number of pixel blocks PB provided in the first column line CL1 can gradually increase toward the central area of the display area DA, and thus, the slope can gradually increase toward the central area of the display area DA. Therefore, in the second column line CL2 provided in the fourth border area BA4, the number of grid blocks MB can gradually increase toward the central area of the display area DA.

[0167] Figure 13 is a diagram showing the relationship between the number of pixel blocks included in the first column line and the number of grid blocks included in the second column line.

[0168] Multiple data lines may correspond to multiple first column lines and multiple second column lines. In this case, based on the size of the pixel block PB, at least one data line may correspond to one first column line. For example, one first column line may correspond to two data lines. The grid block MB may have the same size as the pixel block PB, and thus, one second column line may correspond to two data lines. However, embodiments of the present disclosure are not limited thereto.

[0169] Reference Figure 13 , in the first column line CL1, the change in the number of pixel blocks PB may gradually increase from the first data line toward the 49th data line, and then in the first column line CL1, the change in the number of pixel blocks PB may gradually decrease toward the 177th data line. In this case, the second column line CL2 corresponding to the first column line CL1 with a large change in the number of pixel blocks PB may include a plurality of grid blocks MB in the range of 25 to 30 in number of grid blocks MB.

[0170] In addition, the second column line CL2 corresponding to the first column line CL1 with a small change in the number of pixel blocks PB may include only five grid blocks MB because the number of grid blocks MB gradually decreases.

[0171] In the transparent display panel 110 according to an embodiment of the present disclosure, when the change in the number of pixel blocks PB between adjacent first column lines CL1 is large, a plurality of grid blocks MB may be provided, and thus, the length deviation between the pixel power line and the common power line between adjacent first column lines CL1 may be greatly reduced. On the other hand, in the transparent display panel 110 according to an embodiment of the present disclosure, when the change in the number of pixel blocks PB between adjacent first column lines CL1 is small, fewer grid blocks MB may be provided, and thus the length deviation between the pixel power line and the common power line between adjacent first column lines CL1 may be slightly reduced. Therefore, the transparent display panel 110 according to an embodiment of the present disclosure may uniformly maintain the length deviation between the pixel power line and the common power line in the entire display area DA.

[0172] Figure 14 is a diagram showing an example of applying the transparent display device 100 according to an embodiment of the present disclosure to a vehicle.

[0173] Reference Figure 14 , the transparent display device 100 may be installed inside the vehicle and may display image information. For example, as Figure 14 shown, the transparent display device 100 may be installed between two front seats of the vehicle and may display vehicle control information or vehicle movement information.

[0174] In the present disclosure, like the pixel blocks included in the display area, transmissive areas may be included in the grid blocks that may be included in the border area, and thus, the display area and the border area may have the same light transmittance. The present disclosure can improve the light transmittance of the entire panel and can prevent a sense of difference from occurring between the display area and the border area.

[0175] In addition, in the present disclosure, color filters and black matrices may be included in the grid blocks, and thus, the display area provided with pixel blocks and the border area provided with grid blocks may have similar visibility.

[0176] In addition, in the present disclosure, a plurality of grid blocks may be provided in the border area, thereby reducing the length deviation between common power lines and the length deviation between pixel power lines that occur due to the width difference between the lower part and the upper part of the display area. In the present disclosure, the pixel power lines and the common power lines included in the display area may extend up to the border area between the lower part and the upper part of the display area, thereby reducing the length deviation between pixel power lines and the length deviation between common power lines.

[0177] In addition, in the present disclosure, the pixel power lines and the common power lines provided in the border area may be connected to each other in a grid form to form grid pixel power lines and grid common power lines, and thus, the voltage deviation between pixel power lines can be reduced, and the voltage deviation between common power lines can be reduced. Therefore, the present disclosure can reduce the brightness deviation of the display area and can achieve uniform brightness.

[0178] In addition, in the present disclosure, when the change in the number of pixel blocks between adjacent first column lines is large, a plurality of grid blocks may be provided, and thus, the length deviation between pixel power lines and common power lines between adjacent first column lines can be greatly reduced. In addition, in the present disclosure, when the change in the number of pixel blocks between adjacent first column lines is small, fewer grid blocks may be provided, and thus, the length deviation between pixel power lines and common power lines between adjacent first column lines can be slightly reduced. Therefore, the present disclosure can uniformly maintain the length deviation of pixel power lines and common power lines throughout the display area.

[0179] The above features, structures, and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. In addition, the features, structures, and effects described in at least one embodiment of the present disclosure can be achieved by those skilled in the art through combinations or modifications of other embodiments. Therefore, the content associated with combinations and modifications should be construed as being within the scope of the present disclosure.

[0180] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A transparent display device, comprising: a display area including a plurality of pixel blocks disposed therein and configured to display an image; a frame area disposed at one or more sides of the display area; as well as A plurality of grid blocks are provided in the border area, each of the plurality of grid blocks includes grid power lines having a grid shape, wherein each of the plurality of pixel blocks includes a first transmission area configured to transmit external light, and Each of the plurality of grid blocks includes a second transmission area configured to transmit external light.

2. The transparent display device according to claim 1, wherein: Each of the plurality of pixel blocks has a size that is the same as a size of at least one of the plurality of grid blocks.

3. The transparent display device according to claim 1, wherein: A ratio of a size of the second transmission region in each grid block to a size of an area of ​​each grid block is equal to a ratio of a size of the first transmission region in each pixel block to a size of an area of ​​each pixel block.

4. The transparent display device according to claim 1, wherein: Each of the plurality of pixel blocks includes a power line disposed in the first non-transmission region to have a straight line shape, and Each of the plurality of grid blocks includes the grid power lines disposed in the second non-transmitting region.

5. The transparent display device according to claim 4, wherein: The power lines of each pixel block include pixel power lines extending in a first direction and common power lines extending in the first direction, and The pixel power lines and the common power lines are arranged separately from each other, and the first transmission area is between the pixel power lines and the common power lines.

6. The transparent display device according to claim 5, wherein: The pixel power lines and the common power lines are formed of a single layer.

7. The transparent display device according to claim 4, wherein: The grid power lines of each grid block include grid pixel power lines and grid common power lines, The grid pixel power lines include first grid pixel power lines extending in a first direction and second grid pixel power lines extending in a second direction, and The grid common power lines include a first grid common power line extending in the first direction and a second grid common power line extending in the second direction.

8. The transparent display device according to claim 7, wherein: The first grid pixel power lines and the first grid common power lines are arranged separately from each other, and there is the second transmission area between the first grid pixel power lines and the first grid common power lines, and The second grid pixel power lines and the second grid common power lines are arranged separately from each other, and there is the second transmission area between the second grid pixel power lines and the second grid common power lines.

9. The transparent display device according to claim 7, wherein: The first grid pixel power lines and the first grid common power lines are formed of a plurality of layers, and Wherein, the second grid pixel power lines and the second grid common power lines are formed by a single layer.

10. The transparent display device according to claim 7, wherein: The first grid pixel power lines are formed of a double layer in a region not overlapping with the second grid common power lines, and are formed of a single layer in a region overlapping with the second grid common power lines, and The first grid common power lines are formed of a double layer in a region not overlapping with the second grid pixel power lines, and are formed of a single layer in a region overlapping with the second grid pixel power lines.

11. The transparent display device according to claim 7, wherein: The power lines of each pixel block include pixel power lines extending in the first direction and common power lines extending in the first direction, and The pixel power lines of each pixel block are electrically connected to the grid pixel power lines of each grid block, and the common power lines of each pixel block are electrically connected to the grid common power lines of each grid block.

12. The transparent display device according to claim 1, further comprising a dummy block disposed between a corresponding pixel block among the plurality of pixel blocks and a corresponding grid block among the plurality of grid blocks, in, Each of the plurality of pixel blocks includes a plurality of sub-pixels configured to emit light, and The dummy block includes a plurality of dummy pixels configured not to emit light.

13. The transparent display device according to claim 12, wherein: The dummy block includes a third transmission area configured to transmit external light.

14. The transparent display device according to claim 1, wherein: The display area includes a first side facing a pad area provided with a power pad, a second side facing the first side, and third and fourth sides connecting the first side to the second side, and Wherein, the width of the first side in the display area is different from the width of the second side.

15. The transparent display device according to claim 14, wherein: A width of the first side in the display area is greater than a width of the second side.

16. The transparent display device according to claim 14, wherein: The border area includes: A first frame area disposed at the first side of the display area, the first frame area including the pad area; a second frame area disposed at the second side of the display area; A third frame area disposed at the third side of the display area; and a fourth frame region disposed at the fourth side of the display region, and Wherein, the plurality of grid blocks are arranged in at least one of the third border area and the fourth border area.

17. The transparent display device according to claim 14, wherein: At least one of the third side and the fourth side of the display area is inclined.

18. The transparent display device according to claim 17, wherein: A slope of at least one of the third side and the fourth side of the display area changes from the first side of the display area toward the second side of the display area.

19. The transparent display device according to claim 14, wherein: The display area includes a plurality of first column lines, each of the first column lines is configured with pixel blocks arranged in a second direction, and Among the plurality of first column lines, the first column lines disposed between the first side and the third side of the display area are different in the number of pixel blocks.

20. The transparent display device according to claim 19, wherein: In the first column lines disposed between the first side and the third side of the display area, the number of the pixel blocks gradually increases toward a central area of ​​the display area, and a change in the number of the pixel blocks is different.

21. The transparent display device according to claim 19, wherein: Each of the first column lines disposed between the first side and the second side of the display area among the plurality of first column lines includes the same number of pixel blocks.

22. The transparent display device according to claim 21, wherein: The border area includes a plurality of second column lines, each of the second column lines is configured with grid blocks arranged in the second direction, and Among the plurality of second column lines, the second column lines disposed at the third side of the display area respectively correspond to the first column lines disposed between the first side and the third side of the display area.

23. The transparent display device according to claim 22, wherein: The first column lines disposed between the first side and the third side of the display area include: one first column line having a first variation in the number of the pixel blocks and other first column lines having a second variation in the number of the pixel blocks, the second variation being smaller than the first variation, and The second column line corresponding to the other first column line is smaller in number of grid blocks than the second column line corresponding to the one first column line.

24. The transparent display device according to claim 1, wherein: Each of the plurality of pixel blocks includes a power line disposed in a first non-transmission region, a light emitting device disposed on the power line, and a color filter disposed on the light emitting device, and Each of the plurality of grid blocks includes the grid power lines disposed in the second non-transmitting region and a color filter disposed on the grid power lines.

25. The transparent display device according to claim 13, wherein: The dummy block has the same size as that of the pixel block, and The ratio of the size of the third transmission region in each dummy block to the size of the area of ​​each dummy block is equal to the ratio of the size of the first transmission region in each pixel block to the size of the area of ​​each pixel block.

Images