Method of fabricating optical structure on photonic glass layer substrate

Abstract

Embodiments described herein also relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnects between electrical, optoelectronic and photonic elements. One or more optical silicon photonic elements described herein may be used on a single package substrate in conjunction with one or more optoelectronic integrated circuits (optoelectronic chips) to form co-packaged optical and electrical elements. The methods described herein enable mass fabrication of electrical, optoelectronic, and optical silicon photonic elements having a plurality of optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to silicon photonic integrated circuits and co-packaged optical silicon photonic components. More specifically, the present disclosure relates to devices for co-packaged optical silicon photonic components and methods of fabricating optical structures for optical silicon photonic components. Background Art

[0002] As the network requirements for data traffic continue to increase, network companies that previously used traditional copper cables for communication have found more efficient solutions that can be deployed on a large scale. Today, fiber optic technology dominates the long-distance communication space. Network companies have gradually shifted to using fiber optic cables for long-distance data transmission. By using fiber optic cables, data is transmitted at the speed of light at ultra-high frequencies in the form of photons, allowing for higher data volume transmission.

[0003] As the requirements for data traffic networks increase, there are also requirements for increasing data rates in electronic systems and communication. When the semiconductor industry is balancing the continuously increasing operating speed of integrated circuits and chip solutions that can meet the growing data traffic network demands, an area for improvement that can help the semiconductor industry is to increase the interconnect speed. The typical electrical interconnect solution between transistors on traditional integrated circuits is still currently copper wires for electrons. The problem with using copper wiring for communication and data transmission is usually IR heating, and the electrons traveling through such wiring interact with other atoms, slowing down the electron speed and causing signal loss. Therefore, there is a motivation to reduce the use and length of copper interconnects and wiring in solutions for communication and data transmission technologies. One way to minimize the use of copper interconnects is co-packaged multi-chip modules, where a single packaging substrate includes multiple integrated circuit elements closely assembled together. Such multi-chip modules have been developed, but the use of typical multi-chip modules still largely relies on copper wiring to transmit data to and from the printed circuit board of the multi-chip module.

[0004] Another way to minimize the use of copper wiring in electronic communication systems is to integrate with optical communication system technology, which has been proven to be more advantageous than copper in terms of communication and data transmission due to lower length-related and data rate-related signal losses. More recently, optical components have been integrated on a silicon (Si) substrate for fabricating large-scale silicon photonic integrated circuits that coexist with microelectronic chips. Optical communication technology generally involves different materials and manufacturing processes from electronic communication technology. However, silicon photonics technology has combined optical communication technology with electronic technology based on a common material platform. Using an optical transceiver, a received optical signal can be converted into an electrical signal that can be processed by an integrated circuit, or a processed electrical signal can be converted into an optical signal that can be transmitted through a fiber optic cable.

[0005] Therefore, a co-packaged optical silicon photonics component and a manufacturing method thereof that need to be improved in the technical field to which this case belongs. SUMMARY OF THE INVENTION

[0006] The embodiments described herein relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnects between electrical, optoelectronic, and photonic components. In one embodiment, a method for fabricating electrical and photonic components is provided. The method includes depositing a core material layer on a surface of a substrate that includes a photonic glass layer (PGL), the photonic glass layer having a first refractive index. The core material layer has a second refractive index different from the first refractive index. Next, a patterned layer is deposited over the core material layer, the patterned layer having openings formed therein, with portions of the surface of the core material layer exposed in the openings. The method then removes portions of the core material exposed within the openings of the patterned layer to form a plurality of optical structures. Each optical structure includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each waveguide of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

[0007] In one embodiment, a method for fabricating electrical and photonic components is provided. The method includes depositing a patterned layer above a surface of a substrate that includes a photonic glass layer, the photonic glass layer having a first refractive index and the patterned layer having a plurality of openings formed therein, with portions of the surface of the substrate exposed in the openings. Next, portions of the substrate exposed within the openings of the patterned layer are removed to form a plurality of structures separated by a plurality of trenches in the substrate. The method then removes the patterned layer and deposits a fill layer over the plurality of structures and into the plurality of trenches to form a plurality of optical structures, the fill layer having a second refractive index different from the first refractive index. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each waveguide of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

[0008] In another embodiment, a method for manufacturing electronic and photonic components is provided. The method includes depositing a patterned layer over a surface of a substrate that includes a photon glass layer having a first refractive index, and the patterned layer having a plurality of openings formed therein, with portions of the surface of the substrate exposed through the openings. The method then performs an ion implantation process on the exposed portions of the substrate to implant a plurality of doped ions into the surfaces of the exposed portions of the substrate. The exposed portions of the substrate including the plurality of doped ions define a plurality of optical structures having a second refractive index different from the first refractive index. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein the waveguide of each of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

[0009] In another embodiment, an electro-photonic component assembly is provided having a substrate with a chip mounting region and an optical fiber connector region. The chip mounting region is configured to receive a photon transceiver chip (providing functions such as electrical-to-optical and optical-to-electrical conversion), and the optical fiber connector region is configured to couple to an optical fiber connector. The substrate further includes a plurality of optical structures located between the photon transceiver chip and the optical fiber connector. Each of the plurality of optical structures is operable to transmit light between a first end of each of the plurality of optical structures (configured to receive light transmitted from a plurality of waveguides of the optical transceiver chip, or light to be received by the waveguides of the optical transceiver chip) and a second end of each of the plurality of optical structures (configured to receive light transmitted from a plurality of optical fibers of the optical fiber connector, or light to be received by the optical fibers of the optical fiber connector coupled to the substrate).

[0010] In another embodiment, co-packaged electronic and photonic components are provided. The co-packaged electronic and photonic components include: a package substrate, one or more electrical or optoelectronic integrated circuits mounted on the package substrate, and one or more electronic and photonic components mounted on the package substrate, with each of the one or more electronic and photonic components connected to one or more electrical or optoelectronic integrated circuits. Each of the one or more electronic and photonic components also includes a support substrate having a optical transceiver chip mounting region and an optical fiber connector region. The optical transceiver chip mounting region is configured to receive an optical transceiver chip, and the optical fiber connector region is configured to couple to an optical fiber connector. The support substrate of the one or more electronic and photonic components also includes a plurality of optical structures formed within the support substrate and operable to transmit light between a first end and a second end of the support substrate.

[0011] In one embodiment, a method for manufacturing electronic and photonic components is provided. The method includes: depositing a patterned layer over a surface of a substrate including a photon glass layer, the photon glass layer having a first refractive index, and the patterned layer having a plurality of openings formed therein, with portions of the surface of the substrate exposed in the openings. Next, portions of the substrate exposed within the openings of the patterned layer are removed to form a plurality of structures in the substrate separated by a plurality of trenches. The method then removes the patterned layer and deposits a fill layer over the plurality of structures and into the plurality of trenches to form a plurality of optical structures, the fill layer having a second refractive index different from the first refractive index. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each waveguide of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

[0012] In another embodiment, a method for manufacturing electronic and photonic components is provided. The method includes: depositing a patterned layer over a surface of a substrate including a photon glass layer, the photon glass layer having a first refractive index, and the patterned layer having a plurality of openings formed therein, with portions of the surface of the substrate exposed in the openings. The method then performs an ion implantation process on the exposed portions of the substrate to implant a plurality of doped ions into the surface of the exposed portions of the substrate. The exposed portions of the substrate including the plurality of doped ions define a plurality of optical structures having a second refractive index different from the first refractive index. Each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each waveguide of the plurality of optical structures extends in one or more directions between the first edge and the second edge. Description of the Drawings

[0013] Thus, the above-described features of the present case can be understood in detail, and the present case can be described in more detail by referring to the embodiments. The detailed description of the present case is as briefly outlined above, and some of the embodiments are shown in the drawings. However, note that the drawings only show exemplary embodiments and should not be considered as limiting the scope, and other equivalent embodiments are allowed.

[0014] Figure 1 A perspective view of at least a portion of a packaged substrate according to an embodiment, the packaged substrate having one or more optical silicon photon components formed thereon.

[0015] Figure 2A And 2B A top view of a photon engine according to an embodiment.

[0016] Figures 3A to 3ESchematic cross-sectional view of a part of one or more optical silicon photon devices according to an embodiment.

[0017] Figures 4A to 4G Schematic cross-sectional view of a part of one or more optical silicon photon components according to an embodiment.

[0018] Figures 5A to 5E Schematic cross-sectional view of a part of one or more optical silicon photon components according to an embodiment.

[0019] Figure 6 Flowchart illustrating operations of a method for manufacturing an optical component on a photon glass layer substrate according to an embodiment.

[0020] Figure 7 Flowchart illustrating operations of a method for manufacturing an optical component on a photon glass layer substrate according to an embodiment.

[0021] Figure 8 Flowchart illustrating operations of a method for manufacturing an optical component on a photon glass layer substrate according to an embodiment.

[0022] Figure 9 is according to an embodiment, by using Figure 10 Schematic cross-sectional view of a part of a photon engine formed by using the section line C-C in

[0023] Figure 10 Schematic cross-sectional view of a part of a photon engine formed by using the section line B-B in Figure 2A according to an embodiment.

[0024] Figure 11 Schematic alternative cross-sectional view of a part of a photon engine formed by using the section line B-B in Figure 2A according to an embodiment.

[0025] Figure 12 Schematic cross-sectional view of a part of a pluggable connector formed by using the section line B-B in Figure 2A according to an embodiment.

[0026] For ease of understanding, the same reference numerals are used to denote the same elements common to the figures wherever possible. It is contemplated that the elements and features of one embodiment can be advantageously incorporated into other embodiments without further recitation. Detailed Description

[0027] Embodiments of the present disclosure provided herein relate to optical silicon photonics components and methods for manufacturing optical silicon photonics components. The methods described herein enable the mass manufacturing and fabrication of optical silicon photonics components having a plurality of optical structures formed on a photon glass layer substrate. The optical silicon photonics components further include a silicon photonics chip mounted on the photon glass layer substrate and connected to the plurality of optical structures. The plurality of optical structures optically connect the silicon photonics chip to an optical fiber connector, which is configured for connection to an external optical fiber and operates to propagate optical signals between the optical fiber connector and the silicon photonics chip.

[0028] The embodiments described herein also relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnects between electrical, optoelectronic, and photonic components. One or more of the optical silicon photonics components described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single package substrate to form co-packaged optical and electrical components. The methods described herein enable the mass manufacturing of electrical, optoelectronic, and optical silicon photonics components having a plurality of optical structures (such as waveguides) formed on or integrated with a photon glass layer substrate.

[0029] One embodiment of the co-packaged optical and electrical components described herein includes a package substrate formed with one or more optical silicon photonics components and one or more optoelectronic chips. The one or more optical silicon photonics components are connected to the one or more optoelectronic chips and provide an interface to operably connect the optoelectronic chips to an external network optical fiber connection inserted into the optical silicon photonics components. The methods described herein provide a scalable process for manufacturing optical silicon photonics components having optical structures of different sizes, materials, and properties formed on or integrated with a photon glass layer substrate. The manufacturing of the optical silicon photonics components described herein can also be configured based on changing the electro-optic photonics circuit and network optical fiber connection properties that the optical silicon photonics components can use.

[0030] As used herein, the term "about" means a variation of + / - 10% from the nominal value. It should be understood that such variations can be included in any value provided herein.

[0031] In various embodiments of the present disclosure, a layer or other material is referred to as being deposited. It will be understood that the deposition of such materials can be carried out using any conventional method used in semiconductor manufacturing, such as, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, selective deposition of any of the foregoing, combinations of the foregoing, and any other suitable method. It will be understood that when a method operation is described herein as depositing materials at two or more separate locations, the depositions can occur simultaneously, or the materials can be deposited in separate sub-operations.

[0032] In various embodiments of the present disclosure, a layer or other material is referred to as being etched. It will be understood that the etching of the material can be performed using any conventional method used in semiconductor manufacturing, such methods as, but not limited to, reactive ion etching (RIE), dry etching, wet etching, or laser ablation, combinations of the foregoing, and any other suitable method of removing material. It will be understood that when a method operation is described herein as etching two or more types of materials, the etching can occur simultaneously with the same etching process, or the etching can be carried out in separate sub-operations using different etching processes. For example, an operation described as etching a metal and a dielectric includes a first etching sub-operation using a first etching process for etching the metal, and the operation further includes a second etching sub-operation using a second etching process for etching the dielectric.

[0033] Figure 1Perspective view of a portion of an exemplary co-packaged optical and electrical component 100, the co-packaged optical and electrical component 100 including an electrical or optoelectronic chip 102, the electrical or optoelectronic chip 102 being connected to a photonic integrated interconnect unit 103 by a plurality of optical waveguides or electrical trace interconnects 104, all of the foregoing being formed on or disposed on a package substrate 101. In an embodiment, the electrical or optoelectronic chip 102 may include any high-density chip having a high input / output (I / O) pin count. In one example, the high-density chip has an I / O pin count between 100 and 2000 or an I / O pin count of up to and greater than 2000. Examples of the electrical or optoelectronic chip 102 include, but are not limited to, data center SWITCH chips, artificial intelligence (AI) chips, and the like.

[0034] The photonic integrated interconnect unit 103 includes a fiber optic connector area configured to couple to a fiber optic connector 112 for removably connecting a fiber optic cable 120 to the photonic integrated interconnect unit 103. In an embodiment, the fiber optic cable 120 may be inserted into the fiber optic connector 112 to operably connect the fiber optic cable 120 to the co-packaged optical and electrical component 100. In an embodiment, the photonic integrated interconnect unit 103 is configured to connect a fiber optic cable 120, the fiber optic cable 120 including, but not limited to, a single-mode fiber optic cable having a 9-micron core diameter. The fiber optic connector 112 may further include: a plurality of optical fibers 112A( Figure 10 ) to operably connect a fiber optic cable 120 having 1 to 74 cores, 74 to 148 cores, and up to and greater than 148 cores to the photonic integrated interconnect unit 103.

[0035] In an embodiment, the photonic integrated interconnect unit 103 in the group of co-packaged electrical and optical components 100 is configured to transmit signals between the electrical or optoelectronic chip 102 and the fiber optic cable 120 connected to the photonic integrated interconnect unit 103. The photonic integrated interconnect unit 103 includes a photonic glass layer (PGL) substrate 106, a plurality of optical structures 1101-110 integrated with or formed on the PGL substrate 106 N , mounted on the PGL substrate 106 and coupled to the plurality of optical structures 1101-110 at a first interface 107 NThe optical transceiver integrated circuit (SiPho chip) 108, and at the second interface 109 is connected to the PGL substrate 106 and a plurality of optical structures 1101-110 N The fiber optic connectors 112 of both.

[0036] In an embodiment, the SiPho chip 108 in the photonic integrated interconnect unit 103 operates to convert electrical signals into optical signals and vice versa. The plurality of optical structures 1101-110 in the photonic integrated interconnect unit 103 N Operate to transmit optical signals between the SiPho chip 108 and the fiber optic connector 112, and the optical waveguide or electrical trace interconnect 104 operates to transmit electrical signals or optical signals between the photonic integrated interconnect unit 103 (specifically, the SiPho chip 108) and the electrical or optoelectronic chip 102. The optical waveguide or electrical trace interconnect 104 may include metal traces formed within the package substrate 101, which in some embodiments may include: metal traces formed in a printed circuit board (PCB) substrate, or metal traces formed within a plurality of redistribution layers (such as dielectric layers) formed on a solid substrate (such as a silicon or glass core substrate).

[0037] The photonic engine 103 may further optionally include one or more electronic phy chips 111 coupled to the SiPho chip 108. The electronic phy chips 111 are generally used to assist in the operations performed by the optical chip. In one embodiment, the electronic phy chips 111 may be operatively connected to the SiPho chip 108 to assist the SiPho chip 108 with various electrical functions. As shown, the electronic phy chips 111 may be mounted on top of the SiPho chip 108 and thus directly connected to the SiPho chip 108. Alternatively, the electronic phy chips 111 may be embedded in the PGL substrate 106 and connected to the SiPho chip 108 through the PGL substrate 106 (generally referred to herein simply as the substrate 106). Additionally, the electronic phy chips 111 may be mounted on or embedded in the package substrate 101 and connected to the SiPho chip 108 through the electrical interconnect 104.

[0038] Figures 2A and 2B are top views of a photonic engine 103 according to an embodiment. In some embodiments, as shown in Figure 2A, the photonic engine 103 includes: a SiPho chip 108 mounted near one end of the PGL substrate 106, a fiber optic connector 112 connected to the opposite end of the PGL substrate 106 from the SiPho chip 108, and a plurality of optical structures 1101-110 extending between the SiPho chip 108 and the fiber optic connector 112N 。In an embodiment, each of the plurality of optical structures 1101-110 N includes an optical transmission region for transmitting light in either direction between the first interface 107 and the second interface 109. The light transmitted through the optical structure can be received from one or more of the plurality of waveguides 108A (Figure 2B) of the SiPho chip 108, or from one or more of the plurality of optical fibers within the fiber optic connector 112, with which the optical signal source communicates during use. The SiPho chip 108 is typically configured to receive (e.g., detect) the light transmitted through the optical structures 1101-110 N and also to emit (e.g., transmit) light to the optical structures 1101-110 N to complete communication with external components connected via the fiber optic connector 112. The SiPho chip 108 can be configured to transmit light to the optical structures 1101-110 N by at least using an optical transmitter integrated into the SiPho chip 108, or by using an optical transmitter external to the PGL substrate 106. In the case where the optical transmitter is external to the PGL substrate 106, the light is transmitted through the optical structures 1101-110 N to the SiPho chip 108 and then modulated by the SiPho chip 108 to generate a transmission signal provided to the optical structures 1101-110 N .

[0039] In some embodiments that can be combined with other embodiments described herein, the plurality of optical structures 1101-110 N are formed on the PGL substrate 106 (e.g., directly or indirectly) or integrated with the PGL substrate. Each of the plurality of optical structures 1101-110 N in the photon engine 103 can be formed by one of the various methods described herein.

[0040] In one embodiment that can be combined with other embodiments described herein, the optical transmission regions within each of the plurality 1101-110 N can have the same cross-sectional dimensions, such as height and width. In another embodiment that can be combined with other embodiments described herein, the optical transmission region within at least one of the plurality of optical structures 1101-110 N can have at least one cross-sectional dimension different from that of the other optical structures 110 within the PGL substrate 106, such as one of height and width. In one embodiment that can be combined with other embodiments described herein, the plurality of optical structures 1101-110 NThe light transmission region within each of the PGL substrate 106 may have the same refractive index. In another embodiment that may be combined with other embodiments described herein, when the plurality of optical structures 1101-110 N When compared with the remaining optical structures in the N The light transmission area within at least one of the two may have a different refractive index or multiple different refractive indexes or a gradual gradient of the refractive index or other refractive index change structure.

[0041] In one aspect, the optical structures 1101-110 formed in the PGL substrate 106 N The number of interconnects 104 depends on the number of waveguides 108A that need to be connected in the SiPho chip 108, which may also correspond to the number of fiber connections that need to be connected to the optoelectronic chip 102. In one embodiment, the optoelectronic chip 102 may include seventy-two (72) fiber connections so that seventy-two (72) corresponding interconnects 104 extend from the optoelectronic chip 102 and connect to the seventy-two (72) corresponding optical fibers and waveguides 108A in the SiPho chip 108 of the photonic engine 103. In order to pass through the plurality of optical structures 1101-110 in the photonic glass layer substrate 106 N The SiPho chip 108 is appropriately connected to the fiber optic connector 112, and seventy-two (72) corresponding optical structures 110 are formed on the PGL substrate 106 or integrated with the PGL substrate 106. In the example, N as shown in Figures 2A and 2B will be equal to 72, and thus the optical structures 110 are spaced from one edge of the PGL substrate 106 to the other edge of the PGL substrate in the XY plane. In this example, the optical structure 1101 is located near the top edge of Figure 2A, and the optical structures 110 72 will be located closest to the bottom edge of FIG. 2A. As discussed further below, optical structures 1101-110 N The optical structures 1101-110 are separated and spaced apart by a material having N The light transmitting portion has different optical properties (such as refractive index (n)).

[0042] Multiple optical structures 1101-110 NTypically resized and configured to be properly coupled to a plurality of waveguides 108A within the SiPho chip 108. In one embodiment, the plurality of waveguides 108A (Figure 2B) at the output of the SiPho chip 108 or at a portion communicating with the optical structure have a core with a height dimension of approximately 1 micrometer (μm) of the cross-sectional size. In one configuration, the output of the SiPho chip 108 has a square or rectangular cross-section having at least one dimension with a length equal to approximately 1 μm. For example, the square cross-section of the waveguide 108A may have a core with a height and width of 1 μm. Thus, the light transmitted to and from the SiPho chip 108 will be transmitted through the 1-micrometer waveguides 108A.

[0043] Conversely, the light transmitted to and from the fiber optic cable 120 through the fiber optic connector 112 may have different profile dimensions, such as a core cross-sectional dimension of approximately 9 μm. For example, the fiber optic connector 112 may have a square, rectangular, or circular cross-section with a height dimension of the core of approximately 9 μm. Thus, in some embodiments, each of the plurality of optical structures 1101-110 N is formed such that the light propagating through the plurality of optical structures 1101-110 between the SiPho chip 108 and the fiber optic cable 120 N is correspondingly expanded or compressed depending on the propagation direction of the optical signal. In one example, the plurality of optical structures 1101-110 extending from the second interface 109 adjacent to the 9-mm fiber in the fiber optic connector 112 N has a transmission region with a cross-sectional area that varies at different portions of each structure to facilitate coupling to the plurality of 1-micrometer waveguides 108A in the SiPho chip 108. In one embodiment, the plurality of optical structures 1101-110 N taper from a core size of 9 μm along at least a portion of their length until they approach a core size of 1 μm near the first interface 107, where it is assumed that the varying core size is related to the dimensions of the sides of the optical structure 110 with a square or rectangular cross-sectional shape. In some embodiments, the tapered optical structure 110 has a cross-sectional area ratio that may be greater than 1:1 and less than approximately 1:100, or less than 1:81, when measured at one end of the optical structure 110 compared to the other end. In another embodiment, the plurality of optical structures 1101-110 extending from the second interface 109 adjacent to the fiber optic connector 112 N has a varying refractive index along at least a portion of their length from the second interface 109 to the first interface 107 to facilitate coupling between the optical elements within the SiPho chip 108 and the fiber optic connector 112 with different cross-sectional dimensions.

[0044] In another aspect, the photon engine 103 is configured such that the transmission loss of the optical signal between the first interface 107 and the second interface 109 is approximately or less than 3 dB, including the loss caused by the transmission of the optical signal through the plurality of optical structures 1101-110 N itself. In one embodiment, the transmission loss can largely depend on the coupling at the first interface 107 between the SiPho chip 108 and the plurality of optical structures 1101-110 N As shown in FIG. 2B, in an embodiment, the SiPho chip 108 is mounted on the coupling surface 208 at the chip mounting area 204 of the PGL substrate 106. When mounted on the chip mounting area 204, the plurality of waveguides 108A disposed on the side surface 108B of the SiPho chip 108 are aligned with the plurality of optical structures 1101-110 N visible at the first interface 107.

[0045] In some embodiments that can be combined with other embodiments described herein, the PGL substrate 106 further includes one or more fiducial marks 206 to assist in the alignment and mounting of the SiPho chip 108 on the chip mounting area 204. The one or more fiducial marks 206 operate to guide and assist in aligning the position of the SiPho chip 108 along the X-Y plane of the PGL substrate 106 to ensure that the mounting of the SiPho chip 108 is correctly aligned with one or more electrical contacts (e.g., vias 1006( Figure 10 )) and the optical structure portion of the PGL substrate 106. In view of this, in an embodiment, the error tolerance (to be further discussed below) for coupling or hybridizing the SiPho chip 108 with the plurality of optical structures 1101-110 N together at the first interface 107 can be in the range of 0.1 micron to 2 microns to ensure an optimized connection and achieve the lowest signal loss. In one embodiment, the misalignment of the waveguides 108A with the centers of the optical structures 1101-110 N is maintained such that the lateral misalignment in the Y direction (i.e., the top-to-bottom direction in FIG. 2B) is less than 1 to 2 microns. In some embodiments, the misalignment of the waveguides 108A with the centers of the optical structures 1101-110 N is also maintained such that the misalignment in the Z direction ( Figure 10 or Figure 11) The vertical misalignment on [is] less than 1 to 2 microns. In one embodiment, the variability of the vertical misalignment can depend on the variability of the compression of a plurality of solder balls 1010 or other electrical contacts used to electrically couple the SiPho chip 108 to a plurality of vias 1006 formed in a portion of the PGL substrate 106 ( Figures 10 to 11 ).

[0046] Figure 6 FIGURES 3A - 3E illustrate an exemplary method 600 of operations for fabricating a portion 300 of a PGL substrate 106, such as a portion of an optical structure 1101 - 110 N . A flowchart of the operations of method 600 includes operations 602 - 618. In one embodiment, method 600 is a single substrate process or a batch process involving multiple substrates fabricated simultaneously. At operation 602, as shown in FIGURE 3A, a cladding layer 303 is disposed on the surface of a support substrate 301. The cladding layer 303 can be disposed above the surface using the following processes: liquid material pouring process, spin coating process, liquid spraying process, dry powder coating process, screen printing process, blade coating process, physical vapor deposition process, chemical vapor deposition process, plasma enhanced chemical vapor deposition (PECVD) process, flowable chemical vapor deposition (FCVD) process, atomic layer deposition process, or evaporation process. In one embodiment, the cladding layer 303 is made of a material having a refractive index that is relatively low compared to the refractive index of the core material layer 302 formed in a subsequent operation. In some embodiments, the cladding layer 303 has a refractive index between 1.3 and 1.5. In some embodiments, the cladding layer 303 used in operation 602 can be formed from one or more low refractive index materials, including Si3N4, SiO2, doped SiO2, low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials.

[0047] At operation 604, as shown in FIG. 3A, the core material layer 302 is disposed on the surface of the cladding layer 303 and the support substrate 301. The core material layer 302 can be disposed above the surface of the cladding layer 303 using a liquid material casting process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ALD process, or an evaporation process. In some embodiments, the support substrate 301 comprises a material selected from the group consisting of silicon dioxide (SiO2), boron trioxide (B2O3), and aluminum oxide (Al2O3).

[0048] Depending on the embodiment, the core material layer 302 can be a low refractive index material or a high refractive index material. The material used to form the core material layer 302 has a refractive index different from that of the material used to form the cladding layer 303. In some embodiments, the core material layer 302 has a refractive index between 1.4 and 1.5. In another embodiment, the material used to form the core material layer 302 has a refractive index higher than that of the material used to form the cladding layer 303. Generally, the refractive index of the core material layer 302 is different from that of the cladding layer 303 and is also different from that of the encapsulation layer 314 discussed further below. In one example, the core material layer 302 has a refractive index between 1.45 and 1.50, while the cladding layer 303 and the encapsulation layer 314 have a refractive index between 1.40 and 1.44.

[0049] In an embodiment that can be combined with other embodiments described herein, the core material layer 302 can be formed of one or more materials including, but not limited to: silicon carbide (SiC)-containing materials, silicon oxycarbide (SiOC)-containing materials, titanium dioxide (TiO2)-containing materials, silicon dioxide (SiO2)-containing materials, vanadium(IV) oxide (VO x )-containing materials, aluminum oxide (Al2O3)-containing materials, aluminum-doped zinc oxide (AZO)-containing materials, indium tin oxide (ITO)-containing materials, tin dioxide (SnO2)-containing materials, zinc oxide (ZnO)-containing materials, tantalum pentoxide (Ta2O5)-containing materials, silicon nitride (Si3N4)-containing materials, zirconium dioxide (ZrO2)-containing materials, niobium pentoxide (Nb2O5)-containing materials, cadmium stannate (Cd2SnO4)-containing materials, silicon nitride (SiN)-containing materials, silicon oxynitride (SiON)-containing materials, barium titanate (BaTiO3)-containing materials, diamond-like carbon (DLC)-containing materials, hafnium(IV) oxide (HfO2)-containing materials, lithium niobate (LiNbO3)-containing materials, silicon carbonitride (SiCN)-containing materials, or other materials suitable for forming optical structures.

[0050] At operation 606, the patterned layer 305 is disposed on the core material layer 302. The patterned layer 305 defines an exposed negative portion of the core material layer 302 that, when removed, corresponds to a structural pattern that will enable the formation of the optical structure 110 in a subsequent operation.

[0051] In an embodiment, as Figure 3B and 3C shown and further described in detail in operations 608 to 612 below, disposing the patterned layer 305 on the core material layer 302 may include disposing a hard mask 304 on the core material layer 302, disposing a patterned photoresist 306 on the hard mask 302, the patterned photoresist 306 defining an exposed portion of the hard mask 304, and removing the exposed portion of the hard mask 304 to form a patterned hard mask 304 corresponding to the patterned photoresist 306.

[0052] In another embodiment, disposing the patterned layer 305 on the core material layer 302 at operation 606 may include: forming a patterned photoresist on the core material layer 302 by disposing a photoresist layer on the core material layer 302 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines an exposed negative portion of the core material layer 302. The patterned photoresist will allow selective etching of the core material layer 302 beneath the patterned photoresist because the patterned photoresist protects certain regions of the core material layer 302 from unwanted etching in subsequent processes. In such embodiments, method 600 continues with operation 614 below to remove the negative structure portion 312 of the core material layer 302 defined by the patterned layer 305.

[0053] At operation 608, as shown in FIG. 3B, the hard mask 304 is disposed on the core material layer 302. The hard mask 304 may be disposed above the core material layer 302 using a liquid material pouring process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade coating process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ADL process, or an evaporation process. The hard mask 304 may include, but is not limited to: materials selected from the group consisting of chromium (Cr)-containing materials, silver (Ag)-containing materials, Si3N4-containing materials, SiO2-containing materials, TiN-containing materials, and carbon (C)-containing materials.

[0054] At operation 610, as shown in FIG. 3B, a patterned photoresist 306 is disposed over the core material layer 302 and, when present, also over the hard mask 304. The patterned photoresist 306 allows for selective etching of the material below the patterned photoresist 306, as the patterned photoresist 306 protects certain regions from unwanted etching in subsequent processes. In one example, the patterned photoresist 306 is formed by disposing a photoresist material over the hard mask 304 and performing a photolithography process to pattern and develop the photoresist material. The patterned photoresist 306 defines an exposed portion 310 of the hard mask 304 (i.e., an opening in the hard mask 304). The exposed portion 310 corresponds to the pattern 308 that will be used to form the optical structure 110. The patterned photoresist 306 can be disposed over the hard mask 304 or the core material layer 302 using a spin coating process. The photoresist material 306 can include, but is not limited to, a photosensitive polymer material.

[0055] At operation 612, as shown in FIG. 3C, the exposed portion 310 of the hard mask 304 is removed. Removing the hard mask portion 310 exposes a negative structure portion 312 of the core material layer 302. The negative structure portion 312 corresponds to the structural pattern 308 that will enable the formation of the optical structure 110 in subsequent operations. In one embodiment, the exposed portion 310 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of openings in the hard mask 304.

[0056] At operation 614, as shown in FIG. 3C, the negative structure portion 312 of the core material layer 302 is removed to form a plurality of optical structures 110. In one embodiment, which can be combined with other embodiments described herein, the negative structure portion 312 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of trenches 316 in the core material layer 302. In an embodiment, the removal of the exposed portion 310 in operation 612 and the etching of the negative structure portion 312 in operation 614 can be performed simultaneously or sequentially. In one aspect, the hard mask 304 has a lower etching rate than the material of the core material layer 302.

[0057] At operation 616, the patterned layer 305 is removed. Removing the patterned layer 305 includes removing the hard mask and / or the photoresist layer. In the example shown in FIG. 3D, removing the patterned layer 305 includes removing the hard mask 304 and the patterned photoresist 306. Removing the hard mask 304 can include ion etching, reactive ion etching, or selective wet chemical etching. Removing the patterned photoresist 306 can include using an ashing process or an etching process as described herein.

[0058] At operation 618, as shown in FIG. 3E, an encapsulation layer is disposed over the cladding layer 303 and the plurality of optical structures 110. The encapsulation layer 314 may be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 314 is made of a material having a refractive index that is relatively low compared to the refractive index of the core material layer 302. In some embodiments, the refractive index of the encapsulation layer 314 is between 1.3 and 1.5, such as between 1.40 and 1.44. In some embodiments, more than one encapsulation layer having more than one refractive index may be used.

[0059] In an embodiment that may be combined with other embodiments herein, the encapsulation layer 314 may be formed of one or more low refractive index materials, including Si3N4, SiO2, doped SiO2, low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials. The material used to form the encapsulation layer 314 has a refractive index different from the refractive index of the material used to form the core material layer 302. In one embodiment, the refractive index of the material used to form the encapsulation layer 314 is lower than the refractive index of the material used to form the core material layer 302. The low refractive index materials discussed herein are contrasted with "high" refractive index materials such as amorphous and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials having suitable optical properties. It is contemplated that materials and combinations of materials may be used to form the cladding layer 303, the encapsulation layer 314, and / or the core material layer 302 discussed herein, and these materials may be selected based on the target optical properties of the optical element being fabricated in method 600.

[0060] In another embodiment that may be combined with other embodiments herein, the encapsulation layer 314 may be formed to include an interlayer (not shown) that extends over the top surface of the encapsulation layer 314. The interlayer may be used to separate the encapsulation layer 314 and the optical structures formed by the core material layer 302 from additional optical structures of a second optical structure material layer (not shown). Thus, additional different optical layer optical structures may be formed and layered on top of the portion 300 shown in FIG. 3E without directly contacting the optical structures 110 or the encapsulation layer 314. Additionally, the lower the refractive index of the material used for encapsulation, the lower the aspect ratio of the constituent nanostructures (patterned features) of each optical structure. In one embodiment, lower aspect ratio features result in thinner optical layers, as well as faster and cleaner etching. Thus, the systems and methods herein result in a more efficient manufacturing process in terms of time, cost, and complexity.

[0061] Although the optical structures 110 shown in FIGS. 3A - 3E herein are illustrated as having a generally square or rectangular cross - section, it is contemplated that in other instances, the optical structures may include tapered sidewalls and thus form a trapezoidal cross - section (not shown). In one example, the trapezoidal cross - section is wider near the top of the opening than at the bottom.

[0062] Accordingly, method 600 can be used to form the optical structures 1101 - 110 by using a negative pattering process N , where the optical structures 1101 - 110 N include the remaining portion of the core material layer 302. As illustrated in FIG. 3E, the PGL substrate 106 includes seven optical structures (i.e., optical structures 1101 - 1107), which are disposed on the support substrate 301, and each optical structure is encapsulated and separated by at least a portion of the encapsulation layer 314.

[0063] Figure 7 To illustrate an operation of another exemplary method 700 for manufacturing a portion 400 of the PGL substrate 106 (as shown in FIGS. 4A - 4F), such as a portion of the optical structures 1101 - 110 N . A flowchart of the operations of method 700 is shown. Method 700 includes operations 702 - 718. Method 700 begins at operation 702, where a patterning layer 405 is disposed on a support substrate 401. The patterning layer 405 defines an exposed negative portion of the support substrate 401 that, when removed, corresponds to a structural pattern that will enable the formation of the optical structures 110 in subsequent operations.

[0064] In an embodiment, as Figure 4B and Figure 4C shown and further described in detail in operations 704 - 708 below, disposing the patterning layer 405 on the support substrate 401 may include disposing a hard mask 402 on the support substrate 401; disposing a patterned photoresist 404 on the hard mask 402, where the patterned photoresist 404 defines an exposed portion of the hard mask 402; and removing the exposed portion of the hard mask 402 to form a patterned hard mask 402 corresponding to the patterned photoresist 404.

[0065] In another embodiment, setting the patterned layer 405 on the support substrate 401 in operation 702 may include setting a patterned photoresist directly above the support substrate 401, or setting a photoresist layer on the support substrate 401 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist defines an exposed negative portion of the support substrate 401. The patterned photoresist may allow selective etching of the support substrate 401 below the patterned photoresist, as the patterned photoresist protects certain regions of the support substrate 401 from unwanted etching in subsequent processes. In such an embodiment, method 600 proceeds to operation 710 below to remove the negative structural portion 410 of the support substrate 401 defined by the patterned layer 405.

[0066] At operation 704, as Figure 4A shown, a hard mask 402 is set on the support substrate 401. The hard mask 402 may be set above the support substrate 401 using a liquid material pouring process, a spin coating process, a liquid spraying process, a dry powder coating process, a screen printing process, a blade scraping process, a PVD process, a CVD process, a PECVD process, an FCVD process, an ADL process, or an evaporation process. The hard mask 304 may include, but is not limited to: materials selected from the group consisting of chromium (Cr)-containing materials, silver (Ag)-containing materials, Si3N4-containing materials, SiO2-containing materials, TiN-containing materials, and carbon (C)-containing materials. In some embodiments, the support substrate 401 includes a material selected from the group consisting of silicon dioxide (SiO2), boron trioxide (B2O3), and aluminum oxide (Al2O3).

[0067] At operation 706, a patterned photoresist 404 is set above the support substrate 401 and, when present, is also set above the hard mask 402, as Figure 4B shown. The patterned photoresist 404 allows selective etching of the material below the patterned photoresist 404, as the patterned photoresist 404 protects certain regions from unwanted etching in subsequent processes. In one example, the patterned photoresist 404 is formed by setting a photoresist material on the hard mask 402 and performing a lithography process to pattern and develop the photoresist material. The patterned photoresist 404 defines an exposed portion 408 of the hard mask 402 (i.e., an opening of the hard mask 402). The exposed portion 408 corresponds to the structural pattern 406 to result in the formation of a plurality of optical structures 110. In one example, the patterned photoresist 404 may be set on the hard mask 402 using a spin coating process. The photoresist material 404 may include, but is not limited to, a photosensitive polymer material.

[0068] At operation 708, as Figure 4CAs shown, the exposed portion 408 of the hard mask 402 can be removed. Removing the exposed portion 408 exposes the negative structure portion 410 of the support substrate 401. The negative structure portion 410 corresponds to the structural pattern 406 to result in the formation of the optical structure 110. In one embodiment, the exposed portion 408 is removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of openings in the hard mask 402.

[0069] At operation 710, as Figure 4C shown, the negative structure portion 410 of the support structure 401 is removed to form the patterned structure 406. In an embodiment that can be combined with other embodiments described herein, the negative structure portion 410 of the support substrate 401 can be removed by an ion etching, reactive ion etching, or selective wet chemical etching process to form a plurality of trenches 412 in the support substrate 401. In an embodiment, the removal of the exposed portion 408 in operation 708 and the removal of the portion of the support substrate 401 in operation 712 can be performed simultaneously or sequentially. In one aspect, the hard mask 402 has a lower etching rate than the material of the support substrate 401.

[0070] At operation 712, the patterned layer 405 is removed. Removing the patterned layer 405 can include removing the hard mask and / or the photoresist layer. In Figure 4D the example shown, removing the patterned layer 405 includes removing the hard mask 402 and the patterned photoresist 404, thereby leaving the support substrate 401 having a plurality of patterned structures 406, each patterned structure 406 separated by a plurality of trenches 412. In one embodiment, removing the hard mask 402 can include ion etching, RIE, or selective wet chemical etching. Removing the patterned photoresist 404 can include a conventional ashing process or an etching process.

[0071] At operation 714, as Figure 4E shown, a filling layer 418 is disposed over the support substrate 401 and the patterned structures 406 formed in the support substrate 401. The filling layer 418 can include, but is not limited to: materials selected from the group consisting of Si3N4, SiO2, low refractive index fluoropolymers, hydrogels, and photoresist-containing materials. The filling layer 418 can be disposed over the support substrate 401 and into the plurality of trenches 412 by one or more of PVD, CVD, FCVD, and spin coating processes. The flowable nature of the filling layer 418 allows the filling layer 418 to also flow into each of the plurality of trenches 412.

[0072] In one embodiment, the fill layer 418 is formed of a material having a refractive index different from that of the PGL substrate 106 in the support substrate 401. In some embodiments, the fill layer 418 has a refractive index between 1.4 and 1.5. In another embodiment, the fill layer 418 is formed of a material having a refractive index greater than that of the support substrate 401. In certain embodiments, the fill layer 418 may be formed of a high refractive index material such as amorphous silicon and crystalline silicon, silicon nitride, titanium dioxide, gallium phosphide, tantalum pentoxide, gallium nitride, sulfur-containing materials, polymers, and other materials having suitable optical properties. It is contemplated that materials and combinations of materials may be used to form the fill layer 418 described herein, and these materials may be selected based on the target optical properties of the optical element fabricated in method 700. In one example, the fill layer 418 has a refractive index between 1.45 and 1.50, while the support substrate 401 has a smaller refractive index between 1.40 and 1.44.

[0073] At operation 716, as Figure 4F shown, the excess fill layer portion 418A is removed such that the height of the fill layer 418 within the plurality of trenches 412 is approximately the same as the height of the patterned structure 406 of the support substrate 401. According to one embodiment, the excess fill layer 418A may be removed using a chemical mechanical polishing (CMP) process. Removal of the excess fill layer 418 forms a plurality of optical structures 110 separated by the patterned structure 406 in the substrate 401.

[0074] Although the optical structures 110 shown herein Figures 4A to 4F are illustrated as having a generally square or rectangular cross-section, it is contemplated that in other instances, the optical structures may include tapered sidewalls and thus form a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top of the opening than at the bottom.

[0075] At operation 718, as Figure 4G shown, an encapsulation layer 420 is optionally disposed over the support substrate 401 and the plurality of optical structures 110. The encapsulation layer 420 may be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 420 is made of a low refractive index material compared to the refractive index of the fill layer 418. In some embodiments, the refractive index of the encapsulation layer 420 is between 1.3 and 1.9, such as between 1.40 and 1.44.

[0076] Thus, method 700 can be used to form the optical structures 1101-110 N by using a negative patterning process, the optical structures 1101-110 NIncludes the remainder of the fill layer 418. As Figure 4F and 4G shown, the PGL substrate 106 includes seven optical structures (i.e., optical structures 1101-1107), the optical structures including portions of the fill layer 418 disposed within and thus separated by portions of the support substrate 401.

[0077] Figure 8 To illustrate an exemplary method 800 of operations for fabricating a portion 500 of the PGL substrate 106 (as shown in FIGS. 5A-5E), such as a portion of the optical structures 1101-110 N is a flowchart of the operations of an exemplary method 800. Method 800 includes operations 802 to 808. Method 800 provides for depositing a species of refractive-index-changing material into a portion of a support substrate 501 by an ion implantation process. Ion implantation is a surface modification technique that can change the optical properties of a surface layer of a portion of the support substrate 501. Ion implantation allows precise control of the dopant composition and penetration depth by selecting the species and energy of the dopant ions. In some embodiments, the support substrate 501 includes a material selected from the group consisting of silicon dioxide (SiO2), boron trioxide (B2O3), and aluminum oxide (Al2O3).

[0078] At operation 802, as shown in FIG. 5A, a patterned layer 502 is disposed on the support substrate 501. The patterned layer 502 defines an exposed substrate portion 504 of the support substrate 501 (i.e., the opening of the patterned layer 502). The patterned layer 502 is configured to allow selective implantation of dopant ions into the support substrate 501 disposed below the patterned layer 502, since portions of the patterned layer 502 can act as a mask to impede dopant ions from reaching selected portions of the support substrate 501 below the patterned layer 502.

[0079] The patterned layer 502 can be a patterned photoresist or a patterned hard mask. In one embodiment, the patterned layer 502 can be a patterned photoresist formed of a material including, but not limited to, a polymeric material such as formed from a phenolic resin, an epoxy resin, or an acrylic resin. The patterned photoresist must be thick enough to reliably absorb the ions at the sites. Therefore, it is generally necessary to appropriately select the resist film thickness when adjusting the ion energy of the implantation process. In one example, the patterned layer 502 can be formed by disposing a photoresist material on the substrate 501 and performing a lithography process to pattern and develop the photoresist material. In another embodiment, the patterned layer 502 can be a patterned hard mask. The hard mask can include, but is not limited to: materials selected from the group consisting of chromium (Cr)-containing materials, silver (Ag)-containing materials, Si3N4-containing materials, SiO2-containing materials, TiN-containing materials, and carbon (C)-containing materials.

[0080] At operation 804, as shown in FIG. 5B, an ion implantation process is performed on the support substrate 501. In the ion implantation process, dopant ions are accelerated and implanted into the support substrate 501 through the openings in the patterned layer 502. The dopant ions will include dopant materials that will change the refractive index of the implantation regions located within the openings in the patterned layer 502, and may include at least one of Al, P, F, Cl, P, or the gases N, Ar, or Kr. As described herein, the dopant ions provided in the ion implantation process are generated by a plasma formed by applying a high voltage radio frequency (RF) to the processing region of a plasma process chamber. Subsequently, the plasma-dissociated ions are biased towards the surface of the substrate 106 and implanted to a certain desired depth from the substrate surface. Once implanted, the dopant ions combine with portions of the materials in the support substrate 501 and cause a change in the refractive index in the portions of the PGL substrate 106. In one embodiment, when the ion implantation process is performed within method 800, the support substrate 501 is placed on a substrate support pedestal of a plasma processing chamber, and gas flows into the interior of the plasma process chamber and is ignited to generate a plasma. Subsequently, a bias voltage is applied to the support substrate 501 to accelerate the dopant ions generated in the plasma towards the surface of the support substrate 501. As a result of the plasma and the bias of the support substrate 501, the dopant ions generated in the plasma are implanted into the support substrate 501 to form a part of the support substrate 501. An example of an ion implantation apparatus is the Varian Trident, which is available from Applied Materials, Inc. of Santa Clara, California.

[0081] In an embodiment, as shown in FIG. 5C, the ion implantation process employed in operation 804 modifies the exposed substrate portion 504 of the support substrate 501 to form a plurality of optical structures 110. On the other hand, the substrate region 512 protected by the patterned layer 502 is not modified by the ion implantation process. In one aspect, the modification by ion implantation depends on the ions (light ions or heavy ions) implanted in the PGL substrate 106. The ions implanted in the exposed portion 504 of the PGL substrate 106 may be modified to have an increase in refractive index or a decrease in refractive index. In one embodiment, the optical structures 110 formed by the ion implantation process have a higher refractive index than the refractive indices of the PGL support substrate 501 and the protection region 512.

[0082] At operation 806, as shown in Figure 5E, the patterned layer 502 is removed to form the substrate 106, which includes the support substrate 501 having alternating optical structures 110 and substrate regions 512 formed therein. Removing the patterned layer 502 may include removing a patterned hard mask or a patterned photoresist. Removing the patterned hard mask may include ion etching, reactive ion etching, or selective wet chemical etching. Removing the patterned photoresist may include using the ashing process or etching process described herein.

[0083] In some embodiments, it may be desirable to perform an annealing process on the PGL substrate of the substrate 501 to activate dopant species and remove any damage generated in the optical structures 110 by the implantation process, and / or to better distribute the refractive index-changing dopant material implanted during operation 804 of method 800.

[0084] Although the optical structures 110 shown in Figures 5A - 5E herein are illustrated as having a generally square or rectangular cross-section, it is contemplated that in other instances, the optical structures may include tapered sidewalls and thus form a trapezoidal cross-section (not shown). In one example, the trapezoidal cross-section is wider near the top of the opening than at the bottom.

[0085] At operation 808, as shown in Figure 5E, the encapsulation layer 520 is optionally disposed on the substrate 501 and the plurality of optical structures 110. The encapsulation layer 520 can be formed by using one or more of PVD, CVD, FCVD, and spin coating processes. In one embodiment, the encapsulation layer 520 is made of a low refractive index material having a refractive index lower than that of the implanted portion of the support substrate 501. In some embodiments, the refractive index of the encapsulation layer 520 is between 1.3 and 1.9, such as between 1.40 and 1.44.

[0086] Thus, method 800 can be used to form the optical structures 1101 - 110 N , the optical structures 1101 - 110 N including the implanted portion of the support substrate 501. As shown in Figure 5E, the PGL substrate 106 includes seven optical structures (i.e., optical structures 1101 - 1107), which include exposed portions 504 formed within the support substrate 401.

[0087] Figure 9 For one embodiment, a schematic cross-sectional view of a portion of the photon engine 103 mounted on the package substrate 101 formed by using the cross-sectional line C - C in Figure 10 . As Figure 9As shown, the photon engine 103 includes the bottom surface 106A of a photon glass layer substrate 106 disposed on the top surface 101A of a package substrate 101, where multiple optical structures 1101 - 110 N extend through the PGL substrate 106. In the illustrated embodiment, the multiple optical structures 1101 - 110 extending through the PGL substrate 106 N are each aligned in the X - Z plane of the PGL substrate 106. Although Figure 9 shown as forming a single column in a plane across the PGL substrate 106, multiple optical structures 1101 - 110 may also be formed in other arrangements in the PGL substrate 106 N . For example, more than a single column of optical structures may be formed and vertically stacked. The stacked columns of optical structures may be formed by one or more processes described herein, such as the methods described with respect to N . The arrangement of the multiple optical structures 1101 - 110 Figures 3A to 8 is not intended to limit the scope of the disclosure provided herein. N

[0088] Figure 10 FIG. 2A is a schematic cross - sectional side view of a portion of the photon engine 103 mounted on the package substrate 101 formed by using the section line B - B in FIG. 2. As shown, the package substrate 101 includes multiple circuit traces 1002 that extend from multiple corresponding interconnect pads 1004 integrally formed in the top surface 101A of the package substrate 101. In an embodiment, the multiple circuit traces 1002 form an interconnect 104 that electrically connects the photon engine 103 in contact with the multiple interconnect pads 1004 to an electrical or optoelectronic chip 102. Alternatively, the multiple circuit traces 1002 may electrically connect the photon engine 103 in contact with the multiple interconnect pads 1004 to other integrated circuits disposed on the package substrate 101.

[0089] In some embodiments, multiple vias 1006 extend through a portion of the PGL substrate 106 between the coupling surface 208 and the bottom surface 106A of the PGL substrate 106. In an embodiment, when the photon engine 103 is mounted to the package substrate 101, the multiple vias 1006 are aligned with corresponding interconnect pads 1004 and placed in electrical contact with the corresponding interconnect pads 1004, and the corresponding interconnect pads 1004 are exposed on the top surface 101A of the package substrate 101 and electrically connected to the photon engine 103 through the multiple circuit traces 1002 formed in the package substrate 101. In another embodiment, the multiple vias 1006 may alternatively connect the photon engine 103 to one or more other integrated circuits (chips) embedded in or on the package substrate 101.​

[0090] As Figure 10 shown, the SiPho chip 108 can be actively or passively mounted on the coupling surface 208 of the PGL substrate 106, where the side surface 108B of the SiPho chip 108 is "butt-coupled" to the end face 106B of the PGL substrate 106 at the first interface 107. When the SiPho chip 108 is butt-coupled to the end face 106B of the PGL substrate 106, the end of the waveguide 108A in the SiPho chip 108 is also butt-coupled to the corresponding end of the optical structure 110 (such as the optical structure 1103) formed in the PGL substrate 106 at the fourth coupling interface 1008. The coupling of the multiple waveguides 108A to the multiple optical structures 110 at the fourth interface 1008 may affect the loss of optical signals between the SiPho chip 108 and the PGL substrate 106. In view of this, in order to minimize the coupling loss, one or more of the above-mentioned fiducial marks 206 (Figure 2B) are used during the installation of the SiPho chip 108 to assist in aligning and precisely placing the SiPho chip 108, thereby optimizing the butt-coupling of the multiple waveguides 108A and the multiple optical structures 1101-110 N and minimizing the coupling loss.

[0091] To connect the SiPho chip 108 to the PGL substrate 106, the SiPho chip 108 further includes a plurality of solder connections 1012 that contact a plurality of solder balls 1010, where the plurality of solder balls 1010 are positioned between the plurality of solder connections 1012 and the ends of the respective plurality of vias 1006 on the coupling surface 208. The plurality of solder balls 1010 electrically connect the SiPho chip 108 to the plurality of vias 1006 formed in the photonic glass layer substrate 106. In an embodiment, a plurality of solder balls or other interconnect bumps, posts, or interconnect materials 1010 including planar hybrid bonding techniques can be used to connect the plurality of solder connections 1012 to the plurality of vias 1006 that extend through the PGL substrate 106 to the substrate 101. In the shown embodiment, the plurality of solder balls 1010 and the plurality of vias 1006 connect the plurality of solder connections 1012 to the plurality of interconnect pads 1004 in the substrate 101, thereby electrically connecting the SiPho chip 108 to the plurality of circuit traces 1002 in the package substrate 101 that are connected to the plurality of interconnect pads 1004.

[0092] In an embodiment, the coupling surface 208 of the PGL substrate 106 may further include a plurality of recesses (not shown) for supporting the respective plurality of solder balls 1010 that connect the plurality of solder joints 1012 in the SiPho chip 108 and the plurality of vias 1006 in the PGL substrate 106. The plurality of recesses may be formed to allow the plurality of solder balls 1010 to expand when planarized, such that the contact surfaces of the plurality of solder balls 1010 may be substantially flush with the coupling surface 208. When contacting the solder joints 1012 in the SiPho chip 108, the planarization of the plurality of solder balls 1010 on the coupling surface 208 helps to ensure the uniformity of mounting the SiPho chip 108 on the PGL substrate 106 and increases the contact reliability of the solder balls 1010.

[0093] Figure 10 Also included is a cross-sectional view of a portion of the fiber optic connector 112 according to an embodiment, the portion being coupled to a portion of the PGL substrate 106 at the interface 109. In the configuration, the fiber optic connector 112 may be removably connected to a portion of the photon engine 103 to allow optical signals to be transmitted to and received from the optical structure 110 by using a "butt-coupling" connection configuration.

[0094] Figure 11 is a schematic cross-sectional side view of a portion of the photon engine 103 mounted on the package substrate 101 according to an alternative embodiment. In the illustrated embodiment, the SiPho chip 108 may be passively mounted on the photon glass layer substrate 106 in the second chip mounting region 1106 of the photon glass layer substrate 106. The second chip mounting region 1106 of the PGL substrate 106 further includes a plurality of optical structures 1101-110 N coupling portions 1102 of each of them, the coupling portions extending along the coupling surface 1104 of the PGL substrate 106. When the SiPho chip 108 is mounted on the second chip mounting region 1106, a portion of the plurality of waveguides 108A in the SiPho chip 108 is evanescently coupled to the surface of the corresponding coupling portions 1102 of each of the plurality of optical structures 1101-110 N Evanescent coupling is achieved when two optical waveguides are positioned closely together such that the evanescent field generated by one waveguide reaches the other waveguide before any substantial attenuation of the evanescent field is experienced. The evanescent coupling of the plurality of waveguides 108A to the plurality of optical structures 110 allows optical signals to be transmitted between the coupled waveguides.

[0095] In an embodiment, the evanescent coupling of the waveguide can be formed as a directional coupler, where the evanescent mode of one waveguide overlaps with the mode of a second waveguide. When the evanescent modes of the waveguides overlap, the evanescent fields generated by each waveguide also overlap such that the evanescent field generated by one waveguide can excite a wave in the other waveguide. In view of this, in one aspect, the coupling strength between the plurality of waveguides 108A and the plurality of optical structures 110 can thus be sensitive to the distance between the waveguide 108A and the optical structure 110 and / or the length of the coupling portion 1102. Accordingly, the coupling portion 1102 of the waveguide 108A and the corresponding contact portions are sized and formed to optimize the coupling and minimize the coupling loss.

[0096] Mounting the SiPho chip 108 on the substrate 106 in the chip mounting region 1106 of the substrate 106 further includes: connecting a plurality of solder connections 1012 in the SiPho chip 108 to a plurality of vias 1006 in the PGL substrate 106 using a plurality of solder balls 1010. The plurality of solder balls 1010 can be positioned on the coupling surface 208 adjacent to the coupling portions 1102 of the plurality of optical structures 1101-110 N and aligned between each corresponding solder connection 1012 and via 1006. The plurality of solder balls 1010 can be sized such that when the plurality of solder balls 1010 are flattened due to contact with the SiPho chip 108 mounted on the PGL substrate 106, the plurality of solder balls 1010 are flattened to a height substantially the same as the height of the coupling portions 1102 of the plurality of optical structures 1101-110 N . In the illustrated embodiment, the plurality of solder balls 1010 in contact with the plurality of vias 1006 and the plurality of interconnect pads 1004 electrically connect the SiPho chip 108 to the plurality of circuit traces 1002 in the package substrate 101. Additionally, one or more pedestal structures 1015 can be used to position, support, and / or assist in aligning the SiPho chip 108 within the chip mounting region 204. In one example, the pedestal structure 1015 ( Figure 10 ) is formed to assist in setting the vertical alignment of the waveguide 108A and the optical structure 110. In some embodiments, as Figure 10 shown, the PGL substrate 106 includes one or more pedestal structures 1015 configured to support the SiPho chip 108 in one direction (e.g., the Z direction), the direction being substantially perpendicular to a plane (e.g., the X-Y plane) parallel to the plane in which the optical structures 1101-110 N extend.

[0097] Figure 12Schematic cross-sectional side view of the fiber optic connector 112 portion of the photon engine 103 according to one embodiment. Generally, the fiber optic connector 112 is used to removably connect an external fiber optic cable 120 to the photon engine 103. A plurality of optical fibers 112A of the fiber optic connector 112 transmit optical signals to and from the fiber optic cable 120 inserted into the fiber optic connector 112. The fiber optic connector 112 is configured to allow attachment of the external optical cable 120 to the optical input / output of the photon engine 103 without actively aligning the fiber optic cable 120 to the photon engine 103 on a per-core basis. Thus, the fiber optic connector 120 can be formed and configured to be interoperable with a variety of different fiber optic cable 120 components and standards.

[0098] As Figure 12 shown, the light transmitted along the plurality of optical fibers 112A is guided by a lens assembly to a plurality of optical structures 1101-110 on the PGL substrate 106 N , for subsequent transmission through the photon engine 103. The lens assembly includes a first lens 112B and a third lens 112C formed on the fiber optic connector 112, and a second lens 1202 formed on the substrate 106. In the illustrated embodiment, the light from the fiber optic cable 120 is transmitted along the optical fiber 112A toward the first lens 112B formed near the end of the optical fiber 112A. The first lens 112B guides the light transmitted along the optical fiber 112A toward the second lens 1202 on the PGL substrate 106. The second lens 1202 on the PGL substrate 106 then reflects and redirects the light back to the third lens 112C on the fiber optic connector 112. The third lens 112C finally reflects the light to and redirects it to the optical structure 110 on the PGL substrate 106 for subsequent transmission through the photon engine 103.

[0099] In summary, the embodiments herein relate to optical silicon photonics components and methods for manufacturing optical silicon photonics components. The methods described herein enable high-volume manufacturing and fabrication of optical silicon photonics components having a plurality of optical structures formed on a photon glass layer substrate. The optical silicon photonics components further include a silicon photonics chip mounted on the photon glass layer substrate and connected to the plurality of optical structures. The plurality of optical structures optically connect the silicon photonics chip to a fiber optic connector configured for connection to an external optical fiber and operative to propagate optical signals between the fiber optic connector and the silicon photonics chip.

[0100] Although the foregoing is directed to embodiments of the present case, other and further embodiments of the present case can be designed without departing from the basic scope of the present case, and the scope of the present case is determined by the appended claims.

Claims

1. A method for manufacturing electronic and photonic components, comprising the following steps: Depositing a core material layer on a surface of a substrate comprising a photonic glass layer (PGL), the photonic glass layer having a first refractive index, wherein the core material layer has a second refractive index different from the first refractive index; Depositing a patterned layer over the core material layer, the patterned layer having openings formed therein, and portions of the surface of the core material layer being exposed in the openings; And Removing portions of the core material exposed within the openings of the patterned layer to form a plurality of optical structures, wherein each of the plurality of optical structures comprises a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each waveguide of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

2. The method according to claim 1, further comprising the following steps: Depositing a cladding layer on the surface of the substrate before depositing the core material layer, the cladding layer having a fourth refractive index different from the second refractive index; Removing the patterned layer after removing the portions of the core material exposed within the openings; And Depositing a packaging layer over the plurality of optical structures, wherein the deposited packaging layer has a third refractive index different from the second refractive index.

3. The method according to claim 2, wherein the step of depositing a patterned layer over the core material layer comprises the steps of: depositing a patterned hard mask or forming a patterned photoresist over the core material layer.

4. The method according to claim 2, wherein the step of depositing a patterned layer over the core material layer comprises the steps of: Depositing a hard mask over the core material layer; Forming a patterned photoresist over the hard mask, the patterned photoresist having openings formed therein, and portions of the hard mask being exposed in the openings; And Removing the exposed portions of the hard mask to expose portions of the core material layer.

5. The method according to claim 2, wherein the packaging layer comprises one or more of the following: Si3N4, SiO2, doped SiO2, low refractive index fluoropolymers, nanoparticle films, hydrogels, porous materials, and photoresist-containing materials.

6. The method according to claim 2, wherein the first refractive index and the third refractive index are lower than the second refractive index.

7. The method according to claim 1, further comprising the following step: forming a chip mounting region on the surface of the photonic glass layer at the first edge of the substrate, wherein the chip mounting region is operable to connect a photonic or electronic integrated circuit to the photonic glass layer substrate.

8. The method according to claim 1 further comprises the step of: forming an optical fiber connector on the surface of the photon glass layer at the second edge of the substrate, wherein the optical fiber connector is operable to connect an optical fiber cable to the photon glass layer substrate.

9. The method according to claim 1, wherein the core material layer comprises one or more of the following: silicon carbide (SiC)-containing materials, silicon oxycarbide (SiOC)-containing materials, titanium dioxide (TiO2)-containing materials, silicon dioxide (SiO2)-containing materials, vanadium(IV) oxide (VO x )-containing materials, aluminum oxide (Al2O3)-containing materials, aluminum-doped zinc oxide (AZO)-containing materials, indium tin oxide (ITO)-containing materials, tin dioxide (SnO2)-containing materials, zinc oxide (ZnO)-containing materials, tantalum pentoxide (Ta2O5)-containing materials, silicon nitride (Si3N4)-containing materials, zirconium dioxide (ZrO2)-containing materials, niobium pentoxide (Nb2O5)-containing materials, cadmium stannate (Cd2SnO4)-containing materials, silicon nitride (SiN)-containing materials, silicon oxynitride (SiON)-containing materials, barium titanate (BaTiO3)-containing materials, diamond-like carbon (DLC)-containing materials, hafnium(IV) oxide (HfO2)-containing materials, lithium niobate (LiNbO3)-containing materials, and silicon carbonitride (SiCN)-containing materials.

10. The method according to claim 1, wherein each of the waveguides of the plurality of optical structures comprises: a first end extending from the first edge of the substrate, wherein the first end of the waveguide comprises a first cross-sectional dimension; and a second end extending from the second edge of the substrate, wherein the second end of the waveguide comprises a second cross-sectional dimension, and the second cross-sectional dimension is greater than the first cross-sectional dimension.

11. The method according to claim 10, wherein the first cross-sectional dimension comprises a height dimension of approximately 1 micron, and wherein the second cross-sectional dimension comprises a height dimension of approximately 9 microns.

12. A method for manufacturing electronic and photonic components, comprising the steps of: depositing a patterned layer above the surface of a substrate comprising a photon glass layer, the photon glass layer having a first refractive index, and the patterned layer having a plurality of openings formed therein, portions of the surface of the substrate being exposed in the openings; removing the portions of the substrate exposed within the openings of the patterned layer to form a plurality of structures separated by a plurality of trenches in the substrate; removing the patterned layer; and depositing a filling layer above the plurality of structures and into the plurality of trenches to form a plurality of optical structures, the filling layer having a second refractive index different from the first refractive index, wherein each of the plurality of optical structures comprises a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each of the waveguides of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

13. The method according to claim 12, wherein after depositing the filling layer above the plurality of structures in the substrate and into the plurality of trenches, the excess portion of the filling layer is removed.

14. The method according to claim 13 further comprises the step of: after removing the excess portion of the filling layer, depositing a encapsulation layer above the plurality of structures and the portions of the filling layer deposited in the plurality of trenches, wherein the deposited encapsulation layer has a third refractive index different from the second refractive index.

15. The method according to claim 12, wherein each of the waveguides of the plurality of optical structures comprises: a first end extending from the first edge of the substrate, wherein the first end of the waveguide comprises a first cross-sectional dimension; and a second end extending from the second edge of the substrate, wherein the second end of the waveguide comprises a second cross-sectional dimension, and the second cross-sectional dimension is greater than the first cross-sectional dimension.

16. A method for manufacturing electronic and photonic components, comprising the steps of: A patterned layer is deposited above a surface of a substrate including a photonic glass layer, wherein the photonic glass layer has a first refractive index, and the patterned layer has a plurality of openings formed therein, and a portion of the surface of the substrate is exposed in the openings; An ion implantation process is performed on the exposed portion of the substrate to implant a plurality of doped ions into the surface of the exposed portion of the substrate, wherein the exposed portion of the substrate including the plurality of doped ions defines a plurality of optical structures, the plurality of optical structures having a second refractive index different from the first refractive index, wherein each of the plurality of optical structures includes a waveguide configured to transmit light between a first edge and a second edge of the substrate, and wherein each of the waveguides of the plurality of optical structures extends in one or more directions between the first edge and the second edge.

17. The method according to claim 16, wherein the plurality of doped ions include dopant materials selected from the group consisting of Al, P, F, Cl, P, N, Ar, Kr, and combinations of the foregoing.

18. The method according to claim 16, further comprising the steps of: removing the patterned layer after completion of the ion implantation process, and depositing a packaging layer above the substrate and the plurality of optical structures, wherein the deposited packaging layer has a third refractive index different from the second refractive index.

19. The method according to claim 16, further comprising the steps of: forming a chip mounting region on the surface of the photonic glass layer at the first edge of the substrate, wherein the chip mounting region is operable to connect a photonic or electronic integrated circuit to the substrate.

20. The method according to claim 16, further comprising the steps of: forming an optical fiber connector on the surface of the photonic glass layer at the second edge of the substrate, wherein the optical fiber connector is operable to connect an optical fiber cable to the substrate.

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