Testing device for photoelectric integrated circuit before co-packaging

Abstract

The invention discloses a testing device for an optoelectronic integrated circuit before co-packaging. The testing device comprises a first jig, a first optical transmission assembly, a second optical transmission assembly, an intermediate plate, a testing carrier plate and a second jig, the first jig and the second jig are arranged up and down in the direction perpendicular to the test carrier plate. The first photonic crystal grain and the second electronic integrated circuit are arranged in the accommodating space of the first jig. The first electronic integrated circuit is arranged in the groove part of the second jig. A first signal transmission loop is formed among the test carrier plate, the first electronic integrated circuit, the first photon crystal grain and the second photon crystal grain, and a second signal transmission loop is formed among the test carrier plate, the first electronic integrated circuit, the intermediate plate and the second electronic integrated circuit. Therefore, the problem that the photoelectric integrated circuit must be disassembled or taken back when defects are found in a test after co-packaging is avoided.

Description

Technical Field

[0001] This application relates to the technical field of electrical testing, and particularly to a testing device for optoelectronic integrated circuits before co-packaging. Background Art

[0002] Optoelectronic integrated circuits (OEICs) include photonic integrated circuits and electronic integrated circuits, which use light for data transmission and are applicable to high-performance data exchange, long-distance interconnection, 5G facilities, computing devices, etc. The photonic integrated circuit and the electronic integrated circuit form a co-packaged optical component (CPO) after co-packaging. The packaged semiconductor device usually needs to be tested to obtain various electrical characteristic parameters for the judgment of good product screening. Once a defect is detected in the semiconductor device under test, it is regarded as a defective product and cannot enter the market. However, there is currently a lack of a testing device for co-packaged optical components that can meet customized designs. In addition, a co-packaged semiconductor device detected with a defect may be due to the inability to generate an effective electrical loop between the electronic integrated circuit and the photonic integrated circuit, but the functions of individual components are normal. In other words, defective products in the final testing stage after co-packaging inevitably have to be disassembled or recalled, which will undoubtedly increase the manufacturing cost and lead to problems such as a decrease in the yield rate. Summary of the Invention

[0003] The purpose of this application is to provide a testing device that can be used for the electrical function testing of optoelectronic integrated circuits with a stack structure before co-packaging, so as to solve the problem of increased costs caused by disassembling or recalling defective components when problems are found in the final testing stage after co-packaging.

[0004] Another purpose of this application is to provide a testing device that can meet the testing requirements of photonic integrated circuits with diverse designs.

[0005] Based on the above purposes, the technical solutions provided by this application are as follows:

[0006] The present application provides a test device for an optoelectronic integrated circuit before co-packaging. The optoelectronic integrated circuit includes a first photonic die and a first electronic integrated circuit arranged in a stack. The test device is electrically connected to an automatic test equipment and includes a first fixture, which includes a first base body, a cover plate and a plurality of first conductor components. The first base body includes a first bottom plate and a first side wall. The cover plate covers a top of the first base body and forms an accommodating space with the first bottom plate and the first side wall. The first photonic die is disposed in the accommodating space, and the first bottom plate is provided with a plurality of through holes. The first optical transmission component includes a first end portion, and the first end portion is disposed in the accommodating space and close to the first photonic die. The second optical transmission component includes a second end portion, and the second end portion is disposed in the accommodating space and close to the first photonic die. The first optical transmission component and the second optical transmission component are used to emit a test optical signal to the first photonic die or receive an outgoing optical signal generated by the first photonic die. The interposer is disposed on one side of the first bottom plate. The plurality of first conductor components are arranged at intervals and penetrate through the corresponding through holes of the interposer and the first bottom plate, and are electrically connected between the first photonic die and the first electronic integrated circuit. The test carrier board is electrically connected to the automatic test equipment. A second fixture is disposed on the test carrier board and includes a second base body and a plurality of first signal conductors. The second base body includes a second bottom plate, a second side wall and a groove portion, and the groove portion is formed between the second side wall and the second bottom plate. The first fixture and the second fixture are arranged one above the other in a direction perpendicular to the test carrier board, and the first electronic integrated circuit is disposed in the groove portion. The plurality of first signal conductors penetrate through the second bottom plate and are electrically connected between the first electronic integrated circuit and the test carrier board.

[0007] Optionally, the optoelectronic integrated circuit further includes a second electronic integrated circuit. The first fixture further includes a plurality of second signal conductors, and the second electronic integrated circuit is fixed on the interposer and located in the accommodating space. The plurality of second signal conductors are arranged at intervals and penetrate through the corresponding through holes of the first bottom plate, and are electrically connected between the interposer and the first electronic integrated circuit.

[0008] Optionally, the optoelectronic integrated circuit further includes a second photonic die. The first fixture further includes a plurality of second conductor components. The test device further includes another first optical transmission component and another second optical transmission component. The second photonic die is disposed in the accommodating space. The another first optical transmission component and the another second optical transmission component are respectively disposed in the accommodating space and close to the second photonic die. The plurality of second conductor components are arranged at intervals and penetrate through the corresponding through holes of the interposer and the first bottom plate, and are electrically connected between the second photonic die and the first electronic integrated circuit.

[0009] Optionally, the first fixture further includes a holding member disposed on one side of the first sidewall or the cover plate, and the first photon crystal grain and / or the second photon crystal grain is held by the holding member and suspended in the accommodating space.

[0010] Optionally, the first fixture further includes a first elastic buffer assembly disposed on one side of the cover plate and pressing against the first photon crystal grain and the second photon crystal grain.

[0011] Optionally, the first fixture further includes a first elastic buffer assembly disposed on one side of the cover plate and pressing against the first photon crystal grain and the second electronic integrated circuit.

[0012] Optionally, the first fixture further includes a second elastic buffer assembly disposed on one side of the interposer and pressing against the first electronic integrated circuit.

[0013] Optionally, the testing device further includes a first connecting member and a second connecting member, and the first connecting member is detachably connected to the second connecting member to connect and fix the first fixture and the second fixture to the testing carrier plate.

[0014] Optionally, the first electronic integrated circuit includes a first packaging structure, and the second electronic integrated circuit includes a second packaging structure.

[0015] Optionally, the first sidewall is disposed around the first bottom plate and the accommodating space. The first optical transmission component further includes a first optical fiber, a first connector, and a first connector. The first connector is disposed on the first sidewall. The first optical fiber includes the first end portion, and the first connector is fixed to the first end portion and is pluggable into the first connector.

[0016] Optionally, the first photon crystal grain includes a first optical waveguide. The first optical fiber is aligned with the first optical waveguide, and the first end portion is disposed close to the first optical waveguide.

[0017] Optionally, the first photon crystal grain includes a first optical waveguide. The first connector of the first optical transmission component includes an optical channel and a reflective wall. The reflective wall forms an acute angle with the first optical fiber and the first photon crystal grain. The test optical signal is reflected by the reflective wall to the first optical waveguide, or the outgoing optical signal is reflected by the reflective wall to the first end portion.

[0018] Optionally, the first photonic die includes a first optical waveguide, the first connector of the first optical transmission component includes an optical channel, the cover plate includes a slot, and the slot includes an inclined portion. The inclined portion includes a reflective material with a reflection coefficient greater than that of air and forms an acute angle with the first optical fiber and the first base plate. A part of the first connector is embedded in the slot, and the optical channel extends to the inclined portion. The test optical signal is reflected by the inclined portion to the first optical waveguide, or the output optical signal is reflected by the inclined portion to the first end.

[0019] Optionally, the first photonic die includes a second optical waveguide. The second optical transmission component includes a second optical fiber, a second joint, and a second connector, and the second optical fiber includes the second end. The second connector is inclinedly embedded in the cover plate. The second joint is fixed to the second end and is pluggable and connectable to the second connector, and the second end is located above the second optical waveguide.

[0020] Optionally, the test device further includes a third optical transmission component, including a third optical fiber, a third joint, a third connector, and an internal optical fiber. The third connector is embedded in the first base plate. The third optical fiber includes a third end. The third joint is fixed to the third end and is pluggable and connectable to the third connector. One end of the internal optical fiber is connected to the third connector, and the other end is connected to the first photonic die.

[0021] After testing with the test device and the automatic test equipment of the present application, the first photonic die, the second photonic die, the first electronic integrated circuit, the second electronic integrated circuit, and the interposer can be formed into a co-packaged optical component with a stacked structure in a single package structure through co-packaging technology. Furthermore, the optoelectronic integrated circuit can be pre-tested after the wafer test stage and before co-packaging, effectively avoiding the problems of increased manufacturing costs and reduced yield caused by the need to disassemble or recall defective products during the final test stage after co-packaging of the photonic integrated circuit or the electronic integrated circuit. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 Schematic structural diagram of a test device for an optoelectronic integrated circuit before co-packaging according to an embodiment of the present application.

[0024] Figure 2 Schematic structural diagram of a test device illustrating another embodiment of the present application.

[0025] Figure 3 Schematic structural diagram of a test device illustrating another embodiment of the present application.

[0026] Figure 4 Schematic structural diagram of a test device illustrating another embodiment of the present application.

[0027] Figure 5 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0028] Figure 6 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0029] Figure 7 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0030] Figure 8 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0031] Figure 9 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0032] Figure 10 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device.

[0033] Figure 11 Illustrate Figure 1 Enlarged schematic diagram of a partial structure of the test device. Detailed implementation manners

[0034] The following are detailed descriptions of embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and do not limit the present invention. The description of the structural operations is not used to limit their execution order. Any structure formed by recombining components and having equivalent functions is within the scope covered by the disclosure of the present invention.

[0035] It should be noted that in the corresponding diagrams of the embodiments, lines are used to represent signals. Some lines may be thicker to indicate signal paths with more components, and / or some lines have arrows at one or more ends to indicate the main information flow direction. Such indications are not intended to be restrictive. Instead, the lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit or logic unit. Any represented signal as specified by design requirements or preferences may actually include one or more signals that can travel in either direction and may be implemented using any suitable type of signal scheme.

[0036] In the following and in the claims, the term "coupled" and its derivatives may be used. The term "coupled" herein refers to two or more components that are in direct contact (physically, electrically, magnetically, optically, etc.). The term "coupled" herein may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other.

[0037] As used herein, unless otherwise specified, the ordinal adjectives "first", "second", "third", etc. used to describe general objects merely indicate different instances of similar objects being referred to and are not intended to imply that the objects so described must be in a given order in terms of time, space, arrangement, or any other way.

[0038] This application provides a test device for testing the electrical characteristics of an optoelectronic integrated circuit before co-packaging. In some embodiments, the optoelectronic integrated circuit is an electronic integrated circuit (EIC) including an electrical arithmetic processor and a photonic integrated circuit (PIC) responsible for electro-optical conversion. According to the test device provided by this application, the optoelectronic integrated circuit can adopt 2.5D packaging technology or 3D packaging technology after testing, integrate the electronic integrated circuit and the photonic integrated circuit in a single packaging structure, and form a co-packaged optical component (CPO) with a stacked structure. In other words, the test device disclosed in this application is designed based on the co-packaged optical component with a stacked structure. It should be noted that the photonic integrated circuit to be tested may include at least one optical detection component and a light source module, as well as a plurality of active components and passive components, such as, but not limited to, a filter or a multiplexing structure, an optical power distribution structure, an optical fiber input / output structure, and an optical modulation structure. Since the features of this application do not lie in the detailed structures of the optical active and passive components known to those skilled in the art, they will not be described in detail herein.

[0039] Refer to Figure 1 , Figure 1Schematic structural diagram of a test device for an optoelectronic integrated circuit before co-packaging according to an embodiment of the present application. An embodiment of the present application provides a test device 1, including a first fixture 10, a second fixture 20, a first optical transmission component 31, a second optical transmission component 32, an interposer 40, and a test carrier board 50. The test device 1 of the embodiment of the present application is electrically connected to an automatic test equipment 7 (ATE) and is used for performing electrical function tests on an optoelectronic integrated circuit 6 before co-packaging. In some embodiments, the optoelectronic integrated circuit 6 as the device under test includes a first photonic die 61, a second photonic die 62, a first electronic integrated circuit 63, and a second electronic integrated circuit 64. Preferably, the above electrical function tests include, for example, items such as voltage, current, resistance, reverse leakage, voltage-current relationship, and electrical circuits between the first photonic die 61, the second photonic die 62, the first electronic integrated circuit 63, and the second electronic integrated circuit 64, but are not limited thereto.

[0040] In some embodiments, the first electronic integrated circuit 63 may be a system-on-chip in which multiple processing units with different functions are integrally packaged together, and the second electronic integrated circuit 64 may be a memory, such as a dynamic random access memory or other volatile memory, but is not limited thereto. In some embodiments, the first photonic die 61 and the second photonic die 62 are fabricated using a silicon-on-insulator (SOI) wafer to form silicon photonic dies. It should be noted that the photonic integrated circuit (i.e., the first photonic die 61 and the second photonic die 62) to be tested by the test device 1 may include at least one optical detection component for converting an optical signal into an electrical signal, a light source module for converting an electrical signal into an optical signal, and multiple active components and passive components, such as, but not limited to, a filter or a multiplexing structure, an optical power distribution structure, an optical fiber input / output structure, and an optical modulation structure. Since the features of the present application do not lie in the detailed structures of the optical active and passive components known to those skilled in the art, they will not be described in detail herein.

[0041] As Figure 1As shown, the first fixture 10 includes a first base body 11, a cover plate 12, a plurality of first conductor components 13, a plurality of second signal conductors 14, and a plurality of second conductor components 15. In some embodiments, the first base body 11 has a substantially rectangular cross-section and includes a first bottom plate 111 and a first side wall 112, and the first side wall 112 surrounds the first bottom plate 111. The cover plate 12 can be attached and covered on a top of the first base body 11, and together with the first bottom plate 111 and the first side wall 112, form an accommodation space 110. The size of the accommodation space 110 is sufficient to accommodate the first photon die 61, the second photon die 62, the second electronic integrated circuit 64, and the interposer 40 simultaneously. It should be noted that the depth of the accommodation space 110 is greater than the height after the first photon die 61 or the second photon die 62 is stacked with the interposer 40, or greater than the height after one or more second electronic integrated circuits 64 are stacked with the interposer 40. Preferably, the first bottom plate 111 is provided with a plurality of perforations 1110 arranged at intervals, and the perforations 1110 penetrate the first bottom plate 111 to communicate with the accommodation space 110.

[0042] Please continue to refer to Figure 1 , the interposer 40 is disposed on one side of the first bottom plate 111 and is located within the accommodation space 110. In this embodiment, the interposer 40 is a circuit board and includes a plurality of through holes 401. It should be noted that the configuration of some of the perforations 1110 on the first bottom plate 111 is designed according to the configuration of the through holes 401 on the interposer 40, so that a plurality of first conductor components 13 penetrate the corresponding perforations 1110 on the first bottom plate 111 and the corresponding through holes 401 on the interposer 40, and extend into the accommodation space 110 to electrically connect the first photon die 61. As Figure 1 shown, a plurality of second conductor components 15 respectively penetrate the corresponding perforations 1110 on the first bottom plate 111 and the corresponding through holes 401 on the interposer 40, and extend into the accommodation space 110 to electrically connect the second photon die 62. In some other embodiments, the interposer 40 may not be provided with through holes 401, but instead, by providing a contact array of bumps on the lower surface of the interposer 40 to make electrical contact with the first conductor components 13 and / or the second conductor components 15, and providing another contact array of bumps on the upper surface of the interposer 40 to make electrical contact with the photon integrated circuit.

[0043] It should be noted that part of the first conductor assembly 13 and part of the second conductor assembly 15 serve as power conductors of the photonic integrated circuit. Specifically, the power required for specific components of the first photonic die 61 and the second photonic die 62, such as the optical modulation structure or the light source module, is transmitted from the test carrier 50 to the first photonic die 61 and the second photonic die 62 respectively through the first electronic integrated circuit 63. Through the above structure, when the photonic integrated circuit is subjected to optoelectronic testing, the optical signals of the first optical transmission assembly 31 and the second optical transmission assembly 32 are transmitted out for testing by other first conductor assemblies 13 and second conductor assemblies 15 after the optoelectronic conversion process of the first photonic die 61 and the second photonic die 62.

[0044] As Figure 1 shown, the second electronic integrated circuit 64 is fixed on the interposer 40 and located within the accommodating space 110, and the first photonic die 61 and the second photonic die 62 are arranged around the second electronic integrated circuit 64. Preferably, the upper surface of the interposer 40 has contacts arranged in an array of bumps for electrically connecting the second electronic integrated circuit 64. The second signal conductors 14 are arranged at intervals and penetrate through the corresponding through holes 1110 of the first bottom plate 111, and are electrically connected between the interposer 40 and the first electronic integrated circuit 63 to transmit signals between the second electronic integrated circuit 64 and the first electronic integrated circuit 63. In some embodiments, the first conductor assembly 13, the second signal conductors 14, and the second conductor assembly 15 can be extremely short needles or high-speed probes, or coaxial spring probes, which can be determined according to actual test requirements. Since the features of the present application do not lie in the detailed structure of the probes known to those skilled in the art, they will not be described in detail herein.

[0045] Continuing to refer to Figure 1 , the first fixture 10 further includes two holding members 113, which are provided corresponding to the number of photonic integrated circuits to be tested for holding the first photonic die 61 and the second photonic die 62 in the accommodating space 110. In some embodiments, the holding members 113 can be arranged on the first side wall 112 and have a clamping structure to respectively clamp and fix the first photonic die 61 and the second photonic die 62 to the holding members 113. In other embodiments, the holding members 113 can be arranged on the side of the cover plate 12 facing the accommodating space 110 and have a clamping structure for clamping the first photonic die 61 and the second photonic die 62. That is, the first photonic die 61 and the second photonic die 62 are not fixed to the interposer 40 but are suspended in the accommodating space 110.

[0046] In some embodiments, the first fixture 10 further includes a first elastic buffer component 161, which is made of a material with elasticity and deformability characteristics, such as elastic polymers, rubber, silicone, etc. Preferably, the first elastic buffer component 161 is disposed on one side of the cover plate 12 to press and further fix the first photon die 61, the second photon die 62, and the second electronic integrated circuit 64 toward the intermediate plate 40, so as to ensure that the device under test does not move during the test and affect the test results.

[0047] Continue to refer to Figure 1 , the second fixture 20 is detachably disposed on the test carrier 50, and the test carrier 50 is electrically connected to the automatic test equipment 7. In some embodiments, the second fixture 20 includes a second body 21, a groove portion 210, and a plurality of first signal conductors 23. Specifically, the second body 21 has a substantially rectangular cross-section and includes a second bottom plate 211 and a second side wall 212 disposed around the second bottom plate 211, and the groove portion 210 is formed between the second side wall 212 and the second bottom plate 211. The first electronic integrated circuit 63 is detachably disposed in the groove portion 210. In some embodiments, the second fixture 20 further includes a holding structure (not shown) for holding the first electronic integrated circuit 63. The holding structure can be disposed on the second side wall 212 or the second bottom plate 211 and protrude into the groove portion 210 to carry the first electronic integrated circuit 63. As Figure 1 shown, one end of the plurality of first signal conductors 23 is connected to the test carrier 50, and the other end penetrates the second bottom plate 211 and is electrically connected to the first electronic integrated circuit 63. In addition, the first photon die 61 performs optical signal transmission through the first optical transmission component 31 and the second optical transmission component 32. Similarly, another first optical transmission component 31 and another second optical transmission component 32 are respectively disposed in the accommodation space 110 and close to the second photon die 62 to perform optical signal transmission with the second photon die 62. The method and structure for implementing the optical signal transmission in the present application will be described in detail in the following paragraphs.

[0048] Continue to refer to Figure 1, the first fixture 10 and the second fixture 20 are arranged one above the other in a direction perpendicular to the test carrier board 50. In some embodiments, the first fixture 10 can be positioned above the second fixture 20 by means of an external suspension mechanism (not shown), or can be directly stacked on the second fixture 20, and the second fixture 20 can be fixed to the test carrier board 50 through a fixing member 25. During the testing process of the testing device 1 of the present application, the first photon crystal grain 61 and the second photon crystal grain 62 perform optical signal transmission of optical-to-electricity conversion and electricity-to-optical conversion by using the first optical transmission component 31 and the second optical transmission component 32. Moreover, a first signal transmission loop is formed between the test carrier board 50 and the first electronic integrated circuit 63 and the first photon crystal grain 61 / second photon crystal grain 62, and a second signal transmission loop is formed between the test carrier board 50 and the first electronic integrated circuit 63, the intermediate board 40 and the second electronic integrated circuit 64. Thus, the automatic testing equipment 7 can perform electrical function testing on the optoelectronic integrated circuit composed of the photon integrated circuit and the electronic integrated circuit through the testing device 1.

[0049] Refer to Figure 2 , Figure 2 FIG. shows a schematic structural diagram of the testing device 1 according to another embodiment of the present application. The testing device 1 in the embodiment of the present application can also only test the signal transmission between the photon integrated circuit and the first electronic integrated circuit 63. As Figure 2 shown, only the first photon crystal grain 61 and the second photon crystal grain 62 are provided in the first fixture 10, and the second electronic integrated circuit 64 is not provided on the intermediate board 40. That is, the testing device 1 in this embodiment only tests the signal transmission between the first photon crystal grain 61 and the second photon crystal grain 62 and the first electronic integrated circuit 63. It should be specifically noted that, in Figure 2 the embodiment shown, the first fixture 10 further includes a second elastic buffer assembly 162, which is disposed on the side of the first bottom plate 111 facing the first electronic integrated circuit 63 to press against the first electronic integrated circuit 63 and ensure that the first electronic integrated circuit 63 does not move.

[0050] Refer to Figure 3 , Figure 3 FIG. shows a schematic structural diagram of the testing device 1 according to another embodiment of the present application. In Figure 3In the illustrated test device 1, the first fixture 10 is directly stacked on the second sidewall 212 of the second fixture 20, and the test device 1 further includes a first connecting member 17 and a second connecting member 27, and the first connecting member 17 is detachably connected to the second connecting member 27. In some embodiments, the first connecting member 17 and the second connecting member 27 may be locking structures; preferably, the first connecting member 17 may be a locking pin, and the second connecting member 27 may be a thread formed in the second sidewall 212 of the second base 21 and the test carrier plate 50, and the locking pin penetrates the first sidewall 112 and is locked to the thread to connect and fix the first fixture 10 and the second fixture 20 to the test carrier plate 50. It should be noted that the connection structure of the first connecting member 17 and the second connecting member 27 is not limited to the above. In addition, as Figure 3 shown, the first electronic integrated circuit 63 includes a first packaging structure 630, and the second electronic integrated circuit 64 includes a second packaging structure 640. In other words, the first electronic integrated circuit 63 and the second electronic integrated circuit 64 tested in the embodiments of the present application are packaged chips, but the first photon die 61 and the second photon die 62 are unencapsulated dies.

[0051] Refer to Figure 4 , Figure 4 FIG. illustrates a schematic structural diagram of a test device 1' according to another embodiment of the present application. Figure 4 The illustrated test device 1' and Figure 1 the main difference between the test device 1 is that Figure 4 the test device 1' only tests the signal transmission between the photon integrated circuit and the first electronic integrated circuit 63, and the intermediate plate 40 is disposed outside the first bottom plate 111 of the first base 11, rather than disposed in the accommodation space 110. The structure of the test device 1 that is the same as Figure 1 the test device 1 will not be described in detail here. As Figure 4 shown, the intermediate plate 40 is disposed on the side of the first bottom plate 111 facing the second base 21, and is sandwiched between the first base 11 and the second base 21, and is adjacent to the groove portion 210 of the second fixture 20. The first electronic integrated circuit 63 formed by encapsulating the first die 631 and the first substrate 632 is disposed in the groove portion 210. In this embodiment, the test device 1' further includes a first connecting member 17' and a second connecting member 27', which may be locking structures for connecting and fixing the first fixture 10 to the second fixture 20. In some embodiments, a second elastic buffer assembly 162 may be disposed on the bottom side of the intermediate plate 40 to press and fix the first electronic integrated circuit 63 below.

[0052] Refer to Figures 5 to 11 , Figures 5 to 11Respectively, they are enlarged schematic diagrams of the partial structures of the test device 1 of the present application, to illustrate in detail the structures of the optical transmission components for the first photon crystal grain 61 and the second photon crystal grain 62. It should be specifically noted that Figures 5 to 11 It is mainly used to illustrate the structural relationship between the photonic integrated circuit and the optical transmission component. Therefore, for the sake of clarity, Figures 5 to 11 the interposer 40, the first conductor component 13, the through hole 401 and other components of the test device 1 corresponding to Figure 1 are omitted in the display. The optical transmission component of the embodiment of the present application uses an optical fiber as a medium to transmit optical signals. In some embodiments, the optical fiber can be a single-mode optical fiber, a polarization-maintaining optical fiber or a lens optical fiber, but is not limited to the types of the foregoing optical fibers. The main wavelength transmitted by the optical fiber is in the range of 1100 nanometers (nm) to 2000 nm. Preferably, it is infrared light with a wavelength of 1550 nm. In addition, the principles of the optical transmission components for the first photon crystal grain 61 and the second photon crystal grain 62 are the same, so Figures 5 to 11 only the optical signal transmission between the first optical transmission component 31 and the second optical transmission component 32 and the first photon crystal grain 61 is illustrated as an example.

[0053] As Figure 5 shown, the first optical transmission component 31 includes a first optical fiber 311, a first connector 312 and a first connector 313. Specifically, the first optical fiber 311 includes a first end 3111, which is disposed in the accommodating space 110 and close to the first photon crystal grain 61. The first connector 313 is disposed on the first side wall 112, and the first connector 312 is fixed to the first end 3111 and is detachably connected to the first connector 313. Preferably, the first end 3111 is located at a first vertical level VL1 of the first bottom plate 111. In some embodiments, the first connector 312 can be made of a metal or ceramic material and has a structure such as a ferrule to provide good protection for the first optical fiber 311 and avoid the influence of external factors on the signal transmission. In other embodiments, the first connector 312 can have a grating structure with a V-groove, so that the first optical fibers 311 are arranged in an optical fiber array to reduce the loss of the optical waveguide structure and optical coupling alignment. As Figure 5As shown, the first photon crystal grain 61 includes a first optical waveguide 611, a photodetection component 613, and a light source module 614. Preferably, the first optical waveguide 611 is made of a material with a refractive index greater than that of air, such as a polymer material of silicon, silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. The photodetection component 613 is used to convert the optical signal transmitted by the optical waveguide 611 into an electrical signal, and the light source module 614 is used to convert the electrical signal into an optical signal to be emitted. In this embodiment, the first optical fiber 311 is aligned with the first optical waveguide 611, and the first end 3111 is directly adjacent to the first optical waveguide 611. Specifically, the first optical fiber 311 is used to transmit a test optical signal, which is directly emitted from the first end 3111 to the first optical waveguide 611, so that the test optical signal is transmitted through the first optical waveguide 611 to the photodetection component 613 of the first photon crystal grain 61.

[0054] Referring to Figure 6 , in this embodiment, the first connector 313 of the first optical transmission component 31 includes an optical channel 3131 and a reflective wall 3132, wherein the reflective wall 3132 forms an acute angle with respect to the first optical fiber 311 and the first photon crystal grain 61. In this embodiment, the first end 3111 is located on a second vertical level VL2 of the first base plate 111, and the height of the second vertical level VL2 is greater than the height of the first vertical level VL1. As Figure 6 shown, the first photon crystal grain 61 includes a first optical waveguide 611' having a grating structure. Specifically, the grating structure includes a plurality of V-shaped grooves (not shown) arranged side by side in a row, so that the first optical fibers 311 are arranged in an optical fiber array to reduce the loss of the optical waveguide structure and optical coupling alignment. The test optical signal transmitted by the first optical fiber 311 is reflected by the reflective wall 3132 after being emitted through the optical channel 3131, and is reflected in the downward direction of the cover plate 12 to the first optical waveguide 611', and finally transmitted to the photodetection component 613.

[0055] Referring to Figure 7 , Figure 7 The structure of the first optical transmission component 31 shown is substantially the same as that of Figure 6 the first optical transmission component 31 shown, but Figure 7 the first optical transmission component 31 shown is located below the first photon crystal grain 61. Specifically, as Figure 7 shown, the first connector 313 of the first optical transmission component 31 includes an optical channel 3131 and a reflective wall 3132, wherein the reflective wall 3132 forms an acute angle with respect to the first optical fiber 311 and the first photon crystal grain 61. In this embodiment, the first end 3111 is located on a second vertical level VL2' of the first base plate 111, and the height of the second vertical level VL2' is less than the height of the first vertical level VL1. As Figure 7As shown, a first optical waveguide 611' with a grating structure is provided on the lower surface of the first photon crystal grain 61. The test optical signal transmitted by the first optical fiber 311 is reflected by the reflecting wall 3132 and then reflected from below the first photon crystal grain 61 upward to the first optical waveguide 611'.

[0056] Referring to Figure 8 , the first photon crystal grain 61 includes a first optical waveguide 611', the first connector 313 of the first optical transmission component 31 includes an optical channel 3131, the cover plate 12 includes a groove 121, and the groove 121 includes an inclined portion 122. Specifically, the inclined portion 122 of the cover plate 12 includes a reflective material with a reflection coefficient greater than that of air, forms an acute angle with respect to the first optical fiber 311 and the first bottom plate 111, a part of the first connector 313 is embedded in the groove 121, and the optical channel 3131 extends to the inclined portion 122. The test optical signal transmitted by the first optical fiber 311 is reflected by the inclined portion 122 to the first optical waveguide 611' after passing through the optical channel 3131, and finally transmitted to the optical detection component 613..

[0057] Referring to Figure 9 , the second optical transmission component 32 includes a second optical fiber 321, a second joint 322, and a second connector 323, and the second optical fiber 321 includes a second end portion 3211. Specifically, the second connector 323 is inclinedly embedded in the cover plate 12, the second joint 322 is fixed to the second end portion 3211 and is pluggably connected to the second connector 323. In this embodiment, the first photon crystal grain 61 includes a second optical waveguide 612, and the second end portion 3211 of the second optical fiber 321 is located above the second optical waveguide 612 and is located at a third vertical level VL3 of the first bottom plate 111, and the height of the third vertical level VL3 is different from the height of the first vertical level VL1 or the second vertical level VL2. It should be noted that the angle of the second connector 323 with respect to the first photon crystal grain 61 depends on the design of the second optical waveguide 612. As Figure 9 shown, the second optical fiber 321 is used to transmit a test optical signal, and the test optical signal is directly emitted from above the first photon crystal grain 61 to the second optical waveguide 612 and detected by the optical detection component 613.

[0058] Referring to Figure 10 , in some embodiments, the test device 1 further includes a third optical transmission component 33, which includes a third optical fiber 331, a third joint 332, a third connector 333, and an internal optical fiber 334, and the third optical fiber 331 includes a third end portion 3311. Specifically, the third connector 333 is embedded in the first bottom plate 111, the third joint 332 is fixed to the third end portion 3311 and is pluggably connected to the third connector 333. As Figure 10As shown, one end of the internal fiber 334 is connected to the third connector 333, and the other end is connected to the first photon crystal grain 61. With the above structure, the third optical fiber 331 transmits a test optical signal to the first photon crystal grain 61 through the internal fiber 334. It should be noted that Figures 5 to 10 only a single optical transmission component is shown transmitting the test optical signal and being detected by the optical detection component 613 of the first photon crystal grain 61, but another optical transmission component for receiving the outgoing optical signal emitted by the light source module 614 is omitted for clear display.

[0059] Refer to Figure 11 , Figure 11 illustrative Figure 1 partial structural enlarged schematic diagram of the test device. In this embodiment, the first optical transmission component 31 is disposed on the first sidewall 112 for emitting a test optical signal, and the test optical signal is converted into an electrical signal by the optical detection component 613. The second optical transmission component 32 is disposed on the cover plate 12 for transmitting the outgoing optical signal converted from the electrical signal by the light source module 614. In this embodiment, the test optical signal is transmitted in a horizontal direction relative to the first photon crystal grain 61, and the outgoing optical signal is transmitted to the second optical transmission component 32 above the first photon crystal grain 61 to achieve a test pattern in which the incoming optical signal (i.e., the test optical signal) and the outgoing optical signal are transmitted in different directions. In other embodiments, the test optical signal and the outgoing optical signal are transmitted in the same direction (not shown). It should be noted that the positions of the test optical signal and the outgoing optical signal mainly depend on the optical detection component 613 and the light source module 614 of the first photon crystal grain 61, so as to achieve different test patterns to meet the different designs of the photon integrated circuit to be tested.

[0060] By using the cooperation of the first optical transmission component 31, the second optical transmission component 32 and / or the third optical transmission component 33 provided at different vertical levels as described above, various optical coupling patterns in different directions are formed, thereby realizing the electrical test of different photon integrated circuit designs. It should be specifically noted that according to the design of the optoelectronic integrated circuit, multiple optical transmission components can be provided on each side of the test device 1 of the present application, that is, the optical transmission components in the above other embodiments, to improve the signal transmission efficiency.

[0061] In the test device provided in this application, by means of the cooperation of the multiple optical transmission components, the first fixture, the interposer, the second fixture, and the test carrier board, an automatic test device can perform electrical function tests on a photonic integrated circuit and an electronic integrated circuit before co-packaging. After testing, the first photonic die, the second photonic die, the first electronic integrated circuit, the second electronic integrated circuit, and the interposer can form a co-packaged optical component with a stacked structure in a single packaging structure through co-packaging technology. By means of the test device of this application, the optoelectronic integrated circuit can be tested after the wafer test stage and before the final test stage after co-packaging, effectively avoiding the problems of increased manufacturing costs and reduced yield caused by the need to disassemble or recall a photonic integrated circuit or an electronic integrated circuit due to defects found after co-packaging.

[0062] As used in the specification, "embodiment", "one embodiment", "some embodiments", or "other embodiments" mean that the specific features, structures, or characteristics described in connection with the embodiments are included in at least some embodiments, but not necessarily in all embodiments. The various occurrences of "embodiment", "one embodiment", or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "might", or "could" be included, then the specific component, feature, structure, or characteristic need not be included. If the specification or the claims refer to "a" or "an" component, it does not mean that there is only one such component. If the specification or the claims refer to "additional" components, it does not exclude the existence of more than one additional component.

[0063] Although the embodiments of this application have been disclosed above, they are not intended to limit this application. Any person skilled in the art can make some modifications and refinements without departing from the scope of this application. Therefore, the protection scope of this application shall be defined by the appended claims for patent.

Claims

1. A test device for an optoelectronic integrated circuit before co-packaging, the optoelectronic integrated circuit including a first photonic die and a first electronic integrated circuit arranged in a stack, the test device being electrically connected to an automatic test equipment, characterized in that, The test device includes: A first fixture, including a first base body, a cover plate, and a plurality of first conductor components. The first base body includes a first bottom plate and a first side wall. The cover plate covers the top of the first base body and forms an accommodation space with the first bottom plate and the first side wall. The first photon die is disposed in the accommodation space, and the first bottom plate is provided with a plurality of through holes; A first optical transmission component, including a first end portion, and the first end portion is disposed in the accommodation space and close to the first photon die; A second optical transmission component, including a second end portion, and the second end portion is disposed in the accommodation space and close to the first photon die. The first optical transmission component and the second optical transmission component are used to emit a test optical signal to the first photon die or receive an output optical signal generated by the first photon die; An intermediate plate, disposed on one side of the first bottom plate. The plurality of first conductor components are arranged at intervals and penetrate through the intermediate plate and the corresponding through holes of the first bottom plate, and are electrically connected between the first photon die and the first electronic integrated circuit; A test carrier board, electrically connected to the automatic test equipment; and A second fixture, disposed on the test carrier board, and including a second base body and a plurality of first signal conductors. The second base body includes a second bottom plate, a second side wall, and a groove portion, and the groove portion is formed between the second side wall and the second bottom plate. The first fixture and the second fixture are arranged one above the other in a direction perpendicular to the test carrier board, and the first electronic integrated circuit is disposed in the groove portion. The plurality of first signal conductors penetrate through the second bottom plate and are electrically connected between the first electronic integrated circuit and the test carrier board.

2. The test device for an optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, The optoelectronic integrated circuit further includes a second electronic integrated circuit. The first fixture further includes a plurality of second signal conductors, and the second electronic integrated circuit is fixed on the intermediate plate and located in the accommodation space. The plurality of second signal conductors are arranged at intervals and penetrate through the corresponding through holes of the first bottom plate, and are electrically connected between the intermediate plate and the first electronic integrated circuit.

3. The test device for an optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, The optoelectronic integrated circuit further includes a second photon die. The first fixture further includes a plurality of second conductor components. The test device further includes another first optical transmission component and another second optical transmission component. The second photon die is disposed in the accommodation space. The another first optical transmission component and the another second optical transmission component are respectively disposed in the accommodation space and close to the second photon die. The plurality of second conductor components are arranged at intervals and penetrate through the intermediate plate and the corresponding through holes of the first bottom plate, and are electrically connected between the second photon die and the first electronic integrated circuit.

4. The test device for an optoelectronic integrated circuit before co-packaging according to claim 3, characterized in that, The first fixture further includes a holder, and the holder is disposed on one side of the first side wall or the cover plate. The first photon die and / or the second photon die is held by the holder and suspended in the accommodation space.

5. The test device for the optoelectronic integrated circuit before co-packaging according to claim 3, wherein, The first fixture further includes a first elastic buffer component, which is disposed on one side of the cover plate and presses against the first photon die and the second photon die.

6. The test device for an optoelectronic integrated circuit before co-packaging according to claim 2, characterized in that, The first fixture further includes a first elastic buffer component, which is disposed on one side of the cover plate and presses against the first photon die and the second electronic integrated circuit.

7. The test device for an optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, The first fixture further includes a second elastic buffer component, which is disposed on one side of the interposer and presses against the first electronic integrated circuit.

8. The test device for an optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, It further includes a first connecting member and a second connecting member, and the first connecting member is detachably connected to the second connecting member to connect and fix the first fixture and the second fixture to the test carrier.

9. The test device for an optoelectronic integrated circuit before co-packaging according to claim 2, characterized in that, The first electronic integrated circuit includes a first package structure, and the second electronic integrated circuit includes a second package structure.

10. The test device for the optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, The first side wall is disposed around the first bottom plate and the accommodating space. The first optical transmission component further includes a first optical fiber, a first connector, and a first connector. The first connector is disposed on the first side wall. The first optical fiber includes the first end portion, and the first connector is fixed to the first end portion and is pluggable into the first connector.

11. The test device for an optoelectronic integrated circuit before co-packaging according to claim 10, characterized in that, The first photon die includes a first optical waveguide, the first optical fiber is aligned with the first optical waveguide, and the first end portion is disposed close to the first optical waveguide.

12. The test device for an optoelectronic integrated circuit before co-packaging according to claim 10, wherein, The first photon die includes a first optical waveguide. The first connector of the first optical transmission component includes an optical channel and a reflective wall. The reflective wall forms an acute angle with the first optical fiber and the first photon die. The test optical signal is reflected by the reflective wall to the first optical waveguide, or the outgoing optical signal is reflected by the reflective wall to the first end portion.

13. The test device for an optoelectronic integrated circuit before co-packaging according to claim 10, characterized in that, The first photon die includes a first optical waveguide. The first connector of the first optical transmission component includes an optical channel. The cover plate includes an embedding groove, and the embedding groove includes an inclined portion. The inclined portion includes a reflective material with a reflection coefficient greater than that of air and forms an acute angle with the first optical fiber and the first bottom plate. A part of the first connector is embedded in the embedding groove, and the optical channel extends to the inclined portion. The test optical signal is reflected by the inclined portion to the first optical waveguide, or the outgoing optical signal is reflected by the inclined portion to the first end portion.

14. The test device for an optoelectronic integrated circuit before co-packaging according to claim 1, characterized in that, The first photon die includes a second optical waveguide. The second optical transmission component includes a second optical fiber, a second connector, and a second connector. The second optical fiber includes the second end portion. The second connector is inclinedly embedded in the cover plate. The second connector is fixed to the second end portion and is pluggable into the second connector, and the second end portion is located above the second optical waveguide.

15. The test device for the optoelectronic integrated circuit before co-packaging as described in claim 1 further includes a third optical transmission component, which includes a third optical fiber, a third connector, a third adapter, and an internal optical fiber. The third adapter is embedded in the first base plate. The third optical fiber includes a third end portion. The third connector is fixed to the third end portion and is detachably connected to the third adapter. One end of the internal optical fiber is connected to the third adapter, and the other end is connected to the first photonic die.

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