Impedance test method of multi-layer and multi-order printed circuit board and circuit board

Abstract

According to the impedance test method for the multi-layer and multi-order printed circuit board and the circuit board provided by the embodiment of the invention, the through hole is formed in the inner layer circuit board, the impedance of the inner layer circuit board is tested through the through hole, and the impedance of the inner layer circuit board is tested, so that the circuit board can work normally, and the performance and reliability of electronic equipment are improved. After a layer of outer layer circuit board is added on the outer layer circuit board, a blind hole is manufactured on the outer layer circuit board based on a through hole PAD, a test PAD is made by using the blind hole, and impedance test is performed on the added outer layer circuit board, so that the impedance of the current layer can be measured in time during layer addition, and the impedance can be measured without waiting for a finished product. The actual impedance of each layer can be measured, the rejection rate of the impedance of a final finished product is reduced, the production efficiency is improved, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic manufacturing technology, and in particular, to an impedance testing method and a circuit board for a multi-layer and multi-order printed circuit board. Background Art

[0002] With the rapid development of artificial intelligence technology, artificial intelligence (AI) servers and data centers, as the core infrastructure to support AI applications, in order to address challenges such as data transmission bottlenecks and high losses, have put forward higher requirements for the stability and consistency of the impedance of ultra-high density (UHD) printed circuit boards. Therefore, precise impedance testing is required during the production of UHD printed circuit boards.

[0003] Currently, in the prior art, the impedance detection mode of high multi-layer and high-order UHD printed circuit boards generally simulates impedance production by controlling the line width during inner layer production and measures the overall impedance at the final finished product.

[0004] However, it is difficult for the prior art to accurately test the impedance of each layer during UHD build-up production. It is necessary to measure the overall impedance at the finished product stage. If impedance defects are found at the final finished product, it needs to be scrapped, resulting in higher scrapping costs and a higher finished product scrap rate. Summary of the Invention

[0005] The impedance testing method and circuit board for a multi-layer and multi-order printed circuit board provided by the embodiments of the present application are used to accurately test the impedance of each layer during UHD build-up production and reduce the finished product scrap rate.

[0006] In a first aspect, the impedance testing method for a multi-layer and multi-order printed circuit board provided by the embodiments of the present application includes:

[0007] Pressing n inner core boards to obtain an inner layer circuit board, where n is an integer greater than or equal to 2;

[0008] Making vias on the inner layer circuit board and using the vias to make via pads PAD;

[0009] Testing the impedance of the inner layer circuit board through the vias;

[0010] Successively adding outer layer circuit boards on the basis of the inner layer circuit board;

[0011] After adding each outer layer circuit board, based on the via PAD, making blind vias on the outer layer circuit board, using the blind vias to make test pads, and testing the impedance of the added outer layer circuit board;

[0012] Among them, impedance testing is performed on the outer circuit board of the additional layer, including:

[0013] Connect the sub-outer circuit board and the outer circuit board through blind vias, and connect the test PAD and the test circuit to establish an electrical connection between the sub-outer circuit board and the outer circuit board;

[0014] Use an impedance testing device to send a test signal to the blind via, so that the blind via reflects a reflected signal based on the test signal to the test circuit; use the impedance testing device to calculate and obtain the impedance value of the outer circuit board based on the test signal and the reflected signal;

[0015] Generate an impedance test result according to the impedance value;

[0016] Continue to add a new outer circuit board to the outer circuit board, and repeat the steps of impedance testing for each new outer circuit board until the addition of all outer circuit boards is completed, obtaining a finished multi-layer and multi-order printed circuit board.

[0017] In a possible implementation manner, the through hole is not resin-sealed; the blind via is located at the edge of the through hole PAD.

[0018] In a possible implementation manner, the through hole is resin-sealed; the blind via is located at the edge of the through hole PAD.

[0019] In a possible implementation manner, the through hole is resin-sealed; the blind via is located on the through hole PAD.

[0020] In a possible implementation manner, making blind vias on the outer circuit board includes:

[0021] According to the positions of the blind vias on the previous layer of the outer circuit board, make blind vias at the positions corresponding to the blind vias on the previous layer of the outer circuit board on the outer circuit board.

[0022] In a possible implementation manner, making blind vias on the outer circuit board includes:

[0023] According to the positions of the blind vias on the previous layer of the outer circuit board, make blind vias at positions different from the blind vias on the previous layer of the outer circuit board on the outer circuit board.

[0024] In a second aspect, an embodiment of the present application provides a multi-layer and multi-order printed circuit board, characterized in that it is made by using the impedance testing method of the multi-layer and multi-order printed circuit board according to any one of the first aspect.

[0025] In a possible implementation manner, the through hole is not resin-sealed; the blind via is located at the edge of the through hole PAD.

[0026] In a possible implementation manner, the through hole is resin-sealed; the blind via is located at the edge of the through hole PAD.

[0027] In a possible implementation, resin plugging is performed on the through holes; the blind holes are located on the through hole PADs.

[0028] The impedance testing method and circuit board of the multi-layer and multi-order printed circuit board provided by the embodiments of the present application make through holes on the inner layer circuit board, and test the impedance of the inner layer circuit board through the through holes. By testing the impedance of the inner layer circuit board, it is ensured that the circuit board can work normally, improving the performance and reliability of the electronic device. After adding an outer layer circuit board to the outer layer circuit board each time, based on the through hole PADs, blind holes are made on the outer layer circuit board, and test PADs are made using the blind holes, and the impedance of the added outer layer circuit board is tested. When adding layers, the impedance of the current layer can be measured in a timely manner, without waiting until the finished product to measure the impedance. The actual impedance of each layer can be measured, and then the line width production can be adjusted according to the actual measured impedance value, and defective boards can be picked out and scrapped in a timely manner, reducing the impedance scrap rate of the final finished product, improving production efficiency and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0030] Figure 1 Schematic flow chart of the impedance testing method of the multi-layer and multi-order printed circuit board provided by the embodiments of the present application Figure 1 ;

[0031] Figure 2 Schematic flow chart of the impedance testing method of the multi-layer and multi-order printed circuit board provided by the embodiments of the present application Figure 2 ;

[0032] Figure 3 Schematic structural diagram of the stacked blind hole multi-layer and multi-order printed circuit board provided by the embodiments of the present application;

[0033] Figure 4 Schematic structural diagram of the misaligned stacked blind hole multi-layer and multi-order printed circuit board provided by the embodiments of the present application;

[0034] Figure 5 Schematic structural diagram of the finished multi-layer and multi-order printed circuit board provided by the embodiments of the present application;

[0035] Through the above-mentioned drawings, the clear embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0037] UHD products are mainly applied to artificial intelligence and involve fields such as data centers and autonomous driving. The application scenarios are relatively stable and are usually applied in various scenarios such as deep learning, scientific computing, and video encoding and decoding. From the perspective of future market development prediction, the computing power demand brought by pre-trained large models drives the rapid growth of the artificial intelligence server market. Artificial intelligence servers are the fastest-growing segment in the server industry. With the rapid development of artificial intelligence technology, it puts forward higher requirements for data processing capabilities, transmission speeds, and energy efficiency ratios. Especially in fields such as deep learning and high-performance computing, AI servers and data centers, as the core infrastructure to support AI applications, their performance and efficiency are directly related to the wide application and industrial development of AI technology.

[0038] In the prior art, the impedance detection method for multi-layer and multi-order printed circuit boards is to simulate impedance production by controlling the line width during inner layer production and then measure the impedance through an impedance test module at the final finished product. This type of production method has the following risks:

[0039] 1. When producing the pattern of multi-layer and multi-order printed circuit boards, since the data cannot be accurately measured, the impedance lines can only be controlled according to the median value. The factors affecting impedance printing include the thickness of the dielectric layer, the dielectric constant of the material, the copper thickness, the spacing, and the line width. Since the thickness of the dielectric layer, the dielectric constant of the material, and the copper thickness are fixed during the production of the pattern circuit, when the impedance cannot be measured, only by taking values through slicing and then simulating the impedance, and controlling the line width within a reasonable range that meets both line width control and impedance control, it takes a long time and production boards need to be scrapped.

[0040] 2. It is impossible to monitor in a timely manner whether the impedance meets the requirements. Only when the final product is completed, the impedance is detected by testing the impedance strip. When it is found that the impedance is defective and needs to be scrapped at the final finished product, a large amount of time, manpower, and financial resources are wasted in the middle, and it also affects the delivery.

[0041] 3. It is impossible to 100% detect impedance data online, and there is a risk that impedance defective boards will flow to subsequent processes, increasing the scrapping cost.

[0042] To solve the above technical problems, the following technical conceptions are proposed: Since the impedance testing equipment can test the impedance value of the finished multi-layer and multi-order printed circuit board based on the through-hole, the inventor thought that a unique "through-hole" can be designed on each layer of the circuit board during the production of each additional layer, so that the impedance testing equipment can test the impedance value of the current layer of the circuit board through this blind hole, thereby measuring the impedance values of all circuit boards. Furthermore, the line width production can be adjusted according to the actual measured impedance value, and defective boards can be promptly selected and scrapped, reducing the impedance scrap rate of the final product, improving production efficiency and reducing costs.

[0043] The following uses specific embodiments to elaborate in detail on the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems. These several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0044] Figure 1 Flow schematic of the impedance testing method for the multi-layer and multi-order printed circuit board provided by the embodiment of the present application Figure 1 , as Figure 1 shown, the method includes:

[0045] S101. Press n inner core boards to obtain an inner-layer circuit board, where n is an integer greater than or equal to 2.

[0046] Among them, the inner core board is a thin copper-clad laminate with an etched circuit, and the surface is blackened to enhance the bonding force. Arrange the n inner core boards in a preset order, place the arranged n inner core boards into a laminator, and press the n inner core boards to obtain an inner-layer circuit board.

[0047] S102. Make through-holes on the inner-layer circuit board and make via pads PAD using the through-holes.

[0048] Among them, before manufacturing, it is necessary to determine the position, size of the through-hole, and the shape and size of the pad PAD in the circuit board design file according to the circuit design requirements. The diameter of the through-hole is usually determined according to the thickness of the component pins or connecting wires to be inserted, while the size of the pad PAD needs to consider factors such as welding reliability and the spacing from the surrounding circuit. Use drilling equipment to drill corresponding through-holes on the inner-layer circuit board according to the position and size of the through-holes determined in the design file. During the drilling process, parameters such as the rotation speed and feed speed of the drill bit need to be reasonably adjusted according to the material and thickness of the circuit board to ensure the accuracy and quality of drilling and avoid problems such as rough hole walls and burrs. Deposit a layer of metal on the hole wall of the through-hole through electroplating process to make the through-hole have good electrical conductivity and form an electrical connection. After completing the electroplated through-holes, use photolithography, etching and other processes to make pads PAD connected to the through-holes on the copper foil layer on the surface of the circuit board.

[0049] In a possible implementation, after through-hole electroplating, the through-holes are filled by means of resin plugging or pressure filling with glue.

[0050] S103. Test the impedance of the inner-layer circuit board through the through-holes.

[0051] Specifically, connect the through-hole PAD to the test circuit, and use an impedance test device to send a test signal to the through-hole, so that the through-hole reflects a reflected signal based on the test signal; use the impedance test device to calculate and obtain the impedance value of the inner-layer circuit board based on the test signal and the reflected signal.

[0052] S104. Sequentially add outer-layer circuit boards on the basis of the inner-layer circuit board.

[0053] Specifically, stack the outer-layer circuit board on the inner-layer circuit board and put it into a vacuum laminator for lamination, and then sequentially add outer-layer circuit boards.

[0054] S105. After adding each outer-layer circuit board on the outer-layer circuit board, make blind holes on the outer-layer circuit board based on the through-hole PAD, and use the blind holes to make test PADs, and perform impedance testing on the added outer-layer circuit board.

[0055] Specifically, according to the preset circuit design requirements, determine the position, size and quantity of the blind holes. Use a high-precision CNC drill to drill holes based on the through-hole PAD according to the designed position and depth of the blind holes. Deposit a layer of metal on the hole wall of the blind hole through electroplating process to make the blind hole have good electrical conductivity. After completing the electroplated blind holes, use photolithography and etching processes to make test PADs, and perform impedance testing on the added outer-layer circuit board.

[0056] Among them, impedance testing is performed on the outer circuit board of the additional layer, including the following steps S1051 - S1053:

[0057] S1051. Connect the second outer circuit board and the outer circuit board through blind vias, and connect the test PAD and the test circuit to establish electrical connection between the second outer circuit board and the outer circuit board.

[0058] Specifically, connect the second outer circuit board and the outer circuit board based on the form of through - hole laser blind vias, connect the test PAD and the test circuit, and use a multimeter or other conductivity testing equipment to perform conductivity testing on the connection between the second outer circuit board and the outer circuit board connected by blind vias and the connection between the test PAD and the test circuit. Check for open - circuit phenomena to ensure the reliability of the electrical connection and establish the electrical connection between the second outer circuit board and the outer circuit board.

[0059] S1052. Use an impedance testing device to send a test signal to the blind via, so that the blind via reflects a reflected signal based on the test signal to the test circuit; use the impedance testing device to calculate and obtain the impedance value of the outer circuit board based on the test signal and the reflected signal.

[0060] Specifically, before testing, the impedance testing device needs to be calibrated to ensure its measurement accuracy. Connect the output port of the impedance testing device to the corresponding test point of the blind via through a test probe or fixture, set the parameters of the impedance testing device, such as the frequency range, power, scanning mode, etc. of the test signal, and send the test signal to the blind via. When the test signal is transmitted through the blind via to the test circuit, due to factors such as impedance mismatch, part of the signal will be reflected back. The receiving port of the impedance testing device will capture these reflected signals, and the impedance testing device calculates and obtains the impedance value of the outer circuit board based on information such as the amplitude and phase of the test signal and the reflected signal.

[0061] S1053. Generate an impedance test result based on the impedance value.

[0062] Specifically, after obtaining the impedance value of the outer circuit board, compare it with the impedance value of the preset design requirements. If the impedance value of the outer circuit board is within the allowable tolerance range, it indicates that the electrical performance of the outer circuit board meets the requirements; if the impedance value of the outer circuit board exceeds the tolerance range, it is necessary to further analyze the reasons, which may be problems with the manufacturing process of the blind via, test connection problems, or differences in the material characteristics of the circuit board, etc., and take corresponding measures for adjustment and improvement.

[0063] S106. Continue to add a new outer circuit board to the outer circuit board and repeat the steps of impedance testing for each new outer circuit board until the addition of all outer circuit boards is completed, obtaining a finished multi - layer and multi - order printed circuit board.

[0064] Specifically, repeat the above steps S104 - S105 to continue adding new outer - layer circuit boards to the outer - layer circuit board, and repeat the impedance - testing step for each new outer - layer circuit board until all outer - layer circuit boards are added, obtaining a finished multi - layer and multi - order printed circuit board.

[0065] In the embodiment of the present application, vias are made on the inner - layer circuit board, and the impedance of the inner - layer circuit board is tested through the vias. By testing the impedance of the inner - layer circuit board, it is ensured that the circuit board can work properly, improving the performance and reliability of the electronic device. After adding each outer - layer circuit board to the outer - layer circuit board, based on the via PAD, blind vias are made on the outer - layer circuit board, and test PADs are made using the blind vias, and the impedance of the added outer - layer circuit board is tested. When adding layers, the impedance of the current layer can be measured in a timely manner, without waiting until the finished product to measure the impedance. The actual impedance of each layer can be measured, and then the line width production can be adjusted according to the actual measured impedance value, and defective boards can be picked out and scrapped in a timely manner, reducing the impedance scrap rate of the final product, improving production efficiency and reducing costs.

[0066] Figure 2 is a schematic flow chart of the impedance - testing method for the multi - layer and multi - order printed circuit board provided by the embodiment of the present application Figure 2 , as Figure 2 shown, the method includes:

[0067] S201. Press n inner - layer core boards together to obtain an inner - layer circuit board, where n is an integer greater than or equal to 2.

[0068] S202. Make vias on the inner - layer circuit board and make via pads PAD using the vias.

[0069] S203. Test the impedance of the inner - layer circuit board through the vias.

[0070] S204. Sequentially add outer - layer circuit boards on the basis of the inner - layer circuit board.

[0071] It should be noted that the specific implementation manners of steps S201 to S204 can refer to the specific implementation manners of steps S101 to S104, and will not be elaborated here too much.

[0072] S205. After adding each outer - layer circuit board to the outer - layer circuit board, based on the via PAD and according to the positions of the blind vias on the previous outer - layer circuit board, make blind vias on the outer - layer circuit board, and make test PADs using the blind vias, and test the impedance of the added outer - layer circuit board.

[0073] Among them, whether to make resin - filled vias for the vias, and the relative relationship between the blind vias and the via PAD has the following modes, including:

[0074] Mode 1, where the through holes are not resin plugged; and the blind holes are located at the edges of the through hole PADs.

[0075] Mode 2, where the through holes are resin plugged; and the blind holes are located at the edges of the through hole PADs.

[0076] Mode 3, where the through holes are resin plugged; and the blind holes are located on the through hole PADs.

[0077] Among them, blind holes are made on the outer layer circuit board, including the following two cases:

[0078] Case 1: According to the positions of the blind holes on the previous outer layer circuit board, blind holes are made on the outer layer circuit board corresponding to the positions of the blind holes on the previous outer layer circuit board.

[0079] Exemplarily, as Figure 3 shown, Figure 3 is the structural schematic diagram of the stacked blind hole multi-layer multi-order printed circuit board provided by the embodiment of the present application. As Figure 3 shown, all the blind holes are stacked at the same position.

[0080] Case 2: According to the positions of the blind holes on the previous outer layer circuit board, blind holes are made on the outer layer circuit board at positions different from those of the blind holes on the previous outer layer circuit board.

[0081] Exemplarily, as Figure 4 shown, Figure 4 is the structural schematic diagram of the misaligned stacked blind hole multi-layer multi-order printed circuit board provided by the embodiment of the present application. As Figure 4 shown, all the blind holes are stacked at different positions.

[0082] Among them, impedance testing of the added outer layer circuit board includes the following steps S2051 - S2053:

[0083] S2051: Connect the sub - outer layer circuit board and the outer layer circuit board through the blind holes, and connect the test PAD and the test circuit to establish the electrical connection between the sub - outer layer circuit board and the outer layer circuit board.

[0084] S2052: Use the impedance testing device to send a test signal to the blind hole, so that the blind hole reflects a reflected signal based on the test signal; use the impedance testing device to calculate and obtain the impedance value of the outer layer circuit board based on the test signal and the reflected signal.

[0085] S2053: Generate an impedance test result according to the impedance value.

[0086] It should be noted that the specific implementation manners of steps S2051 to S2053 can refer to the specific implementation manners of steps S1051 to S1053, and will not be elaborated here too much.

[0087] S206. Continue to add a new outer circuit board to the outer circuit board, and repeat the impedance test steps for each new outer circuit board until all outer circuit boards are added to obtain a finished multi-layer and multi-order printed circuit board.

[0088] Exemplarily, the finished multi-layer and multi-order printed circuit board is as Figure 5 shown. Figure 5 FIG. is a schematic structural diagram of the finished multi-layer and multi-order printed circuit board provided by the embodiment of the present application. As Figure 5 shown, the relatively larger white holes are through holes, and the relatively smaller white holes are blind holes.

[0089] In the embodiment of the present application, through holes are made on the inner circuit board, and the impedance of the inner circuit board is tested through the through holes. By testing the impedance of the inner circuit board, it is ensured that the circuit board can work normally, and the performance and reliability of the electronic device are improved. When a signal propagates on a transmission line with mismatched impedance, problems such as reflection, attenuation, and distortion will occur, affecting the integrity and accuracy of the signal. After adding each layer of outer circuit board to the outer circuit board, based on the through hole PAD, blind holes are made on the outer circuit board, and test PADs are made using the blind holes, and the impedance of the added outer circuit board is tested. The impedance of the current layer can be measured in a timely manner during the addition process, without waiting until the finished product to measure the impedance. The actual impedance of each layer can be measured, and then the line width production can be adjusted according to the actual measured impedance value, and defective boards can be picked out and scrapped in a timely manner, reducing the impedance scrap rate of the final product, improving production efficiency and reducing costs.

[0090] In addition, the embodiment of the present application provides a variety of design patterns for through holes and blind holes, which can match printed circuit boards with different types of designs.

[0091] Finally, it should be noted that those skilled in the art will readily think of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A method for impedance testing of a multi-layer and multi-order printed circuit board, characterized in that, Including: Pressing n inner core boards to obtain an inner circuit board, where n is an integer greater than or equal to 2; Making vias on the inner circuit board and making via pads PAD using the vias; Testing the impedance of the inner circuit board through the vias; Successively adding outer circuit boards on the basis of the inner circuit board; After adding each layer of outer circuit board, making blind vias on the outer circuit board based on the via PAD, and making test PADs using the blind vias, and performing impedance testing on the added outer circuit board; Among them, performing impedance testing on the added outer circuit board includes: Connecting the sub-outer circuit board and the outer circuit board through the blind via, and connecting the test PAD and the test circuit to establish the electrical connection between the sub-outer circuit board and the outer circuit board; Using an impedance testing device to send a test signal to the blind via, so that the blind via reflects a reflected signal based on the test signal; using the impedance testing device to calculate and obtain the impedance value of the outer circuit board based on the test signal and the reflected signal; Generating an impedance test result according to the impedance value; Continuing to add new outer circuit boards on the outer circuit board and repeating the steps of the impedance test for each new layer of outer circuit board until all layers of outer circuit boards are added to obtain a finished multi-layer and multi-order printed circuit board.

2. The method according to claim 1, wherein Wherein the via is not resin-plugged; wherein the blind via is located at the edge of the via PAD.

3. The method according to claim 1, wherein Wherein the via is resin-plugged; wherein the blind via is located at the edge of the via PAD.

4. The method according to claim 1, wherein Wherein the via is resin-plugged; wherein the blind via is located on the via PAD.

5. The method according to any one of claims 1 to 4, characterized in that, Making the blind via on the outer circuit board includes: Making a blind via on the outer circuit board at a position corresponding to the blind via on the previous layer of outer circuit board according to the position of the blind via on the previous layer of outer circuit board.

6. The method according to any one of claims 1 to 4, characterized in that, Making the blind via on the outer circuit board includes: Making a blind via on the outer circuit board at a position different from the blind via on the previous layer of outer circuit board according to the position of the blind via on the previous layer of outer circuit board.

7. A multi-layer and multi-stage printed circuit board, characterized in that, Obtained by using the impedance testing method for multi-layer and multi-order printed circuit boards according to any one of claims 1 to 6.

8. The multi-layer and multi-stage printed circuit board according to claim 7, wherein Wherein the via is not resin-plugged; wherein the blind via is located at the edge of the via PAD.

9. The multilayer and multi-stage printed circuit board according to claim 7, characterized in that, Wherein the via is resin-plugged; wherein the blind via is located at the edge of the via PAD.

10. The multilayer and multi-stage printed circuit board according to claim 7, characterized in that, Wherein the via is resin-plugged; wherein the blind via is located on the via PAD.

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