On-off test interface board, channel corresponding relation automatic generation method and storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses an on-off test interface board, a channel corresponding relation automatic generation method and a storage medium, a plurality of square test areas with the same center are arranged on the test interface board, and the square test areas are increased in equal proportion from inside to outside along the diagonal line of the test interface board; the outer side of each square test area is connected with bonding pads with the same number, the bonding pads are evenly distributed at equal intervals, the other ends of the bonding pads are arranged outside the test interface board, and the bonding pads connected with the square test areas on the inner side penetrate through the square test areas on the outer side. The bonding pads are located between the bonding pads connected with the square test areas on the outer side; through special layout of the bonding pads, the test interface board is compatible with to-be-tested chips of various types and various specifications and models, and meanwhile, through the corresponding relation between the bonding pads and the channels, the overall efficiency of chip testing is improved, the accuracy of complex packaging testing is ensured, and the automation testing degree is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to an on-off test interface board, an automatic generation method for channel correspondence, and a storage medium. Background Art

[0002] With the rapid development of semiconductor technology, the chip packaging forms are becoming increasingly diverse, including QFN (Quad Flat No-lead Package), DFN (Dual Flat No-lead Package), DIP (Dual In-line Package), and SIP (System-in-Package), etc. These packaging forms have significant differences in size, pin layout, and electrical characteristics, posing challenges to semiconductor testing. QFN packaged chips are compact in size and have a small pin pitch, which can effectively save circuit board space and are suitable for portable electronic devices with strict space requirements; while DIP packaged chips are relatively large in size and have a large pin pitch, which is convenient for manual soldering and debugging and are commonly used in some traditional electronic devices that are cost-sensitive and have low space requirements. In terms of pin layout, the pins of QFN packaging are distributed around the chip in a flat shape; DFN packaging is similar to QFN, but there are slight differences in pin shape and arrangement; the pins of DIP packaging are in a dual in-line plug-in form and are arranged regularly; as a system-in-package, SIP packaging integrates multiple chips or circuits with different functions, and the pin layout is more complex and may include various types of pins to achieve electrical connection and signal transmission between different chips. In terms of electrical characteristics, chips of different packaging forms also vary in signal transmission speed, power consumption, anti-interference ability, etc. High-speed signal transmission poses higher requirements on the electrical performance of chip packaging. For example, in PCIe Gen5 testing, the signal frequency is as high as several GHz, and problems such as reflection and crosstalk during signal transmission need to be strictly controlled, which requires the chip packaging to have good impedance matching and differential equal-length wiring.

[0003] Traditional test interface boards (LoadBoards) are usually designed for a single packaging type, difficult to be compatible with multiple packages, and require a large amount of manual configuration when adapting to different packages, resulting in low efficiency. When facing the chip testing requirements of different packaging types, traditional test interface boards are difficult to be compatible and need to be frequently replaced with different test interface boards, increasing the test cost and time cost. Moreover, when adapting to different packages, a large amount of manual configuration is often required, such as adjusting the connection of test channels, setting test parameters, etc. This kind of manual operation is not only inefficient but also prone to errors, making it difficult to meet the large-scale and high-efficiency chip testing requirements.

[0004] In addition, with the increase in packaging density and the improvement of signal frequency, the electrical performance and signal integrity of test channels become particularly important. For example, high-speed signal testing requires strict impedance matching and differential equal-length wiring. At the same time, the demand for automation in multi-channel testing is also becoming increasingly prominent. For example, an RF switch matrix is introduced in PCIe Gen5 testing to achieve dynamic switching of multiple channels.

[0005] In the field of semiconductor packaging testing, automated and intelligent testing tools are gradually becoming the trend. For example, automatically generating the mapping relationship of test channels through software tools can significantly reduce the manual configuration time. In addition, the emergence of new packaging technologies such as 3D packaging and multi-chip packaging has further promoted the innovation of testing technologies.

[0006] However, the existing technologies still have deficiencies in terms of multi-package compatibility, channel mapping efficiency, and automation level. Therefore, it is of great practical significance to develop a test interface board that can be compatible with multiple package types, automatically adapt to different package sizes, and automatically generate channel mapping. Summary of the Invention

[0007] Aiming at the deficiencies of the existing technologies, the purpose of the present invention is to provide an on-off test interface board, a method for automatically generating channel correspondence relationships, and a storage medium.

[0008] To achieve the above purpose, the present invention provides the following technical solutions: An on-off test interface board, on which a number of square test areas with the same center are provided. The square test areas increase proportionally from the inside to the outside along the diagonal of the test interface board. The outside of each square test area is connected to the same number of pads, and the pads are evenly distributed at equal intervals. The other ends of the pads are arranged outside the test interface board. Among them, the pads connected to the inner square test area pass through the outer square test area, and the pads connected to the inner square test area are located between the pads connected to the outer square test area.

[0009] In the present invention, preferably, mounting holes are provided on the diagonal of the test interface board.

[0010] In the present invention, preferably, the test interface board is further provided with positioning holes, and the positioning holes are set as an asymmetric mechanism to ensure the correct installation of the chip.

[0011] In the present invention, preferably, the pads are rectangular strips and are made of metal.

[0012] In the present invention, preferably, the pads are circular structures and are evenly distributed in each square test area of the test interface board.

[0013] In the present invention, preferably, each of the pads is correspondingly connected to a unique tester channel, and each of the pads has a channel correspondence relationship set in the tester.

[0014] A method for automatically generating a channel correspondence relationship includes the steps of: Placing the chip to be tested on the test interface board, making the pins of the chip to be tested electrically connected to the pads, and the pads are electrically connected to the tester through channels; The tester starts the test, and at the same time, based on the coordinate matching of the pads, automatically associates the relationship between the pins of the test chip and the test channels; After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated.

[0015] In the present invention, preferably, a matrix switch circuit is further connected between the channel and the tester.

[0016] In the present invention, preferably, when the number of pins of the chip to be tested is less than the maximum connection size of the test interface board, the pin coordinates of the chip to be tested are converted into the LoadBoard coordinate system: X LoadBoard = X MinPackage +Δ X Y LoadBoard = Y MinPackage +Δ Y , where ΔX and ΔY are the offset amounts of the chip to be tested in the X-axis and Y-axis directions on the test interface board, X MinPackage and Y MinPackage are the base amounts in the X-axis and Y-axis directions of the test interface board to be tested.

[0017] Compared with the prior art, the beneficial effects of the present invention are: The test interface board of the present invention is provided with test areas of multiple sizes. By specially arranging the pads, the test interface board is made to be compatible with various types and specifications of chips to be tested. At the same time, through the correspondence relationship between the pads and the channels, the overall efficiency of chip testing is improved, the accuracy of complex packaging testing is ensured, and the degree of automation testing is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of the test interface board described in the present invention.

[0019] Figure 2 It is another schematic structural diagram of the test interface board described in the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0022] Please refer to Figure 1 , in an actual chip test scenario, the design of the test interface board needs to fully consider the diversity and complexity of different chip package types. A preferred embodiment of the present invention provides a continuity test interface board, on which a number of square test areas with the same center are provided, and the square test areas increase proportionally from the inside to the outside along the diagonal of the test interface board. This layout is designed based on in-depth research on the size and pin distribution rules of various chip packages. For example, common package forms such as QFN, DFN, DIP, and SIP have large differences in size, pin layout, and electrical characteristics, but through the design of this multi-size test area, chips with different pin numbers under the same package form can be effectively compatible. The outside of each square test area is connected to the same number of pads, and the pads are evenly distributed at equal intervals. The other end of the pads is arranged outside the test interface board, and the pads connected to the inner square test area pass through the outer square test area and are located between the pads connected to the outer square test area. The test interface board is determined according to the maximum size of QFN or QFP devices, so that the test interface board can be applicable to more specifications of chips. The width of the pads is also determined according to the maximum size. The overall arrangement of the pads is longer inside and shorter outside. The pads near the square test area in the middle position are longer than those in the outer square test area to adapt to chips with different pin numbers under the same package and improve the test efficiency. The outside of each square test area is connected to the same number of pads, and the pads are evenly distributed at equal intervals, which can ensure that chips with different pin numbers can be tested on the same test interface board. At the same time, the uniform distribution and connection method of the pads ensure the reliability and consistency of electrical connection and improve the accuracy and efficiency of chip testing. Specifically, taking a QFN packaged chip as an example, its pins are usually distributed around the chip, and the pin pitch is small. On this test interface board, the inner square test area can accommodate QFN chips with fewer pins. The pads connected to it penetrate through the outer square test area and are located between the outer pads. The outer square test area can accommodate QFN chips with more pins. Such a layout can flexibly adjust the connection positions with the chip pins. For DIP packaged chips with a larger pin pitch, the pitch between the pads of this test interface board is increased to accommodate the DIP packaged chips. The inner and outer square test areas with multiple sizes and the pads connected to them can be used to accommodate the pins of the DIP packaged chips.

[0023] In this embodiment, mounting holes are provided on the diagonal of the test interface board. The mounting holes can adopt standardized sizes and shapes, such as common circular or square shapes, to ensure compatibility with existing fixing devices. The mounting holes can also adopt the size of the largest compatible package. The positions of the mounting holes are set on the diagonal, which can provide a more stable fixing effect and avoid the test interface board from shifting or loosening during use. The number and positions of the mounting holes can be adjusted according to actual needs to adapt to test interface boards of different sizes and shapes. The material and processing technology of the mounting holes can be selected from durable and non-deformable materials to ensure the reliability of long-term use. Through the design of setting the mounting holes on the diagonal, the test interface board is more convenient and efficient during the fixing and installation process with the testing machine, reducing the complexity of manual operation and making the test interface board show higher reliability and usability in practical applications.

[0024] Specifically, when performing chip testing, the test interface board usually needs to be installed at a specific position on the test device and fixed using screws or other fixing parts through the mounting holes. The number of mounting holes is generally 2 - 4, which is adjusted according to the size and shape of the test interface board. For a test interface board with a smaller size, 2 mounting holes may be sufficient to ensure its stability; while for a larger test interface board, 4 mounting holes may be required. The material of the mounting holes is generally selected from high-strength metal materials such as aluminum alloy or stainless steel. These materials have good wear resistance and corrosion resistance, which can ensure that the mounting holes are not easily deformed during long-term use and ensure that the fixing effect of the test interface board is always stable and reliable.

[0025] In this embodiment, the test interface board is also provided with positioning holes. The positioning holes are set outside the test area. In actual operation, if the installation direction of the chip is incorrect, it will not only lead to inaccurate test results, but may also damage the chip or the test interface board. The positioning holes are set as an asymmetric mechanism to ensure the correct installation of the chip, thereby avoiding problems such as test failure or damage caused by incorrect installation.

[0026] Specifically, one common implementation is to design two positioning holes, one circular and the other elliptical. This is for the chip to be tested with circular and elliptical positioning grooves, so that the chip to be tested can only be fitted with the test interface board in one correct direction during installation.

[0027] Specifically, another implementation is to set specific protrusions or grooves around the positioning holes. This is for chips with matching grooves or protrusions. Through the limitation of this physical structure, the correct installation of the chip is ensured. During the production process, high requirements are placed on the dimensional accuracy and position accuracy of the positioning holes. Generally, the diameter tolerance of the positioning holes is controlled within ±0.05 mm, and the position accuracy is controlled within ±0.1 mm to ensure the accuracy of chip installation.

[0028] In this implementation, the asymmetric design of the positioning holes can be achieved in various ways. Through this design, the chip can only be fitted with the test interface board in one correct direction during installation, thus avoiding the possibility of incorrect installation. Through simple physical structure design, the correct installation of the chip is ensured, the reliability and efficiency of the test are improved, and the risks of test failure and equipment damage caused by incorrect installation are reduced.

[0029] In this implementation, the pad is rectangular and strip-shaped and is made of a metal material. Using a rectangular strip-shaped pad can provide a larger contact area, thus improving the stability and reliability of electrical connection.

[0030] Specifically, the design of the pads has an important impact on the electrical performance and reliability of the test. When using rectangular strip-shaped pads, the design of their length and width needs to be optimized according to the size and electrical requirements of the chip pins. Generally, the length can be between 1 - 3 mm, and the width can be between 0.2 - 0.5 mm. Such dimensions can provide a larger contact area, thus improving the stability and reliability of electrical connection. In the manufacturing process, the rectangular strip-shaped pads can be made by the etching process of a printed circuit board (PCB), and the etching accuracy is controlled within ±0.05 mm to ensure the accuracy of the pad size.

[0031] Please refer to Figure 2 , in this implementation, the pads are circular structures and are evenly distributed in each square test area of the test interface board. The pads are evenly distributed in each square test area, which helps to optimize the pad distribution structure, ensure the uniform position of each pad on the test interface board, and avoid electrical performance problems caused by uneven pad shape or distribution. In this way, the versatility and test accuracy of the test interface board can be improved to meet the test requirements of different specifications and forms of ball grid array (BGA) packages.

[0032] Specifically, for circular pads, they are evenly distributed in each square test area. The diameter of the circular pads is generally between 0.3 - 0.8 mm. Through precise wiring technology and manufacturing processes such as laser cutting, it is ensured that each pad is evenly distributed in each square test area. In practical applications, circular pads are suitable for testing ball grid array (BGA) packaged chips. The pins of BGA packaged chips are distributed in a spherical shape at the bottom of the chip, and circular pads can better make electrical connections with these pins. When designing the distribution of circular pads, the pitch and layout of the chip pins need to be considered to ensure accurate connections between the pads and the pins.

[0033] Specifically, circular pads can be realized through precise wiring technology to ensure that each pad is evenly distributed in each square test area. Technologies such as laser cutting can be used to manufacture circular pads to ensure the precise shape and smooth edges of the pads. In addition, the material of the circular pads is selected as a metal with excellent electrical conductivity to ensure good electrical connection performance. The evenly distributed circular pads improve the electrical performance and test accuracy of the test interface board, have higher versatility, and can adapt to the test requirements of various different package forms.

[0034] In this embodiment, each of the pads is correspondingly connected to a unique test machine channel, and a channel correspondence relationship is set for each of the pads in the test machine. Through the channel correspondence relationship, the pins of the chip under test connected to the pads can be located to ensure the accuracy and reliability of the test.

[0035] Specifically, each pad is correspondingly connected to a unique test machine channel, and a channel correspondence relationship is set in the test machine. During the actual test process, when the chip under test is placed on the test interface board and its pins are electrically connected to the pads, the test machine starts the test. The software system inside the test machine automatically associates the relationship between the pins of the test chip and the test channels based on the coordinate matching of the pads. For example, the test machine determines the test channel corresponding to each pin by reading the X and Y coordinate information of the pads on the test interface board and comparing it with the pre-stored chip pin coordinate information. After obtaining the package parameters of the chip under test, the test machine generates a channel relationship mapping table. The package parameters include information such as the number of pins, pin pitch, and pin layout of the chip. Through these parameters, the test machine can generate the channel relationship mapping table more accurately. The channel relationship mapping table is presented in the form of a spreadsheet, which contains information such as pin numbers, pad numbers, and test channel numbers, facilitating the test personnel to view and analyze.

[0036] Another preferred embodiment of the present invention is a method for automatically generating a channel correspondence relationship, including the steps of: Place the chip to be tested on the test interface board, making the pins of the chip to be tested electrically connected to the pads, and the pads are electrically connected to the testing machine through channels; The testing machine starts the test, and at the same time, based on the coordinate matching of the pads, automatically associates the relationship between the pins of the test chip and the test channels; After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated.

[0037] Specifically, place the chip to be tested on the test interface board, making the pins of the chip to be tested electrically connected to the pads, and the pads are electrically connected to the testing machine through channels, realizing the preliminary connection between the chip and the testing machine. After the testing machine starts the test, based on the coordinate matching of the pads, it automatically associates the relationship between the pins of the test chip and the test channels, thus realizing the automatic generation of the test channel relationship. After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated. This automatic matching and generation of the channel relationship mapping table solves the technical problem of the automatic generation of the relationship between the chip pins and the test channels, reduces the manual configuration time, and improves the test efficiency and accuracy. At the same time, a detailed mapping table is generated, which can be saved in the form of an electronic file for subsequent test and analysis.

[0038] In this embodiment, a matrix switch circuit is also connected between the channels and the testing machine to improve the test efficiency and accuracy. The matrix switch circuit is connected between the channels and the testing machine. By using the matrix switch circuit, dynamic switching between multiple channels and the testing machine can be achieved. This design can flexibly select and switch test channels according to needs during the test process, improving the test efficiency and accuracy, and is particularly suitable for multi-channel test scenarios. The application of the matrix switch circuit makes the automatic generation of the channel mapping relationship more efficient, reduces the need for manual intervention, and improves the automation degree of the test. The matrix switch circuit can be designed as an N×M matrix structure, where N and M represent the number of input and output channels respectively. By controlling the switch states in the matrix, the connection between any input channel and output channel can be realized.

[0039] Specifically, the matrix switch circuit is usually designed as an N×M matrix structure, such as an 8×8 or 16×16 matrix. During the test, according to the test requirements, by controlling the switch states in the matrix, the connection between any input channel and output channel can be realized. When it is necessary to test the electrical performance of multiple different pins, the test channels can be quickly switched through the matrix switch circuit, avoiding the cumbersome operation of frequently changing test lines in the traditional test method. The control of the matrix switch circuit can be realized through the software system inside the testing machine. The tester only needs to set the corresponding test parameters in the test software, and the software system will automatically control the switching of the matrix switch circuit.

[0040] Specifically, when the number of pins of the chip under test is less than the maximum connection size of the test interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system: X LoadBoard = X MinPackage +Δ X Y LoadBoard = Y MinPackage +Δ Y , where ΔX and ΔY are the offset amounts of the chip under test in the X-axis and Y-axis directions on the test interface board, X MinPackage and Y MinPackage are the base amounts in the X-axis and Y-axis directions of the test interface board to be tested. When the number of pins of the chip under test is less than the maximum connection size of the test interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system by calculating X LoadBoard and Y LoadBoard to achieve. This method ensures that the pins of the chip under test can be correctly mapped to the pad positions of the test interface board, thus achieving precise electrical connection. ΔX and ΔY represent the offset amounts of the chip under test in the X-axis and Y-axis directions on the test interface board, and X MinPackage and Y MinPackage represent the base amounts of the test interface board in the X-axis and Y-axis directions. Through this coordinate conversion, it can flexibly adapt to chips of different sizes and pin layouts, solve the connection problems caused by insufficient pin numbers, and improve the compatibility and accuracy of testing.

[0041] Specifically, in actual operation, first determine the placement position of the chip under test on the test interface board. Based on the position of the first pin in the upper left corner of the chip under test, the tester calculates the offset amounts ΔX and ΔY in the X-axis and Y-axis directions. X MinPackage and Y MinPackage are the base amounts in the X-axis and Y-axis directions of the test interface board to be tested, and these base amounts can be obtained from the design drawings of the test interface board or actual measurement. For example, for a specific test interface board, X MinPackage may be 10 mm, and Y MinPackage may be 15 mm. By calculating X LoadBoard = X MinPackage + ΔX and Y LoadBoard = Y MinPackage + ΔY to convert the pin coordinates of the chip under test into coordinates in the LoadBoard coordinate system, so as to ensure that the pins of the chip under test can be correctly mapped to the pad positions of the test interface board and achieve precise electrical connection.

[0042] In some other preferred embodiments of the present invention, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the processor is caused to execute the steps of the method as described in the above embodiments.

[0043] If the above functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical disks, etc., which can store program codes.

[0044] The above description is a detailed description of the preferred and feasible embodiments of the present invention, but the embodiments are not intended to limit the scope of the patent application of the present invention. Any equivalent changes or modifications made under the technical spirit disclosed by the present invention should fall within the scope of the patent covered by the present invention.

Claims

1. On-off test interface board, characterized in that, A number of square test areas with the same center are provided on the test interface board. The square test areas increase proportionally from the inside out along the diagonal of the test interface board. The same number of pads are connected to the outside of each square test area. The pads are evenly distributed at equal intervals. The other ends of the pads are located outside the test interface board. Among them, the pads connected to the inner square test area pass through the outer square test area, and the pads connected to the inner square test area are located between the pads connected to the outer square test area.

2. The on-off test interface board according to claim 1, characterized in that, Mounting holes are provided on the diagonal of the test interface board.

3. The on-off test interface board according to claim 2, characterized in that, The test interface board is further provided with positioning holes.

4. The on-off test interface board according to claim 1, characterized in that, The pads are rectangular strips and are made of metal.

5. The on-off test interface board according to claim 1, wherein Each pad is correspondingly connected to a unique test machine channel, and each pad has a channel correspondence relationship set in the test machine.

6. A method for automatically generating channel correspondence relationships, using the on-off test interface board according to any one of claims 1-5, characterized in that, Including the steps: Place the chip to be tested on the test interface board so that the pins of the chip to be tested are electrically connected to the pads, and the pads are electrically connected to the test machine through channels; The test machine starts the test, and at the same time, according to the coordinate matching of the pads, automatically associates the relationship between the test chip pins and the test channels; After obtaining the packaging parameters of the chip to be tested, generate a channel relationship mapping table.

7. The method for automatically generating the channel correspondence relationship according to claim 6, wherein A matrix switch circuit is also connected between the channel and the test machine.

8. The method for automatically generating the channel correspondence relationship according to claim 6, wherein, When the number of pins of the chip to be tested is less than the maximum connection size of the test interface board, convert the pin coordinates of the chip to be tested into the LoadBoard coordinate system: X LoadBoard = X MinPackage +Δ X Y LoadBoard = Y MinPackage +Δ Y , where ΔX and ΔY are the offset amounts of the chip under test in the X-axis and Y-axis directions of the test interface board, X MinPackage and Y MinPackage are the base amounts in the X-axis and Y-axis directions of the test interface board to be tested.

9. A storage medium, characterized in that, There is a computer program stored. When the computer program is executed by a processor, the processor executes the steps of the method for automatically generating the channel correspondence relationship as described in any one of claims 6-8 above.

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