Test equipment for ESD and RF testing of compatible chips

Abstract

The present application proposes a test device for performing electrostatic discharge testing and radio frequency testing on compatible chips, the test device comprising: a first test board comprising: a chip placement area for placing the chip to be tested; a plurality of first rows of pinholes for electrically connecting to the pins of the chip to be tested, the pins including radio frequency input pins and voltage input pins; a second test board comprising: a peripheral circuit area for placing the peripheral circuit of the chip to be tested; a plurality of second rows of pinholes connected to the plurality of first rows of pinholes, the plurality of second rows of pinholes including voltage pinholes and radio frequency pinholes, the voltage pinholes being used to connect the peripheral circuit and connected to the voltage input pins through the first row of pinholes; the radio frequency pinholes being used to connect to a radio frequency tester and connected to the radio frequency input pins through the first row of pinholes.

Description

Technical Field

[0001] The present application relates to the field of radio frequency, and in particular to a testing device for performing electrostatic discharge testing and radio frequency testing on a compatible chip. Background Art

[0002] Electrostatic discharge (ESD) is a crucial component of chip reliability verification. Device-level ESD testing aims to determine whether small amounts of ESD discharge can degrade or damage the performance of devices under test (DUTs), such as integrated circuits (ICs).

[0003] When performing ESD testing on a chip, it's often necessary to apply a transient high voltage to specific pins to examine the impact of this high voltage on the chip's internal circuitry. Due to the chip's small size, its pins can't directly contact the test equipment. Therefore, the chip must be embedded in a carrier (such as a test board) and connected to the test equipment via the carrier's lead pins.

[0004] ESD testing is a DC test and does not involve radio frequency (RF) signals. Therefore, the connectors at the end of the chip carrier, where the chip leads out, are primarily designed to transmit DC signals and cannot directly connect to the RF interface. After ESD testing, the most effective way to determine whether the chip has been damaged is to test its key performance and compare the results before and after the ESD test to identify any differences.

[0005] For RF chips, ESD testing can affect their RF parameters before and after testing. Therefore, it's necessary to test these parameters before and after testing to assess their impact on RF performance. Testing RF parameters requires the RF chip to have complete peripheral circuits, such as resistors, capacitors, and coaxial transmission lines for conducting RF signals.

[0006] However, in current RF chip testing, peripheral circuits cannot participate in ESD testing because they may be affected by the ESD test and may also affect the normal progress of the ESD test. Therefore, it is currently impossible to accurately assess the impact of ESD testing on RF parameters. Summary of the Invention

[0007] In order to realize the electrostatic discharge test and radio frequency test of the chip using a set of test equipment, this application proposes a test equipment that is compatible with the chip for electrostatic discharge test and radio frequency test, so as to accurately evaluate the impact of ESD test on radio frequency parameters.

[0008] The testing device comprises:

[0009] The first test board is used for electrostatic discharge testing, including:

[0010] Chip placement area, used to place the chip to be tested;

[0011] A plurality of first-row pinholes, used to electrically connect to pins of the chip to be tested, wherein the pins include radio frequency input pins and voltage input pins;

[0012] A second test board, used to perform radio frequency testing together with the first test board, comprising:

[0013] The peripheral circuit area is used to place the peripheral circuits of the chip to be tested;

[0014] A plurality of second rows of pinholes are detachably connected to the plurality of first rows of pinholes through a first row of pins, and the plurality of second rows of pinholes include voltage pinholes and RF pinholes. The voltage pinholes are used to connect the peripheral circuit and are connected to the voltage input pins through the first row of pinholes; the RF pinholes are used to connect to an RF tester and are connected to the RF input pins through the first row of pinholes.

[0015] The first row of pins is preferably formed integrally with the second row of pinholes to facilitate disassembly and assembly of the testing device.

[0016] Optionally, the first test board includes a second pin row, and the second test board includes a third pin row. The first pin row of the RF pinholes is surrounded by the second pin row, the third pin row, and at least a portion of the first pin row of the voltage pinholes. This forms a quasi-coaxial structure that shields RF signals and provides good impedance matching, thereby reducing RF signal loss and interference and improving RF signal transmission performance.

[0017] Optionally, the second pin row is located outside the first pin row, and the third pin row is located inside the first pin row; both the second and third pin rows are grounded. Based on the structures of the first and second test boards, this arrangement facilitates wiring design in the first and second test boards.

[0018] Optionally, there is a height difference between the second row of pins and the second test board, and between the third row of pins and the first test board.

[0019] Optionally, the first test board includes a plurality of the second pin rows, and the second test board includes a plurality of the third pin rows; the second pin rows are arranged outside the first pin row of the voltage pin hole, and the third pin rows are arranged inside.

[0020] Optionally, the first test board includes a plurality of second pin rows; the first pin row of the RF pin hole is surrounded by the plurality of second pin rows; or, the second test board includes a plurality of third pin rows; the first pin row of the RF pin hole is surrounded by the plurality of third pin rows.

[0021] Optionally, the peripheral circuit area includes a mounting location for mounting at least one of a resistor, a capacitor, and an inductor.

[0022] Optionally, the second test board further includes:

[0023] A power pinhole, used to connect to the power supply and connected to the mounting position;

[0024] The radio frequency connector is used to connect to the radio frequency tester and is connected to the radio frequency pinhole through a radio frequency connecting line.

[0025] Optionally, the first test board includes at least two metal layers, and the metal layer on the side facing away from the second test board is a reference metal layer;

[0026] The second test board includes at least two metal layers, the metal layer facing the first test board is a reference ground metal layer, or the metal layer facing away from the first test board is a reference ground metal layer.

[0027] In summary, the test device for performing electrostatic discharge and RF testing on compatible chips proposed in this application, particularly through the first row of pinholes, the first row of pins, and the second row of pinholes, can conveniently combine and separate a first test board (i.e., an ESD test board) and a second test board (i.e., an RF test board). The first test board can independently perform ESD testing, ensuring that there is no interference from peripheral circuits surrounding the chip during ESD testing, thus avoiding the impact of peripheral circuits on the ESD test results, thereby improving the accuracy of the test results. Furthermore, the first and second rows of pinholes enable the combination of the first and second test boards, allowing the second test board to carry peripheral circuits, ensuring the accuracy of RF performance testing.

[0028] The integrated design of the test device ensures that RF performance (such as RF parameters) can be measured in the same test environment before and after ESD testing, thereby accurately comparing and evaluating the impact of ESD testing on RF performance.

[0029] In addition, the first test board and the second test board can be put into production at the same time during board manufacturing, and multiple different second test boards can be manufactured at one time to adapt to the RF pin positions of different chips, thereby improving the versatility and flexibility of the device and meeting the testing needs of multiple chips.

[0030] The first row of pinholes and the second row of pinholes are connected via the first row of pins, which can conveniently realize the detachable connection between the first row of pinholes and the second row of pinholes and provide electrical conduction and mechanical support.

[0031] The first test board includes a second pin row, and the second test board includes a third pin row. The first pin row of the RF pin hole is surrounded by the second pin row, the third pin row, and at least part of the first pin row of the voltage pin hole. The first pin row, the second pin row, and the third pin row form a quasi-coaxial structure, ensuring good transmission performance of the RF signal between the boards and reducing signal loss and interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of an ESD test board according to an embodiment of the present application. Figure 1 .

[0033] Figure 2 is a cross-sectional view of an ESD test board according to an embodiment of the present application.

[0034] Figure 3 This is a schematic diagram of a plan view of an RF test board according to an embodiment of the present application. Figure 1 .

[0035] Figure 4 is a cross-sectional view of an RF test board according to an embodiment of the present application.

[0036] Figure 5 Schematic diagram of a testing device for performing an ESD test according to an embodiment of the present application.

[0037] Figure 6 2 is a schematic diagram of a planar stack of test devices when performing RF testing according to an embodiment of the present application.

[0038] Figure 7 It is a cross-sectional view of a testing device when performing RF testing according to an embodiment of the present application.

[0039] Figure 8 This is a schematic diagram of a plan view of an RF test board according to an embodiment of the present application. Figure 2 .

[0040] Figure 9 This is a schematic diagram of an ESD test board according to an embodiment of the present application. Figure 2 .

[0041] Figure 10 is a flow chart of a testing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0043] In this application, the accuracy of the test results is improved by using the ESD test board (i.e., the first test board) and the RF test board (i.e., the second test board) that can be freely split and combined, and the impact of ESD testing on RF performance can be accurately compared and evaluated. Figures 1 to 4 The structures of the ESD test board and the RF test board are described.

[0044] Figure 1 1 is a planar schematic diagram of an ESD test board 100 for ESD testing proposed in this application. The ESD test board can be a printed circuit board (PCB), including a chip placement area 101 and a plurality of first-row pinholes 102. The chip placement area 101 is used to place the chip to be tested that needs to undergo ESD testing and RF testing. The chip to be tested can be a radio frequency chip, such as an amplifier chip, an attenuator chip, a beamforming chip, etc. The plurality of first-row pinholes 102 are used to electrically connect to the plurality of pins of the chip to be tested, respectively, so as to conduct electrical transmission with the pins of the chip to be tested, for example, through Figure 1 The plurality of electrical connection wires 103 shown in FIG. are electrically connected. When the chip under test is placed in the chip placement area 101, the electrical connection wires 103 conduct electricity between the pins of the chip under test and the corresponding pinholes in the first row 102. Because the chip under test needs to undergo ESD testing using DC voltage and RF testing using RF signals, the pins of the chip under test include RF input pins and voltage input pins. The RF input pins are used to input RF signals to the chip under test, and the voltage input pins are used to input voltage to the chip under test.

[0045] In addition, the ESD test board further includes a plurality of first grounding holes 104 (eg, Figure 1 The first row of pinholes 102 (shown as black circles) is used to shield test signals. Since electrical wiring needs to be routed inside the first row of pinholes 102, the multiple first grounding holes 104 are preferably located close to the outside of the first row of pinholes 102 to facilitate wiring. "Close" means as close as possible, for example, with a spacing of less than 3 mm to achieve better shielding.

[0046] Figure 2 Shown Figure 1 The cross-section of the ESD test board along the dotted line A-A' is shown in Figure 2. Figure 2 The hierarchical structure of the ESD test board is described below. Figure 2The ESD test board structure shown in FIG includes two metal layers. Figure 2 As shown, when the ESD test board is combined with the RF test board, the metal layer facing the RF test board is the first top metal layer 201, and the first bottom metal layer 202 facing away from the RF test board serves as the reference ground metal layer for the ESD test board. In other embodiments, the metal layer facing away from the RF test board may be the first top metal layer 201, and the first bottom metal layer 202 facing the RF test board serves as the reference ground metal layer for the ESD test board. The first top metal layer 201 is used for preparing and laying electrical connection wires 103. This two-layer metal structure facilitates the preparation of electrical connection wires and the grounding of the first grounding holes 104, balancing signal quality and test board structural complexity. It is understood that, based on different testing requirements and test environments, the ESD test board may have different numbers of metal layers. For example, only one metal layer may be retained as the ground layer, with the electrical connection wires 103 connected via flying leads. For more complex testing requirements, more metal layers may also be used. For another example, the ESD test board may include three or more metal layers.

[0047] Figure 3 Figure 3 is a schematic plan view of an RF test board 300 for RF testing proposed in this application. The RF test board, which may be a printed circuit board (PCB), includes a plurality of second rows of pinholes 301 and a peripheral circuit area 302. The peripheral circuit area includes multiple mounting locations for peripheral circuits of the chip under test (not shown in the figure to clarify the peripheral circuits). These mounting locations are connected to traces 303 arranged on the metal layer and can be any device capable of mounting electronic components, such as jacks, patches, or solder joints, for mounting the peripheral circuits on the RF test board 300. At least one of a resistor, capacitor, or inductor can be installed in the mounting locations as a peripheral circuit, depending on the needs of the RF test. During RF testing, the peripheral circuit is electrically connected to the chip under test and is used for matching, filtering signal noise, filtering power supply noise, and other functions. This peripheral circuit can ensure the accuracy of RF performance testing or enable matching between different chips under test, thereby completing the RF test circuit and enabling RF testing. The resistors, capacitors, and inductors can be interchangeably positioned, allowing different parameters of resistors, capacitors, and inductors to be selected for different chips under test. Preferably, the peripheral circuit includes an RLC circuit consisting of a resistor, a capacitor, and an inductor.

[0048] When the RF test board and the ESD test board are combined for RF testing, it is necessary to provide an operating voltage and a radio frequency signal to the chip under test. Therefore, the plurality of second rows of pinholes 301 include voltage pinholes 304 and radio frequency pinholes 305. The voltage pinholes 304 are used to transmit the operating voltage, and the radio frequency pinholes 305 are used to transmit the radio frequency signal. In addition, a power pinhole 306 is provided on one side of the peripheral circuit for connecting an external power supply (not shown in the figure to clearly show the external power supply) and the peripheral circuit provided on the mounting position of the trace 303. In order to improve the performance of radio frequency signal transmission, the RF test board can also be provided with an radio frequency connector 307, one end of which is connected to the radio frequency tester (not shown in the figure to clearly show the radio frequency tester), and the other end is connected to the radio frequency pinhole 305 via an radio frequency connecting line 308. The voltage pinhole 304 is used to connect the peripheral circuit. The external power supply is transmitted to the ESD test board through the first row of pinholes corresponding to the voltage pinhole 304 after passing through the power pinhole 306, the peripheral circuit set on the wiring 303, and the voltage pinhole 304 connected to the wiring 303, and then connected to the voltage input pin of the chip to be tested through the electrical connection line. Figure 3 All the second row pinholes connected to the trace 303 are voltage pinholes; the RF pinhole 305 is used to connect to the RF tester (which can be various devices for inputting RF signals). The external RF signal is transmitted to the ESD test board through the RF connector 307, the RF connecting line 308, and the RF pinhole 305, and then transmitted to the ESD test board through the first row of pinholes corresponding to the RF pinhole 305, and is connected to the RF input pin of the chip to be tested through the electrical connection line. Figure 3 The second row of pinholes connected to the RF connection line 308 is a RF pinhole row.

[0049] In addition, the RF test board may also include multiple second grounding holes 309 for grounding to form a shield. Since peripheral circuits need to be arranged outside the second row of pinholes 301, the multiple second grounding holes 309 are preferably arranged closely inside the second row of pinholes 301 to facilitate wiring.

[0050] Figure 4 Shown Figure 3 Cross-sectional view of the RF test board along the dotted line B-B', refer to Figure 4 The layered structure of the RF test board is illustrated, wherein the power pin hole 306 on the right side is not visible in the cross-sectional view and is therefore represented by a dotted line. Figure 4 The RF test board structure shown in FIG includes two metal layers. Figure 4As shown, the RF test board includes a second top metal layer 401 and a second bottom metal layer 402. In some embodiments, when the ESD test board is combined with the RF test board, the metal layer facing away from the ESD test board is the second top metal layer 401, and the side facing the ESD test board is the second bottom metal layer 402 serving as a reference ground metal layer; in other embodiments, when the ESD test board is combined with the RF test board, the metal layer facing the ESD test board is the second top metal layer 401, and the side facing away from the ESD test board is the second bottom metal layer 402 serving as a reference ground metal layer. In this case, the signal traces on the two test boards are placed close together, which can reduce the mismatch effect when the signal passes through the test boards. It is understandable that based on different test requirements and test environments, the RF test board can have different numbers of metal layers.

[0051] Because the first test board and the second test board are detachable independent boards, the first test board and the second test board can be put into production at the same time during plate making. Moreover, since RF testing may need to face different test environments and test conditions, multiple different RF test boards can also be produced at one time for adaptation, thereby improving the versatility and flexibility of the device and meeting the testing needs of multiple chips.

[0052] Next reference Figure 5 and Figure 6 The following describes the structure of using this test device to perform ESD testing and RF testing.

[0053] Figure 5 This is a schematic diagram of the test equipment when performing ESD testing. When performing ESD testing, only the ESD test board is used without combining it with the RF test board. Figure 5 In the illustrated embodiment, the ESD tester 501 is electrically connected to the ESD test board via a pin header 502. The pin header 502 is inserted into the first row of pin holes 102 to connect the ESD tester 501 to the ESD test board. The pin header holes are jacks on the test board that can be plugged into the pin headers. The pin header holes have metal sidewalls for forming an electrical connection with the pin headers.

[0054] When performing an ESD test, such as a Human Body Model (HBM) test, the instantaneous high voltage generated by the ESD tester 501 is transmitted to the first row of pinholes 102 in the ESD test board through the pin header 502, and is then transmitted to the corresponding pins of the chip under test 506 via the electrical connection line 103. The transmission path of the voltage signal is as follows: Figure 5 It is understood that when different test items are performed, the first row of pinholes 102 into which the pin header 502 is inserted is the pinhole connected to the pin corresponding to the test item, thereby completing the ESD test of each pin in turn.

[0055] Figure 6 This is a schematic diagram of the plane stacking of the test equipment during RF testing. Figure 7 For RF testing Figure 7 The cross-sectional view of the test device shown is taken along the dotted line C-C'. When performing RF testing, since an ESD test board is required to carry the chip to be tested, it is necessary to combine the RF test board with the ESD test board. Figure 7 In the illustrated embodiment, when the ESD test board is combined with the RF test board, the RF test board's second bottom metal layer 402, which serves as a reference ground, faces the ESD test board's first top metal layer 201, which carries signals. In other embodiments, the RF test board's second top metal layer 401, which carries signals, faces the ESD test board's first top metal layer 201, which carries signals. In other embodiments, the RF test board's second bottom metal layer 402, which serves as a reference ground, faces the ESD test board's first bottom metal layer 202, which serves as a reference ground; or the RF test board's second top metal layer 401, which carries signals, faces the ESD test board's first bottom metal layer 202, which serves as a reference ground.

[0056] The first row of pinholes and the second row of pinholes are detachably connected by the first row of pinholes. One end of the first row of pinholes is used to connect to the first row of pinholes of the ESD test board 100, and the other end of the first row of pinholes is used to connect to the second row of pinholes of the RF test board 300. Since there are multiple first and second row of pinholes, multiple first row of pinholes can be used, and each first row of pinholes is connected to a corresponding group of first and second row of pinholes. For example Figure 6 The first row of needles 1, 2 and 4, and Figure 7 As shown in the figure, the first row of pins 1 is used to transmit RF signals, the first row of pins 2 and 4 can be connected to a DC power supply, and the first row of pins 2 and 4 can also be connected to the ground. In addition, in order to facilitate the construction or combination of the test device, the second row of pinholes can be integrally formed with the first row of pins.

[0057] refer to Figure 6 and Figure 7 The structure of the test equipment when performing RF testing is described.

[0058] When performing RF testing, the DC power supply 701 is connected to the power pin hole 306 on the RF test board through a connector (e.g., pin header 702). Thus, the DC voltage output by the DC power supply 701 is transmitted to the corresponding voltage input pins of the chip under test 707 via the pin header 702, the power pin hole 306, the peripheral circuit provided on the trace 303, the power pin hole 306, the voltage pin hole 304, the first pin 703, and the electrical connection line 103, thereby providing the operating voltage for the chip under test. The current path is as follows: Figure 7In addition, the RF tester 708 is connected to the RF connector 307, so that the RF signal emitted by the RF tester 708 is transmitted to the RF input pin of the chip under test 707 through the RF connector 307, connected to the RF pinhole 305, the first row of pins 1, the first row of pinholes 102, and the electrical connection line 103, so as to provide the chip under test 707 with an RF signal for RF testing. The current path is as follows: Figure 7 Indicated by the middle dotted line L3.

[0059] In addition, in order to improve the transmission performance of the radio frequency signal, a pin row is arranged around the first pin row 1 connected to the radio frequency pin hole to form a coaxial structure, such as Figure 6 As shown. Four pins are surrounded on the side of the first pin row 1 of the RF pin hole, including the first pin row 2, the second pin row 3, the first pin row 4 and the third pin row 5, thereby forming a quasi-coaxial structure to ensure the integrity of the RF signal transmission. Among them, the first pin row 2 and the first pin row 4 are connected to the voltage pin hole adjacent to the RF pin hole, the second pin row 3 can be detachably set to the first grounding hole on the ESD test board, and the third pin row 5 can be detachably set to the second grounding hole on the RF test board. The second pin row 3 and the third pin row 5 constitute the metal ground in the quasi-coaxial structure, so that the quasi-coaxial structure shields the first pin row 1. In addition, there is a height difference between the second pin row 3 and the RF test board, and between the third pin row 5 and the ESD test board, that is, the second pin row 3 is not connected to the RF test board, and the third pin row 5 is not connected to the ESD test board to avoid short circuits.

[0060] In addition, the first row of needles, the second row of needles and the third row of needles can also be spring needles. Figure 6 Only four pin headers are shown in the top, bottom, left, and right directions of the first pin row 1 to form a quasi-coaxial structure. However, it is understood that the more pin headers are arranged around the first pin row 1, the better the effect. For example, pin headers can be arranged at the remaining eight positions in a nine-square grid centered on the first pin row to form a quasi-coaxial structure with even better effect.

[0061] In addition to the first row of pins in the RF pinholes, a quasi-coaxial structure can also be set for the first row of pins in the voltage pinholes. That is, a second row of pins can be set in multiple first grounding holes on the ESD test board, and a third row of pins can be set in multiple second grounding holes on the RF test board.

[0062] In some embodiments, the first row of pins 1 for transmitting radio frequency signals may be surrounded by a plurality of third row of pins 5 to form a coaxial structure. Figure 8In the RF test board shown, the RF pinhole 305 can be surrounded by the grounded second grounding hole 309. When the first pin row 1 is inserted into the RF pinhole 305 and the third pin row 5 is inserted into the multiple second grounding holes 309 respectively, the grounded third pin row 5 surrounds the first pin row 1, forming a quasi-coaxial structure.

[0063] In some embodiments, the first row of pins 1 for transmitting radio frequency signals may be surrounded by a plurality of second row of pins 3 to form a coaxial structure. Figure 9 In the ESD test board shown, the first row of pinholes 102 for transmitting radio frequency signals can be surrounded by grounded first grounding holes 104. The first row of pins 1 is inserted into the first row of pinholes 102 for transmitting radio frequency signals, and the second row of pins 3 is respectively inserted into multiple first grounding holes 104. The grounded second row of pins 3 surrounds the first row of pins 1 to form a quasi-coaxial structure.

[0064] Finally, reference Figure 10 The flowchart is used to illustrate the test method of performing ESD test and RF test using the test device.

[0065] In step 901, the chip to be tested is mounted on the chip test socket, and the ESD test board and the RF test board are assembled by connecting the first row of pinholes and the second row of pinholes. Figure 6 、 Figure 7 As shown, the ESD test board and the RF test board are electrically connected and combined through a first row of pinholes and a second row of pinholes in a structure such as a pin header or a spring pin.

[0066] In step 902, a radio frequency signal is input to the test device through the radio frequency connector to perform a first radio frequency test. This step is used to obtain the result of the RF test without being affected by the ESD test.

[0067] like Figure 7 As shown, the DC power supply 701 provides the working voltage to the chip under test 707 through the path L2, and the RF tester 708 provides the RF signal required for RF testing to the chip under test 707 through the RF connector 709 and the path L3.

[0068] The radio frequency performance can be tested at the test pin of the chip under test 707, for example, the radio frequency power and voltage intensity output by the chip under test 707 can be tested.

[0069] In step 903, the ESD test board and the RF test board are separated, and the voltage output terminal of the electrostatic discharge tester is connected to the corresponding first row of pinholes to perform an electrostatic discharge test. Since the peripheral circuit of the chip under test will affect the test results of the ESD test during the RF test, and the peripheral circuit may also be affected by the ESD test, the test device is separated to perform the ESD test using only the ESD test board. Figure 5As shown, the DC power supply of the ESD tester 501 inputs a DC voltage to the ESD test board through a path L1 to start the chip under test 506 and adjust the voltage to perform corresponding ESD test items.

[0070] In step 904, the ESD test board and the RF test board are combined again, and a radio frequency signal is input to the test device through the radio frequency connector to perform a second radio frequency test.

[0071] like Figure 7 As shown, DC power supply 701 provides operating voltage to chip under test 707 via path L2. RF tester 708 provides the RF signal required for RF testing to chip under test 707 via RF connector 709 and path L3. The operating voltage and RF signal provided to chip under test 707 in step 904 are the same as those in step 902. This allows RF performance to be measured under the same test environment.

[0072] The radio frequency performance can be tested at the test pin of the chip under test 707, for example, the radio frequency power and voltage intensity output by the chip under test 707 can be tested.

[0073] Since the ESD test will affect the parameters of the chip under test, it is necessary to perform RF testing again after the ESD test to compare the test results with the first RF test.

[0074] In step 905 , the test results of the first RF test and the second RF test are compared to obtain the impact of the electrostatic discharge test on the RF performance.

[0075] By using the above-mentioned testing method using the testing device proposed in this application, the impact of the ESD test on the RF parameters of the chip can be detected without affecting the ESD test results.

[0076] The above is an explanation of the embodiments of the present application by specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this embodiment. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other unless there is a conflict.

[0077] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful in understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0078] Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrase "A / B" means "A or B." The phrase "A and / or B" means "(A and B) or (A or B)."

[0079] As used herein, the term “module” or “unit” may refer to, be or include: an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated or group) processor and / or memory that executes one or more software or firmware programs, a combinational logic circuit and / or other suitable components that provide the described functionality.

[0080] In the accompanying drawings, some structural or method features are shown in a specific arrangement and / or order. However, it should be understood that such specific arrangement and / or order may not be required. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0081] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements or data, these elements or data should not be limited by these terms. These terms are used only to distinguish one feature from another. For example, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature without departing from the scope of the exemplary embodiments.

[0082] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0083] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A test device for performing electrostatic discharge test and radio frequency test on a compatible chip, characterized in that: The testing device comprises: The first test board is used for electrostatic discharge testing, including: Chip placement area, used to place the chip to be tested; A plurality of first-row pinholes, used to electrically connect to pins of the chip to be tested, wherein the pins include radio frequency input pins and voltage input pins; A second test board, used to perform radio frequency testing together with the first test board, comprising: The peripheral circuit area is used to place the peripheral circuits of the chip to be tested; A plurality of second rows of pinholes are detachably connected to the plurality of first rows of pinholes through a first row of pins, and the plurality of second rows of pinholes include voltage pinholes and RF pinholes. The voltage pinholes are used to connect the peripheral circuit and are connected to the voltage input pins through the first row of pinholes; the RF pinholes are used to connect to an RF tester and are connected to the RF input pins through the first row of pinholes.

2. The testing device according to claim 1, wherein: The first test board includes a second row of pins, and the second test board includes a third row of pins; The first row of pins of the RF pinhole is surrounded by the second row of pins, the third row of pins, and at least a portion of the first row of pins of the voltage pinhole.

3. The testing device according to claim 2, characterized in that The second row of needles is located outside the first row of needles, and the third row of needles is located inside the first row of needles; The second row of pins and the third row of pins are both grounded.

4. The testing device according to claim 2, characterized in that There is a height difference between the second row of pins and the second test board, and between the third row of pins and the first test board.

5. The testing device according to claim 2, characterized in that: The first test board includes a plurality of the second pin rows, and the second test board includes a plurality of the third pin rows; The second row of pins is arranged outside the first row of pins of the voltage pin hole, and the third row of pins is arranged inside the first row of pins.

6. The testing device according to claim 1, wherein: The first test board includes a plurality of second pin rows; the first pin row of the RF pin hole is surrounded by the plurality of second pin rows; Alternatively, the second test board includes a plurality of third pin rows; and the first pin row of the RF pin hole is surrounded by the plurality of third pin rows.

7. The testing device according to any one of claims 1 to 6, characterized in that: The peripheral circuit area includes a mounting location for mounting at least one of a resistor, a capacitor, and an inductor.

8. The testing device according to claim 7, characterized in that: The second test board further includes: A power pinhole, used to connect to the power supply and connected to the mounting position; The radio frequency connector is used to connect to the radio frequency tester and is connected to the radio frequency pinhole through a radio frequency connecting line.

9. The testing device according to any one of claims 1 to 6, characterized in that: The first test board comprises at least two metal layers, and the metal layer on the side facing away from the second test board is a reference ground metal layer; The second test board includes at least two metal layers, the metal layer facing the first test board is a reference ground metal layer, or the metal layer facing away from the first test board is a reference ground metal layer.

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