Semiconductor equipment scheduling method and device, equipment and storage medium

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor equipment scheduling method and device, equipment and a storage medium, and the method comprises the steps: generating an initial action sequence through employing a pre-selected scheduling algorithm in a processing operation scene constructed based on wafer processing task information; confirming a recalculation triggering time point according to a preset recalculation mechanism and the initial action sequence; when a recalculation triggering time point is reached, generating a recalculation action sequence and comparing the recalculation action sequence with the initial action sequence to obtain a recalculation consistency result; the feasibility of the recalculation action sequence is judged based on the recalculation consistency result, if yes, a replacement action sequence is generated to replace the initial action sequence, and the recalculation triggering time point is confirmed according to a preset recalculation mechanism and the initial action sequence; according to the method disclosed by the invention, the recalculation process is adjusted through the recalculation mechanism, so that the scheduling algorithm can consider complex scenes of historical planning, the effectiveness and reliability of the generated action sequence are improved, the recalculation time can be greatly shortened, and the recalculation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device scheduling method, apparatus, device, and storage medium. Background Art

[0002] When evaluating the performance of a device scheduling algorithm, a typical scenario is usually constructed and a theoretical production capacity formula is derived. Then, the algorithm will plan all the actions (moves) of all jobs at once and calculate the corresponding algorithm production capacity. If the production capacity of the algorithm reaches the 90% threshold of the theoretical production capacity, it can be determined that the algorithm is applicable to the scheduling process of semiconductor devices.

[0003] However, this ideal state of planning all jobs at once is different from the operations in the actual production environment. In actual operations, jobs are generally issued step by step, which will trigger the algorithm to perform multiple recalculations and segmented planning. Even without adding new jobs, the algorithm may recalculate due to various triggering factors, resulting in a different planning result from the initial full-scale planning, thus affecting the calculation of the algorithm production capacity. Therefore, in order to ensure that the calculation of the algorithm production capacity is consistent with the actual production capacity, a method is needed to detect the consistency of the results between multiple recalculations and one-time calculations of the algorithm.

[0004] There are some problems with the existing scheduling recalculation methods commonly used in the industry: 1. If the time interval between two recalculations is set too large, some nodes may be missed. If the time interval is small, the number of recalculations will increase significantly, resulting in a geometric growth of the detection time. If the interval is set randomly, it may lead to node omission and uneven granularity.

[0005] 2. When triggering recalculation, all unstarted moves are usually deleted, which makes the re-planning of the algorithm relatively easy, but it cannot test the weaknesses of the algorithm in global planning ability.

[0006] 3. If full-scale comparison is performed each time, since the action information includes thousands each time, the calculation time will be very long. For example, if a scenario needs to be recalculated 5000 times, if full-scale comparison is performed each time, it will take 8 - 10 hours to obtain the corresponding scheduling result for one scenario.

[0007] It can be seen that the existing technology still needs to be improved. Summary of the Invention

[0008] In order to overcome the deficiencies of the prior art, the purpose of the present invention is to provide a semiconductor device scheduling method, which adjusts the recalculation process through a recalculation mechanism, enables the scheduling algorithm to take into account complex scenarios of historical planning, improves the accuracy of the generated action sequence, and can greatly shorten the recalculation time.

[0009] In the first aspect of the present invention, a semiconductor device scheduling method is provided, including: obtaining wafer processing task information, constructing a processing operation scenario based on the obtained wafer processing task information; obtaining a preselected scheduling algorithm, and using the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario; obtaining a preset recalculation mechanism, and determining a recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; when the recalculation trigger time point is reached, based on the preset recalculation mechanism, using the scheduling algorithm to generate a recalculation action sequence in the processing operation scenario; comparing the recalculation action sequence and the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result; judging the feasibility of the recalculation action sequence based on the recalculation consistency result, if the recalculation action sequence passes the feasibility judgment, then generating a replacement action sequence based on the recalculation action sequence, using the replacement action sequence to replace the initial action sequence, and returning to execute the determination of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism.

[0010] Optionally, in the first implementation manner of the first aspect of the present invention, the obtaining wafer processing task information and constructing a processing operation scenario based on the obtained wafer processing task information includes: calling an interface API to obtain wafer processing task information, where the wafer processing task information includes processing task parameters, initial state information of semiconductor devices, and detection configuration parameters; constructing a processing operation scenario based on the obtained processing task information, and using a YAML file to configure the dependency relationship and trigger conditions of the wafer processing task; setting the recalculation times of the processing operation scenario to 1 to complete the initialization of the processing operation scenario.

[0011] Optionally, in the second implementation manner of the first aspect of the present invention, the obtaining a preselected scheduling algorithm and using the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario includes: selecting a scheduling algorithm based on the static information of semiconductor devices, where the static information includes the module composition and technical parameters of semiconductor devices; using the selected scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario, where the initial action sequence includes multiple actions, and each action includes an execution module, an execution start time, and an execution end time.

[0012] Optionally, in the third implementation manner of the first aspect of the present invention, the obtaining a preset recalculation mechanism and determining a recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism includes: obtaining a preset recalculation mechanism, where the preset recalculation mechanism includes a pause setting condition; obtaining a set fixed interval of the processing operation scenario, and determining a recalculation trigger initial time point and a recalculation trigger end time point based on the set fixed interval for recalculation trigger; based on the initial action sequence, judging whether there is an action between the recalculation trigger initial time point and the recalculation trigger end time point; if there is no action, then adjusting the recalculation trigger end time point based on the pause setting condition to obtain a recalculation trigger time point.

[0013] Optionally, in the fourth implementation manner of the first aspect of the present invention, when the recalculation trigger time point is reached, based on a preset recalculation mechanism, a recalculation action sequence is generated in the processing operation scenario by using a scheduling algorithm, including: when the recalculation trigger time point is reached, obtaining an action retention range in the preset recalculation mechanism, where the action retention range includes the currently ongoing actions and the unstarted actions within the next 0 - 50 seconds; retaining the action information in the initial action sequence based on the action retention range, and deleting other action information in the initial action sequence; and generating a recalculation action sequence in the processing operation scenario by using the retained action information and the deleted action information.

[0014] Optionally, in the fifth implementation manner of the first aspect of the present invention, comparing the recalculation action sequence and the initial action sequence based on a preset recalculation mechanism to obtain a recalculation consistency result, including: obtaining an action comparison range in the preset recalculation mechanism, where the action comparison range includes the successor actions of cross - cycle actions; comparing whether the parameters and timings of the subsequent actions of the recalculation action sequence are exactly the same as those of the subsequent actions of the initial action sequence to obtain a recalculation consistency result.

[0015] Optionally, in the sixth implementation manner of the first aspect of the present invention, judging the feasibility of the recalculation action sequence based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, then generating a replacement action sequence based on the recalculation action sequence, using the replacement action sequence to replace the initial action sequence, and returning to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism, including: if the recalculation consistency result indicates that the parameters and timings of the subsequent actions of the recalculation action sequence are exactly the same as those of the subsequent actions of the initial action sequence, then integrating the retained action information and the recalculation action sequence to obtain a replacement action sequence, using the replacement action sequence to replace the initial action sequence, and returning to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; if the recalculation consistency result indicates that the parameters and timings of the subsequent actions of the recalculation action sequence are not exactly the same as those of the subsequent actions of the initial action sequence, then generating an error warning instruction and stopping the actions.

[0016] In a second aspect of the present invention, a semiconductor device scheduling apparatus is provided, including: a construction module, configured to obtain wafer processing task information and construct a processing operation scenario based on the obtained wafer processing task information; a generation module, configured to obtain a preselected scheduling algorithm, and generate an initial action sequence based on the constructed processing operation scenario by using the scheduling algorithm; a confirmation module, configured to obtain a preset recalculation mechanism and confirm a recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; a recalculation module, configured to, when the recalculation trigger time point is reached, generate a recalculation action sequence in the processing operation scenario by using the scheduling algorithm based on the preset recalculation mechanism; a comparison module, configured to compare the recalculation action sequence and the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result; an iteration module, configured to judge the feasibility of the recalculation action sequence based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, a replacement action sequence is generated based on the recalculation action sequence, and the initial action sequence is replaced with the replacement action sequence, and then return to execute the step of confirming the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism.

[0017] In a third aspect of the present invention, a semiconductor device scheduling device is provided. The semiconductor device scheduling device includes: a memory and at least one processor, and instructions are stored in the memory; at least one of the processors calls the instructions in the memory so that the semiconductor device scheduling device executes each step of the semiconductor device scheduling method described in any one of the above.

[0018] In a fourth aspect of the present invention, a computer-readable storage medium is provided. Instructions are stored on the computer-readable storage medium, and when the instructions are executed by a processor, each step of the semiconductor device scheduling method described in any one of the above is implemented.

[0019] In the technical solution of the present invention, an initial action sequence is generated in a processing operation scenario constructed based on wafer processing task information by using a preselected scheduling algorithm; a recalculation trigger time point is confirmed according to a preset recalculation mechanism and the initial action sequence; when the recalculation trigger time point is reached, a recalculation action sequence is generated and compared with the initial action sequence to obtain a recalculation consistency result; the feasibility of the recalculation action sequence is judged based on the recalculation consistency result. If it passes, a replacement action sequence is generated to replace the initial action sequence, and then return to execute the step of confirming the recalculation trigger time point according to the preset recalculation mechanism and the initial action sequence. In the method disclosed in the present application, the recalculation process is adjusted through the recalculation mechanism, so that the scheduling algorithm can take into account complex scenarios of historical planning, improve the effectiveness and reliability of the generated action sequence, and can greatly shorten the recalculation time and improve the recalculation efficiency. Description of the Drawings

[0020] Figure 1 It is a logic flowchart of the semiconductor device scheduling method provided by the embodiment of the present invention; Figure 2 Schematic structural diagram of the semiconductor device scheduling apparatus provided by an embodiment of the present invention; Figure 3 Schematic structural diagram of the semiconductor device scheduling equipment provided by an embodiment of the present invention. Detailed implementation manners

[0021] The present invention provides a semiconductor device scheduling method, apparatus, equipment and storage medium. In the present invention, terms such as "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the term "comprising" or "having" and any variation thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or equipment comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0022] For ease of understanding, the specific processes of the embodiments of the present invention are described below. Please refer to Figure 1 One embodiment of the semiconductor device scheduling method in the embodiments of the present invention includes: 101. Obtain wafer processing task information, and construct a processing job scenario based on the obtained wafer processing task information; In this embodiment, the processing job scenario refers to a set of wafer processing task (Job) collections and the initial state of the equipment constructed manually according to the target production capacity requirements of semiconductor production, and is used to simulate the real scenario of triggering recalculation by sequentially issuing Jobs in semiconductor scheduling; constructing a processing job scenario based on the obtained wafer processing task information can not only comprehensively reflect the actual requirements of wafer processing, but also provide a solid data basis for the accurate application of subsequent scheduling algorithms, ensuring the accuracy and scientific nature of scheduling decisions.

[0023] 102. Obtain a preselected scheduling algorithm, and use the scheduling algorithm to generate an initial action sequence based on the constructed processing job scenario; In this embodiment, the generated initial action sequence is an ideal planning result without recalculation intervention, and the initial action sequence serves as a comparison benchmark for subsequent multiple recalculation results, laying a foundation for subsequent dynamic adjustment and optimization.

[0024] 103. Obtain a preset recalculation mechanism, and confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; 104. When reaching the recalculation trigger time point, based on a preset recalculation mechanism, a scheduling algorithm is used to generate a recalculation action sequence in the processing job scenario; In this embodiment, by introducing a preset recalculation mechanism, the recalculation interval is scientifically determined based on the initial action sequence, and when the preset recalculation trigger time point is reached, a recalculation action sequence is flexibly generated; not only realizes the dynamic adjustment and optimization of the scheduling plan, covering all nodes, but also injects a mechanism to losslessly reduce the number of recalculations, thus saving time and ensuring the real-time performance and adaptability of the scheduling recalculation plan.

[0025] 105. Compare the recalculation action sequence with the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result; In this embodiment, by comparing the recalculation action sequence with the initial action sequence, a recalculation consistency result can be obtained; this comparison process not only helps to judge the feasibility of the recalculation action sequence, but also can timely discover and correct potential problems in the scheduling recalculation plan, ensuring the accuracy and stability of the recalculation mechanism.

[0026] 106. Judge the feasibility of the recalculation action sequence based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, a replacement action sequence is generated based on the recalculation action sequence, the initial action sequence is replaced with the replacement action sequence, and the execution returns to confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism.

[0027] This application discloses a semiconductor device scheduling method. By using a preselected scheduling algorithm, an initial action sequence is generated in a processing job scenario constructed based on wafer processing task information; a recalculation trigger time point is confirmed according to a preset recalculation mechanism and the initial action sequence; when the recalculation trigger time point is reached, a recalculation action sequence is generated and compared with the initial action sequence to obtain a recalculation consistency result; the feasibility of the recalculation action sequence is judged based on the recalculation consistency result. If it passes, a replacement action sequence is generated to replace the initial action sequence, and the execution returns to confirm the recalculation trigger time point according to the preset recalculation mechanism and the initial action sequence. The method disclosed in this application adjusts the recalculation process through the recalculation mechanism, enabling the scheduling algorithm to take into account complex historical planning scenarios, improving the effectiveness and reliability of the generated action sequence, and greatly shortening the recalculation time and improving the recalculation efficiency.

[0028] Further, in the embodiment of the present invention, the obtaining of the wafer processing task information and the construction of the processing job scenario based on the obtained wafer processing task information include: 201. Call the interface API to obtain the wafer processing task information, where the wafer processing task information includes processing task parameters, initial state information of the semiconductor device, and detection configuration parameters; In this embodiment, the interface API is called, such as the task assignment interface of the MES system, to obtain the wafer processing task information. The processing task parameters include the number of processing tasks, processing steps, and material constraints; the initial state information of the semiconductor device includes module state information, material position information, and performance parameter information; the detection configuration parameters include setting a fixed interval, and the set fixed interval can be 1 - 4 seconds.

[0029] 202. Construct a processing operation scenario based on the obtained processing task information, and use a YAML file to configure the dependency relationship and trigger conditions of the wafer processing task; In this embodiment, using a YAML file to configure the dependency relationship and trigger conditions of the wafer processing task makes the logical relationship between tasks clearer, facilitating management and maintenance; at the same time, the YAML file has the characteristics of strong readability, easy writing and modification, reducing the difficulty and complexity of task configuration.

[0030] 203. Set the recalculation times of the processing operation scenario to 1 to complete the initialization of the processing operation scenario; In this embodiment, setting the recalculation times of the processing operation scenario to 1 avoids unnecessary repeated calculations and improves calculation efficiency; at the same time, completing the initialization of the processing operation scenario provides a good foundation and guarantee for the subsequent simulation of the wafer processing task.

[0031] Furthermore, in the embodiment of the present invention, the obtaining of the preselected scheduling algorithm and the use of the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario include: 301. Select a scheduling algorithm based on the static information of the semiconductor device, and the static information includes the module composition and technical parameters of the semiconductor device; In this embodiment, before the semiconductor device starts to execute the wafer processing task, the static information of the semiconductor device is obtained once to confirm the scheduling algorithm. During the recalculation process, since the semiconductor device has not changed, there is no need to obtain the static information again, and the initially selected scheduling algorithm can be used; based on the static information of the semiconductor device, a suitable scheduling algorithm can be obtained from the pre - constructed scheduling algorithm library. By selecting a suitable scheduling algorithm, the flow of wafers between devices can be optimized, reducing waiting time and idle time, thereby improving the effectiveness and accuracy of the action sequence generated during the simulation.

[0032] 302. Use the selected scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario. The initial action sequence includes multiple actions, and each action includes an execution module, an execution start time, and an execution end time.

[0033] Further, in the embodiment of the present invention, the obtaining of the preset recalculation mechanism and the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism include: 401. Obtain the preset recalculation mechanism, where the preset recalculation mechanism includes a pause setting condition; 402. Obtain the set fixed interval of the processing operation scenario, and recalculate the initial trigger time point and the recalculation trigger end time point based on the set fixed interval; 403. Based on the initial action sequence, determine whether there is an action between the recalculation trigger initial time point and the recalculation trigger end time point; 404. If there is no action, adjust the recalculation trigger end time point based on the pause setting condition to obtain the recalculation trigger time point.

[0034] In this embodiment, the time interval between the recalculation trigger initial time point and the recalculation trigger end time point is the set fixed interval, that is, the basic interval; the setting of the basic interval fully considers the density of device actions; this interval starts counting from 0 seconds and strictly triggers the recalculation operation according to the rule of gap×n, where gap represents the set fixed interval and n represents the number of recalculations. It has the advantages of uniform recalculation times and small granularity, can cover nodes comprehensively, and ensure that the system can perform necessary calculations and adjustments at appropriate time nodes.

[0035] Further, if there is no action between the recalculation trigger initial time point and the recalculation trigger end time point, this time interval is defined as an actionless interval; for the actionless interval, the pause setting condition is used to adjust the end time of this interval to the execution start time of the first subsequent action to be executed, and this execution start time is defined as the recalculation trigger time; for example, if it is found that there is no action between T1 = 8 seconds and T2 = 12 seconds, and the next action starts at T3 = 100 seconds, then the time points are adjusted to T1' = 8 seconds and T2' = 100 seconds, and the original trigger point at T2 = 12 seconds is deleted; after adjusting the recalculation trigger end time point, one or more recalculation trigger moments generated by the set fixed interval before the recalculation trigger time point and the recalculation trigger initial time point need to be deleted to avoid invalid recalculations; this measure not only ensures the coherence and logic in time, but also effectively avoids invalid recalculations caused by actionless periods, thereby improving the overall operation efficiency and resource utilization rate of the system, ensuring the timeliness of action responses, and minimizing unnecessary calculation burdens to the greatest extent, achieving the perfect combination of high efficiency and precision.

[0036] Further, in the embodiment of the present invention, when reaching the recalculation trigger time point, based on the preset recalculation mechanism, a scheduling algorithm is used to generate a recalculation action sequence in the processing operation scenario, including: 501. When reaching the recalculation trigger time point, obtain the action retention range in the preset recalculation mechanism, where the action retention range includes the currently ongoing actions and the uninitiated actions within the next 0 - 50 seconds; 502. Based on the action retention range, retain the action information in the initial action sequence and delete the other action information in the initial action sequence; In this embodiment, for example, during the recalculation process from 0 to 4 seconds, when reaching the 4th second, pause and perform pre - recalculation processing, retaining the actions ongoing at the current time point. That is, when reaching the 4th second, if there are actions that have been initiated but not completed, those actions will be retained; at the same time, the uninitiated actions within a certain period in the future will also be retained, that is, all uninitiated actions between the 4th second and the 54th second (including the 4th second and the 54th second) are retained, while other uninitiated actions will be deleted.

[0037] 503. Based on the retained action information and the deleted action information, use a scheduling algorithm to generate a recalculation action sequence in the processing job scenario; In this embodiment, the recalculation action sequence is a newly planned action, which is regenerated by the scheduling algorithm according to the spatio - temporal constraints of the retained moves.

[0038] In this embodiment, the retention - deletion mechanism forces the scheduling algorithm to consider the time connection and resource occupancy of the retained actions during recalculation, that is, perform incremental recalculation based on the retained planned actions, simulating the complexity of the algorithm's need to process residual unexecuted actions in the actual production scenario, verifying the global coordination ability of the algorithm during rollback processing and re - planning, avoiding only testing the local planning effect, enabling the recalculation mechanism to better handle complex and changeable processing job scenarios; in addition, by considering the time connection of actions, the algorithm can ensure the continuity of the production process and avoid production delays caused by recalculation.

[0039] Further, in the embodiment of the present invention, comparing the recalculation action sequence and the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result includes: 601. Obtain the action comparison range in the preset recalculation mechanism, where the action comparison range includes the successor actions of cross - cycle actions; 602. Compare whether the parameters and timings of the subsequent actions of the recalculation action sequence are exactly the same as those of the successor actions of the initial action sequence to obtain a recalculation consistency result; In this embodiment, the comparison object is the subsequent associated action of a cross - cycle move (i.e., an action that starts in the previous recalculation and is completed in the subsequent recalculation); when the move start time is earlier than the current recalculation cycle, for example, it starts at the m0th time and the current is the m2nd time, a cross - adjacent comparison method should be adopted. Specifically, if the cleaning move starts at the m0th time, then its subsequent first process move needs to be compared with the corresponding process move at the m2nd time (i.e., skipping the intermediate m1 times) to obtain the recalculation consistency result; when the move start time is adjacent to the current recalculation cycle, for example, it starts at the m1st time and the current is the m2nd time, an adjacent comparison method should be adopted. Specifically, if the cleaning move starts at the m1st time, then its subsequent first process move needs to be directly compared with the immediately adjacent m2nd planning result to obtain the recalculation consistency result.

[0040] In this embodiment, obtaining the action comparison range in the preset recalculation mechanism realizes the accurate positioning of the subsequent actions of cross - cycle actions; in the processing operation scenario, by setting the action comparison range, that is, only comparing the effective key actions, the comparison of all data can be avoided. This not only effectively simplifies the action comparison process, reduces the action information participating in the recalculation, greatly improves the recalculation efficiency, but also ensures the consistency of the action sequence after recalculation, is applicable to various recalculation scenarios, and provides a more efficient and reliable solution for processing operations.

[0041] Further, in the embodiment of the present invention, the feasibility of the recalculation action sequence is judged based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, then a replacement action sequence is generated based on the recalculation action sequence, and the replacement action sequence is used to replace the initial action sequence. Return to execute and confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism, including: 701. If the recalculation consistency result indicates that the parameters and timings of the subsequent actions of the recalculation action sequence are exactly the same as those of the subsequent actions of the initial action sequence, then integrate the retained action information and the recalculation action sequence to obtain a replacement action sequence, use the replacement action sequence to replace the initial action sequence, and return to execute and confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; In this embodiment, the replacement action sequence includes two parts: the retained action information and the recalculation action sequence; among them, the retained action information includes the ongoing moves retained across cycles and the unstarted moves that meet the time window; the recalculation action sequence is the result of the scheduling algorithm re - planning according to the spatio - temporal constraints of the retained moves.

[0042] 702. If the recalculation consistency result indicates that the parameters and timings of the subsequent actions of the recalculation action sequence are not exactly the same as those of the subsequent actions of the initial action sequence, then generate an error warning instruction and stop the action; In this embodiment, through recalculation consistency checking, it is possible to ensure the consistency of the recalculation action sequence with the initial action sequence in terms of parameters and timing, thereby avoiding execution errors caused by action deviations and improving the stability and reliability of the semiconductor device during operation; when the recalculation action sequence is exactly the same as the initial action sequence, return to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism, which can optimize the execution process of the action sequence recalculation and ensure the continuity and integrity of the semiconductor device during operation; when the recalculation action sequence is inconsistent with the initial action sequence, an error warning instruction can be generated and the action can be stopped, avoiding equipment failures or damages caused by incorrect actions and ensuring the safe and stable operation of the semiconductor device.

[0043] Further, in this embodiment, when all actions in the wafer processing task information are completed or when the number of recalculations reaches the preset maximum number, stop returning to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; the maximum number can be 9999 times.

[0044] The semiconductor device scheduling method in the embodiment of the present invention has been described above. Next, the semiconductor device scheduling device in the embodiment of the present invention will be described. Please refer to Figure 2 , an embodiment of the semiconductor device scheduling device in the embodiment of the present invention includes: A construction module 801, configured to obtain wafer processing task information and construct a processing operation scenario based on the obtained wafer processing task information; A generation module 802, configured to obtain a preselected scheduling algorithm, and use the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario; A confirmation module 803, configured to obtain a preset recalculation mechanism and confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; A recalculation module 804, configured to, when the recalculation trigger time point is reached, generate a recalculation action sequence in the processing operation scenario based on the preset recalculation mechanism and using the scheduling algorithm; A comparison module 805, configured to compare the recalculation action sequence and the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result; An iteration module 806, configured to judge the feasibility of the recalculation action sequence based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, generate a replacement action sequence based on the recalculation action sequence, use the replacement action sequence to replace the initial action sequence, and return to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism.

[0045] Above Figure 2The semiconductor device scheduling apparatus in the embodiments of the present invention will be described in detail from the perspective of modular functional entities. Next, the semiconductor device scheduling apparatus in the embodiments of the present invention will be described in detail from the perspective of hardware processing.

[0046] Figure 3 FIG. 4 is a schematic structural diagram of a semiconductor device scheduling apparatus provided by an embodiment of the present invention. The semiconductor device scheduling apparatus 900 may vary greatly due to different configurations or performances, and may include one or more processors (central processing units, CPUs) 910 and a memory 920, and one or more storage media 930 (such as one or more mass storage devices) for storing application programs 933 or data 932. Among them, the memory 920 and the storage media 930 may be transient storage or persistent storage. The programs stored in the storage media 930 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the semiconductor device scheduling apparatus 900. Further, the processor 910 may be configured to communicate with the storage media 930 and execute a series of instruction operations in the storage media 930 on the semiconductor device scheduling apparatus 900 to implement the steps of the semiconductor device scheduling method provided in the foregoing method embodiments.

[0047] The semiconductor device scheduling apparatus 900 may further include one or more power supplies 940, one or more wired or wireless network interfaces 950, one or more input / output interfaces 960, and / or one or more operating systems 931, such as Windows Serve, Mac OS X, Unix, Linux, FreeBSD, and so on. Those skilled in the art can understand that Figure 3 the shown structural diagram of the semiconductor device scheduling apparatus does not limit the semiconductor device scheduling apparatus, and it may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0048] The present invention also provides a computer-readable storage medium. The computer-readable storage medium may be a non-volatile computer-readable storage medium, or may also be a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are run on a computer, the computer is caused to execute the steps of the semiconductor device scheduling method.

[0049] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, or units can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0050] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0051] Finally, it should be noted that the above are only preferred examples of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device scheduling method, characterized in that, Including: Obtain wafer processing task information, and construct a processing operation scenario based on the obtained wafer processing task information; Obtain a preselected scheduling algorithm, and use the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario; Obtain a preset recalculation mechanism, and confirm the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism; When the recalculation trigger time point is reached, based on the preset recalculation mechanism, use the scheduling algorithm to generate a recalculation action sequence in the processing operation scenario; Compare the recalculation action sequence and the initial action sequence based on the preset recalculation mechanism to obtain a recalculation consistency result; Judge the feasibility of the recalculation action sequence based on the recalculation consistency result. If the recalculation action sequence passes the feasibility judgment, generate a replacement action sequence based on the recalculation action sequence, use the replacement action sequence to replace the initial action sequence, and return to execute the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism.

2. The semiconductor device scheduling method according to claim 1, wherein The obtaining of the wafer processing task information and the construction of the processing operation scenario based on the obtained wafer processing task information include: Call the interface API to obtain the wafer processing task information, where the wafer processing task information includes processing task parameters, initial state information of semiconductor equipment, and detection configuration parameters; Construct a processing operation scenario based on the obtained processing task information, and configure the dependency relationship and trigger conditions of the wafer processing task using a YAML file; Set the recalculation times of the processing operation scenario to 1 to complete the initialization of the processing operation scenario.

3. The semiconductor device scheduling method according to claim 1, wherein The obtaining of the preselected scheduling algorithm and the use of the scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario include: Select a scheduling algorithm based on the static information of the semiconductor equipment, where the static information includes the module composition and technical parameters of the semiconductor equipment; Use the selected scheduling algorithm to generate an initial action sequence based on the constructed processing operation scenario. The initial action sequence includes multiple actions, and each action includes an execution module, an execution start time, and an execution end time.

4. The semiconductor device scheduling method according to claim 3, wherein The obtaining of the preset recalculation mechanism and the confirmation of the recalculation trigger time point based on the initial action sequence and the preset recalculation mechanism include: Obtain the preset recalculation mechanism, where the preset recalculation mechanism includes a pause setting condition; Obtain the set fixed interval of the processing operation scenario, and recalculate the initial trigger time point and the recalculation trigger end time point based on the set fixed interval; Based on the initial action sequence, judge whether there is an action between the recalculation trigger initial time point and the recalculation trigger end time point; If there is no action, adjust the recalculation trigger end time point based on the pause setting condition to obtain the recalculation trigger time point.

5. The semiconductor device scheduling method according to claim 1, wherein, The step of when the recalculation trigger time point is reached, based on the preset recalculation mechanism, using the scheduling algorithm to generate a recalculation action sequence in the processing operation scenario includes: When the recalculation trigger time point is reached, obtain the action retention range in the preset recalculation mechanism, where the action retention range includes the currently ongoing actions and the unstarted actions within the next 0 - 50 seconds; Retain the action information in the initial action sequence based on the action retention range, and delete the other action information in the initial action sequence; Based on the reserved action information and the deleted action information, a rescheduling action sequence is generated in the processing job scenario using a scheduling algorithm.

6. The semiconductor device scheduling method according to claim 2, wherein Comparing the rescheduling action sequence with the initial action sequence based on a preset rescheduling mechanism to obtain a rescheduling consistency result, including: Obtaining the action comparison range in the preset rescheduling mechanism, where the action comparison range includes the subsequent actions of cross-cycle actions; Comparing whether the parameters and timings of the subsequent actions of the rescheduling action sequence are exactly the same as those of the subsequent actions of the initial action sequence to obtain a rescheduling consistency result.

7. The semiconductor device scheduling method according to claim 5, wherein Judging the feasibility of the rescheduling action sequence based on the rescheduling consistency result. If the rescheduling action sequence passes the feasibility judgment, a replacement action sequence is generated based on the rescheduling action sequence, and the initial action sequence is replaced with the replacement action sequence. Return to execute and confirm the rescheduling trigger time point based on the initial action sequence and the preset rescheduling mechanism, including: If the rescheduling consistency result indicates that the parameters and timings of the subsequent actions of the rescheduling action sequence are exactly the same as those of the subsequent actions of the initial action sequence, integrate the reserved action information and the rescheduling action sequence to obtain a replacement action sequence, replace the initial action sequence with the replacement action sequence, and return to execute and confirm the rescheduling trigger time point based on the initial action sequence and the preset rescheduling mechanism; If the rescheduling consistency result indicates that the parameters and timings of the subsequent actions of the rescheduling action sequence are not exactly the same as those of the subsequent actions of the initial action sequence, generate an error warning instruction and stop the action.

8. A semiconductor device scheduling apparatus, characterized in that, Including: A construction module for obtaining wafer processing task information and constructing a processing job scenario based on the obtained wafer processing task information; A generation module for obtaining a preselected scheduling algorithm and generating an initial action sequence based on the constructed processing job scenario using the scheduling algorithm; A confirmation module for obtaining a preset rescheduling mechanism and confirming the rescheduling trigger time point based on the initial action sequence and the preset rescheduling mechanism; A rescheduling module for, when the rescheduling trigger time point is reached, generating a rescheduling action sequence in the processing job scenario using a scheduling algorithm based on the preset rescheduling mechanism; A comparison module for comparing the rescheduling action sequence with the initial action sequence based on the preset rescheduling mechanism to obtain a rescheduling consistency result; An iteration module for judging the feasibility of the rescheduling action sequence based on the rescheduling consistency result. If the rescheduling action sequence passes the feasibility judgment, a replacement action sequence is generated based on the rescheduling action sequence, and the initial action sequence is replaced with the replacement action sequence. Return to execute and confirm the rescheduling trigger time point based on the initial action sequence and the preset rescheduling mechanism.

9. A semiconductor device scheduling device, characterized in that, The semiconductor device scheduling device includes: a memory and at least one processor, and instructions are stored in the memory; At least one of the processors calls the instructions in the memory so that the semiconductor device scheduling device executes each step of the semiconductor device scheduling method according to any one of claims 1-7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that, When the instructions are executed by the processor, each step of the semiconductor device scheduling method according to any one of claims 1-7 is implemented.

Images