A processor system

Abstract

The present application discloses a processor system, which relates to the field of computer technology. The system includes a processor node, a scheduler, and a system storage space with a third task set constructed. The processor node includes: a processor and a node storage space; a scheduler for screening a reference processor from the processor; screening a target task set from a candidate task set based on the task volume information of the reference task set, wherein the reference task set is a first task set in the processor storage space possessed by the reference processor, and the candidate task set includes: a reference task set, a second task set in the processor node where the reference processor is located, and a third task set; distributing the reference task to the target task set; and a reference processor for executing the tasks stored in the candidate task set. Through the present application, the technical problem of low processing efficiency of read and write requests in the related art is solved, and the technical effect of improving the processing efficiency of read and write requests is achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processor system. Background Art

[0002] With the continuous advancement of modern technology, the process by which processors handle read and write requests has attracted increasing attention. In multiprocessor systems, read and write requests are typically handled by the processor that generates the request (or task). However, in the NUMA (Non-Uniform Memory Access) architecture, this request allocation method presents significant issues. Due to transmission latency between storage devices and processors, read and write requests can easily cross NUMA nodes for data transmission, resulting in reduced processing efficiency. Furthermore, when processing read and write requests, each processor is prone to a backlog of pending requests, further impacting read and write request processing efficiency. Summary of the Invention

[0003] The present application provides a processor system to at least solve the problem of low processing efficiency of read and write requests in related technologies.

[0004] The present application provides a processor system, comprising: multiple processor nodes, a scheduler, and a system storage space, wherein each processor node comprises: one or more processors and a node storage space, each processor having a processor storage space, a first task set being constructed in the processor storage space, a second task set being constructed in the node storage space, and a third task set being constructed in the system storage space;

[0005] A scheduler is configured to select a reference processor corresponding to the received reference task from the processors; select a target task set from the candidate task set based on the task amount information of the reference task set, wherein the reference task set is a first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, a second task set in the processor node where the reference processor is located, and a third task set; and distribute the reference task to the target task set;

[0006] A reference processor is used to execute tasks stored in the candidate task set.

[0007] According to the present application, since the processor system includes multiple processor nodes, a scheduler and a system storage space, each processor node includes: one or more processors, and a node memory, each processor has a processor storage space, a first task set is constructed in the processor storage space, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space, the scheduler is used to filter out a reference processor corresponding to the received reference task from the processor, and the method of directly processing the reference task by the processor generating the reference task is replaced by the method of processing the reference task by the scheduler filtering the corresponding reference processor to process the reference task, thereby avoiding unnecessary cross-NUMA node transmission of the reference task in the processor system; the scheduler then filters out a target task set from a candidate task set including the reference task set, the second task set in the processor node where the reference processor is located, and the third task set based on the task volume information of the reference task set, and the reference processor is used to execute the tasks stored in the candidate task set, thereby avoiding the situation where only a single fixed processor can process read and write tasks, further improving the processing efficiency of read and write tasks. Therefore, the technical problem of low processing efficiency of read and write requests can be solved, and the technical effect of improving the processing efficiency of read and write requests can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 is a schematic diagram of a processor system according to an embodiment of the present application;

[0010] Figure 2 is a schematic diagram of a processor system incorporating a user-mode storage mechanism according to an embodiment of the present application;

[0011] Figure 3 This is a flowchart of a method for processing a reference task according to an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0013] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0014] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0015] In this embodiment, a processor system is provided. Figure 1 is a schematic diagram of a processor system according to an embodiment of the present application, such as Figure 1 As shown, the processor system includes:

[0016] Multiple processor nodes, schedulers, and system storage space, each processor node includes: one or more processors, and, node storage space, each processor has a processor storage space, a first task set is constructed in the processor storage space, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space;

[0017] A scheduler is configured to select a reference processor corresponding to the received reference task from the processors; select a target task set from the candidate task set based on the task amount information of the reference task set, wherein the reference task set is a first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, a second task set in the processor node where the reference processor is located, and a third task set; and distribute the reference task to the target task set;

[0018] A reference processor is used to execute tasks stored in the candidate task set.

[0019] Through the above content, since the processor system includes multiple processor nodes, a scheduler and a system storage space, each processor node includes: one or more processors, and, a node memory, each processor has a processor storage space, a first task set is constructed in the processor storage space, a second task set is constructed in the node storage space, and a third task set is constructed in the system storage space, the scheduler is used to filter out a reference processor corresponding to the received reference task from the processor, and replaces the method of directly processing the reference task by the processor that generates the reference task by filtering the corresponding reference processor to process the reference task, thereby avoiding unnecessary cross-NUMA node transmission of the reference task in the processor system; the scheduler then filters out a target task set from a candidate task set including the reference task set, the second task set in the processor node where the reference processor is located, and the third task set based on the task volume information of the reference task set, and the reference processor is used to execute the tasks stored in the candidate task set, thereby avoiding the situation where only a single fixed processor can process read and write tasks, further improving the processing efficiency of read and write tasks. Therefore, the technical problem of low processing efficiency of read and write requests can be solved, and the technical effect of improving the processing efficiency of read and write requests can be achieved.

[0020] Optionally, in this embodiment, the processor system may include, but is not limited to, multiple processor nodes, and each processor node may include, but is not limited to, one or more processors. For example, a multi-core CPU (Central Processing Unit) may be regarded as a processor system, but is not limited to being a central processing unit. The multiple cores (i.e., processors) in the multi-core CPU may be divided into, but is not limited to, multiple core sets (i.e., processor nodes).

[0021] Optionally, in this embodiment, the processor system may include but is not limited to system storage space, each processor node may include but is not limited to node storage space, and each processor may include but is not limited to processor storage space, wherein each processor in the processor system may access its own processor storage space with low latency, and may also access the node storage space in the processor node where each processor is located with low latency, but the access delay of each processor to the system storage space will be higher than the access delay to the node storage space in the processor node where each processor is located, and also higher than the access delay to the processor storage space in each processor.

[0022] Optionally, in this embodiment, a first task set may be constructed in the processor storage space of each processor, a second task set may be constructed in the node storage space of each processor node, and a third task set may be constructed in the system storage space. Each first task set may correspond to each processor, but is not limited to one-to-one correspondence, and each second task set may correspond to multiple processors. For example, in a processor system, the first task set a corresponds to processor A, the first task set b corresponds to processor B, the first task set c corresponds to processor C, the second task set d corresponds to processor A and processor B, and the second task set e corresponds to processor C.

[0023] Optionally, in this embodiment, each processor may, but is not limited to, preferentially extracting tasks from the corresponding first task set for execution; if there are no tasks to be executed in the corresponding first task set, extracting tasks from the corresponding second task set for execution; and if there are no tasks to be executed in the corresponding second task set, extracting tasks from the third task set for execution.

[0024] Optionally, in this embodiment, the scheduler may be used, but is not limited to, to determine the scope of the execution subject for the received reference task. The scheduler may be used, but is not limited to, to screen out the reference processor corresponding to the received reference task from the processor, and give priority to determining the reference processor and the processor in the same processor node as the reference processor as the processor that can execute the reference task (i.e., give priority to distributing the reference task to the reference task set and the second task set in the processor node where the reference processor is located). In order to avoid the reference task being completely unable to be executed due to a failure of the processor node where the reference processor is located, the scheduler may be used, but is not limited to, to determine all processors in the processor system as processors that can execute the reference task (i.e., distributing the reference task to the third task set) when the processor node where the reference processor is located is completely unable to process the reference task or the load pressure is high.

[0025] Optionally, in this embodiment, a storage device-core (or processor) binding matrix that minimizes the NUMA distance cost function may be constructed based on, but is not limited to, the topological relationship between the storage device's PCIe (Peripheral Component Interconnect Express) location and the CPU socket, and the NUMA distance cost function. This means establishing a correspondence between the storage device and the processor. The scheduler's selection of a reference processor corresponding to a received reference task from the processors may include, but is not limited to, matching a corresponding processor for the reference storage device corresponding to the reference task from among the corresponding storage devices and processors to obtain the reference processor. The reference task may be, but is not limited to, requesting access to the reference storage device.

[0026] Optionally, in this embodiment, the task quantity information may be, but is not limited to, used to indicate the task quantity of the tasks in the reference task set. It may be, but is not limited to, determining the reference task set as the target task set when the task quantity information is used to indicate that the task quantity of the tasks in the reference task set is less than or equal to a task quantity threshold; and determining the second task set or the third task set in the processor node where the reference processor is located as the target task set when the task quantity information is used to indicate that the task quantity of the tasks in the reference task set is greater than the task quantity threshold.

[0027] Optionally, in this embodiment, when the first task set includes too many tasks, some of the tasks included in the first task set may be migrated to the corresponding second task set, but is not limited to the above.

[0028] Optionally, in this embodiment, when the second task set includes too many tasks, some of the tasks included in the second task set may be migrated to the third task set, but is not limited to the above.

[0029] Optionally, in this embodiment, the processor system of the present application can be applied, but is not limited to, in a task processing flow that does not require switching between user mode and kernel mode, so that when the reference processor executes the tasks stored in the candidate task set, it only needs to use the user mode driver to interact with the storage device without switching to kernel mode, thereby further improving the processing efficiency of read and write requests.

[0030] Figure 2This is a schematic diagram of a processor system incorporating a user-space storage mechanism according to an embodiment of the present application. The top layer of the user-space storage system is the application layer, typically representing applications requiring high-performance storage, such as databases, caches, and distributed file systems. The application layer relies on the user-space storage library / engine to handle storage needs. The user-space storage library / engine is the core component of the user-space storage system, providing storage-related interfaces and implementations, such as data block management, file system implementation, and database storage engine. It handles the reading, writing, allocation, management, and recovery of stored data. User-space storage management manages the use of storage resources, including memory allocation, data caching, persistent storage, space optimization, and data compression. It coordinates data block operations within the library / engine and determines when to persist data to the underlying storage device. In a multitasking environment, I / O request scheduling manages storage requests from applications, ensuring that requests are distributed to storage devices in an orderly and appropriate manner. It typically implements policies such as I / O queues, priority scheduling, and load balancing. Components at this level, called user-space drivers, are responsible for communicating with the underlying hardware storage devices. Traditional storage device drivers typically reside in kernel mode, but in user-space storage systems, drivers can also run in user space, controlling storage devices through specialized technologies such as the Data Processing Unit (DPU), Remote Direct Memory Access (RDMA), and the Storage Performance Development Kit (SPDK). At the lowest level are the actual storage devices, including disks, Solid State Drives (SSDs), Non-Volatile Memory Express (NVMe), and network storage such as iSCSI (Internet Small Computer Systems Interface), NFS (Network File System), and Ceph. These devices provide physical storage space for the user-space storage system.

[0031] As an optional embodiment, the processor system also includes multiple storage devices; a scheduler, used to match a corresponding processor for a target storage device from processors and storage devices with a corresponding relationship to obtain a reference processor, wherein the target storage device is a storage device requested to be accessed by a reference task among multiple storage devices; a scheduler, used to detect a first state of a reference task set indicated by task quantity information; when the first state is that the task quantity of the reference task set is less than a first threshold, determining the reference task set as a target task set; when the first state is that the task quantity of the reference task set is greater than or equal to the first threshold, detecting a second state of a second task set in the processor node where the reference processor is located; when the second state is that the task quantity of the second task set in the processor node where the reference processor is located is less than a second threshold, determining the second task set in the processor node where the reference processor is located as the target task set; when the second state is that the task quantity of the second task set in the processor node where the reference processor is located is greater than or equal to the second threshold, determining the third task set as the target task set.

[0032] Optionally, in this embodiment, the multiple processors included in the processor system may have, but are not limited to, different access delay characteristics to the multiple storage devices included in the processor system, and the multiple processors located in the same processor node may have, but are not limited to, the same access delay characteristics to the same storage device; it may be possible, but not limited to, to match a corresponding processor for the target storage device from processors and storage devices with corresponding relationships so that the processor with lower access delay to the target storage device can execute the reference task first, thereby improving the processing efficiency of read and write requests.

[0033] Optionally, in this embodiment, the scheduler can be used, but is not limited to, to filter out a target task set from a candidate task set based on the first task state of the reference task set, the second task state of the second task set in the processor node where the reference processor is located, and the third task state of the third task set.

[0034] As an optional implementation, the scheduler is also used to aggregate multiple processing requests into one or more processing tasks based on the request information of the processing requests and the processing information of each storage device, wherein the one or more processing tasks include a reference task, the request information is used to indicate the storage device requested to be accessed by the processing request, the request information corresponding to the processing requests included in the processing task is the same, and the processing information is used to indicate the data access capability of each storage device.

[0035] Optionally, in this embodiment, when the scheduler receives a processor request, it may, but is not limited to, not directly distribute the processing request to each task set for processing, but instead aggregates multiple processing requests requesting access to the same storage device into a whole, obtains a processing task, and then distributes each processing task.

[0036] Optionally, in this embodiment, when the scheduler aggregates processing requests into processing tasks, the number of processing requests to be aggregated into one processing task may be determined by, but not limited to, the data access capability of each storage device.

[0037] Through the above content, multiple processing requests are aggregated into one processing task, and a corresponding processor is assigned to the processing task. Compared with assigning a corresponding processor to a processing request, the number of scheduling operations of the scheduler is reduced, saving operation resources.

[0038] As an optional embodiment, a fourth task set is also constructed in the processor storage space; the scheduler is also used to detect the processing priority of each processing request before aggregating multiple processing requests into one or more processing tasks based on the request information of the processing requests and the processing information of each storage device, wherein the processing priority is used to indicate the importance of the processing request; when it is detected that the processing priority of the target request is used to indicate that the importance of the target request is higher than the degree threshold, the target request is distributed to the priority task set, wherein each processing request includes the target request, and the priority task set is the fourth task set in the processor storage space of the target processor corresponding to the target request; the target processor is used to give priority to executing the tasks stored in the priority task set when the priority task set is not empty; when the tasks stored in the priority task set are completed, execute the tasks stored in the first task set in the processor storage space of the target processor, or the tasks stored in the second task set in the processor node where the target processor is located, or the tasks stored in the third task set.

[0039] Optionally, in this embodiment, in addition to constructing the first task set in each processor storage space, a fourth task set can be constructed but is not limited to being constructed, wherein the execution priority of the tasks in the fourth task set in the same processor storage space is higher than the execution priority of the tasks in the first task set.

[0040] Optionally, in this embodiment, the scheduler may, but is not limited to, detect the processing priority of the processing request before aggregating multiple processing requests. Generally speaking, processing requests whose importance indicated by the processing priority is higher than the degree threshold need to be executed at the fastest speed. Therefore, when it is detected that the processing priority of the target request is used to indicate that the importance of the target request is higher than the degree threshold, the target request is distributed to the priority task set so that the target request can be executed quickly.

[0041] Through the above content, the scheduler will not blindly aggregate processing requests, but will distribute processing requests with more urgent execution requirements to the fourth task set with higher execution priority, so that sudden emergency processing requests can be executed quickly, thereby improving the processing efficiency of read and write requests from another level.

[0042] As an optional implementation, the scheduler is also used to detect the data volume requested by the reference task to access; when the data volume is greater than the data volume threshold, the target task set is filtered out from the alternative task set, wherein the alternative task set includes: the second task set and the third task set in the processor node where the reference processor is located; when the data volume is less than or equal to the data volume threshold, the step of filtering out the target task set from the candidate task set according to the task volume information of the reference task set is executed.

[0043] Optionally, in this embodiment, the scheduler can be, but is not limited to, also used to detect the data volume requested by the reference task to access. When the data volume is greater than a data volume threshold, that is, the data volume is too large, the reference task is directly distributed to the second task set or the third task set. This is because a reference task with a large data volume is likely to trigger task migration, causing such a reference task to be migrated to the second task set or the third task set after being distributed to the first task set. The intermediate migration operation increases the useless operation overhead of the system. By no longer allocating such a reference task to the first task set when it is detected that the data volume is greater than the data volume threshold, the waste of operation resources caused by the migration step is reduced.

[0044] As an optional embodiment, the processor system also includes a regulator; the regulator is used to migrate part of the tasks stored in the first adjustment set to the second task set on the same processor node as the first adjustment set when the task quantity parameter in the first adjustment set in each first task set is greater than a third threshold, wherein the task quantity parameter is used to indicate the task quantity of the tasks currently stored in the corresponding task set, and the task set includes the first task set, the second task set and the third task set.

[0045] Optionally, in this embodiment, the processor system may include, but is not limited to, a regulator, and the regulator may be used to adjust the number of tasks stored in the first task set, the second task set, and the third task set.

[0046] Through the above content, when there are too many tasks stored in the first adjustment set, some tasks will be migrated to the corresponding second task set, that is, the tasks that the processor corresponding to the first adjustment set cannot process in time are forwarded to other processors in the same processor node for processing, effectively utilizing the processing capabilities of each processor of the processor node.

[0047] As an optional implementation, the regulator is further configured to migrate part of the tasks stored in the second adjustment set to the third task set when a task quantity parameter in the second adjustment set in each second task set is greater than a fourth threshold.

[0048] Optionally, in this embodiment, the difference between the task amount parameter of the second adjustment set and the fourth threshold may be calculated, but is not limited to, and tasks with the difference amount are extracted from the second adjustment set and migrated to the third task set.

[0049] Optionally, in this embodiment, the fourth threshold value can be, but is not limited to, determined based on the data transmission delay time across processor nodes, and can be, but is not limited to, when the task quantity parameter in the second adjustment set is equal to the fourth threshold value, the time difference between the waiting time before the last executed tail task in the second adjustment set is executed and the migration time of the tail task in the process of executing the tail task across processor nodes by processors in other processor nodes (i.e., the time for migrating from the second task set to the third task set) is within a narrow time difference range.

[0050] Through the above content, by migrating some tasks stored in the second adjustment set to the third task set when the task volume parameter in the second adjustment set is greater than the fourth threshold, when the load pressure of the processors in the same processor node is large, the delay of data transmission across nodes and the waiting delay of task execution can be comprehensively considered, and the processing efficiency of read and write requests can be better improved in combination with actual conditions.

[0051] As an optional embodiment, the regulator is further used to detect a change parameter in the second adjustment set, wherein the change parameter is used to indicate the speed at which the tasks stored in the second adjustment set are executed; when it is detected that the change parameter is used to indicate that the tasks stored in the second adjustment set are executed at a speed higher than a speed threshold, the step of migrating some tasks stored in the second adjustment set to the third task set is canceled or delayed.

[0052] Optionally, in this embodiment, when tasks in the second adjustment set are executed quickly, migration of tasks in the second task set to the third task set may be delayed or canceled to reduce unnecessary migration operations.

[0053] As an optional implementation, the regulator is also used to reduce the migration amount of tasks migrated to the third adjustment set when the task amount parameter in the third adjustment set in each second task set is greater than or equal to the fifth threshold, wherein the fifth threshold is greater than the fourth threshold; the regulator is also used to cancel the migration of tasks to the third task set when the task amount parameter in the third task set is greater than or equal to the sixth threshold.

[0054] Optionally, in this embodiment, when the task volume parameter in each second task set is greater than the fifth threshold, that is, when the load of tasks to be executed in each second task set is too heavy, task migration from the first task set to the second task set can be reduced, but is not limited to.

[0055] Optionally, in this embodiment, when the task volume parameter in the third task set is greater than the sixth threshold, that is, when the load of tasks to be executed in each third task set is too heavy, the task migration from each second task set to the third task set can be canceled, but is not limited to.

[0056] Through the above, when there are too many tasks in the second task set and the third task set, the corresponding task migration is reduced or canceled, thereby avoiding the operational burden on the system caused by unnecessary migration.

[0057] As an optional implementation, the reference processor is used to execute the tasks stored in the reference task set when the reference task set is not empty; to execute the tasks stored in the second task set in the processor node where the reference processor is located when the reference task set is empty and the second task set in the processor node where the reference processor is located is not empty; and to execute the tasks stored in the third task set when the reference task set is empty and the second task set in the processor node where the reference processor is located is empty.

[0058] Optionally, in this embodiment, it is possible but not limited to that when the task amount of the reference task set is greater than or equal to the seventh threshold, the reference processor executes the tasks stored in the reference task set; when the task amount of the reference task set is greater than zero and less than the seventh threshold, the reference processor alternately extracts tasks from the reference task set and the second task set in the processor node where the reference processor is located to execute; when the task amount of the reference task set is equal to zero and the task amount of the second task set in the processor node where the reference processor is located is greater than zero and less than the eighth threshold, the reference processor alternately extracts tasks from the second task set and the third task set in the processor node where the reference processor is located to execute; when the task amount of the reference task set is equal to zero and the task amount of the second task set in the processor node where the reference processor is located is greater than or equal to the eighth threshold, the reference processor executes the tasks stored in the second task set in the processor node where the reference processor is located. Through the above content, the reference processor can reasonably utilize its own processing resources, give priority to processing the tasks assigned to the reference processor by the scheduler, improve the coordination of the system, and thereby improve the processing efficiency of read and write requests / tasks.

[0059] Optional, Figure 3 is a flowchart of a reference task processing method according to an embodiment of the present application, such as Figure 3 As shown, applications can, but are not limited to, create threads or processes to initiate tasks. A scheduler (which can be the operating system's scheduler) is responsible for allocating tasks based on load, priority, and other policies. Tasks are queued in various queues (i.e., task collections) and await processing by a core (i.e., processor). The operating system's scheduler selects an idle core for the task. The task executes on the assigned core, and during execution, the core allocation of other pending tasks may be dynamically adjusted to balance the load. Upon task completion, the result is returned and resources are released.

[0060] As an optional implementation, this application also provides an efficient storage system architecture based on SPDK (Storage Performance Development Kit). By systematically reconstructing the NVMe device control plane and optimizing the user-mode I / O interaction paradigm, this architecture achieves breakthroughs in the full-path performance of the storage stack. An efficient storage system architecture based on SPDK may include, but is not limited to, the following aspects:

[0061] (1) Deep optimization of user-mode storage technology:

[0062] Implementing Kernel Bypass and full-stack acceleration through the SPDK user-mode driver architecture:

[0063] On the one hand, through interrupt-free polling scheduling, that is, adopting CPU affinity binding and exclusive core allocation strategies, running 100% of the polling loop on a dedicated CPU core, eliminating context switching overhead, and through the design of memory isolation management, that is, building a physically continuous memory pool, reducing the TLB Miss (Translation Lookaside Buffer Miss) rate (by 75%) through HugePage (2MB (Megabyte) / 1GB (Gigabyte)) pre-allocation, while achieving DMA (Direct Memory Access) direct access, and through asynchronous event channels, that is, implementing a hardware terminal emulation mechanism in user mode, transmitting storage device status updates through an event notification loop, avoiding entering the kernel, and realizing polling mode driver enhancement, effectively reducing the number of kernel switches; on the other hand, through the design of a lightweight TCP / IP (Transmission Control Protocol / Internet Protocol) protocol stack, that is, based on SPDK The iSCSI acceleration framework strips away redundant protocol header processing logic to achieve zero-copy network transmission. Furthermore, by designing metadata bypass, file system metadata operations are mapped to the FPGA (Field-Programmable Gate Array) hardware accelerator card for processing. User-mode only processes the data plane, enabling user-mode protocol stack reconstruction. This results in a 40Gbps (Gigabits per second) line rate throughput and metadata latency reduced to 3μs (microseconds).

[0064] (2) Multi-core parallel acceleration system:

[0065] Design a NUMA-aware fine-grained parallel architecture to achieve linear scalability:

[0066] 1. Lock-free task distribution mechanism:

[0067] Multi-level ring queue: A single-producer / multi-consumer model is used to build a three-level queue (L1 (i.e., the first task set): in-core cache, L2 (i.e., the second task set): shared within the NUMA node, and L3 (i.e., the third task set): a cross-node global queue). Lock-free synchronization is achieved by combining atomic operations, resulting in a lock contention rate of less than 0.1%.

[0068] Then set up the migration mechanism in queues at different levels:

[0069] L1->L2 migration: Dynamically adjust the size of batch migration based on L1 fill rate;

[0070] batch_size (batch migration size) = max(L1_FILL_RATIO (ratio of migration size to total capacity) × L1_CAPACITY (capacity of the L1 queue), MIN_BATCH (minimum allowed migration size));

[0071] if (batch_size > L2_FREE_SPACE (the capacity free margin of the L2 queue)) batch_size = L2_FREE_SPACE;

[0072] L2->L3 migration: using dual triggering of time window and spatial threshold;

[0073] Triggered when the L2 fill rate is > 60% or no migration has occurred in the last 100ms (milliseconds);

[0074] If L2 data is consumed quickly by consumers on the NUMA node, the push to L3 can be delayed or canceled to reduce unnecessary transmission. Alternatively, when a producer bursts with large amounts of data, L1 can be bypassed directly and written in batches to L2 or L3, reducing the overhead of intermediate steps.

[0075] Table 1 is a threshold setting method for the queue migration mechanism. As shown in Table 1, it can be, but is not limited to, when the task volume of the L1 queue is greater than the high watermark of the L1 queue (i.e., the first threshold), reducing the storage of pending tasks in the L1 queue; when the task volume of the L1 queue is greater than the low watermark of the L1 queue (i.e., the third threshold), migrating some tasks in the L1 queue to the L2 queue; when the task volume of the L2 queue is greater than the low watermark of the L2 queue (i.e., the fourth threshold), migrating some tasks in the L2 queue to the L3 queue; when the task volume of the L2 queue is greater than or equal to the high watermark of the L2 queue (i.e., the fifth threshold), restricting the migration of tasks from the L1 queue to the L2 queue; and when the task volume of the L3 queue is greater than the high watermark of the L3 queue (i.e., the sixth threshold), suspending the migration of tasks from the L2 queue to the L3 queue.

[0076] Table 1

[0077]

[0078] This application also provides dynamic load feedback regulation: the load indicators of each core are collected in real time through the PMU (Performance Monitoring Unit), and the PID (Proportional-Integral-Derivative) controller is used to dynamically adjust the task sharding weight, that is, to adjust the data volume of multiple requests included in a task.

[0079] Before actually processing read and write requests, this application also designed NUMA topology-aware scheduling: Based on the relationship between the device's PCIe location and the CPU slot topology, an optimal device (i.e., storage device)-core (i.e., processor) binding matrix is constructed (based on the principle of minimizing the NUMA distance cost function), reducing the proportion of cross-node accesses to less than 5%. A second-level cache is also established within the local NUMA node, using the LRU-K (Least Recently Used-K) algorithm to manage hot data, achieving a cache hit rate of over 92%.

[0080] (3) I / O acceleration engine implementation:

[0081] Build an end-to-end zero-copy pipeline processing architecture:

[0082] This application automatically adjusts I / O aggregation granularity (range: 64-256 requests / batch) based on the number of SSD parallel units, and combines a priority preemption mechanism to ensure that high-priority requests have a latency of <50μs. The host application / file system issues discrete I / O requests through the NVMe driver. The request receiving end is the SSD controller's front-end interface layer (PCIe PHY (Physical Layer) + NVMe protocol parser module). The processing execution end includes a scheduler that dynamically generates a 64-256 variable aggregation window based on the number of SSD parallel units (NAND (Not AND) channels / Chip Enable pins). The priority arbiter implements preemptive scheduling. When a high-priority request arrives, it freezes the current low-priority batch processing and processes the high-priority request through a dedicated fast path. Finally, the NAND flash management unit (FTL (Flash Translation Layer)) maps the aggregated batch operations to physical blocks.

[0083] The above process of aggregating multiple IO requests into a single IO task can be implemented, but is not limited to, through the following code:

[0084] def adjust_batch_size():

[0085] if nand_channels_idle > 4 and pcie_traffic < 50%:

[0086] return 256; # Maximize throughput mode

[0087] elif cache_hit_ratio > 70%:

[0088] return 128; # Cache acceleration mode

[0089] else:

[0090] return 64; # Low latency priority mode

[0091] # Intelligent learning module injection (based on LSTM to predict the next 3ms load)

[0092] if neural_engine.predict_load() == "BURSTY":

[0093] apply_prefetch_window(32); # Preload part of the request

[0094] Regarding the processing of higher priority IO requests, the critical path of execution will be preempted:

[0095] The hardware filter only allows high-priority requests with an interval of ≤10μs to trigger preemption; the NAND controller's Multi-Plane Operation Suspend instruction (0x85h CMD (Command)) is used to temporarily suspend the processing of ordinary aggregated I / O requests; the PRP list breakpoints of the current DMA transfer are saved in a dedicated cache (On-chip SRAM (On-chip Static Random Access Memory)); the design hard real-time constraints: time window isolation: insert checkpoints every 50μs (hardware-enforced checkpoints); worst-case latency modeling: WCL (Worst Case Latency) = (DMA Suspend Period × 2) + NAND_resume_latency (NAND resume latency) + PCIe_ACK_time (PCIe acknowledgment time).

[0096] In order to ensure that higher-priority IO requests can also be quickly executed in the storage device, storage resources can be reserved in the storage device, but are not limited to. Table 2 is a resource reservation strategy. As shown in Table 2, the storage resources of the storage device can be divided into a preemptive reserved pool dedicated to higher-priority IO requests and a regular batch provided for aggregation of ordinary IO requests.

[0097] Table 2

[0098]

[0099] To optimize I / O request processing speed, scattered I / O requests can be aggregated into a single SG (scatter-gather) descriptor chain, but are not limited to this. A single NVMe submission queue entry (SQE) can carry 128 logical block addresses (LBAs), increasing SQE utilization by a factor of 6. The DMA engine in the host NVMe driver aggregates scattered PRP lists (physical memory page addresses) into a scatter-gather descriptor chain. On the protocol encapsulation side: NVMe submits the SQ Controller (queue controller), which encapsulates the chain descriptor into a single SQE, achieving: a single SQE carries 128 LBAs (the relevant solution only has 21 LBAs); the SQE payload is increased by 6 times (effectively reducing the queue depth occupancy); on the processing execution side: the SSD controller's command parsing unit parses the SG chain structure through the hardware accelerator; in the process of data flowing to the terminal: write operation: data is written to multiple parallel NAND Dies (NAND flash memory chips) through the on-chip SRAM (Static Random Access Memory) buffer pool; read operation: aggregated data blocks are transferred back to the host memory through the PCIe link DMA.

[0100] Optionally, this application also designs zero-copy transmission acceleration through physical address transparent relay and persistent memory direct writing: the application buffer is directly mapped to the SPDK memory pool through mmap (Memory Map), and the NVMe DMA engine directly reads user space data (eliminating two memory copies and achieving 98% bandwidth utilization); the PMDK library is used to implement user-mode App Direct mode to access Persistent Memory, reducing data write latency to 300ns (nanoseconds).

[0101] (IV) Storage Protocol and Data Organization Innovation:

[0102] Protocol layer optimization for distributed storage and big data scenarios:

[0103] The traditional 24-byte RPC (Remote Procedure Call) header is compressed to 8 bytes (retaining the opcode and sequence number), and a hardware CRC32C (Cyclic Redundancy Check 32C) checksum replaces the full TCP checksum (reducing network overhead by 60%) to streamline the RPC protocol header. Metadata compression encoding: Delta Encoding + Zstandard algorithm compresses the directory tree structure, reducing metadata size to 15% of its original size. Adaptive sharding: Dynamically adjusts shard size (variable granularity from 4KB to 1MB) based on the number of parallel units within the SSD, enabling parallel writes across dies / planes (increasing write throughput by 4.2x). Erasure coding hot and cold tiering: Cold data is encoded with EC (Erasure Coding) and stored sequentially, while hot data is replicated. This reduces storage costs by 35% while ensuring access latency for hot data is no more than 2ms. Leveraging topology-aware data distribution: Based on improvements to the Ceph CRUSH (Controlled Replication Scalable Hashing in Distributed Storage Systems) algorithm and the addition of hardware topology parameters such as NUMA nodes and SSD channels, the probability of data locality has been increased to 85%. A machine learning prefetching engine has also been introduced: using an LSTM (Long Short-Term Memory) model to predict access patterns, it preloads data into the local NUMA node cache (prefetch accuracy >80%, improving random read performance by 3x).

[0104] The following is the relevant code implementation of this solution:

[0105] Implementing user-mode I / O through SPDK's NVMe driver:

[0106] struct spdk_nvme_qpair *qpair = spdk_nvme_get_io_qpair(nvme_device);

[0107] spdk_nvme_cmd cmd;

[0108] cmd.opcode = SPDK_NVME_CMD_READ;

[0109] cmd.nsid = 1;

[0110] cmd.slba = lba;

[0111] cmd.dlen = data_len;

[0112] cmd.metadata_len = metadata_len;

[0113] / / Submit the command to the queue

[0114] spdk_nvme_submit_cmd(qpair, &cmd, data_buf, metadata_buf, cb_fn, cb_arg);

[0115] Task distribution is achieved through a lock-free ring queue:

[0116] / / Define a lock-free ring queue structure

[0117] struct ring_buffer {

[0118] uint64_t head;

[0119] uint64_t tail;

[0120] void *buffer[];

[0121] };

[0122] / / Initialize the circular queue

[0123] void init_ring_buffer(struct ring_buffer *rb, size_t size) {

[0124] rb->head = 0;

[0125] rb->tail = 0;

[0126] / / Allocate memory and initialize the buffer

[0127] }

[0128] / / The producer adds tasks to the queue

[0129] bool enqueue_task(struct ring_buffer *rb, void *task) {

[0130] uint64_t next_head = (rb->head + 1) % RING_BUFFER_SIZE;

[0131] if (next_head == rb->tail) {

[0132] / / The queue is full, return failure

[0133] return false;

[0134] }

[0135] rb->buffer[rb->head] = task;

[0136] rb->head = next_head;

[0137] return true;

[0138] }

[0139] / / Consumer takes tasks from the queue

[0140] bool dequeue_task(struct ring_buffer *rb, void **task) {

[0141] if (rb->head == rb->tail) {

[0142] / / The queue is empty, return failure

[0143] return false;

[0144] }

[0145] *task = rb->buffer[rb->tail];

[0146] rb->tail = (rb->tail + 1) % RING_BUFFER_SIZE;

[0147] return true;

[0148] }

[0149] Each CPU core has an independent task queue. The system distributes tasks to each queue through polling or load balancing algorithm:

[0150] / / Multi-core task distribution

[0151] void distribute_task(void *task, struct ring_buffer **queues, intnum_cores) {

[0152] / / Select the target core based on the current load

[0153] int target_core = select_target_core(queues, num_cores);

[0154] enqueue_task(queues[target_core], task);

[0155] }

[0156] int select_target_core(struct ring_buffer **queues, int num_cores){

[0157] / / Polling algorithm

[0158] static int current_core = 0;

[0159] return current_core++;

[0160] }

[0161] Through the above solutions, full-stack architecture innovation and deep collaboration with hardware can achieve orders of magnitude improvement in performance, resource efficiency and reliability.

[0162] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0163] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0164] The above is a detailed introduction to a processor system provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A processor system, characterized in that: include: Multiple processor nodes, schedulers, and system storage space, each processor node comprising: one or more processors, and, node storage space, each processor having a processor storage space, a first task set constructed in the processor storage space, a second task set constructed in the node storage space, and a third task set constructed in the system storage space; The scheduler is configured to filter out a reference processor corresponding to the received reference task from the processors; filter out a target task set from a candidate task set based on task amount information of the reference task set, wherein the reference task set is the first task set in the processor storage space of the reference processor, and the candidate task set includes: the reference task set, the second task set in the processor node where the reference processor is located, and the third task set; and distribute the reference task to the target task set; The reference processor is configured to execute tasks stored in the candidate task set; Wherein, the processor system further includes a plurality of storage devices; The scheduler is configured to match a corresponding processor for a target storage device from processors and storage devices having a corresponding relationship to obtain the reference processor, wherein the target storage device is a storage device requested to be accessed by the reference task among the multiple storage devices; The scheduler is used to detect the first state of the reference task set indicated by the task quantity information; when the first state is that the task quantity of the reference task set is less than a first threshold, determine that the reference task set is the target task set; when the first state is that the task quantity of the reference task set is greater than or equal to the first threshold, detect the second state of the second task set in the processor node where the reference processor is located; when the second state is that the task quantity of the second task set in the processor node where the reference processor is located is less than a second threshold, determine that the second task set in the processor node where the reference processor is located is the target task set; when the second state is that the task quantity of the second task set in the processor node where the reference processor is located is greater than or equal to the second threshold, determine that the third task set is the target task set.

2. The processor system according to claim 1, wherein: The scheduler is further used to aggregate multiple processing requests into one or more processing tasks based on the request information of the processing requests and the processing information of each of the storage devices, wherein the one or more processing tasks include the reference task, the request information is used to indicate the storage device requested to be accessed by the processing request, the request information corresponding to the processing requests included in the processing tasks is the same, and the processing information is used to indicate the data access capability of each of the storage devices.

3. The processor system according to claim 2, wherein: A fourth task set is also constructed in the processor storage space; The scheduler is further configured to, before aggregating the plurality of processing requests into one or more processing tasks based on the request information of the processing requests and the processing information of each of the storage devices, detect a processing priority of each of the processing requests, wherein the processing priority is used to indicate the importance of the processing request; and in a case where it is detected that the processing priority of the target request is used to indicate that the importance of the target request is higher than a threshold, distribute the target request to a priority task set, wherein each of the processing requests includes the target request, and the priority task set is the fourth task set in the processor storage space of the target processor corresponding to the target request; The target processor is used to give priority to executing the tasks stored in the priority task set when the priority task set is not empty; and to execute the tasks stored in the first task set in the processor storage space of the target processor, or the tasks stored in the second task set in the processor node where the target processor is located, or the tasks stored in the third task set when the tasks stored in the priority task set are completed.

4. The processor system according to claim 1, wherein: The scheduler is also used to detect the data volume requested by the reference task to access; when the data volume is greater than the data volume threshold, the target task set is filtered out from the alternative task set, wherein the alternative task set includes: the second task set and the third task set in the processor node where the reference processor is located; when the data volume is less than or equal to the data volume threshold, the step of filtering out the target task set from the candidate task set based on the task volume information of the reference task set is executed.

5. The processor system according to claim 1, wherein: The processor system further includes a regulator; The regulator is used to migrate part of the tasks stored in the first adjustment set to the second task set on the same processor node as the first adjustment set when the task quantity parameter in the first adjustment set in each of the first task sets is greater than a third threshold, wherein the task quantity parameter is used to indicate the task quantity of the tasks currently stored in the corresponding task set, and the task set includes the first task set, the second task set and the third task set.

6. The processor system according to claim 5, wherein: The regulator is further configured to migrate part of the tasks stored in the second adjustment set to the third task set when the task quantity parameter in the second adjustment set in each of the second task sets is greater than a fourth threshold.

7. The processor system according to claim 6, wherein: The regulator is further configured to detect a change parameter in the second adjustment set, wherein the change parameter is configured to indicate a speed at which the tasks stored in the second adjustment set are executed; and when it is detected that the change parameter indicates that the tasks stored in the second adjustment set are executed at a speed higher than a speed threshold, cancel or delay the step of migrating some of the tasks stored in the second adjustment set to the third task set.

8. The processor system according to claim 6, wherein: The regulator is further configured to reduce the migration amount of tasks migrated to the third adjustment set when the task amount parameter in the third adjustment set in each of the second task sets is greater than or equal to a fifth threshold, wherein the fifth threshold is greater than the fourth threshold; The regulator is further configured to cancel migrating tasks to the third task set when a task quantity parameter in the third task set is greater than or equal to a sixth threshold.

9. The processor system according to claim 1, wherein: The reference processor is used to execute the tasks stored in the reference task set when the reference task set is not empty; to execute the tasks stored in the second task set in the processor node where the reference processor is located when the reference task set is empty and the second task set in the processor node where the reference processor is located is not empty; and to execute the tasks stored in the third task set when the reference task set is empty and the second task set in the processor node where the reference processor is located is empty.

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