Configuration method and device for instruction set arithmetic unit in multi-core processor

Abstract

The embodiment of the invention provides a configuration method and device for an instruction set arithmetic unit in a multi-core processor. The method comprises the steps that the chip area requirement of the to-be-configured multi-core processor and the vector instruction set extension requirement of each core in the multi-core processor are obtained; according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, selecting a configuration scheme corresponding to the current to-be-configured multi-core processor from the preset instruction set arithmetic unit configuration schemes; based on the configuration scheme, the instruction set arithmetic unit is configured in the current multi-core processor, configuration is flexibly carried out according to an actual application scene in the actual application process, particularly in the scene where the multi-core processor is used, support of each processor core to the V-shaped expansion arithmetic unit can be flexibly controlled in the multi-core processor, and therefore the multi-core processor can be more flexibly controlled. The operation utilization rate of each core in the multi-core processor is greatly improved, and waste of resources is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of multi-core processors, and specifically, to a method, apparatus, computer device, and storage medium for configuring an instruction set operation unit in a multi-core processor. Background Art

[0002] In the RISC-V architecture (RISC-V is an open-source instruction set architecture that defines a set of basic opcodes and registers, as well as some optional extended instructions), the "V" extension can be used for standard server and application processor platform profiles. Other platforms, including embedded platforms, can choose to implement a subset of these extensions. The basic vector extension, which is designed to serve as the basis for other vector extensions in various fields, including cryptography and machine learning, consumes a large amount of hardware resources, such as the instruction set operation unit.

[0003] As Figure 1 shown in , in the related art, in a multi-core processor, an instruction set operation unit is configured for each core. In this configuration, the maximum instruction set processing performance is provided for the multi-core processor. Although the instruction set processing performance is strong, since an instruction set operation unit is configured for each core in the multi-core processor, the chip area of the multi-core processor is particularly large, resulting in performance waste in many scenarios and very low cost performance. Summary of the Invention

[0004] In the embodiments of the present application, a method, apparatus, computer device, and storage medium for configuring an instruction set operation unit in a multi-core processor are provided.

[0005] In the first aspect of the embodiments of the present application, a method for configuring an instruction set operation unit in a multi-core processor is provided, including: Obtaining the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; According to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, selecting a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set operation unit configuration scheme; Based on the configuration scheme, configuring the instruction set operation unit in the current multi-core processor, wherein the preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with an instruction set operation unit; Grouping all the cores of the multi-core processor, and each group of cores shares an instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set arithmetic units, where the number of instruction set arithmetic units is less than the number of cores of the multi-core processor; All cores in the multi-core processor share one instruction set arithmetic unit.

[0006] In an optional embodiment of the present application, the chip area requirements for the multi-core processor to be configured include a primary chip area and a secondary chip area, where the primary chip area is less than the secondary chip area, and the vector instruction set extension requirements for each core in the multi-core processor include a primary vector instruction set extension requirement and a secondary vector instruction set extension requirement, where the primary vector instruction set extension requirement is less than the secondary vector instruction set extension requirement.

[0007] In an optional embodiment of the present application, according to the chip area requirements and the vector instruction set extension requirements for each core in the multi-core processor, selecting a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set arithmetic unit configuration scheme includes: When the chip area requirements for the multi-core processor to be configured and the vector instruction set extension requirements for each core in the multi-core processor are both primary, the configuration scheme for the current multi-core processor to be configured is that all cores in the multi-core processor share one instruction set arithmetic unit; When the chip area requirements for the multi-core processor to be configured are secondary and the vector instruction set extension requirements for at least some cores in the multi-core processor are secondary, according to the different vector instruction set extension requirements for each core in the multi-core processor, select a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than all cores sharing one instruction set arithmetic unit.

[0008] In an optional embodiment of the present application, when the chip area requirements for the multi-core processor to be configured are secondary and the vector instruction set extension requirements for at least some cores in the multi-core processor are secondary, according to the different vector instruction set extension requirements for each core in the multi-core processor, selecting a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than all cores sharing one instruction set arithmetic unit includes: When the chip area requirements for the multi-core processor to be configured are secondary and the vector instruction set extension requirements for a part of all cores in the multi-core processor are secondary, the configuration scheme corresponding to the current multi-core processor to be configured is that for some cores in the multi-core processor, each core is configured with one instruction set arithmetic unit, where each core configured with an instruction set arithmetic unit has a secondary vector instruction set extension requirement, and each core not configured with an instruction set arithmetic unit has a primary vector instruction set extension requirement.

[0009] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirement of at least some cores in the multi-core processor is level two, according to the different vector instruction set extension requirements of each core in the multi-core processor, select a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than sharing one instruction set operation unit by all cores, including: When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirements of all cores in the multi-core processor are level two, if the instruction set processing times of all cores are dispersed in multiple time periods, and after grouping all cores according to the instruction set processing time, the instruction set processing times of each group of cores do not conflict, then the configuration scheme of the current multi-core processor is to group all cores of the multi-core processor, and each group of cores shares one instruction set operation unit.

[0010] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirement of at least some cores in the multi-core processor is level two, according to the different vector instruction set extension requirements of each core in the multi-core processor, select a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than sharing one instruction set operation unit by all cores, including: When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirements of all cores in the multi-core processor are level two, if the instruction set processing times of all cores are concentrated within a preset time period, then the configuration scheme of the current multi-core processor is that all cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor.

[0011] In an optional embodiment of the present application, the method further includes: For multiple cores sharing one instruction set operation unit, when at least two cores simultaneously send instruction set processing requests to the shared one instruction set operation unit, arbitrate the instruction set processing requests simultaneously sent by the multiple cores according to a preset arbitration mechanism to determine the processing order of the shared one instruction set operation unit for the multiple instruction set processing requests.

[0012] The second aspect of the embodiments of the present application provides a configuration device for an instruction set operation unit in a multi-core processor, including: An acquisition module, configured to acquire the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; A selection module, configured to select, according to the chip area requirement and the vector instruction set extension requirement of each core in a multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set operation unit configuration scheme; A configuration module, configured to configure instruction set operation units in the current multi-core processor based on the configuration scheme, wherein, the preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with one instruction set operation unit; Group all cores of the multi-core processor, and each group of cores shares one instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in the multi-core processor share one instruction set operation unit.

[0013] In a third aspect of the embodiments of the present application, there is provided a computer device, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the configuration method of the instruction set operation unit in the multi-core processor as described in any one of the above are implemented.

[0014] In a fourth aspect of the embodiments of the present application, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the configuration method of the instruction set operation unit in the multi-core processor as described in any one of the above are implemented.

[0015] The above technical solutions provided by the embodiments of the present application have at least some or all of the following advantages compared with the prior art: The configuration method of the instruction set operation unit in the multi-core processor described in the embodiments of the present application includes: obtaining the chip area requirements of the multi-core processor to be configured and the vector instruction set extension requirements of each core in the multi-core processor; selecting a configuration scheme corresponding to the current multi-core processor to be configured from the preset instruction set operation unit configuration schemes according to the chip area requirements and the vector instruction set extension requirements of each core in the multi-core processor; and configuring the instruction set operation unit in the current multi-core processor based on the configuration scheme. The preset instruction set operation unit configuration schemes are one of the following four configuration schemes: for some cores in the multi-core processor, each core is configured with one instruction set operation unit; all the cores of the multi-core processor are grouped, and each group of cores shares one instruction set operation unit; all the cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor; all the cores in the multi-core processor share one instruction set operation unit, and it can be flexibly configured according to the actual application scenario in the actual application process. Especially in the scenario of using a multi-core processor, the support of each processor core for the "V" extension operation unit can be flexibly controlled in the multi-core processor, greatly improving the operation utilization rate of each core in the multi-core processor and avoiding waste of resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings: Figure 1 It is a schematic diagram of the configuration of the instruction set operation unit in the multi-core processor provided by the related art; Figure 2 It is a flowchart of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application; Figure 3 It is a schematic diagram of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application applied to the scenario where for some cores in the multi-core processor, each core is configured with one instruction set operation unit; Figure 4 It is a schematic diagram of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application applied to the scenario where all the cores of the multi-core processor are grouped and each group of cores shares one instruction set operation unit; Figure 5 It is a schematic diagram of the configuration method of the instruction set operation unit in the multi-core processor provided by an embodiment of the present application applied to the scenario where all the cores of the multi-core processor freely share multiple instruction set operation units; Figure 6Schematic diagram of the configuration method of the instruction set operation unit in a multi-core processor provided by an embodiment of the present application, applied to the scenario where all cores in the multi-core processor share one instruction set operation unit; Figure 7 Schematic diagram of the configuration device structure of the instruction set operation unit in a multi-core processor provided by an embodiment of the present application; Figure 8 Schematic diagram of the computer device structure provided by an embodiment of the present application. Detailed implementation manners

[0017] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further details the exemplary embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0018] Please refer to Figure 2 , the configuration method of the instruction set operation unit in the multi-core processor provided by the embodiment of the present application includes the following steps S100 to S300: S100, obtaining the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; S200, according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor, selecting a configuration scheme corresponding to the current multi-core processor to be configured from the preset instruction set operation unit configuration schemes; S300, based on the configuration scheme, configuring the instruction set operation unit in the current multi-core processor, wherein, the preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with an instruction set operation unit; Grouping all cores of the multi-core processor, and each group of cores shares one instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, wherein the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in the multi-core processor share one instruction set operation unit.

[0019] In an optional embodiment of the present application, the chip area requirements for the multi-core processor to be configured include a first-level chip area and a second-level chip area, where the first-level chip area is smaller than the second-level chip area, and the vector instruction set expansion requirements for each core in the multi-core processor include a first-level vector instruction set expansion requirement and a second-level vector instruction set expansion requirement, where the first-level vector instruction set expansion requirement is smaller than the second-level vector instruction set expansion requirement.

[0020] In an optional embodiment of the present application, the first-level chip area is within a first preset area range, and the second-level chip area is within a second preset area range, where the maximum value of the first preset area range is smaller than the minimum value of the second preset area range. The first-level vector instruction set expansion requirement is that no instruction set processing performance is required, and the second-level vector instruction set expansion requirement is that instruction set processing performance is required.

[0021] In an optional embodiment of the present application, according to the chip area requirements and the vector instruction set expansion requirements for each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from a preset instruction set arithmetic unit configuration scheme, including: When the chip area requirements for the multi-core processor to be configured and the vector instruction set expansion requirements for each core in the multi-core processor are both at the first level, the configuration scheme for the current multi-core processor to be configured is that all cores in the multi-core processor share one instruction set arithmetic unit; When the chip area requirements for the multi-core processor to be configured are at the second level and the vector instruction set expansion requirements for at least some cores in the multi-core processor are at the second level, according to the different vector instruction set expansion requirements for each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than all cores sharing one instruction set arithmetic unit.

[0022] See Figure 3 , when we pursue the minimum area in the first-level chip area in a multi-core processor system, we also need each core to be able to use the instruction set arithmetic unit. A shared instruction set arithmetic unit can be configured for each processor core. In this configuration, the most extreme area and cost performance are provided for the multi-core processor system, while also taking into account the requirement that each core can use the instruction set arithmetic unit.

[0023] In an optional embodiment of the present application, when the chip area requirements for the multi-core processor to be configured are at the second level and the vector instruction set expansion requirements for at least some cores in the multi-core processor are at the second level, according to the different vector instruction set expansion requirements for each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than all cores sharing one instruction set arithmetic unit, including: When the chip area requirement of the multi-core processor to be configured is level 2 and some of the cores in all the cores in the multi-core processor have level 2 vector instruction set extension requirements, the current configuration scheme corresponding to the multi-core processor to be configured is to configure an instruction set operation unit for each of the some cores in the multi-core processor, wherein each core configured with an instruction set operation unit has level 2 vector instruction set extension requirements, and each core not configured with an instruction set operation unit has level 1 vector instruction set extension requirements.

[0024] See also Figure 4 In a multi-core processor system, when the area and the computing performance of the instruction set operation unit need to be balanced, the instruction set operation unit can be configured for some cores, that is, an instruction set operation unit is configured for each core that requires instruction set processing performance, and no instruction set operation unit is configured for the core that does not require instruction set processing performance. In this configuration, the optimal distribution of instruction set operation units for the multi-core processor system can be deeply coupled with different application requirements.

[0025] In an optional embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirement of at least some cores in the multi-core processor is level 2, according to the different vector instruction set extension requirements of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from configuration schemes other than the configuration scheme in which all cores share one instruction set operation unit, including: When the chip area requirement of the multi-core processor to be configured is level 2 and the vector instruction set extension requirements of all cores in the multi-core processor are all level 2, if the instruction set processing time of all cores is dispersed in multiple time periods, and after all cores are grouped according to the instruction set processing time, the instruction set processing time of each group of cores does not conflict, then the configuration scheme of the current multi-core processor is to group all the cores of the multi-core processor, and each group of cores shares one instruction set operation unit.

[0026] See also Figure 5 When a multi-core processor system needs to balance area and computing performance, the cores of the multi-core processor system are grouped sequentially or randomly, and a shared instruction set operation unit is provided for each group of cores, wherein multiple cores with staggered instruction set processing times can be grouped into a group of cores. Under this configuration, the multi-core processor system can reduce area while balancing computing performance.

[0027] In an alternative embodiment of the present application, when the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirement of at least some cores in the multi-core processor is level two, according to the different vector instruction set extension requirements of each core in the multi-core processor, a configuration scheme corresponding to the current multi-core processor to be configured is selected from the configuration schemes other than sharing one instruction set operation unit by all cores, including: When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirements of all cores in the multi-core processor are level two, if the instruction set processing times of all cores are concentrated within a preset period, the configuration scheme of the current multi-core processor is that all cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor.

[0028] See Figure 6 , when the multi-core processor system needs to balance area and instruction set processing performance and efficiently utilize the instruction requests of each core, configuring freely shared instruction set operation units for the multi-core processor system can maximize the utilization rate of each instruction set operation unit, and each core can schedule all instruction set operation units. In this configuration, the multi-core processor system can not only reduce the area, but also maintain the instruction set processing performance of the full configuration, and fully utilize the resources of the instruction set operation units.

[0029] In an alternative embodiment of the present application, Figure 6 The cores and instruction set operation units in respectively serve as the master device and slave device connected through a configurable bus interconnection network to generate a bus interconnection system. The working process of this bus interconnection system includes the following steps: Permission information is configured on each master device, where the permission information includes security information and access device identification information; The permission information of each master device is sent to the corresponding slave device port through the user command bit field of the bus; The slave device port checks the received permission information. If the check passes, the subsequent service logic is executed. If the check fails, the request is terminated and an error response is returned.

[0030] In an alternative embodiment of the present application, the permission information of the master device is obtained through bus bundling or programming. When the permission information of the master device is obtained through bus bundling, the address of the slave device port corresponding to the current master device is unique; when the permission information of the master device is obtained through programming, the slave device port corresponding to the current master device includes multiple address ranges.

[0031] In an optional embodiment of the present application, for a slave device port with a unique address, information on whether the port is secure, permission information for read / write execution, and vector logic module information are configured; For slave device ports with multiple address ranges, multiple address regions and corresponding region enable information, region base addresses, region address masks, information on whether the region is secure, permission information for read / write execution, and vector logic module information for each address region are configured.

[0032] In an optional embodiment of the present application, when the address of the slave device port is unique, the slave device port verifies the received permission information, including: If the received permission information is security information and the slave device port is not secure, it is determined that the verification passes; if the received permission information is security information and the slave device port is secure, it is determined that the verification passes when the received permission information meets the requirements of the read / write execution permission information and the vector logic module information at the same time; if the received permission information is not security information and the slave device port is secure, it is determined that the verification fails; if the received permission information is not security information and the slave device port is not secure, it is determined that the verification passes when the received permission information meets the requirements of the read / write execution permission information and the vector logic module information at the same time.

[0033] In an optional embodiment of the present application, when the slave device port includes multiple address ranges, the slave device port verifies the received permission information, including: Compare the transfer address in the received permission information with the multiple address ranges. If the transfer address matches the base address and the address mask of the target region, and the region enable of the target region is enabled, then verify the received permission information according to the information on whether the region of the target region is secure, the read / write execution permission information, and the vector logic module information.

[0034] In an optional embodiment of the present application, verifying the received permission information according to the information on whether the region of the target region is secure, the read / write execution permission information, and the vector logic module information includes: If the received permission information is security information and the region of the target region is not secure, it is determined that the verification passes; if the received permission information is security information and the region of the target region is secure, it is determined that the verification passes when the received permission information meets the requirements of the read / write execution permission information and the vector logic module information at the same time; if the received permission information is not security information and the region of the target region is secure, it is determined that the verification fails; if the received permission information is not security information and the region of the target region is not secure, it is determined that the verification passes when the received permission information meets the requirements of the read / write execution permission information and the vector logic module information at the same time.

[0035] In an optional embodiment of the present application, the multiple address intervals include a designated address interval and a non-designated address interval, and comparing the transmission address in the received permission information with the multiple address intervals includes: comparing the transmission address in the received permission information with the non-specified address interval; When the transfer address does not match the base address and the address mask of each address interval in the non-specified address interval, it is determined that the transfer address matches the base address and the address mask of the specified address interval.

[0036] In an optional embodiment of the present application, in the three application scenarios of each group of cores sharing one instruction set operation unit, all cores of the multi-core processor freely sharing multiple instruction set operation units, and all cores of the multi-core processor sharing one instruction set operation unit, the method further includes: For multiple cores that share an instruction set operation unit, when at least two cores simultaneously issue instruction set processing requests to the shared instruction set operation unit, the instruction set processing requests simultaneously issued by the multiple cores are arbitrated according to a preset arbitration mechanism to determine the processing order of the multiple instruction set processing requests by the shared instruction set operation unit.

[0037] In an optional embodiment of the present application, the preset arbitration mechanism may be the instruction set processing priority of the core, and multiple cores that simultaneously issue instruction set processing requests are sorted according to the instruction set processing priority to obtain the instruction set processing order of the core.

[0038] Based on the flexible and modular characteristics of the RSIC-V instruction architecture, this application provides a variety of solutions for configuring instruction set operation units to cope with application scenarios of different multi-core processor chips, allowing multi-core processor systems to use instruction set operation units more flexibly and efficiently.

[0039] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0040] See also Figure 7 An embodiment of the present application provides a configuration device 700 for an instruction set operation unit in a multi-core processor, comprising: An obtaining module 710, configured to obtain the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; A selecting module 720, configured to select a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set arithmetic unit configuration scheme according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; A configuring module 730, configured to configure the instruction set arithmetic unit in the current multi-core processor based on the configuration scheme, wherein, the preset instruction set arithmetic unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with an instruction set arithmetic unit; Group all the cores of the multi-core processor, and each group of cores shares an instruction set arithmetic unit; All the cores of the multi-core processor freely share multiple instruction set arithmetic units, wherein the number of instruction set arithmetic units is less than the number of cores of the multi-core processor; All the cores in the multi-core processor share an instruction set arithmetic unit.

[0041] The configuration device of the instruction set arithmetic unit in the multi-core processor of the present application provides a different configuration of the instruction set arithmetic unit from the traditional multi-core processor system, and provides four unique schemes to meet the trade-off requirements of the multi-core processor system for area and instruction set processing performance in different application scenarios.

[0042] For the specific limitations of the above device 700, reference may be made to the limitations on the configuration method of the instruction set arithmetic unit in the multi-core processor in the foregoing text, which will not be elaborated here. Each module in the above device 700 can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of the processor, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0043] In one embodiment, a computer device is provided, and the internal structure diagram of the computer device can be as Figure 8As shown. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it realizes a configuration method for an instruction set operation unit in a multi-core processor as described above. It includes: including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it realizes any step in the configuration method for the instruction set operation unit in the multi-core processor as described above.

[0044] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it can realize any step in the configuration method for an instruction set operation unit in a multi-core processor as described above.

[0045] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0046] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the function specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0047] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device realizes the processFigure 1 one process or multiple processes and / or blocks Figure 1 functions specified in one block or multiple blocks.

[0048] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0049] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0050] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A configuration method for an instruction set operation unit in a multi-core processor, characterized in that Including: Obtaining the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; Selecting a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set operation unit configuration scheme according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; Based on the configuration scheme, configuring the instruction set operation unit in the current multi-core processor; Among them, the preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with an instruction set operation unit; Grouping all cores of the multi-core processor, and each group of cores shares an instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in the multi-core processor share an instruction set operation unit.

2. The method according to claim 1, characterized in that, The chip area requirement of the multi-core processor to be configured includes a primary chip area and a secondary chip area, where the primary chip area is less than the secondary chip area, and the vector instruction set extension requirement of each core in the multi-core processor includes a primary vector instruction set extension requirement and a secondary vector instruction set extension requirement, where the primary vector instruction set extension requirement is less than the secondary vector instruction set extension requirement.

3. The method according to claim 2, wherein Selecting a configuration scheme corresponding to the current multi-core processor to be configured from a preset instruction set operation unit configuration scheme according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor includes: When both the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor are at the primary level, the configuration scheme of the current multi-core processor to be configured is that all cores in the multi-core processor share an instruction set operation unit; When the chip area requirement of the multi-core processor to be configured is at the secondary level and the vector instruction set extension requirement of at least some cores in the multi-core processor is at the secondary level, selecting a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than all cores sharing an instruction set operation unit according to the different vector instruction set extension requirements of each core in the multi-core processor.

4. The method according to claim 3, wherein When the chip area requirement of the multi-core processor to be configured is at the secondary level and the vector instruction set extension requirement of at least some cores in the multi-core processor is at the secondary level, selecting a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than all cores sharing an instruction set operation unit according to the different vector instruction set extension requirements of each core in the multi-core processor includes: When the chip area requirement of the multi-core processor to be configured is at the secondary level and the vector instruction set extension requirement of a part of all cores in the multi-core processor is at the secondary level, the configuration scheme corresponding to the current multi-core processor to be configured is that for some cores in the multi-core processor, each core is configured with an instruction set operation unit, where each core configured with an instruction set operation unit has a vector instruction set extension requirement at the secondary level, and each core not configured with an instruction set operation unit has a vector instruction set extension requirement at the primary level.

5. The method according to claim 3, characterized in that, When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirement of at least some cores in the multi-core processor is level two, according to the different vector instruction set extension requirements of each core in the multi-core processor, select a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than sharing one instruction set operation unit by all cores, including: When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirements of all cores in the multi-core processor are level two, if the instruction set processing times of all cores are dispersed in multiple time periods, and after grouping all cores according to the instruction set processing time, the instruction set processing times of each group of cores do not conflict, the configuration scheme of the current multi-core processor is to group all cores of the multi-core processor, and each group of cores shares one instruction set operation unit.

6. The method according to claim 3, wherein When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirement of at least some cores in the multi-core processor is level two, according to the different vector instruction set extension requirements of each core in the multi-core processor, select a configuration scheme corresponding to the current multi-core processor to be configured from the configuration schemes other than sharing one instruction set operation unit by all cores, including: When the chip area requirement of the multi-core processor to be configured is level two and the vector instruction set extension requirements of all cores in the multi-core processor are level two, if the instruction set processing times of all cores are concentrated within a preset time period, the configuration scheme of the current multi-core processor is that all cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor.

7. The method according to claim 1, wherein The method further includes: For multiple cores sharing one instruction set operation unit, when at least two cores simultaneously send instruction set processing requests to the shared one instruction set operation unit, arbitrate the instruction set processing requests simultaneously sent by the multiple cores according to a preset arbitration mechanism to determine the processing order of the shared one instruction set operation unit for the multiple instruction set processing requests.

8. An instruction set arithmetic unit configuration device in a multi-core processor, characterized in that Including: An acquisition module, configured to acquire the chip area requirement of the multi-core processor to be configured and the vector instruction set extension requirement of each core in the multi-core processor; A selection module, configured to select a configuration scheme corresponding to the current multi-core processor to be configured from the preset instruction set operation unit configuration schemes according to the chip area requirement and the vector instruction set extension requirement of each core in the multi-core processor; A configuration module, configured to configure the instruction set operation unit in the current multi-core processor based on the configuration scheme, where the preset instruction set operation unit configuration scheme is one of the following four configuration schemes: For some cores in the multi-core processor, each core is configured with one instruction set operation unit; Group all cores of the multi-core processor, and each group of cores shares one instruction set operation unit; All cores of the multi-core processor freely share multiple instruction set operation units, where the number of instruction set operation units is less than the number of cores of the multi-core processor; All cores in the multi-core processor share one instruction set operation unit.

9. A computer device, comprising: It includes a memory and a processor, and the memory stores a computer program. It is characterized in that when the processor executes the computer program, the steps of the configuration method of the instruction set operation unit in the multi-core processor described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the configuration method of the instruction set operation unit in the multi-core processor described in any one of claims 1 to 7 are implemented.

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