Circuit and method for task monitoring

Abstract

The invention relates to a circuit and a method for task monitoring. Monitoring circuitry that performs logical task monitoring and temporal task monitoring on a plurality of tasks includes task recording circuitry and task management circuitry that receives as inputs a plurality of task signals, each task signal indicating an execution status of a respective task. The task management circuit includes a management circuit configured to operate in at least three modes depending on respective events corresponding to detecting a rising edge of a given task signal, occurrence of a trigger signal, or detecting a falling edge of a given task signal being monitored. In each mode, the management circuit is configured to check whether a variable representing an operational state of a task contains an expected value corresponding to an occurrence of an event that enables the respective mode, and output a result of the check operation in an error signal for a given task being monitored.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Italian Patent Application No. 102024000000096, filed on January 4, 2024, which is hereby incorporated herein by reference. Technical field

[0003] The solution described herein relates to techniques for logically and temporally monitoring multiple tasks executed in a processing system.

[0004] One or more embodiments can be applied to a processing system, particularly in an embedded system, especially a system operating according to the ISO26262 standard. Background art

[0005] Timing is an important property of an embedded system. Safe behavior requires the system to perform its actions and reactions at the correct time. The correct time can be described by a set of timing constraints that must be met. Monitoring of the logical and temporal flow of a program sequence is used in the automotive industry and is mentioned in the ISO26262 standard "Road vehicles – Functional safety", particularly in Table D.10, which is an international standard for the functional safety of electrical and / or electronic systems installed in mass - production road vehicles, as a countermeasure for detecting faults in a processing unit (e.g., the CPU of a microcontroller). In the ISO26262 standard, both logical and temporal flow monitoring are implemented to achieve the highest level of diagnostic coverage.

[0006] Logical flow monitoring checks the sequence of program tasks executed by a processing system to detect defective program sequences. A defective program sequence exists if the individual tasks of a program (e.g., software modules, functions, or statements) are processed in the wrong sequence. Temporal flow monitoring checks the reliability of program execution considering periodic and maximum timing constraints. These two specific software countermeasures run periodically to detect and respond to faults within the FTTI (Fault - Tolerant Time Interval), where FTTI is defined as the period of time during which one or more faults may occur in the system before a hazardous event. Typical values of FTTI range between 1 ms and 10 ms.

[0007] Currently, all automotive microcontrollers targeting higher Automotive Safety Integrity Levels (ASILs) defined by ISO 26262 provide hardware support (e.g., watchdog timer) to implement both logical flow monitoring and time flow monitoring. This watchdog timer generally supports both windowed mode and keyed service mode, which allows for efficient monitoring in any case. However, it is the application's responsibility to insert control flow checkpoints with sufficient granularity to achieve the required diagnostic coverage. Therefore, the implementation of these specific software countermeasures requires significant effort during the application design phase and a high runtime computational load of the microcontroller, i.e., it is proportional to the granularity of the control flow checkpoints. Summary of the Invention

[0008] Based on the foregoing description, there is a need to find a solution to overcome one or more of the drawbacks outlined previously.

[0009] According to one or more embodiments, this is achieved by a circuit having the features specifically set forth in the appended claims. Additionally, embodiments relate to related methods.

[0010] The claims are an integral part of the technical teaching of the disclosure provided herein.

[0011] As mentioned previously, various embodiments of the present disclosure relate to a monitoring circuit for performing logical task monitoring and time task monitoring on multiple tasks executed in a processing system. The monitoring circuit includes:

[0012] A task management circuit;

[0013] A task recording circuit;

[0014] The task management circuit receives multiple task signals as inputs, each task signal indicating the execution status of a corresponding task, and the task management circuit includes a management circuit configured to operate in at least three modes depending on corresponding events associated with the detection of a rising edge or a falling edge of a given task signal being monitored among the multiple task signals or the occurrence of a trigger signal;

[0015] In each mode, the management circuit is configured to check whether a variable representing at least the operating state of the task contains an expected value corresponding to the occurrence of the event enabling the corresponding mode and output the result of the check operation in an error signal for the given task being monitored.

[0016] In a variant embodiment, the management circuit is configured to check a variable indicating whether the task was active or inactive before the occurrence of the event.

[0017] In a variant embodiment, the management circuit is further configured to check a variable indicative of the mode prior to the occurrence of an event.

[0018] In a variant embodiment, in each of at least three modes, the task management circuit is further configured to:

[0019] Store a first timestamp value corresponding to the occurrence of an event in a shared timestamp register;

[0020] Send a corresponding command for each corresponding mode determined by the respective event to the task recording circuit;

[0021] Store a second timestamp value corresponding to the sending of the corresponding command for each corresponding mode determined by the respective event in a capture register;

[0022] Send the first timestamp and the second timestamp value to the task recording circuit;

[0023] The task recording circuit includes at least a table information structure, the table information structure including records storing the second timestamp value and the stored corresponding commands, each record corresponding to a first timestamp value;

[0024] The task recording circuit is configured to calculate the duration of a given task being monitored for the given task being monitored based on the second timestamp value stored for the given task corresponding to each of the events; and check whether the duration of the given task being monitored corresponds to a duration expected value or is included within a range of duration values, and if the duration of the given task is different from the duration expected value or outside the range, then output a signal indicative of an error.

[0025] In a variant embodiment, the error signal includes the timestamp of the error check, and in particular also includes the error type indicated by the indication of the event under which the error was checked.

[0026] In a variant embodiment, the task management circuit includes a plurality of edge detector circuits, each edge detector circuit coupled to a respective task signal, each edge detector circuit being configured to generate a detectable pulse signal at the rising edge and the falling edge of the corresponding task signal, in particular, having a duration of at least one clock cycle.

[0027] In a variant embodiment, the task management circuit further includes:

[0028] A free-running counter;

[0029] A counter capture register;

[0030] The counter capture register is configured to store values captured from a free-running counter corresponding to the occurrence times of events in multiple tasks. In particular, when a rising edge of a task signal among multiple task signals is detected, especially when a rising edge of a given task signal being monitored is detected, the free-running counter is reset.

[0031] In a variant embodiment, the task management circuit further includes:

[0032] A task reload selection register configured to store an identifier of a selected task signal being monitored among multiple task signals;

[0033] A task enable register configured to store a bit corresponding to each task signal among multiple task signals, the bit indicating whether the corresponding task signal is being monitored;

[0034] A task software trigger register configured to store multiple bits corresponding to multiple task signals, and the asserted bits among the multiple bits determine that the task manager generates a software trigger signal. In particular, the software trigger signal is a detectable pulse signal having a duration of at least one clock cycle.

[0035] And particularly further includes a task periodicity register configured to store a bit corresponding to each task signal among multiple task signals, the bit indicating whether the corresponding task signal is periodic, that is, whether it has rising edges occurring at regular intervals.

[0036] In a variant embodiment, the management circuit includes:

[0037] A timestamp counter;

[0038] A task number register for storing a task number identifying which task signal is being monitored;

[0039] A shared task timestamp register configured to store a first timestamp of the timestamp counter;

[0040] A task error register configured to store a timestamp of the error check when an error occurs, and in particular, also store the error type represented by an indication of the event under which the error is checked;

[0041] Multiple task execution registers corresponding to respective task signals and storing variables representing the operating states of the tasks;

[0042] Multiple task timestamp registers, each task timestamp register storing a value in the shared task timestamp register when the corresponding task signal is being monitored;

[0043] Multiple task status registers that store values representing the status of each task signal, the status corresponding to a command;

[0044] The management circuit receives as inputs signals generated by a plurality of edge detector circuits, data from a task reload select register, data from a task enable register, data from a task periodic register, and data from a task software trigger register;

[0045] The management circuit is configured to generate a set of output signals including commands to a task recording circuit, the set of output signals including a start signal, a software trigger signal, a stop signal, and also a task number signal, a first timestamp signal and a second timestamp signal, a task timestamp signal and a task error signal, the content of these signals depending on in which of at least three modes the management circuit operates depending on the corresponding event, and in particular, the set of signals also includes a periodic task signal and a reload signal.

[0046] In a variant embodiment, in response to detecting a rising edge of a task signal among the plurality of task signals, the management circuit is configured to operate in a first mode and includes steps in the following order:

[0047] Check whether the value stored in the task execution register is equal to the expected value corresponding to the occurrence of the event enabling the corresponding mode, and in the case of no, output the result of the check operation in the error signal for the given task being monitored including issuing a task error signal that includes the timestamp of the incorrect check, and in particular also includes the error type indicated by the indication of the event under which the error was checked;

[0048] Write in the task number register the value indicating which task signal among the plurality of task signals is being monitored;

[0049] Read the value stored in the timestamp counter and copy that value in the corresponding shared task timestamp register for the given task signal, increment the value stored in the timestamp counter, in particular increment it by 1;

[0050] Write in the task execution register the expected value corresponding to the occurrence of the subsequent expected event, in particular write a value equal to 1 corresponding to the issuance of the trigger signal;

[0051] Read the value stored in the shared task timestamp register and copy that value in the task timestamp register for the given task signal;

[0052] Write in the task status register the command corresponding to the first mode, in particular write a command indicating task start, and

[0053] Generate the corresponding first mode command received by the task recording circuit.

[0054] In a variant embodiment, in response to detecting a software trigger of a task signal among a plurality of task signals, the management circuit is configured to operate in a second mode, including steps in the following order:

[0055] Check whether the value stored in the task execution register is equal to an expected value corresponding to the occurrence of an event enabling the corresponding mode, and in the case of no, output the result of the check operation in an error signal for a given task being monitored, including emitting a task error signal that includes a timestamp of the incorrect check and, in particular, also includes an error type represented by an indication of the event under which the error was detected;

[0056] Write a value indicating which task signal among the plurality of task signals is being monitored in the task number register;

[0057] Read the value stored in the task timestamp register of a given task signal and copy the value in the corresponding shared task timestamp register of the given task signal;

[0058] Write an expected value corresponding to the occurrence of a subsequent expected event in the task execution register, in particular, write a value equal to 2 corresponding to the emission of a falling edge signal;

[0059] Write a command corresponding to the second mode in the task status register, in particular, a command indicating the ongoing task; and

[0060] Generate a corresponding second mode command received by the task recording circuit.

[0061] In a variant embodiment, in response to detecting a falling edge of a task signal among a plurality of task signals, the management circuit is configured to operate in a third mode, including steps in the following order:

[0062] Check whether the value stored in the task execution register is equal to an expected value corresponding to the occurrence of an event enabling the corresponding mode, and in the case of no, output the result of the check operation in an error signal for a given task being monitored, including emitting a task error signal that includes a timestamp of the incorrect check and, in particular, also includes an error type represented by an indication of the event under which the error was detected;

[0063] Write a value indicating which task signal among the plurality of task signals is being monitored in the task number register;

[0064] Read the value stored in the task timestamp register of a given task signal and copy the value in the corresponding shared task timestamp register of the given task signal;

[0065] Write an expected value corresponding to the occurrence of a subsequent expected event in the task execution register, in particular a value equal to 0 corresponding to the emission of a rising edge signal;

[0066] Write a command corresponding to the third mode in the task status register, in particular a command indicating the stopping of the task; and

[0067] Generate a corresponding third mode command received by the task recording circuit.

[0068] In a variant embodiment, the task recording circuit is configured to perform steps in the following order in response to the occurrence of one of the commands, in particular a start signal, a software trigger signal or a stop signal:

[0069] Read the task timestamp signal and select a record among multiple records according to the value of the task timestamp signal;

[0070] Read the value stored in the counter capture register and copy the value at the task start time, task delay time or task stop time according to the detected command;

[0071] Write a value indicating whether a start signal, a software trigger signal or a stop signal has occurred in the task status field of the previously selected record.

[0072] In a variant embodiment, the first mode, second mode and third mode of operation further include the step of checking whether the bit stored in the task enable register is asserted, in which case proceeding to the next step, and in the negative case, terminating the execution of the first mode of operation, the second mode of operation or the third mode of operation.

[0073] In a variant embodiment, the first mode, second mode and third mode of operation further include the step of reading the bit stored in the task periodicity register and generating a task periodicity signal as an output, the task periodicity signal being asserted if the bit is asserted and de-asserted if the bit is de-asserted, and

[0074] The table information structure includes records storing second timestamp values and stored commands, and each record corresponding to the first timestamp value includes a periodic task table and an aperiodic task table, both including records storing second timestamp values and stored commands, each record corresponding to the first timestamp value, and performing the storage in the periodic task table or the aperiodic task table respectively depending on whether the bit stored in the task periodicity register is asserted or not.

[0075] The recording circuit is configured to read the periodic task signal and select the periodic task table or the aperiodic task table according to the value of the periodic task signal.

[0076] In a variant embodiment, the first mode of operation further comprises the steps of:

[0077] Checking whether the value stored in the task reload selection register and associated with a given task signal is associated with the task signal being monitored; and

[0078] If so, generating a reload signal received by the timestamp counter to reset the value stored therein;

[0079] If not, proceeding to the next step.

[0080] In a variant embodiment, the third mode of operation further comprises the step of resetting the task timestamp register to a default value, in particular, the default value being equal to zero.

[0081] In a variant embodiment, the task recording circuit further comprises a recording check sub-circuit configured to perform steps in the following order in response to detecting the occurrence of a stop signal:

[0082] Comparing the recorded task number corresponding to the occurrence of the stop signal with the expected task number;

[0083] Calculating the recorded task duration corresponding to the occurrence of the stop signal as the difference between the task stop time and the task start time;

[0084] Comparing the task duration with the expected task duration and / or with a minimum threshold and with a maximum threshold;

[0085] When it is detected that the task duration is less than the minimum threshold or greater than the maximum threshold, if the duration of a given task is different from the expected duration value or outside the range, then outputting a signal indicating an error and generating a task recording error message.

[0086] The solution described herein also relates to a method for performing logical task monitoring and time task monitoring on multiple tasks executed in a processing system, the method comprising operations performed by a circuit according to an embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0088] Figure 1 A block diagram showing a circuit for logical task monitoring and time task monitoring according to an embodiment of the present solution is shown;

[0089] Figure 2 A diagram showing an example of a task signal according to an embodiment of the present solution is shown;

[0090] Figure 3 A block diagram showing a task management circuit according to an embodiment of the present solution is presented;

[0091] Figure 4 A block diagram showing a signal manager circuit according to an embodiment of the present solution is presented;

[0092] Figure 5 A flowchart showing a method executed by the signal manager circuit when a rising edge signal is detected is presented;

[0093] Figure 6 A flowchart showing a method executed by the signal manager circuit when a software trigger signal is detected is presented;

[0094] Figure 7 A flowchart showing a method executed by the signal manager circuit when a falling edge signal is detected is presented; and

[0095] Figure 8 A block diagram showing a task record circuit according to an embodiment of the present solution is presented. Detailed Description of the Invention

[0096] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0097] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0098] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0099] Parts, elements, or components of the figures that have been described with reference to previous figures are denoted by the same reference numerals used previously in those figures; to avoid overburdening this detailed description, the description of these previously described elements will not be repeated subsequently.

[0100] The solutions described herein refer to circuits and corresponding methods for logical task monitoring and time task monitoring in a processing system.

[0101] In this regard, Figure 1Exemplary embodiments of the present solution are shown. The circuit 100 for logical task monitoring and time task monitoring includes two sub - circuits, namely a task management circuit 110 and a task recording circuit 120. The task monitoring circuit 100 receives a plurality of task signals TS1...TS N as inputs, where N is the total number of tasks supported by the circuit. The plurality of task signals indicate the execution status of the corresponding tasks being executed in an external processing system, and the task monitoring circuit 100 generates two signals as outputs, namely a task error signal 908 and a task recording error 909.

[0102] Figure 2 A timing diagram is shown, which represents a detailed example of the variation of the task signal TS i over time t. Each task signal TS1...TS N is a two - level signal that is asserted when a request to execute a task occurs at the requested execution time TRE, resulting in a rising edge RE in the task signal TS i . The signal TS i remains high for the entire task execution duration and is immediately de - asserted when the task execution ends at the end execution time TFE, resulting in a falling edge FE in the task signal TS i .

[0103] Figure 3 A detailed block diagram of the task management circuit 110 is illustrated. The task management circuit 110 receives a plurality of task signals TS1...TS N as inputs and generates a reload signal 901, a start signal 902, a software trigger signal 903, a stop signal 904, a periodic task signal 905, a task number 906, a first timestamp 907, a task error signal 908, and a counter capture signal 910 as outputs. The first timestamp is either a task timestamp or a task event timestamp. The task management circuit 110 includes: a plurality of edge detector circuits ED1…ED N , which are respectively coupled to the plurality of task signals TS1...TS N ; a task reload selection register 111; a task enable register 112; a task periodic register 113; a task software trigger register 114; a free - running counter 115; a counter capture register 116; an OR gate 117; and a signal manager circuit 130.

[0104] Each edge detector circuit ED i is configured to generate a detectable pulse signal, that is, a pulse signal with a duration of at least one complete clock cycle, when a rising edge or a falling edge is detected on the corresponding input signal TS i . When the input signal TS is detected...i When a rising edge occurs on it, the edge detector circuit ED i generates a rising edge signal RS i ; while when a falling edge is detected on the input signal TS i the edge detector circuit ED i generates a falling edge signal FS i .

[0105] The task reload select register 111 is configured to store a pointer to a task signal TS among multiple task signals TS1...TS N in such a way that the user can select a specific task signal TS i , for example, by storing a pointer to the task signal TS i in the task reload select register 111 to trigger the assertion of a reload signal 901 sent to the free-running counter 115. The signal manager circuit 130 connected to the task reload select register 111 can access the value stored in the task reload select register 111. In particular, in order to store a pointer to the value of any signal among the received task signals TS1...TS i , the task reload select register 111 includes a number of bits equal to the binary logarithm of the total number N of received task signals. N

[0106] In addition, since the task signals are numbered starting from 1, it is necessary to store the value x - 1 in the task reload select register 111 to select the task TS x to generate a counter reload signal. Thus, for example, if the user desires to select the task signal TS3 to trigger the reload of the counter on the occurrence of a rising edge, then it stores the value 3 - 1 = 2 in the task reload select register 111 to correctly point to the desired task signal.

[0107] The task enable register 112 is configured to store N bits, where N is the number of received task signals, and these bits are respectively coupled to the corresponding task signals among multiple task signals TS1...TS N in such a way that each bit of the task enable register 112 is coupled to one and only one task signal TS i . Each bit indicates whether monitoring of the corresponding task signal is enabled. The signal manager circuit 130 connected to the task enable register 112 can access the value stored in the task enable register 112. Thus, for example, if the user desires to enable monitoring of the task signal TS3, then it asserts the corresponding bit in the task enable register 112, for example, the bit occupying the third position in the register. Conversely, to disable monitoring of the task, the corresponding bit in the task enable register 112 is de-asserted.​

[0108] The task periodicity register 113 is configured to store N bits, where N is the number of received task signals, and these bits are respectively coupled to the corresponding task signals in a plurality of task signals TS1...TS N in such a way that each bit of the task periodicity register 113 is coupled to one and only one task signal TS i . Each bit indicates whether the corresponding task signal is periodic, that is, whether the rising edge of the task signal occurs at regular time intervals. The signal manager circuit 130 to which the task periodicity register 113 is connected can access the value stored in the task periodicity register 113. Thus, for example, if the user desires to declare the task signal TS3 as periodic, then it asserts the corresponding bit in the task periodicity register 113, for example, the bit occupying the third position in the register. Conversely, to declare the task as aperiodic, then the corresponding bit in the task periodicity register 113 is de-asserted.

[0109] The task software trigger register 114 is configured to store N bits, where N is the number of received task signals, and these bits are respectively coupled to the corresponding task signals in a plurality of task signals TS1...TS N in such a way that each bit of the task software trigger register 114 is coupled to one and only one task signal TS i . Each bit indicates whether the signal manager circuit 130 is to generate a software trigger signal 903 associated with the corresponding task signal TS i during the upcoming clock cycle. The signal manager circuit 130 to which the task software trigger register 114 is connected can access the value stored in the task software trigger register 114. Specifically, since each task signal in the plurality of task signals TS1...TS N is associated with a bit of the task software trigger register 114, a software trigger signal can be generated separately for each task TS i . In addition, the task software trigger register 114 is self-clearing, that is, it is configured to reset its content after a fixed number of clock cycles. Thus, for example, if the user desires to generate a software trigger signal 903 associated with the task TS3, then it includes such an instruction that is used to assert the corresponding bit in the task software trigger register 114 at the desired position in the source code of the task TS3, for example, the bit occupying the third position in the register. After asserting the bit in the task software trigger register 114, the software trigger signal 903 associated with the desired task is generated, and subsequently the content of the task software trigger register 114 is automatically cleared.

[0110] The free-running counter 115 circuit is configured as a timer and is configured to reset its value when receiving a reload signal 901. The reload signal 901 is a pulse signal having a detectable duration, i.e., a duration of at least one complete clock cycle, and thus its purpose is to define a time window for monitoring tasks.

[0111] The counter capture register 116 is configured to capture the value of the free-running counter 115 when a start signal 902, a software trigger signal 903, or a stop signal 904 occurs. For this purpose, the OR gate 117 receives the start signal 902, the software trigger signal 903, and the stop signal 904 as input signals and generates a signal containing the result of the OR operation between the input signals 902, 903, and 904 as output. The output signal generated by the OR gate 117 is received by the counter capture register 116, and the counter capture register 116 captures the value stored in the free-running counter 115 while receiving the asserted signal. Therefore, the counter capture register 116 stores the occurrence time of the execution request, the start time of the execution, and the stop time of the execution for each monitored task, which is called the start time of the monitoring window. The data stored in the counter capture register 116 is transmitted to other components by means of the counter capture signal 910, and this data can correspond to a second timestamp value or a task timing timestamp value, corresponding to one of the asserted start signal 902, software trigger signal 903, and stop signal 904. It should be emphasized that in a variant embodiment, the counter capture register 116 can store two or three second timestamps, corresponding respectively to the occurrence of the start signal 902 and the stop signal 904 (e.g., the signal becomes high), or corresponding to the occurrence of the start signal 902, software trigger signal 903, or stop signal 904, and send them simultaneously in the capture signal 910, i.e., store them in the recording circuit simultaneously.

[0112] The signal manager circuit 130 receives rising edge signals and falling edge signals RS N from a plurality of edge detector circuits ED1…ED i 、FS i and the data stored in the task reload selection register 111, task enable register 112, task periodicity register 113, and task software trigger register 114 as inputs.

[0113] The signal manager circuit or management circuit 130 generates the start signal 902, software trigger signal 903, stop signal 904, periodic task signal 905, task number 906, task event timestamp 907, and task error signal 908, as well as the reload signal 901 received by the free-running counter 115, as outputs.

[0114] In Figure 4, a detailed block diagram of the signal manager circuit 130 is illustrated.

[0115] The signal manager circuit 130 includes a task number register 131; a timestamp register 132; a task error register 133; then the signal manager circuit includes a set of registers assigned one to each task signal, i.e., a plurality of task execution registers 134, one for each task signal, i.e., N registers; a plurality of task timestamp registers 135, one for each task signal; and a plurality of task status registers 136, one for each task signal. In addition, the signal manager circuit 130 includes a timestamp counter 137.

[0116] In particular, the task number register 131 is configured to store a task number that identifies a plurality of task signals TS1 . . . TS N Which task signal TS i is being processed and its contents are carried by the task number signal 906. The task timestamp register 132 is configured to be triggered when an event occurs, in particular when a rising edge RS is detected as described in detail below. i , send software trigger signal 114, detect falling edge FS i The value of the time stamp counter 137 is stored when an error occurs, and its content is carried by the task time stamp signal 907, that is, the first time stamp signal. The task error register 133 is configured to store information such as the error type, the task TS that generated the error, and the task time stamp counter 137 when an error occurs. i The number i and related timestamp and other information.

[0117] The task execution register 134 is configured to store the task signal TS i Associated information for further processing, which represents the task TS i Whether it is currently executing, so this register can store N values, N is the total number of monitored tasks. The number of bits required to store such values ​​can vary depending on the embodiment considered.

[0118] The task time stamp register 135 is configured to store the time stamp associated with each task signal TS i The associated timestamp value KT is called the timestamp counter 137 i , whose value indicates the position of the task in the execution sequence. Similar to the task execution register 134, the task timestamp register 135 can store N values, where N is the total number of monitored tasks.

[0119] The plurality of task status registers 136 are configured to store information indicating a plurality of task signals TS1 . . . TS N Each task in TS iThe value of the status. Therefore, similar to the aforementioned registers 134 and 135, the task status register 136 can store N values, where N is the total number of tasks being monitored.

[0120] The signal manager circuit 130 is configured to read the values stored in the connected registers and receive rising edge signals and falling edge signals from multiple edge detector circuits ED 1。。。 ED N and generate the aforementioned output signals, which are then sent to the task recording circuit 120.

[0121] The task signal manager 130 is configured to execute different instructions based on the received input signals. Specifically, the task signal manager 130 implements different methods when detecting three different events: receiving a rising edge signal RS from multiple edge detector circuits ED1…ED N ; detecting an asserted bit in the task software trigger register 114; and receiving a falling edge signal FS from multiple edge detector circuits ED1…ED i ; and receiving a falling edge signal FS from multiple edge detector circuits ED1…ED N The falling edge signal FS of i .

[0122] Figure 5 A flowchart representing method 500 is shown, which corresponds to an embodiment of the first mode of operation of the task manager. The first mode of this operation is executed when receiving a rising edge signal RS from multiple edge detector circuits ED1…ED N , that is, the rising edge signal RS originating from the edge detector circuit ED i . At the start and end of the flowchart, conventional START and END blocks are shown, and these blocks are also shown here and i At the start and end of the flowchart, conventional START and END blocks are shown, and these blocks are also shown here and Figure 6 and Figure 7 These blocks are also shown in.

[0123] In the first step 501, the signal manager circuit 130 checks the bit BE i stored in the task enable register 112 and associated with the edge detector circuit ED i to see if it is asserted. If the bit BE i is asserted, that is, the monitoring of the task TS i is enabled, then the signal manager circuit 130 proceeds to step 502.

[0124] In step 502, the signal manager circuit 130 checks the value KA i stored in the task execution register 134 and associated with the edge detector circuit ED i indicating whether the associated task TS i is equal to 0. If the value KAi If it is not equal to 0, then the signal manager circuit 130 jumps to step 512, where a task error signal 908 is generated. The signal contains relevant information such as the number of the task that caused the error, the error type, and the relevant timestamp. These pieces of information are stored in registers 134, 135, and 136 of the signal manager circuit 130 respectively, and then the execution of method 500 ends.

[0125] Conversely, if the value KA i is equal to 0, then the signal manager circuit 130 proceeds to step 503.

[0126] Therefore, in summary, the task execution register 134 stores the value KA i indicating whether the task TS i is currently being executed.

[0127] In step 503, the signal manager circuit 130 checks whether the value KR stored in the task reload selection register 111 is associated with the task signal TS i indicating that the generation of the reload signal 901 is triggered by the rising edge of the task signal TS i . If so, then the signal manager circuit 130 proceeds to step 504, where the reload signal 901 is generated and the internal timestamp counter 137 is reset. Conversely, if the value stored in the task reload selection register 111 refers to a task signal different from the task signal TS i , then the signal manager circuit 130 proceeds to step 505.

[0128] In step 505, the signal manager circuit 130 reads the bit BP i stored in the task periodic register 113 and associated with the edge detector circuit ED i , and generates the task periodic signal 905 as an output. If the bit BP i is asserted, then the task periodic signal 905 is asserted, and vice versa. If the bit BP i is de-asserted, then the task periodic signal 905 is de-asserted.

[0129] Subsequently, in step 506, the signal manager circuit 130 writes in the task number register 131 a value indicating which one of the multiple task signals TS1…TS N the task signal TS i being processed is. Thus, for example, if the rising edge signal RS3 of the task signal TS3 causes the signal manager circuit 130 to execute method 500, then after this step 506, a value equal to 3 is stored in the task number register 131.

[0130] Subsequently, in step 507, the signal manager circuit 130 reads the value stored in the timestamp counter 137 and copies that value in the task timestamp register 132. Additionally, the value stored in the timestamp counter 137 is incremented by 1.

[0131] Subsequently, in step 508, the signal manager circuit 130 writes the value KA i in the task execution register 134 to 1. This step prevents the signal manager circuit 130 from entering the same branch of method 500, particularly at step 502, and prepares the signal manager circuit 130 to execute the method corresponding to the detected software trigger signal or falling edge, which is further described below.

[0132] Subsequently, in step 509, the signal manager circuit 130 reads the value stored in the task timestamp register 132 and copies that value in the task timestamp register 135.

[0133] Subsequently, in step 510, the signal manager circuit 130 writes the value KS i in the task status register 136 to the value "START", which represents a command issued in the first mode, particularly a command for the recording circuit 120, i.e., a first mode command. In various embodiments, fewer bits may be used to represent this value "START", for example, by using the value 1. As described in more detail below, KS i can sequentially take three values, each value representing an expected value depending on the previous mode and the current mode, i.e., in the case of this first mode 500, after the last detected falling edge (third mode 700, described below), the expected value of KS i is 0 and the current value is set to 1.

[0134] Finally, in step 511, the signal manager circuit 130 generates a start signal 902, which is received by the task recording circuit 120, and then the execution of method 500 ends.

[0135] It should be emphasized here that in an embodiment, the process 500 corresponding to the first mode of operation may be substantially limited to operations 502 and 506 to 511, and other operations 501, 503 - 505 may optionally be present.

[0136] Similarly, Figure 6 A flowchart representing method 600 is shown, which corresponds to an embodiment of the second mode of operation of the task manager 110, which is executed when a software trigger signal is received. This method 600 corresponds to the second mode of operation of the circuit, particularly the second mode of operation of the task manager and the recorder.

[0137] In a first step 601, the signal manager circuit 130 checks a bit BE stored in the task enable register 112 and associated with the edge detector circuit ED i to see if it is asserted. If the bit BE i is asserted, that is, monitoring of the task TS i is enabled, then the signal manager circuit 130 proceeds to step 602. i is enabled, then the signal manager circuit 130 proceeds to step 602.

[0138] In step 602, the signal manager circuit 130 checks a value KA stored in the task execution register 134 and associated with the edge detector circuit ED i to see if it is equal to 1. If the value KA i is not equal to 1, then the signal manager circuit 130 jumps to step 609, where a task error signal 908 is generated, which contains relevant information such as the number of the task that caused the error, the type of error, and the relevant timestamp, which are stored in registers 134, 135, and 136 of the signal manager circuit 130 respectively, and then the execution of method 600 ends. i is not equal to 1, then the signal manager circuit 130 jumps to step 609, where a task error signal 908 is generated, which contains relevant information such as the number of the task that caused the error, the type of error, and the relevant timestamp, which are stored in registers 134, 135, and 136 of the signal manager circuit 130 respectively, and then the execution of method 600 ends.

[0139] Conversely, if the value KA i is equal to 1, then the signal manager circuit 130 proceeds to step 603.

[0140] In step 603, the signal manager circuit 130 reads a bit BP stored in the task periodic register 113 and associated with the edge detector circuit ED i and generates a task periodic signal 905 as output, and if the bit BP i is asserted, then the task periodic signal 905 is asserted, and vice versa, if the bit BP i is de-asserted, then the task periodic signal 905 is de-asserted. i is de-asserted, then the task periodic signal 905 is de-asserted.

[0141] Subsequently, in step 604, the signal manager circuit 130 writes a value in the task number register 131 indicating which one of the multiple task signals TS1...TS N is being processed. Thus, for example, if a software trigger from task signal TS3 causes the signal manager circuit 130 to execute method 600, then after this step 604, a value equal to 3 is stored in the task number register 131. i is being processed. Thus, for example, if a software trigger from task signal TS3 causes the signal manager circuit 130 to execute method 600, then after this step 604, a value equal to 3 is stored in the task number register 131.

[0142] Subsequently, in step 605, the signal manager circuit 130 reads the value stored in the timestamp counter 137 and copies that value in the task timestamp register 132.

[0143] At this stage, the signal manager circuit 130 maintains the value in the task execution register 134 as 1 to indicate that the task is still in progress.

[0144] Subsequently, in step 606, the signal manager circuit 130 writes the value "ONGOING" in the task status register 136. In various embodiments, fewer bits can be used to represent the value "ONGOING", for example, by using the value 2.

[0145] Finally, in step 607, the signal manager circuit 130 generates a software trigger signal 903, which is received by the task recording circuit 120, and then the execution of method 600 ends.

[0146] It should be emphasized here that, in an embodiment, the process 600 corresponding to the second mode of operation can be substantially limited to operations 604 - 607, and other operations 601, 603 can optionally exist.

[0147] Similarly, in Figure 7 FIG. shows a flowchart representing method 700, which corresponds to an embodiment of the third mode of operation of task manager 110, and the third mode of operation is executed when receiving a falling edge signal from multiple edge detector circuits ED1... ED N i.e., originating from edge detector circuit ED i When the falling edge signal is received.

[0148] In the first step 701, the signal manager circuit 130 checks the bit BE i stored in the task enable register 112 and associated with the edge detector circuit ED i to see if it is asserted. If the bit BE i is asserted, that is, monitoring of task TS i is enabled, then the signal manager circuit 130 proceeds to step 702.

[0149] In step 702, the signal manager circuit 130 checks the value KA i stored in the task execution register 134 and associated with the edge detector circuit ED i to see if it is equal to 1. If the value KA i is not equal to 1, then the signal manager circuit 130 jumps to step 710, where a task error signal 908 is generated, which contains relevant information such as the number of the task that caused the error, the error type, and the relevant timestamp, and these information are respectively stored in the registers 134, 135, 136 of the signal manager circuit 130, and then the execution of method 700 ends.

[0150] On the contrary, if the value KSi If it is equal to 1, then the signal manager circuit 130 proceeds to step 703.

[0151] In step 703, the signal manager circuit 130 reads the bit BP i stored in the task periodic register 113 and associated with the edge detector circuit ED i , and generates a task periodic signal 905 as an output. If the bit BP i is asserted, then the task periodic signal 905 is asserted, and vice versa. If the bit BP i is de-asserted, then the task periodic signal 905 is de-asserted.

[0152] Subsequently, in step 704, the signal manager circuit 130 writes in the task number register 131 a value indicating which one of the multiple task signals TS1…TS N is being processed. Thus, for example, if the falling edge signal FS3 of the task signal TS3 causes the signal manager circuit 130 to execute method 700, then after this step 704, a value equal to 3 is stored in the task number register 131. i

[0153] Subsequently, in step 705, the signal manager circuit 130 reads the value stored in the timestamp counter 137 and copies this value in the task timestamp register 132.

[0154] Subsequently, in step 706, the signal manager circuit 130 writes a value equal to 0 in the task execution register 134. This step prevents the signal manager circuit 130 from entering the same branch of method 700, particularly at step 702, and prepares the signal manager circuit 130 to execute method 500 corresponding to a new rising edge detected on the monitored task signals TS1…TS N .

[0155] Optionally, in step 707, the signal manager circuit 130 resets the task timestamp register 135 to a default value, such as 0.

[0156] Subsequently, in step 708, the signal manager circuit 130 writes the value "STOP" in the task status register 136. In various embodiments, fewer bits may be used to represent this value "STOP", for example by using the value 0.

[0157] Finally, in step 709, the signal manager circuit 130 generates a stop signal 904, which is received by the task recording circuit 120, and then the execution of method 700 ends.

[0158] It should be emphasized here that, in the embodiment, the process 700 corresponding to the third mode of operation may be substantially limited to operations 702, 704 - 706, 708, 709, and the other operations 701, 703, 707 may optionally exist.

[0159] In Figure 8 FIG. shows a detailed block diagram of the task recording circuit 120. The task recording circuit 120 receives a reload signal 901, a start signal 902, a software trigger signal 903, a stop signal 904, a periodic task signal 905, a task number 906, a task event timestamp 907, and a counter capture signal 910 as inputs, and generates a task recording error 909 as an output. The task recording circuit 120 is configured to store data provided by the task management circuit 110. To this end, the task recording circuit 120 includes two tables: a periodic task table 121 and an aperiodic task table 122. The periodic task table 121 includes M rows RP1…RP M , each row RP j is associated with a record having a specific timestamp generated by the task management circuit 110, and the periodic task table includes the following fields: a task number 123a, a task start time 124a, a task delay time 125a, a task stop time 126a, and a task status 127a. Similarly, the aperiodic task table 122 includes M rows RN1…RN M , each row RN j is associated with a record having a specific timestamp generated by the task management circuit 110, and the aperiodic task table includes a task number 123b, a task start time 124b, a task delay time 125b, a task stop time 126b, and a task status 127b. In addition, the task recording circuit 120 includes a record checking sub - circuit 128.

[0160] It should be noted here that the table herein is intended to refer to a record structure having multiple fields. In the example, the multiple fields are a task number 123b, a task start time 124b, a task delay time 125b, a task stop time 126b, and a task status 127b, and each record, that is, the rows RN1...RN M , is indexed by the timestamp 907.

[0161] When receiving the reload signal 901, the task recording circuit is configured to clear the contents of both the periodic task table 121 and the aperiodic task table 122. As expected, the task recording circuit is configured to store data from the task management circuit 110. In particular, such a task recording circuit 120 implements three different methods, which are executed when receiving the start signal 902, the software trigger signal 903, or the stop signal 904, respectively.

[0162] Specifically, upon occurrence of the start signal 902, the task recording circuit 120 reads the periodic task signal 905 and selects a table accordingly to save data, that is, if the periodic task signal 905 is asserted, then the periodic task table 121 is selected, or conversely, if the periodic task signal 905 is de-asserted, then the aperiodic task table 122 is selected.

[0163] Subsequently, the task timestamp signal 907 is read to select the correct record of the selected table, that is, the correct record RP j or RN j . After selecting the record, the task number signal 906 is read and the task number signal is copied into the corresponding task number field 123a or 123b according to the selected table, and then the task recording circuit 120 writes the value read from the counter capture signal 910 into the task start time field 124a or 124b according to the selected table. Then, finally, according to the selected table, the value "START" is written into the task status field 127a or 127b, and this value can be represented by a value equal to 1, for example.

[0164] Similarly, upon occurrence of the software trigger signal 903, the task recording circuit 120 reads the periodic task signal 905 and selects a table accordingly to save data, that is, if the periodic task signal 905 is asserted, then the periodic task table 121 is selected, or conversely, if the periodic task signal 905 is de-asserted, then the aperiodic task table 122 is selected.

[0165] Subsequently, the task timestamp signal 907 is read to select the correct record of the selected table, that is, the correct row RP j or RN j . After selecting the record, the task number signal 906 is read and the task number signal is copied into the corresponding task number field 123a or 123b according to the selected table, and then the task recording circuit 120 writes the value read from the counter capture signal 910 into the task delay time field 125a or 125b according to the selected table. Then, finally, according to the selected table, the value "SW_TRG" is written into the task status field 127a or 127b, and this value can be represented by a value equal to 2, for example.

[0166] Finally, upon occurrence of the stop signal 904, the task recording circuit 120 reads the periodic task signal 905 and selects a table accordingly to save data, that is, if the periodic task signal 905 is asserted, then the periodic task table 121 is selected, or conversely, if the periodic task signal 905 is de-asserted, then the aperiodic task table 122 is selected.

[0167] Subsequently, the task timestamp signal 907 is read to select the correct record of the selected table, i.e., to select the correct row RP in chronological order j or RN j . After selecting the record, the task number signal 906 is read and the task number signal is copied in the corresponding task number field 123a or 123b according to the selected table. Then, the task recording circuit 120 writes the value read from the counter capture signal 910 in the task stop time field 126a or 126b according to the selected table. Then, finally, according to the selected table, the value "STOP" is written in the task status field 127a or 127b, and this value can be represented by a value equal to 3, for example.

[0168] When the value "STOP" is written in the task status field 127a or 127b belonging to record RP j or RN j , the record checking sub-circuit 128 compares the task number 123a or 123b with the expected value, i.e., checks whether the tasks are executed in the correct order, thereby performing a logical task monitoring operation. For this purpose, the record checking sub-circuit 128 can store, for example, the expected execution order to be compared with the recorder order in a table.

[0169] Always after the occurrence of writing the value "STOP" in the task status field 127a or 127b belonging to record RP j or RN j , the record checking sub-circuit 128 calculates the task duration of the corresponding record RP j or RN j , and the task duration is defined as the difference between the task stop time 126a or 126b and the task start time 124a or 124b. Then the task duration is compared with a reference value, i.e., checks whether the task is executed within an acceptable amount of time, thereby performing a time task monitoring operation. In various embodiments, this operation of comparing the task duration with a reference value can be replaced by checking whether the task duration is included within a time range defined by a minimum time threshold and a maximum time threshold. Therefore, such a record checking sub-circuit 128, especially in a table, can store the expected reference value or alternatively store the reference time range, especially can also store the expected value of the task number 123a.

[0170] Therefore, based on the above, the circuit 100 for performing logical task monitoring and time task monitoring on multiple tasks executed in a processing system includes a task management circuit (e.g., 110) and a task recording circuit (e.g., 120), and the multiple tasks are tasks of a microprocessor or a microcontroller or an ECU (electronic control circuit), for example. The task management circuit 110 receives such as TS1…TS NMultiple task signals such as these are used as inputs, and each task signal is, for example, TS i , indicating the execution status of the corresponding task, and the task management circuit 110 includes a management circuit, for example, the signal manager circuit 130, which in Examples 500, 600, 700 is configured to operate in at least three modes depending on the corresponding event, and the corresponding event corresponds to detecting the rising edge of a given task signal (i.e., TS i ), such as RS i ), for example, the software trigger signal 114, the falling edge FS i , the occurrence of the trigger signal (such as 114), or detecting the falling edge of a given task signal (i.e., TS i ) monitored (i.e., processed) by the circuit 100 (such as, FS i ).

[0171] In each mode, for example, in modes 500, 600, 700, the management circuit 130 is configured to check whether the variable representing the operation status of the task TS i contains an expected value corresponding to the occurrence of an event (such as, RS i , 114, FS i ), thereby enabling the corresponding mode, such as modes 500, 600, 700, outputting the result of the check operation in an error signal, and for the given task TS i being monitored, outputting the signal 908. Thus, this part of the circuit performs logical monitoring.

[0172] Then, for performing time monitoring, the task management circuit (such as, 110) is configured to be in each of at least three modes 500, 600, 700 and is further configured to:

[0173] Store in a shared timestamp register (such as, 132) the first timestamp value indicated by 907 corresponding to the occurrence of the event;

[0174] For each corresponding mode 500, 600, 700 determined by the corresponding events RS i , 114, FS i , send a corresponding command to the task recording circuit 120, that is, one of the commands 902, 903, 904 that controls the operation of the recording circuit 120 later;

[0175] Store in the capture register 116 a second timestamp corresponding to the sending of each command (such as, 902, 903, 904), and this second timestamp is indicated by 905 in the example;

[0176] Send the timestamp value in the first timestamp register 135 to the task recording circuit 120;

[0177] The task recording circuit 120 includes at least table information structures, such as tables 121 and 122. However, in an embodiment, there may be a single table without the periodic / aperiodic distinction. The table information structure includes records that store second timestamp values (e.g., 905) and store these commands (e.g., 902, 903, 904). Each record corresponds to a first timestamp value 907. That is, the first timestamp value 907 indicates in which row of tables 121 and 122 the information is stored;

[0178] The task recording circuit (e.g., 120) is configured to be based on a given task TS i The stored corresponding to event RS i 、114、FS i For each of them, the second timestamp value 905, calculate the duration of the given task TS being monitored i For the given task TS being monitored i And is configured to check whether the duration of the given task TS being monitored i Corresponds to the expected duration value, that is, whether it corresponds to a definite value, or whether it is included in the range of duration values. If the duration of the given task TS i Is different from the expected duration value or outside the range, then output a signal 909 indicating an error.

[0179] As described above, the second timestamp can be stored as a single value and then sent to the task recording circuit 120, for example, at the end of modes 500, 600, 700. In a variant embodiment, the register 116 can store two or three second timestamps corresponding respectively to the start signal 902 and the stop signal 904, or corresponding respectively to the start signal 902, the software trigger signal 903, or the stop signal 904, and send them simultaneously in the capture signal 910, that is, store them simultaneously in the recording circuit 120, for example, after the "STOP" signal.

[0180] Therefore, the advantages of the above solution are clear. The proposed solution allows time task monitoring and logic task monitoring of multiple tasks executed in a processing system, while avoiding further resource overhead due to such task monitoring operations. In addition, the proposed solution also provides the advantage of allowing users to insert control flow checkpoints more flexibly. Of course, without prejudice to the principles of the present invention, the details of the construction and embodiments can vary greatly from what is described and illustrated herein by way of example only, without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A monitoring circuit for performing logical task monitoring and time task monitoring on multiple tasks executed in a processing system, the monitoring circuit comprising: A task recording circuit; And A task management circuit communicatively coupled to the task recording circuit and configured to receive a plurality of task signals as inputs, each task signal indicating an execution state of a corresponding task, wherein the task management circuit includes a management circuit configured to: Operate in at least three modes depending on a corresponding event corresponding to detecting a rising edge or a falling edge of a given task signal being monitored among the plurality of task signals or the occurrence of a trigger signal; And In each mode, check whether a variable indicating at least an operating state of the task contains an expected value corresponding to the occurrence of the corresponding event enabling the corresponding mode, and output the result of the check in an error signal for the corresponding task being monitored.

2. The monitoring circuit according to claim 1, wherein the management circuit is configured to check a first variable that indicates whether the task is active or inactive before the occurrence of the corresponding event.

3. The monitoring circuit according to claim 2, wherein the management circuit is further configured to check a second variable indicating the mode before the occurrence of the corresponding event.

4. The monitoring circuit according to claim 1, wherein in each of the at least three modes, the task management circuit is further configured to: Store a first timestamp value corresponding to the occurrence of the corresponding event in a shared timestamp register; Send a corresponding command of each corresponding mode determined by the corresponding event to the task recording circuit; Store a second timestamp value corresponding to the sending of the corresponding command of each corresponding mode determined by the corresponding event in a capture register; And Send the first timestamp value and the second timestamp value to the task recording circuit; Wherein the task recording circuit includes at least a table information structure, the table information structure including a plurality of records storing the second timestamp value and the stored corresponding commands, each record corresponding to the first timestamp value; And Wherein the task recording circuit is configured to calculate a duration of a given task being monitored based on the second timestamp value stored for the given task corresponding to each of the events; Check whether the duration of the given task being monitored corresponds to a duration expected value or is within a range of duration values; and if the duration of the given task is different from the duration expected value or outside the range, then output a signal indicating an error.

5. The monitoring circuit according to claim 4, wherein the error signal includes an incorrect checked timestamp.

6. The monitoring circuit according to claim 5, wherein the task management circuit includes a plurality of edge detector circuits, wherein each edge detector circuit is coupled to a corresponding task signal and configured to generate a detectable pulse signal.

7. The monitoring circuit according to claim 6, wherein the task management circuit further includes: A free-running counter; And A counter capture register configured to store a value captured from the free-running counter corresponding to the time of the occurrence of the event among the plurality of tasks.

8. The monitoring circuit according to claim 7, wherein the task management circuit further comprises: A task reload selection register configured to store an identifier of a given task signal being monitored among the plurality of task signals; A task enable register configured to store a bit corresponding to each task signal among the plurality of task signals, the bit indicating whether the corresponding task signal is being monitored; and A task software trigger register configured to store a plurality of bits corresponding to the plurality of task signals, and the asserted bits among the plurality of bits determine that the task manager generates a detectable pulse signal as a software trigger signal.

9. The monitoring circuit according to claim 8, wherein the management circuit comprises: A timestamp counter; A task number register storing a task number identifying which task signal is being monitored; A shared task timestamp register configured to store a first timestamp of the timestamp counter; A task error register configured to store a timestamp of an error check when an error occurs; A plurality of task execution registers corresponding to respective task signals, storing variables representing the operating states of the tasks; A plurality of task timestamp registers, each task timestamp register storing a value in the shared task timestamp register when the corresponding task signal is being monitored; And A plurality of task status registers storing values representing the status of each task signal, the status corresponding to the respective commands; Wherein the management circuit is configured to: Receive as inputs signals generated by the plurality of edge detector circuits, data from the task reload selection register, data from the task enable register, data from the task periodic register, and data from the task software trigger register; And Generate a set of output signals including commands to the recording circuit, the output signals including a start signal, a software trigger signal, a stop signal, a task number signal, a task timestamp signal, and a task error signal, the content of these signals depending on which of the at least three modes the management circuit operates in depending on the corresponding event.

10. The monitoring circuit according to claim 9, wherein, In response to detecting a rising edge of a task signal among the plurality of task signals, the management circuit is configured to operate in a first mode of operation and sequentially includes: First check whether the value stored in the task execution register is equal to a first expected value corresponding to the occurrence of an event enabling the corresponding mode, and in response to the first check being false, output the result of the first check in an error signal for the given task being monitored, including emitting a task error signal including a timestamp of the error check; Write a value indicating which task signal among the plurality of task signals is being monitored in the task number register; Read the value stored in the timestamp counter and copy the value in the corresponding shared task timestamp register of the given task signal, incrementing the value stored in the timestamp counter; Write a first expected value corresponding to the occurrence of a first subsequent expected event in the task execution register; Read the value stored in the shared task timestamp register and copy the value in the task timestamp register of the given task signal; Write a corresponding command corresponding to the first mode in the task status register; and Generate a corresponding first mode command received by the task recording circuit.

11. The monitoring circuit according to claim 10, wherein, In response to detecting a software trigger for a task signal among the plurality of task signals, the management circuit is configured to operate in a second mode of operation, including in sequence: A second check to determine whether the value stored in the task execution register is equal to a second expected value corresponding to the occurrence of an event enabling the corresponding mode, and in response to the second check being false, output the result of the second check in an error signal for a given task being monitored, including emitting a task error signal including a timestamp of the check with the error; Write a value in the task number register indicating which task signal among the plurality of task signals is being monitored; Read the value stored in the task timestamp register of a given task signal and copy the value in the corresponding shared task timestamp register of the given task signal; Write a command corresponding to the second mode in the task status register; and Generate a corresponding second mode command received by the task recording circuit.

12. The monitoring circuit according to claim 11, wherein, In response to detecting a falling edge of a task signal among the plurality of task signals, the management circuit is configured to operate in a third mode of operation, including in sequence: A third check to determine whether the value stored in the task execution register is equal to a third expected value corresponding to the occurrence of an event enabling the corresponding mode, and in response to the third check being false, output the result of the third check in an error signal for a given task being monitored, including emitting a task error signal including a timestamp of the check with the error; Write a value in the task number register indicating which task signal among the plurality of task signals is being monitored; Read the value stored in the task timestamp register of a given task signal and copy the value in the corresponding shared task timestamp register of the given task signal; Write a third expected value corresponding to the occurrence of a second subsequent expected event in the task execution register; Write a command corresponding to the third mode in the task status register; and Generate a corresponding third mode command received by the task recording circuit.

13. The monitoring circuit according to claim 12, wherein the task recording circuit is configured to, in response to detecting the occurrence of one of the commands: Read the task timestamp signal and select a record from among the plurality of records according to the value of the task timestamp signal; Read the value stored in the counter capture register and copy the value at the task start time, task delay time, or task stop time according to the detected command; And Write a value indicating whether a start signal, software trigger signal, or stop signal occurrence has been detected in the task status field of the previously selected record.

14. The monitoring circuit according to claim 13, wherein the first mode, second mode, and third mode of operation further include checking whether the bit stored in the task enable register is asserted, and in response to checking that the bit is valid, proceeding to the next step, and in response to checking that the bit is invalid, terminating the execution of the first mode of operation, second mode of operation, or third mode of operation.

15. The monitoring circuit according to claim 12, wherein: The first mode, second mode, and third mode of operation further include reading bits stored in a task periodic register and generating a task periodic signal as an output, where if the bit is asserted, the task periodic signal is asserted, and if the bit is de-asserted, the task periodic signal is de-asserted; The table information structure includes records storing second timestamp values and storage commands, and each record corresponding to the first timestamp value includes a periodic task table and an aperiodic task table, both including records storing second timestamp values and storage commands, each record corresponding to the first timestamp value, and the storage is performed in the periodic task table or the aperiodic task table respectively depending on whether the bit stored in the task periodic register is asserted; And The recording circuit is configured to read the periodic task signal and select the periodic task table or the aperiodic task table according to the value of the task periodic signal.

16. The monitoring circuit according to claim 10, wherein the first mode of operation further includes: Fourthly, checking whether the value stored in the task reload selection register and associated with a given task signal is associated with the task signal being monitored; And In response to the fourth check being yes, generating a reload signal received by the timestamp counter to reset the value stored therein; Or In response to the fourth check being no, proceeding to the next step.

17. The monitoring circuit according to claim 12, wherein the third mode of operation further includes resetting the task timestamp register to a default value.

18. The monitoring circuit according to claim 12, wherein the task recording circuit further includes a recording check sub-circuit, and the recording check sub-circuit is configured to sequentially execute in response to detecting the occurrence of a stop signal: Comparing the task number of the record corresponding to the occurrence of the stop signal with the expected task number; Calculating the task duration of the record corresponding to the occurrence of the stop signal as the difference between the task stop time and the task start time; Comparing the task duration with the expected task duration and / or with a minimum threshold and a maximum threshold; and When it is detected that the task duration is less than the minimum threshold or greater than the maximum threshold, if the duration of a given task is different from the expected duration value or outside the range, then outputting a signal indicating an error and generating a task recording error message.

19. A method for performing logical task monitoring and time task monitoring on multiple tasks executed in a processing system, the method comprising: Receiving, by a task management circuit of the processing system, a plurality of task signals as inputs, each task signal indicating the execution status of a corresponding task; Operating, by a management circuit of the task management circuit, in at least three modes depending on corresponding events corresponding to the rising edge or falling edge of a given task signal being monitored among the plurality of task signals or the occurrence of a trigger signal; In each mode, checking, by the management circuit, whether at least a variable representing the operating state of the task contains an expected value corresponding to the occurrence of the corresponding event enabling the corresponding mode; And The management circuit outputs the result of the check in the error signal for the corresponding task being monitored.

20. The method according to claim 19, further comprising the management circuit checking a first variable that indicates whether the task was active or inactive before the corresponding event occurred.

21. The method according to claim 19, further comprising, for each of the at least three modes: The task management circuit stores a first timestamp value corresponding to the occurrence of the corresponding event in a shared timestamp register; The task management circuit sends a corresponding command for each corresponding mode determined by the corresponding event to the task recording circuit of the processing system; The task management circuit stores a second timestamp value corresponding to the sending of the corresponding command for each corresponding mode determined by the corresponding event in a capture register; The task management circuit sends the first timestamp value and the second timestamp value to the task recording circuit; and The task recording circuit stores at least a table information structure that includes a plurality of records containing the second timestamp value and the corresponding command, each record corresponding to the first timestamp value; The task recording circuit calculates the duration of the given task being monitored based on the second timestamp value stored for the given task corresponding to each of the events, to check whether the duration of the given task being monitored corresponds to a duration expected value or is within a range of duration values; and If the duration of the given task is different from the duration expected value or outside the range, then the task recording circuit outputs a signal indicating an error.

Images