A single-chip computer RAM block fault detection method and dedicated transformer acquisition terminal

Abstract

The present invention relates to a single-chip microcomputer RAM block fault detection method and a dedicated variable acquisition terminal. In the method, during the single-chip microcomputer program initialization phase, a first mode write / read operation is performed on multiple RAM blocks to perform fault detection on the multiple RAM blocks. The first mode write / read operation includes performing data write operations and data read operations on all fault detection bits. During the single-chip microcomputer program operation phase, a second mode write / read operation is periodically performed on the multiple RAM blocks to perform periodic fault detection on the multiple RAM blocks. The second mode write / read operation includes performing data write operations and data read operations on respective master detection bits and some slave detection bits corresponding to the multiple RAM blocks. When the second mode write / read operation is periodically performed on the multiple RAM blocks, the portion of the slave detection bits of each RAM block that undergo data write operations and data read operations changes periodically. This method ensures detection effectiveness while minimizing the impact of data write / read bit occupation during the fault detection process on the normal operation of the single-chip microcomputer main program.

Description

Technical Field

[0001] Multiple embodiments of this specification relate to the technical field of single-chip microcomputer fault detection, and specifically to a single-chip microcomputer RAM block fault detection method and a dedicated transformer acquisition terminal. Background Art

[0002] Microcontroller systems typically include multiple RAM blocks, each of which contains a large number of data write / read bits. These write / read bits are the fundamental units for storing and reading data in the microcontroller. When a RAM block experiences an anomaly, a common manifestation is the inability to write or read data from the write / read bits. To detect such RAM block failures, a method can be used to assign a preset value and then read the actual written value. Specifically, a preset value is written to a write / read bit in the RAM block, then the value at that location is read and compared with the preset value. If the two values ​​do not match, this indicates a possible failure in the data write / read bit.

[0003] However, during the execution of the main program of the microcontroller, it is necessary to frequently perform write and read operations on the RAM blocks to complete various calculation, storage and transmission tasks. Therefore, the above-mentioned additional value writing and reading operations for fault detection will inevitably affect the normal data writing and reading operations during the operation of the main program, thereby disrupting the normal operation rhythm of the main program and causing problems such as operation delays. Summary of the Invention

[0004] The embodiments of this specification provide a single-chip microcomputer RAM block fault detection method and a dedicated variable acquisition terminal, which can ensure the fault detection effect while minimizing the impact of data write and read bit occupation during the fault detection process on the normal operation of the single-chip microcomputer main program.

[0005] The technical solution is as follows:

[0006] The embodiments of this specification provide a method for detecting a RAM block fault in a single-chip microcomputer, including:

[0007] Selecting a plurality of data write and read bits in the plurality of RAM blocks as a plurality of fault detection bits corresponding to the plurality of RAM blocks, respectively, wherein the plurality of fault detection bits in each RAM block include at least one master detection bit and a plurality of slave detection bits;

[0008] During a single-chip computer program initialization phase, a first mode write and read operation is performed on the plurality of RAM blocks, wherein the first mode write and read operation includes performing data write operations and data read operations on all fault detection bits, and based on consistency between the written data and the read data when performing the first mode write and read operations on the plurality of RAM blocks, fault detection is performed on the plurality of RAM blocks;

[0009] During the single-chip computer program running stage, second-mode write and read operations are periodically performed on multiple RAM blocks. The second-mode write and read operations include performing data write operations and data read operations on the main detection bits and part of the slave detection bits corresponding to each of the multiple RAM blocks. When the second-mode write and read operations are periodically performed on multiple RAM blocks, part of the slave detection bits for each RAM block that perform data write operations and data read operations are changed periodically. When the second-mode write and read operations are periodically performed on multiple RAM blocks, periodic fault detection is performed on the multiple RAM blocks based on the consistency of the periodic write data and the read data. The main program of the single-chip computer continues to operate normally through the unoccupied data write and read bits during the periodic fault detection process.

[0010] As a preferred solution, for each RAM block, the master detection bit is located at the head of the RAM block, and the multiple slave detection bits are respectively located at the ends of the write and read bits of multiple array variables in the RAM block.

[0011] As a preferred solution, for each RAM block, the master detection bit is located at the head of the RAM block, and multiple slave detection bits are evenly distributed in the RAM block;

[0012] Before periodically performing the second mode write and read operations on the plurality of RAM blocks, the method further includes:

[0013] Partitioning the multiple RAM blocks respectively to obtain multiple RAM data write / read areas corresponding to the multiple RAM blocks, wherein the multiple RAM data write / read areas have the same number of slave detection bits;

[0014] Wherein, the part involved in each RAM block in the second mode write and read operation of each cycle needs to be selected from the multiple RAM data write and read areas corresponding thereto respectively;

[0015] The part of the slave detection bit for each RAM block performing data write operation and data read operation changes periodically by cyclically changing the position of the slave detection bit selected in each corresponding RAM data write / read area in the RAM data write / read area from the head of the RAM data write / read area to the tail of the RAM data write / read area.

[0016] As a preferred solution, the first mode write and read operations include:

[0017] Performing a data writing operation of a first preset value on all fault detection bits;

[0018] Performing a data reading operation on all fault detection bits to obtain first read data corresponding to all fault detection bits;

[0019] Performing a data writing operation of a second preset value on all fault detection bits;

[0020] Performing a data reading operation on all fault detection bits to obtain second read data corresponding to all fault detection bits;

[0021] The first preset value and the second preset value are in an inverse relationship.

[0022] As a preferred solution, the fault detection of the multiple RAM blocks based on the consistency between the written data and the read data when the first mode write and read operations are performed on the multiple RAM blocks includes:

[0023] Obtaining a first consistency condition based on a first preset value and first read data corresponding to each of the fault detection bits;

[0024] Obtaining a second consistency condition based on the second preset value and the second read data corresponding to each of the fault detection bits;

[0025] Based on the first consistency condition and the second consistency condition, fault detection is performed on the plurality of RAM blocks.

[0026] As a preferred solution, the second mode write and read operations in each cycle include:

[0027] Performing a data writing operation of a first preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks;

[0028] Performing a data reading operation on the master detection bits and part of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain third read data corresponding to the master detection bits and part of the slave detection bits corresponding to the current cycle;

[0029] Performing a data writing operation of a second preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks;

[0030] Performing a data reading operation on the master detection bits and the portion of slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain fourth read data corresponding to the master detection bits and the portion of slave detection bits corresponding to the current cycle;

[0031] The first preset value and the second preset value are in an inverse relationship.

[0032] As a preferred solution, in the process of performing periodic fault detection on multiple RAM blocks based on the consistency of periodic written data and read data, the fault detection of each period includes:

[0033] Obtaining third consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the first preset value and the master detection bits in the multiple RAM blocks and the third read data corresponding to each of the slave detection bits corresponding to the current cycle;

[0034] Obtaining fourth consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the second preset value and the fourth read data corresponding to each of the master detection bits and the portion of slave detection bits corresponding to the current cycle in the multiple RAM blocks;

[0035] Based on the third consistency status and the fourth consistency status corresponding to the multiple RAM blocks, fault detection of the current cycle is performed on the multiple RAM blocks.

[0036] As a preferred solution, the performing fault detection on the multiple RAM blocks in the current cycle based on the third consistency status and the fourth consistency status corresponding to each of the multiple RAM blocks includes:

[0037] When there is no inconsistency in the third consistency condition and the fourth consistency condition corresponding to each of the plurality of RAM blocks, the fault detection result of the current cycle is no fault;

[0038] When there is a RAM block with inconsistency in the third consistency condition and the fourth consistency condition, the RAM block with inconsistency in the third consistency condition and the fourth consistency condition is regarded as a RAM block to be detected for the second time, and enters the second fault detection link;

[0039] The secondary fault detection link includes:

[0040] Re-performing a first preset number of second-mode write and read operations on all RAM blocks deemed to be RAM blocks to be re-detected, to obtain a new third consistency status and a new fourth consistency status corresponding to all RAM blocks to be re-detected under each second-mode write and read operation;

[0041] When there is no new third consistency situation and inconsistency in the new fourth consistency situation of the RAM blocks to be detected for the second time under the second mode write and read operations for a number greater than or equal to the second preset number, all RAM blocks to be detected for the second time are regarded as out-of-bounds fault RAM blocks, otherwise the third mode write and read operations are performed on all RAM blocks, and the third mode write and read operations include data writing operations and data reading operations on all fault detection bits not involved in the current cycle, and based on the third consistency situation and fourth consistency situation corresponding to each of the multiple RAM blocks, the new third consistency situation and new fourth consistency situation corresponding to each of the RAM blocks to be detected for the second time under each second mode write and read operation, and the consistency of written data and read data when the third mode write and read operations are performed on all RAM blocks, fault detection is performed on all RAM blocks.

[0042] As a preferred solution, the third mode write and read operations include:

[0043] Performing a data writing operation of a first preset value on all fault detection bits not involved in the current cycle;

[0044] Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain fifth read data corresponding to all fault detection bits not involved in the current cycle;

[0045] Performing a data writing operation of a second preset value on all fault detection bits not involved in the current cycle;

[0046] Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain sixth read data corresponding to all fault detection bits not involved in the current cycle;

[0047] The first preset value and the second preset value are in an inverse relationship.

[0048] In a second aspect, an embodiment of this specification provides a dedicated variable acquisition terminal, which uses a single-chip RAM block fault detection method described in the first aspect of the above embodiment to perform fault detection on the RAM block in its internal single-chip microcomputer.

[0049] In a third aspect, an embodiment of this specification provides an electronic device comprising a processor and a memory; the processor is connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the steps described in the first aspect of the above embodiment.

[0050] In a fourth aspect, an embodiment of this specification provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the steps described in the first aspect of the above embodiment.

[0051] The beneficial effects of the technical solutions provided by some embodiments of this specification include at least:

[0052] By combining the main detection bit with some slave detection bits, with the main detection bit fixed and the slave detection bits changing periodically to perform data writing and data reading operations for fault detection, the fault detection effect can be guaranteed while minimizing the impact of data writing and reading bit occupation during the fault detection process on the normal operation of the main program of the microcontroller. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 This is a flow chart of a method for detecting a RAM block fault in a single-chip microcomputer provided in an embodiment of this specification.

[0055] Figure 2 This is a structural diagram of a single-chip RAM block fault detection system provided in an embodiment of this specification.

[0056] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of this specification will be described clearly and completely below in conjunction with the drawings in the embodiments of this specification.

[0058] Throughout this specification, the claims, and the accompanying drawings, the terms "first," "second," "third," and the like are used to distinguish between different items, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may include other steps or elements inherent to the process, method, product, or apparatus.

[0059] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the functions and arrangements of the elements described without departing from the scope of this specification. Various examples may appropriately omit, replace, or add various processes or components. For example, the described methods may be performed in an order different from the order described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in other examples.

[0060] Reference Figure 1 As shown, Figure 1 A flowchart of a method for detecting a RAM block fault in a single-chip microcomputer provided in one embodiment of this specification may at least include:

[0061] Step 102: Selecting a plurality of data write and read bits from the plurality of RAM blocks as a plurality of fault detection bits corresponding to the plurality of RAM blocks, wherein the plurality of fault detection bits in each RAM block include at least one master detection bit and a plurality of slave detection bits;

[0062] Step 104: During the MCU program initialization phase, a first mode write / read operation is performed on the plurality of RAM blocks. The first mode write / read operation includes performing data write operations and data read operations on all fault detection bits. Fault detection is performed on the plurality of RAM blocks based on consistency between the written data and the read data when performing the first mode write / read operation on the plurality of RAM blocks.

[0063] Step 106: During the single-chip microcomputer program running phase, a second mode write and read operation is periodically performed on the plurality of RAM blocks. The second mode write and read operation includes respectively performing data write operations and data read operations on the master detection bits and part of the slave detection bits corresponding to the plurality of RAM blocks. When the second mode write and read operation is periodically performed on the plurality of RAM blocks, part of the slave detection bits for each RAM block performing the data write operation and the data read operation changes periodically. When the second mode write and read operation is periodically performed on the plurality of RAM blocks, periodic fault detection is performed on the plurality of RAM blocks based on the consistency of the periodic written data and the read data. The main program of the single-chip microcomputer continues to operate normally during the periodic fault detection process through the unoccupied data write and read bits.

[0064] The microcontroller RAM block fault detection method described in multiple embodiments of this specification performs data writing and data reading operations for fault detection by combining a main detection bit with some slave detection bits, with the main detection bit being fixed and the slave detection bits changing periodically. This can ensure the fault detection effect while minimizing the impact of data write and read bit occupation during the fault detection process on the normal operation of the microcontroller main program.

[0065] It should be noted that during the microcontroller program initialization phase, the program has not yet officially run, so the first mode write and read operations can be performed on all fault detection bits to ensure that all write and read bits in all RAM blocks function normally before the program officially runs.

[0066] In some embodiments of the present specification, for each RAM block, the master detection bit is located at the head of the RAM block, and multiple slave detection bits are respectively located at adjacent ends of multiple array variable write and read bits in the RAM block.

[0067] As you can understand, the RAM block header stores metadata, which is used to manage operations such as memory block allocation and release, as well as data addressing. Therefore, when a program is running, the metadata stored in the RAM block header needs to be frequently accessed for memory management operations. This high frequency of access makes the RAM block header the most active part of the entire memory, resulting in a higher probability of failure. Therefore, in the embodiments of this specification, the primary detection bit is located at the RAM block header.

[0068] It is also understandable that when a program writes to an array variable, if the boundaries are not checked correctly, the program may write to a position outside the array variable write and read bits (note: and usually overflow backwards), which may cause the program to crash or data to be corrupted. Therefore, the position adjacent to the end of the array variable write and read bit is more prone to failure. Therefore, multiple slave detection bits are respectively located at the positions adjacent to the ends of the array variable write and read bits in the RAM block.

[0069] In some embodiments of the present specification, for each RAM block, the master detection bit is located at the head of the RAM block, and the multiple slave detection bits are evenly distributed in the RAM block;

[0070] Before periodically performing the second mode write and read operations on the plurality of RAM blocks, the method further includes:

[0071] Partitioning the multiple RAM blocks respectively to obtain multiple RAM data write / read areas corresponding to the multiple RAM blocks, wherein the multiple RAM data write / read areas have the same number of slave detection bits;

[0072] Part of the detection bits involved in each RAM block in the second mode write and read operations of each cycle need to be selected from the corresponding multiple RAM data write and read areas.

[0073] It can be understood that in the embodiments of this specification, the RAM blocks are partitioned, and the partial slave detection bits involved in each RAM block in the second mode write and read operations of each cycle need to be selected from the multiple RAM data write and read areas corresponding thereto, so as to ensure that the partial slave detection bits in the second mode write and read operations of each cycle are dispersed in multiple RAM data write and read areas, rather than concentrated in a certain write and read position of the RAM block, and further ensure the detection effect of the fault detection on the basis of avoiding the normal operation of the main program of the single-chip microcomputer due to the occupation of data write and read bits during the fault detection process as much as possible.

[0074] Furthermore, the part of the slave detection bit for each RAM block performing data write operations and data read operations changes periodically by cyclically changing the position of the slave detection bit selected in each corresponding RAM data write / read area in the RAM data write / read area from the head of the RAM data write / read area to the tail of the RAM data write / read area.

[0075] The following examples illustrate:

[0076] For example, a RAM block is divided into RAM data write-read area 1, RAM data write-read area 2, and RAM data write-read area 3. In RAM data write-read area 1, slave detection bit 1, slave detection bit 2, and slave detection bit 3 are sequentially provided from the RAM data write-read area head to the RAM data write-read area tail. In RAM data write-read area 2, slave detection bit 4, slave detection bit 5, and slave detection bit 6 are sequentially provided from the RAM data write-read area head to the RAM data write-read area tail. In RAM data write-read area 3, slave detection bit 7, slave detection bit 8, and slave detection bit 9 are sequentially provided from the RAM data write-read area head to the RAM data write-read area tail.

[0077] The above cycle pattern can be understood as follows: in cycle 1, in the RAM block, slave detection bits 1, 4, and 7 are selected as partial slave detection bits for data write and data read operations. In cycle 2, slave detection bits 2, 5, and 8 are selected as partial slave detection bits for data write and data read operations. In cycle 3, slave detection bits 3, 6, and 9 are selected as partial slave detection bits for data write and data read operations.

[0078] This cyclical change pattern of the slave detection bits improves the uniformity of the selected slave detection bits within the RAM block during each cycle, ensuring consistent fault detection frequencies across all write and read locations within the RAM block. Furthermore, the regularity of the data write and read bits used for fault detection further helps guide the microcontroller's main program in utilizing unoccupied data write and read bits.

[0079] In some embodiments of this specification, the first mode write and read operations include:

[0080] Performing a data writing operation of a first preset value on all fault detection bits;

[0081] Performing a data reading operation on all fault detection bits to obtain first read data corresponding to all fault detection bits;

[0082] Performing a data writing operation of a second preset value on all fault detection bits;

[0083] Performing a data reading operation on all fault detection bits to obtain second read data corresponding to all fault detection bits;

[0084] The first preset value and the second preset value are in an inverse relationship.

[0085] It can be understood that when performing fault detection, it is impossible to simultaneously test the fault detection bit's ability to write 0 and write 1 by only performing one write and read operation of the preset value. Therefore, two write and read operations are performed using the first preset value and the second preset value, which are in an inverse code relationship, to achieve comprehensive testing of the ability to write 0 and write 1.

[0086] The method of performing fault detection on the multiple RAM blocks based on consistency between written data and read data when performing first mode write and read operations on the multiple RAM blocks includes:

[0087] Obtaining a first consistency condition based on a first preset value and first read data corresponding to each of the fault detection bits;

[0088] Obtaining a second consistency condition based on the second preset value and the second read data corresponding to each of the fault detection bits;

[0089] Based on the first consistency condition and the second consistency condition, fault detection is performed on the plurality of RAM blocks.

[0090] That is, based on the first consistency condition and the second consistency condition, the functional conditions of writing 0 and writing 1 corresponding to all fault detection bits are obtained, and further specific fault detection can be performed.

[0091] In some embodiments of this specification, the second mode write and read operations in each cycle include:

[0092] Performing a data writing operation of a first preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks;

[0093] Performing a data reading operation on the master detection bits and part of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain third read data corresponding to the master detection bits and part of the slave detection bits corresponding to the current cycle;

[0094] Performing a data writing operation of a second preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks;

[0095] Performing a data reading operation on the master detection bits and the portion of slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain fourth read data corresponding to the master detection bits and the portion of slave detection bits corresponding to the current cycle;

[0096] The first preset value and the second preset value are in an inverse relationship.

[0097] It can be understood that the second mode write and read operations are consistent with the first mode write and read operations, and also require two write and read operations using the first preset value and the second preset value which are in an inverse relationship, to achieve comprehensive detection of the write 0 and write 1 capabilities.

[0098] In some embodiments of this specification, in the process of performing periodic fault detection on multiple RAM blocks based on the consistency between periodic written data and read data, each periodic fault detection includes:

[0099] Obtaining third consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the first preset value and the master detection bits in the multiple RAM blocks and the third read data corresponding to each of the slave detection bits corresponding to the current cycle;

[0100] Obtaining fourth consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the second preset value and the fourth read data corresponding to each of the master detection bits and the portion of slave detection bits corresponding to the current cycle in the multiple RAM blocks;

[0101] Based on the third consistency status and the fourth consistency status corresponding to the multiple RAM blocks, fault detection of the current cycle is performed on the multiple RAM blocks.

[0102] That is, based on the third consistency condition and the fourth consistency condition, the functional conditions of writing 0 and writing 1 corresponding to the main detection bit and some slave detection bits corresponding to the current cycle are obtained, and further specific fault detection can be performed.

[0103] In some embodiments of this specification, performing fault detection on the multiple RAM blocks in the current cycle based on the third consistency status and the fourth consistency status corresponding to each of the multiple RAM blocks includes:

[0104] When there is no inconsistency in the third consistency condition and the fourth consistency condition corresponding to each of the plurality of RAM blocks, the fault detection result of the current cycle is no fault;

[0105] When there is a RAM block with inconsistency in the third consistency condition and the fourth consistency condition, the RAM block with inconsistency in the third consistency condition and the fourth consistency condition is regarded as a RAM block to be detected for the second time, and enters the second fault detection link;

[0106] The secondary fault detection link includes:

[0107] Re-performing a first preset number of second-mode write and read operations on all RAM blocks deemed to be RAM blocks to be re-detected, to obtain a new third consistency status and a new fourth consistency status corresponding to all RAM blocks to be re-detected under each second-mode write and read operation;

[0108] When there is no new third consistency situation and inconsistency in the new fourth consistency situation of the RAM blocks to be detected for the second time under the second mode write and read operations for a number greater than or equal to the second preset number, all RAM blocks to be detected for the second time are regarded as out-of-bounds fault RAM blocks, otherwise the third mode write and read operations are performed on all RAM blocks, and the third mode write and read operations include data writing operations and data reading operations on all fault detection bits not involved in the current cycle, and based on the third consistency situation and fourth consistency situation corresponding to each of the multiple RAM blocks, the new third consistency situation and new fourth consistency situation corresponding to each of the RAM blocks to be detected for the second time under each second mode write and read operation, and the consistency of written data and read data when the third mode write and read operations are performed on all RAM blocks, fault detection is performed on all RAM blocks.

[0109] It can be understood that when a RAM block has inconsistencies in the third consistency situation and the fourth consistency situation, it means that there is a faulty write-read bit in the RAM block. Generally speaking, when there is a fault in a certain write-read position in a RAM block, the probability of faults occurring at other write-read positions in the RAM block also increases. Further, the probability of faulty write-read bits existing in the remaining RAM blocks belonging to the same microcontroller also increases. Therefore, global fault detection should be performed on all write-read bits at this time. However, in the embodiments of this specification, in order to minimize the impact on the normal operation of the main program of the single-chip microcomputer due to the occupation of data write and read bits during the fault detection process, global fault detection is not directly performed on all data write and read bits (Note: performing global detection means that data needs to be written and read from all data write and read bits, and the write and read data consistency judgment is performed on each data write and read bit separately. Although this fault detection mode is more comprehensive, the main program of the single-chip microcomputer has no available remaining data write and read bits and needs to wait for normal operation to resume after fault detection, resulting in a longer delay). Instead, a first preset number of second-mode write and read operations are re-performed on all RAM blocks that are considered to be RAM blocks to be re-detected, so as to obtain new third consistency conditions and new fourth consistency conditions corresponding to all RAM blocks to be re-detected under each second-mode write and read operation. In other words, the write and read operations of the first preset value and the second preset value are repeatedly performed on the main detection bits and some slave detection bits corresponding to the current cycle in the RAM blocks to be re-detected (in this case, only some data write and read bits are occupied. Therefore, when performing fault detection, the main program of the single-chip microcomputer can still continue to operate normally based on the unoccupied data write and read bits).

[0110] Furthermore, when no RAM blocks to be re-checked have the new third consistency condition and inconsistencies in the new fourth consistency condition under the second mode write and read operations for a number greater than or equal to the second preset number, all RAM blocks to be re-checked are considered RAM blocks with boundary-crossing faults. This indicates that the data write and read inconsistencies in the RAM blocks to be re-checked were caused by data boundary crossings, rather than other substantial faults. Since data boundary crossings typically occur at a single point, it is sufficient to resolve the data boundary crossing fault at that location, without further global fault detection.

[0111] If there is no new third consistency condition and inconsistency in the new fourth consistency condition of the RAM block to be re-tested under the second preset number of second-mode write-read operations, it is considered that a substantial fault problem has occurred, and therefore a global fault detection for all write-read bits is required. Finally, the third consistency condition and fourth consistency condition corresponding to each of the multiple RAM blocks, the new third consistency condition and new fourth consistency condition corresponding to each of the RAM blocks to be re-tested under each second-mode write-read operation, and the consistency of the written data and the read data when the third-mode write-read operation is performed on all RAM blocks can be combined to perform fault detection on all RAM blocks. (Note: that is, all data write-read bits that have failed are found, and subsequent fault processing is performed based on the conditions of all failed write-read bits).

[0112] The first preset number and the second preset number can be set manually according to needs, and the second preset number is smaller than the first preset number.

[0113] It should be explained that the above substantial failures are mostly caused by failures in the RAM bus, which in turn cause crosstalk failures and / or self-excitation failures, and crosstalk failures and self-excitation failures usually occur together.

[0114] The crosstalk failure is manifested as follows: the data in multiple data write and read bits will be crosstalked into the same value, and the crosstalked data write and read bits have a certain random variability, but the range of the crosstalked data write and read bits is relatively wide, and the crosstalk failure usually occurs continuously.

[0115] The self-excited fault is manifested as one or more BIT bits being set to 1 all the time and unable to pass normal write and read control, that is, the fault of a fixed data write and read bit is in a continuous state.

[0116] The out-of-bounds fault is caused by the data that should have been written to the target write-read bit during the operation of the microcontroller main program occupying the adjacent data write-read bit position. Therefore, after the preset value is written to the fault detection bit, as the microcontroller main program runs, even if it is declared in advance that the fault detection bit is currently used for fault detection and normal data writing is not allowed, the data written to the fault detection bit for fault detection may still be overwritten by the data of its adjacent data write-read bit due to out-of-bounds. In addition, the length of the data written in the data write-read bit adjacent to the fault detection bit will change during the operation of the microcontroller main program, and according to experience, the length of the data written in the data write-read bit adjacent to the fault detection bit usually does not exceed the preset boundary length. The occurrence of out-of-bounds is an occasional situation. Therefore, if the preset value is written to the same fault detection bit multiple times, the number of out-of-bounds faults should be relatively small.

[0117] Therefore, based on the above, we can conclude that:

[0118] If a RAM block with inconsistencies in the third and fourth consistency conditions exists due to a self-excitation fault, the inconsistency cannot be eliminated no matter how many times the second mode write and read operations are subsequently performed.

[0119] If a crosstalk failure causes a RAM block with inconsistencies in the third or fourth consistency conditions, although the crosstalked data write and read bits have a certain degree of random variability, the crosstalked data write and read bits are relatively wide and occur continuously. Therefore, based on the fact that multiple slave detection bits are evenly distributed in the RAM block, even if the crosstalked data write and read bits may change, there is only a small probability that the multiple evenly distributed slave detection bits in the RAM block will simultaneously experience crosstalk disappearance. Therefore, by re-performing the first preset number of second-mode write and read operations on all RAM blocks that are considered to be RAM blocks to be re-tested, there should be no or a small number of second-mode write and read operations that do not have inconsistencies in the new third or fourth consistency conditions.

[0120] If the RAM blocks with inconsistencies in the third consistency situation and the fourth consistency situation are caused only by an out-of-bounds failure, the second mode write and read operations are performed again for the first preset number of times on all RAM blocks that are regarded as RAM blocks to be re-detected. There should be RAM blocks to be re-detected that do not have inconsistencies in the new third consistency situation and the new fourth consistency situation under a large number of second mode write and read operations.

[0121] Therefore, when there is no RAM block to be re-detected with inconsistency in the new third consistency situation and the new fourth consistency situation under the second mode write and read operations greater than or equal to the second preset number, all RAM blocks to be re-detected are regarded as out-of-bounds fault RAM blocks.

[0122] In some embodiments of this specification, the third mode write and read operations include:

[0123] Performing a data writing operation of a first preset value on all fault detection bits not involved in the current cycle;

[0124] Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain fifth read data corresponding to all fault detection bits not involved in the current cycle;

[0125] Performing a data writing operation of a second preset value on all fault detection bits not involved in the current cycle;

[0126] Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain sixth read data corresponding to all fault detection bits not involved in the current cycle;

[0127] The first preset value and the second preset value are in an inverse relationship.

[0128] It can be understood that for the third mode write and read operation, it is consistent with the first mode write and read operation and the second mode write and read operation, and also needs to perform two write and read operations respectively through the first preset value and the second preset value which are in an inverse code relationship between the two to achieve comprehensive detection of the ability to write 0 and write 1.

[0129] In order to reduce the number of data write and read bits in the write and read operations, in the third mode write and read operations, data write operations and data read operations are only performed on all fault detection bits not involved in the current cycle.

[0130] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0131] See next Figure 2 , Figure 2 The structure diagram of a single-chip RAM block fault detection system provided by an embodiment of this specification is shown, which may at least include:

[0132] A setting module is configured to select a plurality of data write and read bits in the plurality of RAM blocks as a plurality of fault detection bits corresponding to the plurality of RAM blocks, wherein the plurality of fault detection bits in each RAM block include at least one master detection bit and a plurality of slave detection bits;

[0133] A write-read module, which performs a first mode write-read operation on a plurality of RAM blocks during the initialization phase of the single-chip computer program, wherein the first mode write-read operation includes performing a data write operation and a data read operation on all fault detection bits;

[0134] The write-read module also periodically performs a second-mode write-read operation on the plurality of RAM blocks during the microcontroller program running phase. The second-mode write-read operation includes respectively performing a data write operation and a data read operation on a master detection bit and a portion of a slave detection bit corresponding to each of the plurality of RAM blocks. When the second-mode write-read operation is periodically performed on the plurality of RAM blocks, the portion of the slave detection bits on each RAM block that performs the data write operation and the data read operation changes periodically.

[0135] a fault detection module, performing fault detection on the plurality of RAM blocks based on consistency between written data and read data when performing a first mode write and read operation on the plurality of RAM blocks;

[0136] The fault detection module also performs periodic fault detection on the multiple RAM blocks based on the consistency of the periodic written data and read data when periodically performing the second mode write and read operations on the multiple RAM blocks.

[0137] The various embodiments in this specification are described in a progressive manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from the other embodiments. In particular, the embodiment of the single-chip microcomputer RAM block fault detection system is generally similar to the embodiment of the single-chip microcomputer RAM block fault detection method, so its description is relatively simple. For relevant portions, refer to the description of the embodiment of the single-chip microcomputer RAM block fault detection method.

[0138] The embodiments of this specification also provide a dedicated transformer acquisition terminal, which uses the single-chip computer RAM block fault detection method described in the above embodiment to perform fault detection on the RAM block in its internal single-chip computer.

[0139] The dedicated transformer acquisition terminal is an indispensable device in the power system. Through its efficient data acquisition, transmission, and processing functions, it provides strong support for the real-time monitoring, remote control, and fault diagnosis of the power system, thereby improving the operational efficiency and safety of the power system. Therefore, it is particularly important to detect faults in its internal single-chip microcomputer, and it is even more important to ensure the continued normal operation of the main program in the single-chip microcomputer when performing fault detection on the internal single-chip microcomputer, so as to ensure the real-time and normal collection, transmission, and processing of data. Therefore, the embodiments of this specification also provide a dedicated transformer acquisition terminal that uses the single-chip microcomputer RAM block fault detection method described in the above embodiments to perform fault detection on the RAM blocks in its internal single-chip microcomputer.

[0140] See also Figure 3A schematic structural diagram of an electronic device provided in an embodiment of this specification is shown.

[0141] like Figure 3 As shown, the electronic device 300 may include: at least one processor 301 , at least one network interface 304 , a user interface 303 , a memory 305 and at least one communication bus 302 .

[0142] The communication bus 302 may be used to implement the connection and communication between the above components.

[0143] The user interface 303 may include buttons, and the optional user interface may also include a standard wired interface or a wireless interface.

[0144] The network interface 304 may include, but is not limited to, a Bluetooth module, an NFC module, a Wi-Fi module, and the like.

[0145] Among them, the processor 301 may include one or more processing cores. The processor 301 uses various interfaces and lines to connect the various parts of the entire electronic device 300, and executes various functions of the electronic device 300 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 305, and calling data stored in the memory 305. Optionally, the processor 301 can be implemented in at least one hardware form of DSP, FPGA, and PLC. The processor 301 can integrate one or a combination of CPU, GPU, and modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; and the modem is used to handle wireless communications. It is understandable that the above-mentioned modem may not be integrated into the processor 301, but may be implemented separately through a chip.

[0146] Memory 305 may include either RAM or ROM. Optionally, memory 305 may include non-transitory computer-readable media. Memory 305 may be used to store instructions, programs, codes, code sets, or instruction sets. Memory 305 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, sound playback function, image playback function, etc.), instructions for implementing the aforementioned method embodiments, etc.; the data storage area may store data related to the aforementioned method embodiments, etc. Memory 305 may also optionally be at least one storage device located remotely from the processor 301. Memory 305, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a fault detection application. Processor 301 may be configured to invoke the fault detection application stored in memory 305 and execute the steps of the fault detection method described in the aforementioned embodiments.

[0147] The embodiments of this specification also provide a computer-readable storage medium storing instructions that, when executed on a computer or processor, cause the computer or processor to perform one or more steps of the aforementioned fault detection method embodiments. If the components of the aforementioned electronic device are implemented as software functional units and sold or used as independent products, they may be stored in the computer-readable storage medium.

[0148] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this specification are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state drive (SSD)).

[0149] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When executed, the program can include the processes of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks. The technical features of this embodiment and the implementation scheme can be combined in any manner unless they conflict.

[0150] The embodiments described above are merely preferred embodiments of this specification and are not intended to limit the scope of this specification. Without departing from the design spirit of this specification, various modifications and improvements made to the technical solutions of this specification by ordinary technicians in this field should fall within the scope of protection determined by the claims of this specification.

Claims

1. A method for detecting a RAM block fault in a single-chip microcomputer, wherein the single-chip microcomputer includes multiple RAM blocks, characterized in that: include: Selecting a plurality of data write and read bits in the plurality of RAM blocks as a plurality of fault detection bits corresponding to the plurality of RAM blocks, respectively, wherein the plurality of fault detection bits in each RAM block include at least one master detection bit and a plurality of slave detection bits; During a single-chip computer program initialization phase, a first mode write and read operation is performed on the plurality of RAM blocks, wherein the first mode write and read operation includes performing data write operations and data read operations on all fault detection bits, and based on consistency between the written data and the read data when performing the first mode write and read operations on the plurality of RAM blocks, fault detection is performed on the plurality of RAM blocks; During a single-chip computer program running phase, a second-mode write and read operation is periodically performed on the plurality of RAM blocks. The second-mode write and read operation includes respectively performing data write operations and data read operations on a master detection bit and a portion of slave detection bits corresponding to each of the plurality of RAM blocks. When the second-mode write and read operation is periodically performed on the plurality of RAM blocks, a portion of the slave detection bits on each RAM block that performs the data write operation and the data read operation is periodically changed. When the second-mode write and read operation is periodically performed on the plurality of RAM blocks, periodic fault detection is performed on the plurality of RAM blocks based on consistency between the periodic written data and the read data. The main program of the single-chip computer continues to operate normally during the periodic fault detection process through the unoccupied data write and read bits. For each RAM block, the main detection bit is located at the head of the RAM block; In the process of performing periodic fault detection on multiple RAM blocks based on the consistency between periodic written data and read data, the fault detection of each period includes: Obtaining third consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the first preset value and the master detection bits in the multiple RAM blocks and the third read data corresponding to each of the slave detection bits corresponding to the current cycle; Obtaining fourth consistency status corresponding to each of the multiple RAM blocks in the current cycle based on the second preset value and the fourth read data corresponding to each of the master detection bits and the portion of slave detection bits corresponding to the current cycle in the multiple RAM blocks; Performing fault detection on the multiple RAM blocks in a current cycle based on the third consistency status and the fourth consistency status corresponding to each of the multiple RAM blocks; The performing fault detection on the multiple RAM blocks in the current cycle based on the third consistency status and the fourth consistency status corresponding to each of the multiple RAM blocks includes: When there is no inconsistency in the third consistency condition and the fourth consistency condition corresponding to each of the plurality of RAM blocks, the fault detection result of the current cycle is no fault; When there is a RAM block with inconsistency in the third consistency condition and the fourth consistency condition, the RAM block with inconsistency in the third consistency condition and the fourth consistency condition is regarded as a RAM block to be detected for the second time, and enters the second fault detection link; The secondary fault detection link includes: Re-performing a first preset number of second-mode write and read operations on all RAM blocks deemed to be RAM blocks to be re-detected, to obtain a new third consistency status and a new fourth consistency status corresponding to all RAM blocks to be re-detected under each second-mode write and read operation; When there is no new third consistency situation and inconsistency in the new fourth consistency situation of the RAM blocks to be detected for the second time under the second mode write and read operations for a number greater than or equal to the second preset number, all RAM blocks to be detected for the second time are regarded as out-of-bounds fault RAM blocks, otherwise the third mode write and read operations are performed on all RAM blocks, and the third mode write and read operations include data writing operations and data reading operations on all fault detection bits not involved in the current cycle, and based on the third consistency situation and fourth consistency situation corresponding to each of the multiple RAM blocks, the new third consistency situation and new fourth consistency situation corresponding to each of the RAM blocks to be detected for the second time under each second mode write and read operation, and the consistency of written data and read data when the third mode write and read operations are performed on all RAM blocks, fault detection is performed on all RAM blocks.

2. The method for detecting a fault in a single chip microcomputer RAM block according to claim 1, wherein: For each RAM block, the plurality of slave detection bits are respectively located at positions adjacent to the ends of the write and read bits of the plurality of array variables in the RAM block.

3. The method for detecting a fault in a single chip microcomputer RAM block according to claim 1, wherein: For each RAM block, multiple slave detection bits are evenly distributed in the RAM block; Before periodically performing the second mode write and read operations on the plurality of RAM blocks, the method further includes: Partitioning the multiple RAM blocks respectively to obtain multiple RAM data write / read areas corresponding to the multiple RAM blocks, wherein the multiple RAM data write / read areas have the same number of slave detection bits; Wherein, the part involved in each RAM block in the second mode write and read operation of each cycle needs to be selected from the multiple RAM data write and read areas corresponding thereto respectively; The part of the slave detection bit for each RAM block performing data write operation and data read operation changes periodically by cyclically changing the position of the slave detection bit selected in each corresponding RAM data write / read area in the RAM data write / read area from the head of the RAM data write / read area to the tail of the RAM data write / read area.

4. The method for detecting a fault in a single chip microcomputer RAM block according to claim 1, wherein: The first mode write and read operations include: Performing a data writing operation of a first preset value on all fault detection bits; Performing a data reading operation on all fault detection bits to obtain first read data corresponding to all fault detection bits; Performing a data writing operation of a second preset value on all fault detection bits; Performing a data reading operation on all fault detection bits to obtain second read data corresponding to all fault detection bits; The first preset value and the second preset value are in an inverse relationship.

5. The method for detecting a fault in a single chip microcomputer RAM block according to claim 4, wherein: The method of performing fault detection on the multiple RAM blocks based on consistency between written data and read data when performing first mode write and read operations on the multiple RAM blocks includes: Obtaining a first consistency condition based on a first preset value and first read data corresponding to each of the fault detection bits; Obtaining a second consistency condition based on the second preset value and the second read data corresponding to each of the fault detection bits; Based on the first consistency condition and the second consistency condition, fault detection is performed on the plurality of RAM blocks.

6. The method for detecting a fault in a single chip microcomputer RAM block according to claim 3, wherein: The second mode write and read operations in each cycle include: Performing a data writing operation of a first preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks; Performing a data reading operation on the master detection bits and part of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain third read data corresponding to the master detection bits and part of the slave detection bits corresponding to the current cycle; Performing a data writing operation of a second preset value on the master detection bits and a portion of the slave detection bits corresponding to the current cycle in the plurality of RAM blocks; Performing a data reading operation on the master detection bits and the portion of slave detection bits corresponding to the current cycle in the plurality of RAM blocks to obtain fourth read data corresponding to the master detection bits and the portion of slave detection bits corresponding to the current cycle; The first preset value and the second preset value are in an inverse relationship.

7. The method for detecting a RAM block fault in a single chip computer according to claim 1, wherein: The third mode write and read operations include: Performing a data writing operation of a first preset value on all fault detection bits not involved in the current cycle; Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain fifth read data corresponding to all fault detection bits not involved in the current cycle; Performing a data writing operation of a second preset value on all fault detection bits not involved in the current cycle; Performing a data reading operation on all fault detection bits not involved in the current cycle to obtain sixth read data corresponding to all fault detection bits not involved in the current cycle; The first preset value and the second preset value are in an inverse relationship.

8. A dedicated transformer acquisition terminal, characterized in that: A single-chip microcomputer RAM block fault detection method according to any one of claims 1 to 7 is used to perform fault detection on a RAM block in an internal single-chip microcomputer.

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