CXL memory device, data transmission method, computing device and system

Abstract

The invention provides a CXL memory device, a data transmission method, a computing device and a system, and under the condition that the computing device sends a scanning instruction to a first CXL controller, the first CXL controller determines the connection state of each CXL controller, and then performs unified addressing on each CXL controller. Thereby, the computing device may determine routing configuration information based on the address information for each CXL controller. In a case where the computing device sends an access request, the first CXL controller may determine and gate a target transmission channel with the target CXL controller based on the routing configuration information. And the computing device can access the target memory through the target transmission channel. Therefore, cross-level access to multiple memories can be realized without adding external cables of the computing equipment, and the scale and capacity of the external CXL memory of the computing equipment can be further improved.

Description

Technical Field

[0001] This application relates to the field of computing, and particularly to a Compute Express Link (CXL) memory device, a data transmission method, a computing device, and a system. Background Art

[0002] With the development of technology, Compute Express Link (CXL) provides a new solution for the interconnection between processors, memories, and accelerators, improving the communication between processors and accelerators, memory expansion devices, etc.

[0003] However, CXL memory devices are often single-master extended, and the master chips in the CXL memory device are independent of each other. When the host needs to access the CXL memory device, an external cable needs to be connected to the CXL memory device. The connection method through the external cable has a delay overhead, and the utilization rate of both the host-side port and the CXL memory device port is relatively low, restricting the scale of memory expansion. Summary of the Invention

[0004] This application provides a CXL memory device, a data transmission method, a computing device, and a system, which can expand the scale and capacity of the external memory device of the computing device and improve the overall performance of the computing device.

[0005] In a first aspect, an embodiment of this application provides a Compute Express Link (CXL) memory device. The CXL memory device includes a first CXL controller, a second CXL controller, a first memory, and a second memory; the first CXL controller is coupled to the first memory; the second CXL controller is coupled to the second memory; the first CXL controller is coupled to the second CXL controller through a High-Speed Interconnect (HSI) bus; the first CXL controller is coupled to a computing device; the first CXL controller is configured to: send unified addressing information to the computing device; where the unified addressing information is determined based on the address information of the first memory and the address information of the second memory; receive routing configuration information; the routing configuration information is determined by the computing device based on the unified addressing information; based on the routing configuration information, determine a target transmission channel; the target transmission channel includes a link between the first CXL controller and the second CXL controller; in response to an access request from the computing device, access the second memory by the computing device through the target transmission channel.

[0006] In the above method, the first CXL controller is communicatively coupled to the computing device, and the second CXL controller is coupled to the first CXL controller and not directly coupled to the computing device. The computing device can access the second memory under the second CXL controller through the target transmission channel between the first CXL controller and the second CXL controller determined by the first CXL controller. Without the need to connect more external cables, the scale and capacity of the external CXL memory of the computing device can be expanded.

[0007] In an embodiment of the present application, the first CXL controller is further configured to: in response to a scan instruction from a computing device, determine the connection status between the first CXL controller and the second CXL controller; when the connection status between the first CXL controller and the second CXL controller meets a first preset connection status, obtain the address information of the first memory and the address information of the second memory; and perform unified addressing on the address information of the first memory and the address information of the second memory.

[0008] It can be understood that when the connection statuses of both the first CXL controller and the second CXL controller meet the conditions, determining the address information of the first memory and the second memory can ensure the reliability of data transmission and promptly detect memories in an abnormal state.

[0009] In an embodiment of the present application, the first CXL controller is configured to determine a target transmission channel based on routing configuration information, including: receiving an access request; and determining the target transmission channel based on the access request and the routing configuration information.

[0010] It can be understood that based on the routing configuration information, a target transmission channel can be selected from multiple transmission channels. Thus, the computing device can accurately and quickly access the second memory.

[0011] In an embodiment of the present application, the first CXL controller is further configured to: trigger and select to enable the link between the first CXL controller and the second CXL controller based on the routing configuration information and the unified addressing information.

[0012] In an embodiment of the present application, the first CXL controller is configured to enable the computing device to access the second memory through the target transmission channel, including: receiving the write data of the computing device; writing the write data into the second memory through the link between the first CXL controller and the second CXL controller; or reading data from the second memory through the link between the first CXL controller and the second CXL controller; and sending the read data to the computing device.

[0013] It can be understood that the computing device can still perform read and write access to the second memory through the target transmission channel without being coupled to the second CXL controller. Thus, it can be achieved that the computing device can perform data access based on the transmission channel between CXL controller stations without the need for external cable connection.

[0014] Second aspect, an embodiment of the present application provides a data transmission method, which is applied to a computing device. The computing device is coupled to a CXL memory device. The CXL memory device includes a first CXL controller, a second CXL controller, a first memory, and a second memory. The first CXL controller is coupled to the first memory. The second CXL controller is coupled to the second memory. The first CXL controller and the second CXL controller are coupled through a high-speed interconnect bus HSI. The method includes: receiving unified addressing information sent by the first CXL controller; where the unified addressing information is determined based on the address information of the first memory and the address information of the second memory; determining routing configuration information based on the unified addressing information; sending the routing configuration information to the first CXL controller; the routing configuration information is used to determine a target transmission channel; the target transmission channel includes a link between the first CXL controller and the second CXL controller; accessing the second memory through the target transmission channel.

[0015] In the above method, the computing device is communicatively connected to the first CXL controller, and the second CXL controller is connected to the first CXL controller. The computing device can obtain unified addressing information by sending a scan instruction to the first CXL controller, and then determine the routing configuration information. At the same time, the computing device can also access the second memory through the target transmission channel between the first CXL controller and the second CXL controller. Without the need to connect more external cables, the computing device only needs to connect one port to access all the memories on multiple CXL controllers, achieving the effect of doubling the memory capacity that can be accessed under a single interface.

[0016] In an embodiment of the present application, the method further includes: sending a scan instruction to the first CXL controller; the scan instruction is used to trigger the first CXL controller to determine the connection status between the first CXL controller and the second CXL controller.

[0017] Third aspect, an embodiment of the present application provides a computing device, which includes a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program instructions; the processor is used to execute the program to implement the data transmission method.

[0018] Fourth aspect, an embodiment of the present application provides a computing system, which includes a Compute Express Link (CXL) memory device and a computing device; wherein, the CXL memory device is coupled to the computing device.

[0019] In an embodiment of the present application, the CXL memory device is coupled to the computing device through a CXL switch device. Description of the Drawings

[0020] The embodiments of the present application will be described in more detail with reference to the accompanying drawings, and the above and other objects, features, and advantages of the present application will become more apparent. The drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation to the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0021] Figure 1 Schematically shows a schematic diagram of a system application architecture according to an embodiment of the present application.

[0022] Figure 2 Schematically shows a schematic diagram of a CXL memory device according to an embodiment of the present application.

[0023] Figure 3 Schematically shows a flowchart of a data transmission method applied to a first CXL controller according to an embodiment of the present application.

[0024] Figure 4 Schematically shows a flowchart of another data transmission method according to an embodiment of the present application.

[0025] Figure 5 Schematically shows a flowchart of determining a target transmission channel according to an embodiment of the present application.

[0026] Figure 6 Schematically shows a schematic diagram of a direct connection mode according to an embodiment of the present application.

[0027] Figure 7 Schematically shows a schematic diagram of a switch mode according to an embodiment of the present application.

[0028] Figure 8 Schematically shows a flowchart of another data transmission method according to an embodiment of the present application.

[0029] Figure 9 Schematically shows a schematic diagram of yet another data transmission method according to an embodiment of the present application.

[0030] Figure 10 Schematically shows a block diagram of another CXL memory device according to an embodiment of the present application.

[0031] Figure 11 Schematically shows a schematic diagram of yet another data transmission method according to an embodiment of the present application.

[0032] Figure 12 Schematically shows a schematic diagram of a CXL memory board according to an embodiment of the present application.

[0033] Figure 13Schematically shows a schematic diagram of another CXL memory board according to an embodiment of the present application.

[0034] Figure 14 Schematically shows a schematic diagram of a dual-node interconnection method according to an embodiment of the present application.

[0035] Figure 15 Schematically shows a schematic diagram of a three-node interconnection method according to an embodiment of the present application.

[0036] Figure 16 Schematically shows a schematic diagram of a four-node interconnection method according to an embodiment of the present application.

[0037] Figure 17 Schematically shows a block diagram of a computing device according to an embodiment of the present application.

[0038] Figure 18 Schematically shows a block diagram of a computing system according to an embodiment of the present application. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present application more obvious, the exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0040] The implementation manners of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0041] Please refer to Figure 1 , which shows a schematic diagram of a system application architecture according to an embodiment of the present application.

[0042] As Figure 1 shown, the system architecture may include: a first computing device 111, a second computing device 112, and a CXL memory device 113. Among them, the CXL memory device 113 includes a first CXL controller 1131, a first memory 1132, a second CXL controller 1133, and a second memory 1134.

[0043] In some embodiments, the first computing device 111 may be communicatively connected to the first CXL controller 1131 through a port. The second computing device 112 may be communicatively connected to the second CXL controller 1133 through a port. The first computing device 111 and the first CXL controller 1131 communicate through the CXL protocol, for example, the Input / Output protocol (CXL.io), the Access Cache protocol (CXL.cache), and the Access Memory protocol (CXL.mem). In some embodiments, the interface on the side of the first computing device 111 may be connected to the port on the side of the first CXL controller 1131 by an external cable to enable the first computing device 111 to access the first memory 1132.

[0044] In some embodiments, the first CXL controller 1131 may be communicatively connected to the second CXL controller 1133, for example, through a high-speed interconnect bus.

[0045] In some embodiments, the first computing device 111 and the second computing device 112 may be computing devices with data processing, logical operation, and storage functions. For example, the first computing device 111 and the second computing device 112 may include computing devices such as servers, tablets, desktop computers, laptops, notebooks, computing nodes, or netbooks. Among them, the server may be different types of servers such as rack servers, blade servers, or tower servers. The server may include one computing node or multiple computing nodes, each computing node includes at least one CPU, and when the server includes multiple computing nodes, the multiple CPUs in the multiple computing nodes share a set of operating systems.

[0046] In some embodiments, the first memory 1132 and the second memory 1134 may be used to provide storage space. For example, the first computing device 111 accesses the first memory 1132 to input or read and write stored data. The system architecture shown in the embodiments of the present application may also include multiple CXL memory devices 113.

[0047] In some embodiments, the first CXL controller 1131 is configured to receive a request from the first computing device 111 to write data to the storage space provided by the first memory 1132, or to read data from the storage space provided by the first memory 1132.

[0048] In some embodiments, the first CXL controller 1131 may be a control chip integrated in the CXL memory device 113, which may also be referred to as a memory expansion (CXL memory expander) chip, a CXL memory controller (CXL memory expander controller), or a CXL memory pooling (CXL memory expander pooling) chip. The first memory 1132 may be the actual physical carrier that provides storage space in the first CXL controller 1131.

[0049] In some embodiments, the first memory 1132 may include a read only memory (ROM), a random access memory (RAM), such as a dynamic random access memory (DRAM), a static random access memory (SRAM). The first CXL controller 1131 may include multiple first memories 1132. When there is one memory, the memory may be RAM or ROM. When there are multiple memories, the multiple memories may all be RAM, or the multiple memories may all be ROM, or some of the multiple memories are RAM and some are ROM. Of course, the embodiments of the present application do not limit the medium type, quantity, deployment method, etc. of the memory.

[0050] In addition, in the embodiments of the present application, the second CXL controller 1133 also has the same functions as the first CXL controller 1131, which will not be elaborated here.

[0051] According to the embodiments of the present application, the first computing device 111 may send an access request to the first CXL controller 1131 via an external cable, thereby realizing access to the first memory 1132. The second computing device 112 may send an access request to the second CXL controller 1133 via an external cable, thereby realizing access to the second memory 1134.

[0052] According to the embodiments of the present application, the first computing device 111 may also send an access request to the first CXL controller 1131 for accessing the second memory 1134. The first CXL controller 1131 may determine a target transmission channel based on the access request sent by the first computing device 111 and the routing configuration information stored locally, so that the first computing device 111 can read and write the second memory 1134 through the target transmission channel.

[0053] In some embodiments, the second computing device 112 may send an access request for the first memory 1132 to the second CXL controller 1133. The second CXL controller 1133 may determine a target transmission channel based on the access request sent by the second computing device 112 and the routing configuration information stored locally, for channel gating between the first CXL controller 1131 and the second CXL controller 1133. Consequently, the second computing device 112 can read and write to the first memory 1132 through the target transmission channel.

[0054] A Compute Express Link (CXL) memory device provided by an embodiment of the present application will be described below:

[0055] Please refer to Figure 2 , Figure 2 which is a schematic diagram of a CXL memory device provided by an embodiment of the present application. As Figure 2 shown, the CXL memory device 200 includes a first CXL controller 201, a second CXL controller 202, a first memory 203, and a second memory 204; the first CXL controller 201 is coupled to the first memory 203; the second CXL controller 202 is coupled to the second memory 204; the first CXL controller 201 and the second CXL controller 202 are coupled through a high-speed interconnect bus HSI; the first CXL controller 201 is coupled to a computing device.

[0056] The following is an introduction to the first CXL controller based on Figure 3 this. Figure 3 A flowchart of a data transmission method applied to the first CXL controller provided by an embodiment of the present application is schematically shown. As Figure 3 shown, the data transmission method, which is applied to the first CXL controller, includes:

[0057] S301. Send unified addressing information to the computing device; wherein, the unified addressing information is determined based on the address information of the first memory and the address information of the second memory.

[0058] In an embodiment of the present application, the address information of the first memory and the address information of the second memory at least include the capacities of the first memory and the second memory, the corresponding CXL controllers, and their locations. Exemplarily, the address information of the second memory may include its capacity size and physical address. It can be understood that the address information can at least be used to indicate the location of the memory. For example, based on the address information of a certain memory, it can be determined that the memory is located under the second controller in the second CXL memory device. It should be noted that a CXL memory device may include multiple CXL controllers, each CXL controller may include multiple memories, and the computing device may be coupled to multiple CXL memory devices.

[0059] In an embodiment of the present application, the unified addressing information can be determined based on a first CXL memory device and a second CXL memory device. Specifically, the first CXL controller can allocate different specific addresses for the CXL controllers and memories in the first CXL memory device and the second CXL memory device based on the same instruction and address format. Among them, the specific address can refer to a specific storage format, or a specific system identifier, etc. For example, the first CXL controller allocates specific addresses for the first CXL controller, the second CXL controller, the first memory, and the second memory respectively based on the address information.

[0060] It can be understood that the unified addressing information can at least include the specific address of the first memory and the address information of the first memory corresponding to the specific address, the specific address of the second memory, and the address information of the second memory corresponding to the specific address.

[0061] Furthermore, the first CXL controller can send the unified addressing information to the computing device.

[0062] In an embodiment of the present application, before the above S301, the following process may also be included as Figure 4 shown. Figure 4 The flowchart schematically shows another data transmission method according to an embodiment of the present application.

[0063] S401. In response to a scan instruction from the computing device, determine the connection status between the first CXL controller and the second CXL controller.

[0064] In an embodiment of the present application, the computing device can send a scan instruction to the first CXL controller to scan the first CXL controller. The first CXL controller can receive the scan instruction and determine the connection status between the first CXL controller and the second CXL controller based on the scan instruction.

[0065] In an embodiment of the present application, the connection status between the first CXL controller and the second CXL controller can include the physical connection status, signal strength status, communication protocol status, etc. between the first CXL controller and the second CXL controller. For example, determine whether the second CXL controller is in a normal working state, determine whether the first memory and the second memory are normally connected, determine whether the communication protocol status between the first CXL controller and the second CXL controller is normal, etc.

[0066] S402. When the connection status between the first CXL controller and the second CXL controller meets the first preset connection status, obtain the address information of the first memory and the address information of the second memory.

[0067] In the embodiment of the present application, the first preset connection state may refer to that all connections between the first CXL controller and the second CXL controller are connected or all ready. When the indicators of each CXL controller meet the conditions, the first CXL controller can obtain the address information of each memory.

[0068] It can be understood that the first preset connection state can be set based on different application scenarios. Exemplarily, if the scan instruction sent by the computing device includes scanning the first CXL controller, the first preset connection state can be that all connections of the first CXL controller are ready. Another example is that if the scan instruction sent by the computing device includes scanning the first CXL controller and the second CXL controller, the first preset connection state can be that all connections of the first CXL controller and the second CXL controller are ready.

[0069] In addition, in the embodiment of the present application, when the connection state of the first CXL controller and / or the second CXL controller does not meet the first preset connection state, the first CXL controller cannot obtain the corresponding address information. Exemplarily, when the connection state of the second CXL controller is displayed as an abnormal connection, the first CXL controller cannot obtain the address information of the second CXL controller and the second memory.

[0070] S403. Perform unified addressing on the address information of the first memory and the address information of the second memory.

[0071] Specifically, the first CXL controller can perform unified addressing on the address information of the first memory and the second memory based on the same address format and instruction, and allocate a specific address to each memory. When the computing device needs to access a certain memory, the first CXL controller can determine the specific address corresponding to the memory through the corresponding instruction and address format. And based on the address information corresponding to the specific address in the unified addressing information, determine the location, capacity size, etc. of the memory that the computing device actually wants to access in the system. Thus, allocating specific addresses to each memory according to the actual situation of different memories can enable the computing device to perform read and write operations on different memories based on the same access method, so as to improve the convenience of access of the computing device.

[0072] According to the embodiment of the present application, when the connection state of each CXL controller meets the conditions, the address information of each memory can be accurately obtained. Thus, it is ensured that during the data transmission process, the data can be accurately transmitted to the destination memory, avoiding incorrect data transmission.

[0073] S302. Receive routing configuration information, where the routing configuration information is determined by the computing device based on the unified addressing information.

[0074] In an embodiment of the present application, the computing device may determine and send routing configuration information according to the unified addressing information reported by the first CXL controller. The first CXL controller may receive the routing configuration information sent by the computing device.

[0075] In an embodiment of the present application, the unified addressing information may at least reflect the mapping relationship between memory - address information - specific addresses, and the routing configuration information may be determined based on at least the above mapping relationship.

[0076] In an embodiment of the present application, the first CXL controller may be interconnected with multiple CXL controllers through a high - speed interconnect bus HSI. Further, every two CXL controllers are interconnected through the high - speed interconnect bus HSI. In this case, it can be understood that the first CXL controller is configured with multiple transmission channels to connect with multiple CXL controllers. The high - speed interconnect bus HSI may be the actual physical carrier of the transmission channels.

[0077] In this case, the routing configuration information may at least include specific addresses, address information, memory, transmission channels, etc. Specifically, the routing configuration information can be used to at least determine the address information of a certain memory, and based on this address information, determine the transmission channel between the first CXL controller and the CXL controller corresponding to this address information. Exemplarily, the computing device may send an access request to access memory A. The first CXL controller may then convert the access request into a corresponding specific address. Further, the first CXL controller may, based on this specific address, determine the address information corresponding to this specific address from the routing configuration information, and through this address information, determine the memory actually accessed by the computing device, as well as the location, capacity, etc. of this memory. Further, the first CXL controller may, based on the location of this memory, determine the CXL controller corresponding to this memory from the routing configuration information, and determine the transmission channel connected to this CXL controller from the routing configuration information.

[0078] S303. Determine a target transmission channel based on the routing configuration information; the target transmission channel includes the link between the first CXL controller and the second CXL controller.

[0079] In an embodiment of the present application, multiple CXL controllers are interconnected through the high - speed interconnect bus HSI and communicate with each other through the CXL protocol. Based on this, the transmission channel may refer to the transmission link for transmitting data between every two CXL controllers through the high - speed interconnect bus HSI based on the CXL protocol.

[0080] Further, the above S303 may further include S501 and S502. Specifically, S501 and S502 are as Figure 5 shown. Figure 5Schematically shows a flowchart for determining a target transmission channel according to an embodiment of the present application.

[0081] S501. Receive an access request.

[0082] In an embodiment of the present application, the first CXL controller may receive an access request sent by a computing device. Among them, the access request may at least include address information of the computing device, access type information, and information about the object of this access, etc. For example, the access request may include the device identifier of the computing device, the MAC address, the write operation type information, and the memory information of the object of this access. Here, the memory information may include memory identifier, memory virtual address, etc. Specifically, the computing device is coupled to the CXL memory device. On the side of the computing device, all the memories included in the CXL memory device can be known. Each memory can be presented to the computing device side in a specific identifier or virtual address manner. In response to the computing device clicking or needing to access a certain memory, the identifier or virtual address information of this memory can be generated in the access request.

[0083] S502. Determine a target transmission channel based on the access request and routing configuration information.

[0084] In an embodiment of the present application, the first CXL controller may receive an access request and obtain the memory information of the object of this access from the access request. Further, the first CXL controller may convert the memory information of the object of this access into a corresponding specific address through specific instructions and address formats, etc. On this basis, the first CXL controller may, based on this specific address, query the routing configuration information to determine the address information corresponding to this specific address, and the memory corresponding to this address information, such as memory B, and the location where this memory B is located. For example, this memory B is under the second CXL controller. When the first CXL controller knows the location where this memory B is located, it may select the transmission channel connected to the second CXL controller as the target transmission channel among multiple transmission channels connected to other CXL controllers.

[0085] In an embodiment of the present application, the first CXL controller is further configured to: trigger the gating of the link between the first CXL controller and the second CXL controller based on the routing configuration information and unified addressing information.

[0086] Specifically, based on the routing configuration information and unified addressing information, when the target transmission channel is determined, the target transmission channel can be gated, that is, the link between the first CXL controller and the second CXL controller can be gated, so that the computing device can access the second memory based on the link between the first CXL controller and the second CXL controller.

[0087] According to the embodiments of the present application, a mapping relationship between the memory and the transmission channel is established through routing configuration information. Thus, the location of the memory to be accessed and the target CXL controller corresponding to the memory can be determined through the routing configuration information. In the case of determining the target CXL controller, the transmission channel corresponding to the target CXL controller is determined from multiple transmission channels through the routing configuration information as the target transmission channel. In this way, data transmission between different CXL controllers is realized. For a computing device, only by coupling one port, access to the entire memory in the CXL memory device can be achieved. For the CXL memory device, all memories can be coupled to the computing device through one port, and thus can be connected to more computing devices through the same port.

[0088] S304. In response to the access request of the computing device, the computing device accesses the second memory through the target transmission channel.

[0089] In the embodiments of the present application, when the target transmission channel is gated, the computing device can access the second memory under the second CXL controller through the target transmission channel between the first CXL controller and the second CXL controller.

[0090] In the embodiments of the present application, the above-mentioned S304 for the computing device to access the second memory through the target transmission channel includes: receiving the write data of the computing device; writing the write data into the second memory through the link between the first CXL controller and the second CXL controller.

[0091] In the embodiments of the present application, the above-mentioned S304 for the computing device to access the second memory through the target transmission channel further includes: reading data from the second memory through the link between the first CXL controller and the second CXL controller; sending the read data to the computing device.

[0092] According to the embodiments of the present application, based on the corresponding relationship among the memory, the address information, and the transmission channel in the routing configuration information, the target transmission channel is determined, so that the computing device can directly access the second memory through the target transmission channel. Thus, the computing device can realize read and write access to the second memory under the second CXL controller that is not directly coupled to it.

[0093] According to an embodiment of the present application, the first CXL controller is communicatively connected to a computing device, and the second CXL controller is coupled to the first CXL controller and not directly coupled to the computing device. The first CXL controller can perform unified addressing on each CXL controller so that the computing device can determine routing configuration information based on the unified addressing information. Further, the first CXL controller can determine a target transmission channel between the first CXL controller and the second CXL controller through the routing configuration information so as to accurately transmit data. Thereby, the computing device can access the second CXL controller through the target transmission channel. It realizes the expansion of the scale and capacity of the CXL memory externally connected to the computing device without connecting more external cables. At the same time, it can realize the ability to address the second CXL controller and access the memory thereunder through the first CXL controller.

[0094] Figure 6 and Figure 7 are two exemplary connection modes. Figure 6 Schematically shows the direct connection mode of the embodiment of the present application.

[0095] As Figure 6 shown, in the direct connection mode, the first computing device is connected to the first CXL controller, and the first CXL controller is connected to the second CXL controller through a high-speed interconnect bus HIS.

[0096] In some embodiments, when the first computing device needs to access the second memory of the second CXL controller, it does not need to pass through the physical cable connecting the first computing device to the second CXL controller. Instead, the first CXL controller performs routing configuration to select the link of the target transmission channel, enabling the first computing device to directly access the memory data under the second CXL controller.

[0097] Figure 7 Schematically shows the switch mode of the embodiment of the present application.

[0098] As Figure 7 shown, in the switch mode, referring to the description of Figure 6 , in the switch connection mode, without connecting the second CXL controller, the first computing device can still directly access the second memory under the second CXL controller through the high-speed interconnect bus between the first CXL controller and the second CXL controller. In this case, the switch interface can connect more CXL controllers, thereby further expanding the memory capacity.

[0099] The following describes another data transmission method provided by the embodiment of the present application:

[0100] Please refer to Figure 8 , Figure 8The flowchart of another data transmission method provided by an embodiment of this application. This method is applied to a computing device. The computing device is coupled to a CXL memory device; the CXL memory device includes a first CXL controller, a second CXL controller, a first memory, and a second memory; the first CXL controller is coupled to the first memory; the second CXL controller is coupled to the second memory; the first CXL controller and the second CXL controller are coupled through a high-speed interconnect bus HSI.

[0101] As Figure 8 shown, the data transmission method includes S801, S802, S803, and S804:

[0102] S801. Receive the unified addressing information sent by the first CXL controller; wherein, the unified addressing information is determined based on the address information of the first memory and the address information of the second memory.

[0103] S802. Determine the routing configuration information based on the unified addressing information.

[0104] In an embodiment of this application, the computing device can receive the unified addressing information sent by the first CXL controller. The unified addressing information at least includes a specific address, and the address information of the first memory and the second memory. Further, the computing device can determine the routing configuration information based on the unified addressing information. The routing configuration information can at least include a specific address, the mapping relationship between the address information and the memory, and the transmission channels from the first CXL controller to each other CXL controller. It can be understood that in the case of determining the location of the memory that the computing device needs to access, it can be determined which CXL controller the memory belongs to based on the routing configuration information. Further, in the case of determining which CXL controller the computing device needs to access, based on the routing configuration information, the transmission channel from the determined first CXL controller to this CXL controller can be used as the target transmission channel.

[0105] S803. Send the routing configuration information to the first CXL controller; the routing configuration information is used to determine the target transmission channel; the target transmission channel includes the link between the first CXL controller and the second CXL controller.

[0106] S804. Access the second memory through the target transmission channel.

[0107] In an embodiment of this application, the computing device can access the second memory that needs to be accessed based on the target transmission channel determined by the first CXL controller. For example, write data to the second memory, or read data from the second memory.

[0108] According to an embodiment of the present application, a computing device is communicatively connected to a first CXL controller, and a second CXL controller is connected to the first CXL controller. The computing device can send a scan instruction to the first CXL controller to obtain unified addressing information, and then determine routing configuration information. At the same time, the computing device can also access the second CXL controller through a target transmission channel between the first CXL controller and the second CXL controller. Without the need to connect more external cables, the computing device only needs to connect to one port to access all the memories on multiple CXL controllers, achieving the effect of doubling the memory capacity that can be accessed under a single interface.

[0109] In an embodiment of the present application, the data transmission method further includes: sending a scan instruction to the first CXL controller; the scan instruction is used to trigger the first CXL controller to determine the connection status between the first CXL controller and the second CXL controller.

[0110] In an embodiment of the present application, the computing device can send a scan instruction to the first CXL controller. In response to receiving the scan instruction, the first CXL controller determines the connection status between the first CXL controller and the second CXL controller.

[0111] Through the embodiment of the present application, multiple memories controlled by different CXL controllers can be uniformly arranged within the same board level. The computing device can access the memories under multiple CXL controllers through one interface. For example, the computing device is connected to a Compute Express Link (CXL) memory device through the interface. The computing device can know all the memories included in the CXL memory device on the computing device side. Further, the computing device can send an access request for accessing the memory to the CXL memory device. It can be assumed that the CXL memory device includes three CXL controllers, each CXL controller includes a memory, and the computing device is coupled to the first CXL controller. Then, the first CXL controller can determine a target transmission channel based on the access request and the routing configuration information, and perform gating, so that the computing device can access the target memory based on the target transmission channel.

[0112] Please refer to the following Figure 9 for a description of a data transmission method according to an embodiment of the present application. As Figure 9 shown, Figure 9 schematically shows a schematic diagram of another data transmission method according to an embodiment of the present application.

[0113] The application architecture of the embodiment of the present application may include a computing device, a first CXL controller, and a second CXL controller. The computing device can communicate with the first CXL controller based on the CXL protocol. The second CXL controller can communicate with the first CXL controller through a high-speed interconnect bus based on the CXL protocol.

[0114] As Figure 9 shown, after the computing device starts up, it can complete negotiation with the first CXL controller. After the first CXL controller and the second CXL controller are powered on, they can be initialized. Exemplarily, the channel determination module and the channel gating module in the first CXL controller complete the initialization settings.

[0115] The computing device can send a scan instruction to the first CXL controller. In response to receiving the scan instruction, the first CXL controller checks the connection status of the first CXL controller and the second CXL controller. Exemplarily, it can check the physical connection status, communication protocol status, signal status, etc. of the first CXL controller and the second CXL controller. When the connection status of the first CXL controller and the second CXL controller meets the conditions, such as all connections of the first CXL controller and the second CXL controller are ready, the first CXL controller can perform unified addressing on the first CXL controller and the second CXL controller.

[0116] In the embodiment of the present application, the first CXL controller can report the unified addressing information to the computing device. The computing device performs routing configuration according to the unified addressing information and distributes the routing configuration information to the first CXL controller. The first CXL controller can save the routing configuration information and send the routing configuration information to the second CXL controller. The second CXL controller can receive and save the routing configuration information for subsequent use. The first CXL controller can also return a routing configuration success message to the computing device to indicate that the first CXL controller has successfully saved the routing configuration information.

[0117] In the embodiment of the present application, the computing device can send an access request for the second CXL controller to the first CXL controller. Based on the access request, the first CXL controller can search for the routing configuration information and determine and select the target transmission channel.

[0118] In some embodiments, the first CXL controller can communicate with the second CXL controller. Furthermore, the first CXL controller and the second CXL controller can implement data access across CXL controllers based on the target transmission channel.

[0119] In the embodiment of the present application, the first CXL controller can also feedback the information of the target transmission channel to the computing device so that the computing device can perform read and write access to the second CXL controller based on the target transmission channel.

[0120] On the other hand, the embodiment of the present application provides a data transmission device, and the data transmission device includes: a channel determination module and a channel gating module.

[0121] The channel determination module is configured to send unified addressing information to the computing device; wherein, the unified addressing information is determined based on the address information of the first memory and the address information of the second memory; receive routing configuration information; the routing configuration information is determined by the computing device based on the unified addressing information; based on the routing configuration information, determine the target transmission channel; the target transmission channel includes a link between the first CXL controller and the second CXL controller; in response to an access request from the computing device, access to the second memory by the computing device is realized through the target transmission channel.

[0122] The channel gating module is configured to trigger the gating of the link between the first CXL controller and the second CXL controller based on the routing configuration information and the unified addressing information.

[0123] It can be understood that each CXL controller may include a channel determination module and a channel gating module. Exemplarily, the first CXL controller may include a first channel determination module and a first channel gating module. The second CXL controller may include a second channel determination module and a second channel gating module. The first CXL controller may be communicatively connected to the first computing device, and the second CXL controller may be communicatively connected to the first CXL controller. The first channel determination module may check the connection status between the first CXL controller and the second CXL controller and determine the unified addressing information. The first channel determination module may also save the routing configuration information and determine the target transmission channel. The first channel gating module may trigger the gating of the link between the first CXL controller and the second CXL controller based on the target transmission channel configuration information.

[0124] It can be understood that in the case where a second computing device accesses the first CXL controller via the second CXL controller, the second channel determination module and the second channel gating module may perform the gating of the target transmission channel with the first channel gating module in the above manner, so that the second computing device can access the first CXL controller via the second CXL controller through the target transmission channel.

[0125] Figure 10 Schematically shows another block diagram of a CXL memory device according to an embodiment of the present application. As Figure 10 shown, the CXL memory device may include a first CXL controller and a first memory. The first CXL controller may further include a channel determination module, a channel gating module, and a memory control module.

[0126] In the embodiment of the present application, the channel determination module may perform unified addressing, save the routing configuration information, and determine the target transmission channel based on the routing configuration information. The channel gating module may perform the gating of the transmission channel between CXL controllers.

[0127] It can be understood that the first CXL controller may further include a plurality of first memories, the CXL memory device may further include a plurality of CXL controllers, and each CXL controller may include a plurality of memories. The number and form of the memories are not limited herein.

[0128] As follows Figure 11 shown Figure 11 is a schematic diagram of another data transmission method in an embodiment of the present application.

[0129] For the description of the computing device, please refer to Figure 9 , which will not be elaborated here. In an embodiment of the present application, the channel determination module may determine a target transmission channel based on the routing configuration information, and send the relevant information of the target transmission channel to the channel gating module. The channel gating module may then perform gating of the target transmission channel based on the relevant information of the target transmission channel. Thus, the computing device may access other CXL memory devices based on the target transmission channel.

[0130] Next, a schematic diagram of a CXL memory board integrated with multiple storage devices in an embodiment of the present application will be described.

[0131] Please refer to Figure 12 , Figure 12 a schematic diagram of a CXL memory board according to an embodiment of the present application.

[0132] As Figure 12 shown, a first CXL controller and a second CXL controller are integrated on the CXL memory board. The first CXL controller and the second CXL controller each have two external ports, namely EP0 to EP3. The first CXL controller and the second CXL controller are connected by a high-speed interconnect bus. The first CXL controller and the second CXL controller are respectively connected to memories. It can be understood that the first CXL controller and its corresponding memory, and the second CXL controller and its corresponding memory together constitute a CXL memory device.

[0133] In the above manner, the first computing device can access all the memories on the CXL memory board through any one of the ports EP0 to EP3. By way of example, the first computing device can be connected to EP0 through port RP and send a scan instruction to the second CXL controller. Based on this scan instruction, the second CXL controller can check the connection status of the first CXL controller, the second CXL controller, and the corresponding memories, and perform unified addressing on the first CXL controller and the second CXL controller. Thereby, the unified addressing information is reported to the first computing device. The first computing device can determine the routing configuration information based on this unified addressing information and send the routing configuration information to the second CXL controller. The second CXL controller can receive and store the routing configuration information locally. The second CXL controller can also send the routing configuration information to the first CXL controller. The first CXL controller can receive and store the routing configuration information locally.

[0134] Furthermore, when the first computing device sends an access request to read the memory of the first CXL controller through EP0 to the second CXL controller, the second CXL controller can determine the target transmission channel based on this access request and the routing configuration information, and gate the target transmission channel. Thereby, the first computing device can access the memory of the first CXL controller through the second CXL controller.

[0135] In some embodiments, the computing devices connected to the CXL memory board can share the memory of the CXL memory board. For example, if the fourth computing device needs to access the memory under the second CXL controller, the fourth computing device can directly access the memory under the second CXL controller through the high-speed interconnection bus between the first CXL controller and the second CXL controller, without connecting the fourth computing device port and the second CXL controller port through an external cable, achieving the purpose of reducing overhead and improving efficiency.

[0136] In the embodiments of the present application, the two CXL controllers in the CXL memory board are interconnected, and the computing device only needs to access one port to realize the access to all the memories in the CXL memory board. Compared with the independent CXL controllers in the CXL memory board, the memory capacity accessed under one port can be doubled, thereby improving the ability to access memories across CXL controllers within the board and further expanding the expansion scale of the computing device's external CXL memory devices.

[0137] Figure 13 Schematic diagram of another CXL memory board according to an embodiment of the present application.

[0138] As Figure 13As shown in the figure, a first CXL controller, a second CXL controller, a third CXL controller, and a fourth CXL controller are integrated on the CXL memory board. Each of the first CXL controller, the second CXL controller, the third CXL controller, and the fourth CXL controller has two ports externally, namely EP0 to EP7. The first CXL controller, the second CXL controller, the third CXL controller, and the fourth CXL controller are connected to each other through a high-speed interconnect bus. The first CXL controller, the second CXL controller, the third CXL controller, and the fourth CXL controller are respectively connected to corresponding memories.

[0139] Referring to the above description of Figure 12 , the first computing device can access all the memories on the CXL memory board through any one of the ports EP0 to EP7. Thus, the expansion scale of the CXL memory device externally connected to the computing device can be further expanded.

[0140] In addition, in the embodiments of the present application, there can be multiple cascading methods between multiple CXL controllers. Exemplarily, as Figures 14 to 16 shown. Figure 14 Schematically shows a dual-node interconnection method according to an embodiment of the present application. Figure 15 Schematically shows a three-node interconnection method according to an embodiment of the present application. Figure 16 Schematically shows a four-node interconnection method according to an embodiment of the present application. It can be understood that the embodiments of the present application may also include other cascading methods, which are not limited herein.

[0141] As Figures 14 to 16 shown, multiple CXL controllers can be connected through a high-speed interconnect bus. Thus, the local CXL controller can be capable of accessing the memories under the remote CXL controller. In some embodiments, the isolation and gating of the transmission channels between CXL controllers can be performed through a channel gating module, thereby achieving efficient access to CXL memory across CXL controllers within the board level, and further improving the capacity and scale of CXL memory expansion of the server node.

[0142] Figure 17 Schematically shows a block diagram of a computing device according to an embodiment of the present application;

[0143] As Figure 17 shown, a computing device 1700 according to an embodiment of the present application includes a memory 1701 and a processor 1702; the memory 1701 and the processor 1702 are coupled; the memory 1701 is used to store computer program instructions; the processor 1702 is used to execute the program to implement the above data transmission method.

[0144] Figure 18Schematically shows a block diagram of a computing system according to an embodiment of the present application;

[0145] As Figure 18 shown, a computing system 1800 according to an embodiment of the present application includes a Compute Express Link (CXL) memory device 1801 and a computing device 1802; wherein, the CXL memory device 1801 is coupled to the computing device 1802.

[0146] In the embodiment of the present application, the CXL memory device is coupled to the computing device through a CXL switch device.

[0147] Above, a CXL memory device, a data transmission method, a computing device, and a system according to an embodiment of the present application have been described with reference to the accompanying drawings. In response to a scan instruction sent by the computing device, the first CXL controller uniformly addresses each CXL controller by determining the connection status of each CXL controller. Thus, the computing device can determine the routing configuration information based on the unified addressing information. When the computing device sends an access request, the first CXL controller can determine and select a target transmission channel between the first CXL controller and the target CXL controller based on the routing configuration information. The computing device can access the target memory through the target transmission channel. Thus, without increasing the external wiring of the computing device, cross-level access to multiple memories can be achieved, and thus the scale and capacity of the CXL memory externally connected to the computing device can be improved.

[0148] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. In addition, the specific details of the above application are only for the purposes of illustration and facilitation of understanding, and not for limitation. The above details do not limit the present application to necessarily adopt the above specific details for implementation.

[0149] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended words, meaning "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used herein refer to the word "and / or" and can be used interchangeably with each other unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with each other.

[0150] In addition, as used herein, "or" as used in a list of items beginning with "at least one" indicates a disjunctive list such that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Further, the phrase "exemplary" does not mean that the examples described are preferred or better than other examples.

[0151] It should also be noted that in the systems and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present application.

[0152] Various changes, substitutions, and alterations to the technologies described above can be made without departing from the teachings of the technology defined by the appended claims. In addition, the scope of the claims of the present application is not limited to the specific aspects of the processes, machines, manufactures, compositions of events, means, methods, and acts described above. Processes, machines, manufactures, compositions of events, means, methods, or acts that are currently available or to be developed later that perform substantially the same function or achieve substantially the same result as the corresponding aspects described above can be utilized. Accordingly, the appended claims include such processes, machines, manufactures, compositions of events, means, methods, or acts within their scope.

[0153] The foregoing description of the claimed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Thus, the present application is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

[0154] The foregoing description has been presented for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A computing fast link CXL memory device, characterized in that, The CXL memory device includes a first CXL controller, a second CXL controller, a first memory, and a second memory; the first CXL controller is coupled to the first memory; the second CXL controller is coupled to the second memory; the first CXL controller and the second CXL controller are coupled through a high-speed interconnect bus HSI; the first CXL controller is coupled to a computing device; The first CXL controller is configured to: Send unified addressing information to the computing device; wherein, the unified addressing information is determined based on the address information of the first memory and the address information of the second memory; Receive routing configuration information; the routing configuration information is determined by the computing device based on the unified addressing information; Based on the routing configuration information, determine a target transmission channel; the target transmission channel includes a link between the first CXL controller and the second CXL controller; In response to an access request from the computing device, access to the second memory by the computing device is realized through the target transmission channel.

2. The CXL memory device according to claim 1, wherein The first CXL controller is further configured to: In response to a scan instruction from the computing device, determine the connection state between the first CXL controller and the second CXL controller; When the connection state between the first CXL controller and the second CXL controller meets a first preset connection state, obtain the address information of the first memory and the address information of the second memory; Perform unified addressing on the address information of the first memory and the address information of the second memory.

3. The CXL memory device according to claim 1 or 2, characterized in that, The first CXL controller is configured to determine a target transmission channel based on the routing configuration information, including: Receive the access request; Based on the access request and the routing configuration information, determine the target transmission channel.

4. The CXL memory device according to any one of claims 1-3, characterized in that, The first CXL controller is further configured to: Based on the routing configuration information and the unified addressing information, trigger the gating of the link between the first CXL controller and the second CXL controller.

5. The CXL memory device according to any one of claims 1-4, characterized in that, The first CXL controller is configured to realize access to the second memory by the computing device through the target transmission channel, including: Receive the write data from the computing device; Write the write data into the second memory through the link between the first CXL controller and the second CXL controller; Or, Read data from the second memory through the link between the first CXL controller and the second CXL controller; Send the read data to the computing device.

6. A data transmission method, applied to a computing device, characterized in that, The computing device is coupled to the CXL memory device; the CXL memory device includes a first CXL controller, a second CXL controller, a first memory, and a second memory; the first CXL controller is coupled to the first memory; the second CXL controller is coupled to the second memory; the first CXL controller and the second CXL controller are coupled through a high-speed interconnect bus HSI; The method includes: Receive the unified addressing information sent by the first CXL controller; wherein, the unified addressing information is determined based on the address information of the first memory and the address information of the second memory; Determine routing configuration information based on the unified addressing information; Send the routing configuration information to the first CXL controller; the routing configuration information is used to determine a target transmission channel; the target transmission channel includes a link between the first CXL controller and the second CXL controller; Access the second memory through the target transmission channel.

7. The data transmission method according to claim 6, wherein The method further includes: Send a scan instruction to the first CXL controller; the scan instruction is used to trigger the first CXL controller to determine the connection status between the first CXL controller and the second CXL controller.

8. A computing device, characterized in that, The computing device includes a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program instructions; the processor is used to execute the program to implement the data transmission method according to claim 6 or 7.

9. A computing system, characterized in that, The computing system includes the computing express link CXL memory device according to any one of claims 1-5 and the computing device according to claim 8; Wherein, the CXL memory device is coupled to the computing device.

10. The computing system according to claim 9, wherein The CXL memory device is coupled to the computing device through a CXL switching device.

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