Method, medium, device and product for data transmission

Abstract

The invention discloses a method for data transmission, a medium, equipment and a product, and relates to the technical field of nonvolatile memory host controller interfaces, and the method comprises the following steps: under the condition that a plurality of DMA engines are started, according to different priorities and descriptor acquisition times, determining an acquisition sequence of a plurality of DMA descriptors and a descriptor corresponding to a DMA engine of a first priority, according to the method, descriptors corresponding to DMA engines of other priorities are obtained before the descriptors corresponding to DMA engines of other priorities are obtained, when the number of times that the descriptors corresponding to DMA engines of the second priority are obtained exceeds the preset first number of times, the DMA engines of the second priority will be temporarily skipped, and descriptors corresponding to DMA engines of the third priority will be obtained; and executing actual data transmission according to the descriptor sequence determined according to the acquisition sequence, so that the problem that the data transmission delay is possibly increased when the DMA descriptors are acquired in a polling manner is solved, and the effect that the transmission of key data is completed preferentially is achieved.

Description

Technical Field

[0001] This application relates to the technical field of non-volatile memory host controller interfaces, and particularly to methods, media, devices, and products for data transmission. Background Art

[0002] In modern computer systems, an NVMe controller is used to manage data transmission between non-volatile storage devices and a host system. Among them, the DMA technology plays a very important role in the data interaction process between non-volatile storage devices and the host system. To improve data transmission efficiency, an NVMe controller may embed one or more DMA engines.

[0003] In related technologies, generally, a polling method is adopted to obtain DMA descriptors. In this way, in the case of multiple DMA requests, even if some tasks have high priorities, they still need to wait for processing in the polling order, which may lead to an increase in data transmission latency. Summary of the Invention

[0004] This application provides methods, media, devices, and products for data transmission to at least solve the problem in related technologies that when using the polling method to obtain DMA descriptors, in the case of multiple DMA requests, even if some tasks have high priorities, they still need to wait for processing in the polling order, which may lead to an increase in data transmission latency.

[0005] This application provides a method for data transmission, including: when enabling multiple direct memory access engines based on a transmission instruction, determining an acquisition order for obtaining direct memory access descriptors based on the priorities of the direct memory access engines; among them, the descriptor corresponding to the direct memory access engine configured with the first priority is acquired before the descriptors corresponding to the direct memory access engines configured with other priorities. If there is no descriptor corresponding to the direct memory access engine with the first priority, acquire the descriptor corresponding to the direct memory access engine with the second priority. If the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number, acquire the descriptor corresponding to the direct memory access engine with the third priority; perform data transmission based on the acquisition order.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for data transmission when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, where the computer program implements the steps of any of the above methods for data transmission when executed by a processor.

[0008] The present application also provides a computer program product, including a computer program, which when executed by a processor, implements the steps of any one of the above methods for data transmission.

[0009] Through the present application, in the case of enabling multiple DMA engines, the acquisition order of multiple DMA descriptors is determined according to different priorities and the number of descriptor acquisitions. The descriptor corresponding to the DMA engine with the first priority is acquired before the descriptors corresponding to other priority DMA engines. When the number of acquisitions of the descriptor corresponding to the DMA engine with the second priority exceeds a preset first number, the DMA engine with the second priority will be temporarily skipped, and the descriptor corresponding to the DMA engine with the third priority will be acquired, and the actual data transmission is performed according to the descriptor sequence determined by the above acquisition order; Therefore, it is possible to solve the problem in the related art that when polling is used to acquire DMA descriptors, in the case of multiple DMA requests, even if some tasks have high priority, they need to wait for processing according to the polling order, which may lead to an increase in data transmission delay, achieving the effect of parallel operation of multiple DMA engines, making full use of hardware resources, and ensuring the priority completion of the transmission of key data based on the priority mechanism; At the same time, it is also possible to balance the resource allocation between tasks with different priorities. By setting the first number, it is possible to prevent low-priority tasks from not being executed for a long time; In addition, high-priority tasks can be quickly responded to, which is suitable for application scenarios sensitive to latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 Shows a schematic diagram of the application environment architecture of the method for data transmission provided by the present application; Figure 2 Shows a schematic flowchart of the method for data transmission provided by the present application; Figure 3 Shows a schematic flowchart of the order for acquiring direct memory access descriptors; Figure 4 Shows a schematic flowchart of the DMA engine in an embodiment of the present application for processing the first instruction; Figure 5 Shows a schematic structural diagram of the device for data transmission in an embodiment of the present application; Figure 6 Shows a schematic structural diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0013] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] The concepts involved in the present application are introduced below. The Non-Volatile Memory Host Controller Interface Specification (Non-Volatile Memory Express, abbreviated as NVMe) is a technical standard for managing data transfer between non-volatile storage devices such as solid-state drives and host systems. NVMe defines a set of instruction sets and interface specifications, which can significantly improve data transfer speed and efficiency and reduce latency compared with traditional storage interfaces. In modern computer systems, the NVMe controller is responsible for coordinating the interaction between non-volatile storage devices and host systems according to this standard and is a key component for realizing efficient data storage and reading.

[0015] The Central Processing Unit (CPU), the core component of a computer, is also known as the brain of the computer. The CPU is responsible for executing instructions in computer programs, performing various data operations and logical judgments. In the process of data transfer, traditional data transfer methods require the CPU to frequently participate in operations such as reading data from storage devices and then transferring it to memory, which will consume a large amount of CPU resources and affect the efficiency of the CPU in processing other tasks. The emergence of technologies such as direct memory access is to reduce the burden of the CPU in data transfer and enable the CPU to focus more on complex operations and logical processing work.

[0016] Direct Memory Access (DMA) is a technology that allows external devices (such as hard disks or network cards) to directly exchange data with the system memory. A DMA controller is a unique peripheral that transfers data within the system and can be regarded as a controller that can connect internal and external memories and each DMA-capable peripheral through a set of dedicated buses.

[0017] In this way, during the data interaction process, without the frequent intervention of the CPU, the DMA controller can autonomously transfer data directly to the memory or read data from the memory, which can reduce the CPU overhead and significantly improve the data transfer efficiency of NVMe devices.

[0018] To improve the data transfer efficiency, an NVMe controller may embed one or more DMA engines. According to the instructions issued by the host, the firmware can configure the DMA engine descriptor address through registers, and prepare the DMA engine descriptor or a linked list composed of DMA engine descriptors in advance and place them in the local memory. The DMA engine first obtains the DMA engine descriptor, and then, according to the information described in the DMA engine descriptor, performs data transfer.

[0019] For an NVMe controller architecture involving multiple DMA engines, multiple DMA engines can access common resources. For example, it is the cache for the interaction between the NVMe controller and the host, or the cache for the interaction between the NVMe controller and the local memory. When enabling the NVMe controller architecture involving multiple DMA engines, arbitration is usually required. Common arbitration methods include round-robin arbitration and weighted round-robin arbitration, etc., and the priority can be configured through the firmware. Each DMA engine can execute the tasks issued by the host based on the priority order and the DMA engine descriptor instructions.

[0020] However, in the related technology, the following problems existing in the DMA data transfer mechanism in the NVMe controller may affect the overall performance of data transfer and the immediacy of data processing.

[0021] First, in the related technology, the polling method is generally used to obtain the DMA descriptor. In this way, in the case of multiple DMA requests, even if some tasks have high priorities, they need to wait for processing in the polling order, which may lead to an increase in data transfer latency. Especially in the case of busy bus tasks or bus task jams, it will affect the data transfer efficiency to a greater extent.

[0022] Second, when the NVMe controller processes a large number of host commands, after the firmware parses the host commands, it will configure the DMA descriptor linked list according to the commands and place the configured DMA descriptor linked list in the local memory. The processing of specific commands, especially read and write commands, generally takes a long time, and there are multiple commands waiting in line to be allocated to the DMA engine for processing. At the same time, in the case of emergency commands, the DMA engine needs to wait until the current DMA descriptor linked list is executed before it can process the emergency commands, resulting in a low response speed of the NVMe controller to emergency commands and affecting the real-time performance and reliability of the system.

[0023] Third, the NVMe controller can execute reading the commands / data sent by the host, or reading the local DMA descriptors / data, or writing local data / descriptors, etc. through the host interaction common port or the local interaction common port. After the reading is completed, it returns the data / completion information, etc. When arbitrating multiple requests, the aforementioned common port will adopt a polling method so that all transmission requests are treated equally. However, in actual applications, different tasks may have different importance and timeliness requirements, and the simple polling method cannot meet the diverse needs. In addition, although the data / metadata and their pointers are output or read from the same port, they are divided into two ports when the common port makes a request. The arbitration mechanism in the related technology does not fully consider this structural feature, which may lead to unbalanced data transmission and low efficiency.

[0024] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Figure 1 The application environment architecture diagram of the method for data transmission provided by the present application is shown. As Figure 1 shown, the specific application environment architecture or specific hardware architecture on which the execution of the method for data transmission provided by the present application depends includes: a central processing unit 10 and a non-volatile memory host controller interface specification (Non-Volatile Memory Express, abbreviated as NVMe) controller 11 that interacts with the central processing unit 10. Figure 1 The bidirectional arrows in represent that there are two data transmission paths. For example, the bidirectional arrow between the central processing unit 10 and the NVMe controller 11 represents that there is a data transmission path from the central processing unit 10 to the NVMe controller 11 and a data transmission path from the NVMe controller 11 to the central processing unit 10.

[0026] Among them, the NVMe controller 11 includes a High-speed Advanced eXtensible Interface protocol (AXI H) read interface 1101 for interacting with a host, an AXI H write interface 1102 for interacting with the host, a Memory-Mapped Advanced eXtensible Interface protocol (AXI M) write interface 1103 for interacting with local memory, and an AXI M read interface 1104 for interacting with local memory.

[0027] The NVMe controller 11 performs data interaction with the first bus 14 based on the AXI H read interface 1101 and the AXI H write interface 1102 respectively. The NVMe controller 11 also performs data interaction with the second bus 15 based on the AXI M write interface 1103 and the AXI M read interface 1104.

[0028] The first bus 14 side includes a peripheral component interconnect express (PCIe) 13 and a host 12. The second bus 15 side includes a Double Data Rate SDRAM (DDR) 16.

[0029] The NVMe controller 11 further includes multiple embedded direct memory access engines, such as a first Direct Memory Access (DMA) engine 1105, a second DMA engine 1106, and a third DMA engine 1107. The NVMe controller 11 also includes a submission queue management 1108 and a completion queue management 1109. The submission queue management 1108 is connected to the AXI H read interface 1101 and the AXI H write interface 1102, and the completion queue management 1109 is connected to the AXI H read interface 1101. It should be noted that in order to reduce Figure 1 the cross lines in Figure 1 the connection line between the submission queue management 1108 and the AXI H write interface 1102 is not indexed.

[0030] The NVMe controller 11 further includes a Direct Memory Access (DMA) descriptor acquisition module 1110. The DMA descriptor acquisition module 1110 includes a first direct memory access engine enabling unit 1111, a second direct memory access engine enabling unit 1112, and a third direct memory access engine enabling unit 1113. The DMA descriptor acquisition module 1110 transmits the acquired DMA descriptors to the corresponding DMA engines. The DMA descriptor acquisition module 1110 is respectively connected to a first DMA engine 1105, a second DMA engine 1106, and a third DMA engine 1107.

[0031] Each DMA engine also performs data transmission with an AXI H read interface 1101, an AXI H write interface 1102, an AXI M write interface 1103, and an AXI M read interface 1104. For example, the first DMA engine 1105 performs data transmission with the AXI H read interface 1101, the AXI H write interface 1102, the AXI M write interface 1103, and the AXI M read interface 1104. It should be noted that, in order to reduce Figure 1 the cross lines in Figure 1 the connection lines between the second DMA engine 1106 and the AXI H read interface 1101, the AXI H write interface 1102, the AXI M write interface 1103, and the AXI M read interface 1104 are not indexed. Similarly, the connection lines between the third DMA engine 1107 and the AXI H read interface 1101, the AXI H write interface 1102, the AXI M write interface 1103, and the AXI M read interface 1104 are not indexed either.

[0032] An embodiment of the present application provides a method for data transmission. Figure 2 The flowchart of the method for data transmission provided by the present application is shown. As Figure 2 shown, the method for data transmission includes: Step S201, when multiple direct memory access engines are enabled based on a transmission instruction, determine the acquisition order of obtaining direct memory access descriptors based on the priorities of the respective direct memory access engines; wherein, the descriptor corresponding to the direct memory access engine configured with the first priority is acquired prior to the descriptors corresponding to the direct memory access engines configured with other priorities. If there is no descriptor corresponding to the direct memory access engine with the first priority, acquire the descriptor corresponding to the direct memory access engine with the second priority. If the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number, acquire the descriptor corresponding to the direct memory access engine with the third priority.

[0033] In this step, the NVMe controller embeds multiple DMA engines, and the NVMe controller processes data transfer commands and other commands sent by the host. The processing flow of the NVMe controller includes that the NVMe controller passes the commands sent by the host to the firmware through the interface for interacting with the firmware. After the firmware parses the commands, it combines the DMA descriptors obtained based on the command parsing to form a linked list of DMA descriptors, and stores the linked list of DMA descriptors in a specific area of the local memory.

[0034] The firmware configures the corresponding DMA engine control register to enable the DMA engine. On the hardware side, after perceiving that the DMA is enabled, it reads the descriptors according to the previously configured DMA descriptor addresses and executes the corresponding commands. It should be noted that during the initialization of the NVMe controller, the firmware will inform the NVMe controller of the address of the DMA descriptor (or linked list) by configuring the DMA descriptor address register.

[0035] A transfer instruction is used to represent a data transfer command that needs to directly access the host memory. The acquisition order of obtaining the DMA descriptor is determined by the priority of the configured DMA engine. If the DMA engine with the highest priority is enabled, the descriptor corresponding to the DMA engine with the highest priority is preferentially obtained; if there is no DMA engine with the highest priority enabled, or all the descriptors corresponding to the DMA engine with the highest priority have been executed, the descriptor corresponding to the DMA engine with the second highest priority is obtained.

[0036] If there is no DMA engine with the second highest priority enabled, or the number of times of obtaining the descriptor corresponding to the DMA engine with the second highest priority is greater than the preset first number, the descriptor corresponding to the direct memory access engine with the third highest priority is obtained.

[0037] Step S202: Perform data transfer based on the acquisition order.

[0038] In this step, if the DMA engine with the highest priority is enabled, the descriptor corresponding to the DMA engine with the highest priority is preferentially obtained, and data transfer is performed based on the descriptor corresponding to the DMA engine with the highest priority.

[0039] If there is no DMA engine with the highest priority enabled, or all the descriptors corresponding to the DMA engine with the highest priority have been executed, the descriptor corresponding to the DMA engine with the second highest priority is obtained, and data transfer is performed based on the descriptor corresponding to the DMA engine with the second highest priority.

[0040] If there is no second-priority DMA engine enabled, or the number of times of obtaining the descriptor corresponding to the second-priority DMA engine is greater than the preset first number, obtain the descriptor corresponding to the third-priority direct memory access engine, and perform data transmission based on the descriptor corresponding to the third-priority direct memory access engine.

[0041] Through this application, since when at least one DMA engine is enabled, priorities are assigned to each DMA engine, and the acquisition order of multiple DMA descriptors is determined according to different priorities and the number of descriptor acquisitions. When the number of times of obtaining the descriptor corresponding to the second-priority DMA engine exceeds the preset first number, the second-priority DMA engine will be temporarily skipped, and the descriptor corresponding to the third-priority DMA engine will be obtained, and the actual data transmission will be performed according to the descriptor sequence determined by the above acquisition order. Therefore, it is possible to solve the problem in the related art that when polling is used to obtain DMA descriptors, in the case of multiple DMA requests, even if some tasks have high priorities, they still need to wait for processing in the polling order, which may lead to an increase in data transmission delay, achieving the effect of parallel operation of multiple DMA engines, making full use of hardware resources, and ensuring the priority completion of key data transmission based on the priority mechanism. At the same time, it is also possible to balance the resource allocation between tasks with different priorities. By setting the preset first number, it is possible to prevent low-priority tasks from not being executed for a long time. In addition, high-priority tasks can be quickly responded to, which is suitable for application scenarios sensitive to latency.

[0042] In some alternative embodiments, the foregoing method for data transmission further includes: configuring priorities, and the acquisition order corresponding to each priority; configuring the priorities to include a first priority, a second priority, and a third priority, wherein the descriptor corresponding to the direct memory access engine with the first priority is obtained before the descriptors corresponding to the direct memory access engines with other priorities.

[0043] In this embodiment, the priorities of each DMA engine can be configured based on registers. Through the priority configuration of the DMA engine, when multiple DMA engines are working simultaneously, arbitration is performed based on the DMA engine priorities before obtaining common resources. Here, the common resources can be the cache for the NVMe controller to interact with the host, or the cache for the NVMe controller to interact with the local memory, etc.

[0044] Specifically, a DMA descriptor control register can be added. Based on the DMA descriptor control register, the priorities of each DMA engine can be configured. The attributes of the DMA descriptor control register are readable and writable. A two-bit first field [1:0] can be used to represent the priority of the DMA engine. In the embodiments of the present application, a two-bit first field is used to exemplarily illustrate the method for data transmission in the embodiments of the present application. [1:0] is used to represent bit0 and bit1 in the first field. The first field can be configured as 00b, 01b, 10b, or 11b, where b represents binary.

[0045] If the first field corresponding to the target DMA engine is configured as 11b, the target DMA engine is the DMA engine with the first priority, indicating the Urgent priority. If the first field corresponding to the target DMA engine is configured as 10b, the target DMA engine is the DMA engine with the second priority, indicating the High priority. If the first field corresponding to the target DMA engine is configured as 01b, the target DMA engine is the DMA engine with the third priority, indicating the Medium priority. If the first field corresponding to the target DMA engine is configured as 00b, the target DMA engine is the DMA engine with the fourth priority, indicating the Low priority.

[0046] Among them, the first priority is higher than the second priority, the second priority is higher than the third priority, and the third priority is higher than the fourth priority. That is, the first priority is the highest priority in the current priority mechanism.

[0047] A priority status signal can be added. The priority status signal includes the first priority status (urgent_state), the second priority status (high_state), the third priority status (medium_state), and the fourth priority status (low_state). The bit width of the priority status signal is equal to the number of engines of the DMA embedded in the NVMe controller, and the reset value is zero. The priorities of each DMA engine can be represented based on the priority status signal. For example, if the priority of DMA0 is configured as 11b, that is, the first (urgent) priority, the bit corresponding to the first priority status (urgent_state) of DMA0 is set high. If the priorities of DMA1, DMA2, and DMA3 are configured as non-11b, the first priority status urgent_state signals corresponding to DMA3, DMA2, DMA1, and DMA0 are 0001b.

[0048] Similarly, if the priority of DMA1 is configured as 10b, i.e., the second (high) priority, and the priorities of DMA0, DMA2, and DMA3 are configured as non-10b, the second priority status high_state signals corresponding to DMA3, DMA2, DMA1, and DMA0 are 0010b. The firmware configures the DMA descriptor priority to be consistent with the priority of the DMA engine. Based on the DMA descriptor acquisition module, the DMA descriptors are acquired from high to low according to the priority.

[0049] In this way, compared with the polling method in the related art, by allocating the first priority to the high-priority DMA engine, it can be ensured that critical tasks always acquire descriptors first, which can meet the low-latency requirements of hard real-time systems. At the same time, different tasks can be configured with different priorities, which can achieve fine-grained control of task execution. In addition, acquiring descriptors strictly in the order of priority can eliminate conflicts caused by multiple DMA engines accessing the descriptor list simultaneously.

[0050] In some alternative embodiments, the foregoing method for data transmission further includes: configuring the preset weights of the direct memory access engines with each target priority, and the direct memory access engines with each target acquisition priority include the direct memory access engines with the second priority and the third priority; based on the preset weights, it is characterized that after acquiring the descriptors corresponding to the direct memory access engines with the target priority for a preset number of times, the descriptors corresponding to the direct memory access engines with the next priority of the target priority are acquired.

[0051] In this embodiment, the preset weights of the DMA engines with each target priority can be configured based on registers. A DMA weight register can be added, and based on the DMA weight register, the preset weights of the DMA engines with each target priority are configured. Since the DMA descriptors with the first priority are always acquired before the DMA descriptors with other priorities, the DMA engines with the target priority in this embodiment do not include the DMA engines with the first priority.

[0052] Specifically, the preset weight of the fourth priority, i.e., the preset third number of times, can be represented by the [9:0] bits in the second field, the preset weight of the third priority, i.e., the preset second number of times, can be represented by the [19:10] bits in the second field, and the preset weight of the second priority, i.e., the preset first number of times, can be represented by the [29:20] bits in the second field. Independent counters can be configured for each priority, and the counters start counting from zero. When a DMA descriptor command with the target priority is executed, the target priority counter performs an increment operation. If the count value of the target priority counter is equal to the preset weight of the target priority minus one, the count value of the target priority counter is reset to zero. The [31:30] bits in the second field are reserved.

[0053] In this way, precise bandwidth control of non-critical tasks can be achieved by configuring weights for DMA engines with priorities other than the first priority. At the same time, by forcing the requests of the next priority of the target priority to be processed after a preset number of acquisitions represented by the preset weight, complete blocking of low-priority tasks can be avoided.

[0054] In some alternative embodiments, based on the priorities of the respective direct memory access engines, the order of obtaining direct memory access descriptors is determined, and based on this order, data transfer includes: determining whether there is a direct memory access engine with the first priority among the enabled direct memory access engines; if there is a direct memory access engine with the first priority, obtaining the descriptor of the direct memory access engine with the first priority, and performing data transfer based on the descriptor of the direct memory access engine with the first priority.

[0055] In this embodiment, the enabling condition of the priority status signal is continuously monitored. If the DMA engine with the first priority is enabled, the descriptor corresponding to the DMA engine with the first priority is selected. An interface for configuring the priority and weight values of the DMA descriptors can be provided in the firmware. During system startup or operation, based on actual requirements, through this interface, the priorities and weight values for obtaining each DMA descriptor can be flexibly configured to ensure that the hardware can perform arbitration according to the set rules.

[0056] In this way, the acquisition delay of the DMA descriptor with the first priority is low, which can meet the requirements of industrial real-time performance. When the bus tasks are busy, the DMA tasks with the first priority can be processed preferentially, reducing data transfer delay.

[0057] In some alternative embodiments, based on the priorities of the respective direct memory access engines, the order of obtaining direct memory access descriptors is determined, and based on this order, data transfer further includes: determining whether there is a direct memory access engine with the first priority among the enabled direct memory access engines; if there is no direct memory access engine with the first priority, determining whether there is a direct memory access engine with the second priority among the enabled direct memory access engines; if there is a direct memory access engine with the second priority, determining whether the number of times of obtaining the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number; if the number of times of obtaining the descriptor corresponding to the direct memory access engine with the second priority is less than or equal to the preset first number, obtaining the descriptor corresponding to the direct memory access engine with the target number in the direct memory access engine with the second priority, performing data transfer based on the descriptor corresponding to the direct memory access engine with the target number, and incrementing the number of times of obtaining the descriptor corresponding to the direct memory access engine with the second priority by one.

[0058] Figure 3 A flowchart showing the order of obtaining direct memory access descriptors is presented. As Figure 3 shown, in this embodiment, the process of obtaining the order of DMA descriptors includes: Step S301, determine whether any direct memory access engine is enabled. If not, go to step S301. If there is an enabled DMA engine, go to step S302.

[0059] Step S302, determine whether weighted round-robin arbitration is performed. If not, go to step S303. If so, go to step S304. Specifically, weighted round-robin arbitration is to determine the acquisition order of obtaining direct memory access descriptors based on the priorities of each direct memory access engine.

[0060] Step S303, determine the acquisition order of obtaining direct memory access descriptors in a round-robin manner.

[0061] Step S304, determine whether there is a direct memory access engine with the first priority among the enabled direct memory access engines. If so, go to step S305. If not, go to step S306.

[0062] Step S305, perform round-robin arbitration on the direct memory access engine with the first priority, determine the direct memory access engine with the first priority of the target number, and go to step S304.

[0063] Specifically, if there is only one direct memory access engine with the first priority, select the direct memory access engine with the first priority, and based on the direct memory access descriptor acquisition module, obtain the descriptor corresponding to the direct memory access engine with the first priority. If there are multiple direct memory access engines with the first priority, perform round-robin on the multiple direct memory access engines with the first priority. Among the multiple direct memory access engines with the first priority, determine the direct memory access engine with the first priority of the target number, obtain the descriptor corresponding to the direct memory access engine with the first priority of the target number, and point the pointer to the next numbered direct memory access engine with the first priority. Among them, the target number is used to represent the direct memory access engine with the smallest number or the largest number among multiple direct memory access engines.

[0064] Step S306, determine whether there is a direct memory access engine with the second priority among the enabled direct memory access engines. If there is, go to step S307. If not, go to step S308.

[0065] Step S307: Determine whether the number of times of obtaining the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number. If so, proceed to step S308; if not, proceed to step S309.

[0066] Step S308: Determine whether there is a direct memory access engine with the third priority among the enabled direct memory access engines. If so, proceed to step S310; if not, proceed to step S311.

[0067] Step S309: Poll and arbitrate the direct memory access engines with the second priority to determine the direct memory access engine with the second priority of the target number, and then proceed to step S304.

[0068] Specifically, if there is only one direct memory access engine with the second priority, select this direct memory access engine with the second priority, and based on the direct memory access descriptor acquisition module, obtain the descriptor corresponding to this direct memory access engine with the second priority. If there are multiple direct memory access engines with the second priority, poll the multiple direct memory access engines with the second priority, determine the direct memory access engine with the second priority of the target number among the multiple direct memory access engines with the second priority, obtain the descriptor corresponding to the direct memory access engine with the second priority of the target number, and increment the number of times of obtaining the descriptor corresponding to the direct memory access engine with the second priority by one.

[0069] Step S310: Determine whether the number of times of obtaining the descriptor corresponding to the direct memory access engine with the third priority is greater than a preset second number. If so, proceed to step S311; if not, proceed to step S312.

[0070] Step S311: Determine whether there is a direct memory access engine with the fourth priority among the enabled direct memory access engines. If so, proceed to step S313; if not, proceed to step S304.

[0071] Step S312: Poll and arbitrate the direct memory access engines with the third priority to determine the direct memory access engine with the third priority of the target number, and then proceed to step S304.

[0072] Specifically, if there is only one direct memory access (DMA) engine with the third priority, select this DMA engine with the third priority, and based on the DMA descriptor acquisition module, acquire the descriptor corresponding to this DMA engine with the third priority. If there are multiple DMA engines with the third priority, poll the multiple DMA engines with the third priority, determine the DMA engine with the third priority of the target number among the multiple DMA engines with the third priority, acquire the descriptor corresponding to the DMA engine with the third priority of the target number, and increment the number of times of acquiring the descriptor corresponding to the DMA engine with the third priority by one.

[0073] Step S313: Determine whether the number of times of acquiring the descriptor corresponding to the DMA engine with the fourth priority is greater than the preset third number. If so, proceed to step S304; if not, proceed to step S314.

[0074] Step S314: Poll and arbitrate the DMA engines with the fourth priority to determine the DMA engine with the fourth priority of the target number, and then proceed to step S304.

[0075] Specifically, if there is only one DMA engine with the fourth priority, select this DMA engine with the fourth priority, and based on the DMA descriptor acquisition module, acquire the descriptor corresponding to this DMA engine with the fourth priority. If there are multiple DMA engines with the fourth priority, poll the multiple DMA engines with the fourth priority, determine the DMA engine with the fourth priority of the target number among the multiple DMA engines with the fourth priority, acquire the descriptor corresponding to the DMA engine with the fourth priority of the target number, and increment the number of times of acquiring the descriptor corresponding to the DMA engine with the fourth priority by one.

[0076] Among them, if there are multiple descriptors for each DMA with the same priority, poll and select them in ascending or descending order of the number one by one, and then select the remaining DMA descriptors.

[0077] In this way, by adopting the multi-level priority mechanism, it is ensured that tasks with higher priorities can always preempt the bandwidth, which can reduce the latency of high-priority tasks. Through the preset weights, dynamic fairness control is performed. When the second priority continuously acquires descriptors exceeding the preset first number, the bus is forcibly released to the third priority to ensure system-level fairness.

[0078] In some alternative embodiments, the foregoing method for data transmission further includes: obtaining a first instruction, and configuring a first descriptor corresponding to a target direct memory access (DMA) engine based on the first instruction, where the first instruction is executed prior to the transmission instruction; determining whether there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed in the target direct memory access engine; if there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed, determining whether the descriptor corresponding to the direct memory access engine that is being executed is the last descriptor in the transmission instruction; if it is the last descriptor in the transmission instruction, or if there is no transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed, obtaining the first descriptor corresponding to the target direct memory access engine and performing data transmission.

[0079] In this embodiment, based on the first instruction representing an emergency command, such as an emergency termination or a firmware submission command, etc. An emergency command control (emergency_cmd_ctrl) register, a first descriptor address register, and a first instruction processing logic can be added on the hardware side. The firmware receives multiple first instructions representing emergency commands, configures a first descriptor (E-DMA) corresponding to the DMA engine for each first instruction to obtain a first descriptor linked list, and can place the first descriptor linked list at the first descriptor address. The firmware maintains the first descriptor (E-DMA) linked list.

[0080] In the emergency command control register, when bit [0] is set high, it represents that the current is the first instruction processing stage, and bits [31:1] represent the number of first instructions to be processed. The number of emergency command control registers is the same as the number of DMA engines.

[0081] The first descriptor address register is used to represent the address where the first instruction descriptor is placed, and can be configured during the initialization of the NVMe controller. The number of first descriptor address registers is the same as the number of DMA engines.

[0082] The first instruction processing logic includes a first signal, a second signal, a third signal, and a fourth signal. Among them, the first signal (emergency_cmd_flag) is used to represent whether there is a first instruction to be processed currently, the second signal (emergency_cmd_cnt) is used to represent the number of first instructions being processed currently, the third signal (dma_desc_pending_addr) is used to save the address of the descriptor to be executed in the interrupted DMA linked list, and the fourth signal (dma_desc_pending_flag) is used to represent that there is a DMA command to be processed.

[0083] Figure 4 The flowchart showing the process of the DMA engine in the embodiment of the present application for processing the first instruction is asFigure 4 As shown in Figure 4 , the process of the DMA engine processing the first instruction includes: Step S401, the firmware receives multiple first instructions characterizing emergency commands.

[0084] Step S402, select the target direct memory access engine to process the first instruction.

[0085] Step S403, configure the first descriptor list and place the first descriptor list at the address of the first descriptor list corresponding to the target direct memory access engine.

[0086] Step S404, configure bit zero of the emergency command control register to one, configure bits one to thirty-one of the emergency command control register to represent the number of emergency commands in step S401, and enable the target direct memory access engine.

[0087] Step S405, configure the first signal of the target direct memory access engine to the enabled state.

[0088] Specifically, when the hardware senses that bit [0] of the emergency command control register (emergency_cmd_ctrl) is set high, raise the first signal (emergency_cmd_flag).

[0089] Step S406, determine whether there is a transfer instruction being executed in the target direct memory access engine. If so, go to step S407; if not, go to step S408.

[0090] Step S407, wait for the transfer instruction being executed to complete, and go to step S409.

[0091] Step S408, point the pointer for obtaining the descriptor address to the first descriptor address, and go to step S411.

[0092] Step S409, determine whether the end field of the transfer instruction being executed is zero. If so, go to step S410; if not, go to step S408.

[0093] Specifically, if there is a command in the configured DMA descriptor list being executed in the target DMA engine, determine whether the end field (end of chain, abbreviated as EOC) in the descriptor corresponding to the target DMA engine is zero. Among them, the EOC field in each DMA descriptor in the list indicates whether the descriptor is the last descriptor in the DMA descriptor list. If it is zero, that is, the transfer instruction being executed is not the last command in the configured DMA descriptor list; if it is one, that is, the transfer instruction being executed is the last command in the configured DMA descriptor list.

[0094] Step S410: Store the address of the next direct memory access descriptor in the direct memory access descriptor linked list into the third signal register, and then transfer to step S408.

[0095] Specifically, the target DMA engine pauses the commands in the configured DMA descriptor linked list being executed, stores the address of the next direct memory access descriptor in the direct memory access descriptor linked list into the dma_desc_pending_addr register, and raises the dma_desc_pending_flag signal.

[0096] Step S411: Execute the first instruction, and then transfer to step S412.

[0097] Specifically, the target DMA engine preferentially obtains the descriptors in the E-DMA linked list, executes the emergency task represented by the first instruction. After each execution, the emergency_cmd_cnt is incremented by 1 until it reaches the value of the [31:1] field indicated by the emergency_cmd_ctrl register minus 1, indicating that all emergency tasks are completed.

[0098] Step S412: After the execution of the first instruction ends, continue to execute the transfer instruction indicated by the previously interrupted descriptor linked list.

[0099] Specifically, obtain the descriptor from the address indicated by the dma_desc_pending_addr register, continue to process the commands in the previously interrupted descriptor linked list, and at the same time lower the dma_desc_pending_flag signal.

[0100] In this way, by designing a dedicated emergency command processing mechanism, adding an emergency command control register, an E-DMA descriptor address register, and corresponding processing logics, it is ensured that when an emergency command arrives, the current task can be quickly paused, the emergency command can be preferentially processed, and the original task can be seamlessly resumed after the processing is completed, greatly enhancing the system's response ability and real-time performance to emergency commands.

[0101] In some alternative embodiments, configuring the first descriptor corresponding to the target direct memory access engine includes any of the following methods: If there are multiple priorities in the direct memory access engine, determine the direct memory access engine with the highest priority as the target direct memory access engine, and allocate the first descriptor to the direct memory access engine with the highest priority; If each direct memory access engine has the same priority, determine any one direct memory access engine as the target direct memory access engine, and allocate the first descriptor to the target direct memory access engine.

[0102] In this embodiment, when an emergency command is allocated, if multiple DMA engines have different priorities, the emergency task can be preferentially allocated to the DMA engine with the highest priority, and the DMA engine with the highest priority is used as the target DMA engine. If all DMA engines have the same priority, a DMA engine can be randomly selected to execute the emergency task. For example, DMA0 is selected as the target DMA engine to execute the emergency task.

[0103] In this way, through reasonable scheduling of the DMA engine, waste of hardware resources can be reduced, and the flexibility in processing the emergency task represented by the first instruction can be improved.

[0104] In some alternative embodiments, configuring the first descriptor corresponding to the target direct memory access engine further includes: if there is a dynamic direct memory access engine in the direct memory access engines, determining the dynamic direct memory access engine as the target direct memory access engine, and when there is a first instruction, allocating the first descriptor to the dynamic direct memory access engine; if there is no first instruction, enabling the dynamic direct memory access engine based on the transfer instruction.

[0105] In this embodiment, the DMA engines embedded in the NVMe controller are divided into a normal DMA engine (N-DMA) and a dynamic DMA engine (D-DMA). The D-DMA is used to process normal transfer instructions and the first instruction. In the absence of the first instruction, it is used as the N-DMA, and in the presence of the first instruction, it preferentially processes the first instruction. The dynamic DMA engine can be identified by a preset bit in the hardware status register.

[0106] In this way, the normal descriptor and the first descriptor corresponding to the dynamic DMA engine share the descriptor storage area, which can reduce memory occupancy and improve the utilization rate of hardware resources. Based on the first instruction, the parameters of the dynamic DMA engine can be dynamically reconfigured. For example, the burst address increment can improve the flexible configuration ability of the system.

[0107] In some alternative embodiments, the foregoing method for data transfer further includes: if the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transfer instruction, interrupting the execution of the transfer instruction, storing the descriptor corresponding to the next direct memory access engine in the sequence to a preset position; obtaining the first descriptor corresponding to the target direct memory access engine for data transfer; after the execution of the first descriptor corresponding to the first instruction ends, reading the descriptor corresponding to the next direct memory access engine in the sequence from the preset position and continuing the execution of the transfer instruction.

[0108] In this embodiment, a hardware comparator can be used to detect the end field of the descriptor list in real time. When it is determined that the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transfer instruction, an interrupt of the task being executed can be triggered, and the next descriptor can be pre-stored in a preset buffer.

[0109] In each DMA engine circuit, an emergency command processing logic circuit is added. This circuit monitors the status of the emergency_cmd_ctrl register. When an emergency command is detected, according to the established processing flow, operations such as pausing the task being executed, obtaining the E-DMA descriptor list, and resuming subsequent tasks are implemented. At the same time, a dedicated address register circuit is designed to store the dma_desc_pending_addr and the E-DMA descriptor address.

[0110] In this way, through the processing mechanism of the emergency command characterized by the first instruction, it is ensured that the system can quickly respond and give priority to processing the emergency command in the face of an emergency command, improving the real-time performance and reliability of the system.

[0111] The common bus port is used to arbitrate multiple requests of the NVMe controller. Taking the AXI read port for interaction between the bus and the host as an example, it is necessary to process requests such as fetching the submission queue command request, fetching the submission queue command address request, DMA read data request, DMA read metadata request, DMA read data address request, DMA read metadata address request, fetching the completion queue address request, etc. The polling method is adopted to treat all transfer requests equally. However, in practical applications, different tasks may have different importance and timeliness requirements, and the simple polling method cannot meet the diverse needs.

[0112] In some alternative embodiments, the aforementioned method for data transfer further includes: determining a preset request weight corresponding to the request type based on the request type of the transfer instruction; determining the next transfer instruction for data transfer based on the preset request weight and the number of transfers of the transfer instructions of each request type; if the number of transfers of the transfer instruction corresponding to the transfer target request type is greater than the preset number of transfers, determining the next transfer instruction for data transfer based on the transfer instructions corresponding to other request types.

[0113] In this embodiment, a preset request weight can be assigned to the request type of each transfer instruction. The first request type is used to represent a high-priority request with high timeliness requirements; the second request type is used to represent a medium-priority request with a large amount of data; the third request type is used to represent a low-priority request with lower timeliness requirements.

[0114] Specifically, the arbitration process of the common port module includes, in the case of system initialization, configuring an initial preset request weight for each request type and initializing a weight counter; the arbiter selects the next request to be processed based on the weighted round-robin algorithm according to the weight values and counter statuses of each request type. The higher the weight value, the greater the probability of being selected; when a request of a certain request type is selected and processed, its corresponding counter is incremented by 1. When the counter reaches the weight value, the counter is reset to zero, and the priority of this request type is decreased.

[0115] In this way, the arbitration method of the AXI transmission module in the related art is changed from simple round-robin arbitration to weighted round-robin arbitration, and different weight values are assigned to different requests. According to factors such as the importance, timeliness, and data volume of each request, the weight values are reasonably and flexibly set, so that high-priority requests can obtain more transmission opportunities in arbitration, thereby improving the overall data transmission efficiency.

[0116] In some optional embodiments, the foregoing method for data transmission further includes: configuring a preset request weight corresponding to a request type; configuring the preset request weight corresponding to the first request type as a first preset transmission count; configuring the preset request weight corresponding to the second request type as a second preset transmission count; based on the preset request weight, after it is characterized that the transmission instruction corresponding to the target request type exceeds the preset transmission count, determining the next transmission instruction for data transmission among the transmission instructions corresponding to other request types.

[0117] In this embodiment, a first preset request weight can be configured for the transmission instruction of the first request type, a second preset request weight can be configured for the transmission instruction of the second request type, and a third preset request weight can be configured for the transmission instruction of the third request type. An independent weight counter can be set for each request type. When the counter of a certain request type reaches its weight value, the priority of this request type is decreased, and other request types obtain arbitration opportunities.

[0118] Specifically, the preset request weight of the submission queue command request can be configured as the first preset transmission count; the preset request weight of the DMA read data request or the DMA read metadata request can be configured as the second preset transmission count; the preset request weight of the completion queue address request can be configured as the third preset transmission count. Among them, the first preset transmission count is greater than the second preset transmission count, and the second preset transmission count is greater than the third preset transmission count. For example, the first preset transmission count can be set to 5, the second preset transmission count can be set to 3, and the third preset transmission count can be set to 2.

[0119] In this way, it is possible to prevent a single request type from monopolizing the bus and ensure the fairness of the execution of each request.

[0120] In some optional embodiments, the aforementioned method for data transmission also includes: adjusting the preset request weight corresponding to the request type; if the request response time of the transmission instruction of the target request type is greater than the preset time threshold, increasing the preset request weight corresponding to the target request type.

[0121] In this embodiment, the preset request weight can be dynamically adjusted based on factors such as the importance, timeliness and data volume of the request. The weight value of each request type can also be dynamically adjusted according to the real-time load of the system and the execution of the task.

[0122] Specifically, when the system detects that the response time of a command request submitted to the queue exceeds a preset threshold, its weight value can be temporarily increased and the new weight value can be passed to the hardware weight register to implement dynamic weight adjustment to ensure that it can get priority in arbitration opportunities.

[0123] In this way, high-priority requests can be guaranteed to obtain arbitration opportunities in a timely manner.

[0124] In the related art, each DMA engine needs two request ports to obtain data, metadata, data address or metadata address, which greatly prolongs the arbitration time of the common port, especially when there are a large number of DMA engines.

[0125] In some optional embodiments, the aforementioned method for data transmission further includes: merging an instruction for transmitting target data and an instruction for transmitting a storage address of the target data into a target data transmission instruction; and based on the target data transmission instruction, enabling a direct memory access engine to perform data transmission.

[0126] In this embodiment, a compliant instruction encoding can be used to implement an instruction fusion architecture. The hardware execution process includes an instruction decoding stage, an address generation stage, and a transmission trigger stage. In the instruction decoding stage, the opcode verification and address alignment check can be completed within a preset clock cycle based on a dedicated hardwired logic.

[0127] In this way, the arbitration time of the public port can be reduced, the data transmission efficiency and the utilization efficiency of hardware resources can be improved. At the same time, the reasonable scheduling mechanism makes fuller use of hardware resources and reduces resource waste.

[0128] In some optional implementations, the firmware, as a key part of controlling the hardware behavior, needs to perform corresponding functional implementation and optimization.

[0129] In the firmware, an interface for configuring the priority and weight value of DMA descriptors is provided. When the system is started or running, the priority and weight value of each DMA descriptor can be flexibly configured through this interface according to actual needs to ensure that the hardware can arbitrate according to the set rules.

[0130] For emergency command processing, the firmware is responsible for maintaining relevant information of emergency commands, such as creating and managing the E-DMA descriptor linked list. When an emergency command is detected, the firmware immediately configures DMA descriptors for it, forms the E-DMA descriptor linked list, and places the linked list at the specified E-DMA descriptor address. At the same time, the firmware needs to interact with the hardware and notify the hardware of the arrival of the emergency command by setting operations such as the emergency_cmd_ctrl register.

[0131] In the arbitration mechanism of the common port module, the firmware is responsible for dynamically adjusting the weight values of each request type according to the real-time load situation of the system and the execution situation of tasks. For example, by monitoring parameters such as the response time of the submission queue command request, when the response time exceeds the preset threshold, the weight value is timely increased in the firmware, and the new weight value is passed to the weight register of the hardware to achieve dynamic weight adjustment.

[0132] In some alternative embodiments, at the hardware level, for the DMA descriptor acquisition arbitration mechanism, emergency command processing, and common port module arbitration mechanism proposed above. DMA descriptor acquisition arbitration mechanism: The priority signals (urgent_state, high_state, medium_state, low_state) of each DMA engine are connected to the arbitration circuit, and the arbitration circuit generates a selection signal according to the priority and weight value to determine which DMA descriptor to acquire next.

[0133] For emergency command processing, in each DMA engine circuit, an emergency command processing logic circuit is added. This circuit monitors the status of the emergency_cmd_ctrl register. When an emergency command is detected, according to the established processing flow, operations such as pausing the task being executed, acquiring the E-DMA descriptor linked list, and resuming subsequent tasks are implemented. At the same time, a dedicated address register circuit is designed to store the dma_desc_pending_addr and the E-DMA descriptor address.

[0134] For the common port module arbitration mechanism, independent weight registers and counter registers are set for each request type, and the arbitration circuit selects the next request to be processed according to the values of these registers and the weighted round-robin algorithm.

[0135] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation.

[0136] Embodiments of the present application also provide a device for data transmission. Figure 5 The structure diagram of the device for data transmission according to the embodiments of the present application is shown. As Figure 5 shown, the device for data transmission includes: a descriptor order acquisition module 501, configured to determine the acquisition order of direct memory access descriptors based on the priorities of each direct memory access engine when multiple direct memory access engines are enabled based on a transmission instruction; wherein, the descriptor corresponding to the direct memory access engine configured with the first priority is acquired prior to the descriptors corresponding to the direct memory access engines configured with other priorities. If there is no descriptor corresponding to the direct memory access engine with the first priority, the descriptor corresponding to the direct memory access engine with the second priority is acquired. If the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number, the descriptor corresponding to the direct memory access engine with the third priority is acquired; a transmission module 502, configured to perform data transmission based on the acquisition order.

[0137] In some alternative embodiments, the aforementioned device for data transmission further includes: a first configuration module, configured to configure the priorities and the acquisition order corresponding to each priority; configure the priorities to include a first priority, a second priority, and a third priority, wherein the descriptor corresponding to the direct memory access engine with the first priority is acquired prior to the descriptors corresponding to the direct memory access engines with other priorities.

[0138] In some alternative embodiments, the aforementioned device for data transmission further includes: a second configuration module, configured to configure the preset weights of the direct memory access engines with each target priority, and the direct memory access engines with each target priority include the direct memory access engine with the second priority and the direct memory access engine with the third priority; based on the preset weights, it is indicated that after acquiring the descriptors corresponding to the direct memory access engines with the target priority for a preset number of times, the descriptors corresponding to the direct memory access engines with the next priority of the target priority are acquired.

[0139] In some alternative embodiments, the descriptor order acquisition module includes: a first descriptor order acquisition unit, configured to determine whether there is a direct memory access engine with the first priority among the enabled direct memory access engines; if there is a direct memory access engine with the first priority, acquire the descriptor of the direct memory access engine with the first priority and perform data transmission based on the descriptor of the direct memory access engine with the first priority.

[0140] In some alternative embodiments, the descriptor order acquisition module further includes: a second descriptor order acquisition unit configured to determine whether there is a direct memory access engine with a first priority among the enabled direct memory access engines; if there is no direct memory access engine with a first priority, determine whether there is a direct memory access engine with a second priority among the enabled direct memory access engines; if there is a direct memory access engine with a second priority, determine whether the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority is greater than a preset first number; if the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority is less than or equal to the preset first number, acquire the descriptor corresponding to the direct memory access engine with the target number in the direct memory access engine with the second priority, perform data transmission based on the descriptor corresponding to the direct memory access engine with the target number, and increment the number of times of acquiring the descriptor corresponding to the direct memory access engine with the second priority by one.

[0141] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: a first instruction execution module configured to acquire a first instruction and, based on the first instruction, configure a first descriptor corresponding to a target direct memory access engine, wherein the first instruction is executed prior to the transmission instruction; determine whether there is a transmission instruction for acquiring a descriptor corresponding to the direct memory access engine that is being executed in the target direct memory access engine; if there is a transmission instruction for acquiring a descriptor corresponding to the direct memory access engine that is being executed, determine whether the descriptor corresponding to the direct memory access engine that is being executed is the last descriptor in the transmission instruction; if it is the last descriptor in the transmission instruction, or if there is no transmission instruction for acquiring a descriptor corresponding to the direct memory access engine that is being executed, acquire the first descriptor corresponding to the target direct memory access engine and perform data transmission.

[0142] In some alternative embodiments, the first instruction execution module includes: a first instruction execution configuration unit configured to configure the first descriptor corresponding to the target direct memory access engine in any of the following ways: if there are multiple priorities in the direct memory access engine, determine the direct memory access engine with the highest priority as the target direct memory access engine and allocate the first descriptor to the direct memory access engine with the highest priority; if all direct memory access engines have the same priority, determine any one of the direct memory access engines as the target direct memory access engine and allocate the first descriptor to the target direct memory access engine.

[0143] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: a second instruction execution module, configured to, if the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transmission instruction, interrupt the execution of the transmission instruction, store the descriptor corresponding to the next direct memory access engine in the sequence to a preset position; obtain the first descriptor corresponding to the target direct memory access engine to perform data transmission; after the execution of the first descriptor corresponding to the first instruction ends, read the descriptor corresponding to the next direct memory access engine in the sequence from the preset position, and continue the execution of the transmission instruction.

[0144] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: an arbitration module, configured to determine a preset request weight corresponding to the request type based on the request type of the transmission instruction; determine the next transmission instruction for data transmission based on the preset request weight and the number of transmissions of the transmission instructions of each request type; if the number of transmissions of the transmission instruction corresponding to the target request type is greater than the preset number of transmissions, determine the next transmission instruction for data transmission based on the transmission instructions corresponding to other request types.

[0145] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: an arbitration configuration module, configured to configure the preset request weight corresponding to the request type; configure the preset request weight corresponding to the first request type as the first preset number of transmissions; configure the preset request weight corresponding to the second request type as the second preset number of transmissions; based on the preset request weight, after indicating that the number of transmissions of the transmission instruction corresponding to the target request type is greater than the preset number of transmissions, determine the next transmission instruction for data transmission among the transmission instructions corresponding to other request types.

[0146] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: an adjustment module, configured to adjust the preset request weight corresponding to the request type; if the request response time of the transmission instruction of the target request type is greater than the preset time threshold, increase the preset request weight corresponding to the target request type.

[0147] In some alternative embodiments, the aforementioned apparatus for data transmission further includes: a merging module, configured to merge the instruction for transmitting the target data and the instruction for transmitting the storage address of the target data into a target data transmission instruction; based on the target data transmission instruction, enable the direct memory access engine to perform data transmission.

[0148] For the description of the features in the embodiments corresponding to the apparatus for data transmission, reference may be made to the relevant description in the embodiments corresponding to the method for data transmission, which will not be elaborated herein one by one.

[0149] Embodiments of the present application further provide an electronic device. Figure 6The structural schematic diagram of the electronic device according to the embodiment of the present application is shown, as Figure 6 shown, including a memory 60 and a processor 20. A computer program is stored in the memory 60, and the processor 20 is configured to run the computer program to execute the steps in any of the above method embodiments for data transmission.

[0150] The electronic device further includes an input device 30 and an output device 40. The processor 20, the memory 60, the input device 30, and the output device 40 can be connected through a bus or other means. Figure 6 Here, taking the connection through the bus as an example.

[0151] The embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any of the above method embodiments for data transmission when running.

[0152] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk, or optical disc, etc., various media that can store computer programs.

[0153] The embodiment of the present application further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above method embodiments for data transmission.

[0154] The embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above method embodiments for data transmission.

[0155] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0156] The above has introduced in detail a method, medium, device, and product for data transmission provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for data transmission, characterized in that, Including: When enabling multiple direct memory access (DMA) engines based on a transfer instruction, determine the acquisition order of obtaining DMA descriptors based on the priorities of the respective DMA engines; Among them, the descriptor corresponding to the DMA engine configured with the first priority is acquired prior to the descriptors corresponding to the DMA engines configured with other priorities. If there is no descriptor corresponding to the DMA engine with the first priority, acquire the descriptor corresponding to the DMA engine with the second priority. If the number of times of acquiring the descriptor corresponding to the DMA engine with the second priority is greater than a preset first number, acquire the descriptor corresponding to the DMA engine with the third priority; Perform data transfer based on the acquisition order.

2. The method for data transmission according to claim 1, wherein The method further includes: Configure the priorities and the acquisition order corresponding to each of the priorities; Configure the priorities to include a first priority, a second priority, and a third priority. Among them, the descriptor corresponding to the DMA engine with the first priority is acquired prior to the descriptors corresponding to the DMA engines with other priorities.

3. The method for data transmission according to claim 1 or 2, characterized in that, The method further includes: Configure the preset weights of the DMA engines with each target priority. The DMA engines with each target priority include the DMA engine with the second priority and the DMA engine with the third priority; Based on the preset weights, it is characterized that after acquiring the descriptors corresponding to the DMA engines with the target priority for a preset number of times, acquire the descriptors corresponding to the DMA engines with the next priority of the target priority.

4. The method for data transmission according to claim 1, characterized in that, The determining the order of obtaining DMA descriptors based on the priorities of the respective DMA engines and performing data transfer based on the order includes: Judge whether there is a DMA engine with the first priority among the enabled DMA engines; If there is a DMA engine with the first priority, acquire the descriptor of the DMA engine with the first priority and perform data transfer based on the descriptor of the DMA engine with the first priority.

5. The method for data transmission according to claim 1, wherein, The determining the order of obtaining DMA descriptors based on the priorities of the respective DMA engines and performing data transfer further includes: Judge whether there is a DMA engine with the first priority among the enabled DMA engines; If there is no DMA engine with the first priority, judge whether there is a DMA engine with the second priority among the enabled DMA engines; If there is a DMA engine with the second priority, judge whether the number of times of acquiring the descriptor corresponding to the DMA engine with the second priority is greater than the preset first number; If the number of times of obtaining the descriptor corresponding to the direct memory access engine of the second priority is less than or equal to the preset first number, obtain the descriptor corresponding to the direct memory access engine with the target number in the direct memory access engine of the second priority, and based on the descriptor corresponding to the direct memory access engine with the target number, perform data transmission, and increment the number of times of obtaining the descriptor corresponding to the direct memory access engine of the second priority by one.

6. The method for data transmission according to claim 1, wherein, The method further includes: Obtain a first instruction, and based on the first instruction, configure a first descriptor corresponding to the target direct memory access engine, where the first instruction is executed prior to the transmission instruction; Determine whether there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed in the target direct memory access engine; If there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed, determine whether the descriptor corresponding to the direct memory access engine that is being executed is the last descriptor in the transmission instruction; If it is the last descriptor in the transmission instruction, or if there is no transmission instruction for obtaining a descriptor corresponding to the direct memory access engine that is being executed, obtain the first descriptor corresponding to the target direct memory access engine and perform data transmission.

7. The method for data transmission according to claim 6, characterized in that, The configuring the first descriptor corresponding to the target direct memory access engine includes any one of the following methods: If there are multiple priorities in the direct memory access engine, determine the direct memory access engine with the highest priority as the target direct memory access engine, and allocate the first descriptor to the direct memory access engine with the highest priority; If each of the direct memory access engines has the same priority, determine any one of the direct memory access engines as the target direct memory access engine, and allocate the first descriptor to the target direct memory access engine.

8. The method for data transmission according to claim 6, wherein The method further includes: If the descriptor corresponding to the direct memory access engine that is being executed is not the last descriptor in the transmission instruction, interrupt the execution of the transmission instruction, and store the descriptor corresponding to the next direct memory access engine in the sequence at a preset position; Obtain the first descriptor corresponding to the target direct memory access engine and perform data transmission; After the execution of the first descriptor corresponding to the first instruction ends, read the descriptor corresponding to the next direct memory access engine in the sequence from the preset position, and continue the execution of the transmission instruction.

9. The method for data transmission according to claim 1, wherein The method further includes: Based on the request type of the transmission instruction, determine the preset request weight corresponding to the request type; Based on the preset request weight and the transmission times of the transmission instructions of each request type, determine the next transmission instruction for data transmission; If the number of times of transmitting the transmission instruction corresponding to the target request type is greater than the preset transmission times, determine the next transmission instruction for data transmission based on the transmission instructions corresponding to other request types.

10. The method for data transmission according to claim 9, wherein The method further includes: Configure the preset request weight corresponding to the request type; Configure the preset request weight corresponding to the first request type as the first preset transmission count; Configure the preset request weight corresponding to the second request type as the second preset transmission count; Based on the preset request weight, after it is indicated that the transmission instruction corresponding to the target request type is greater than the preset transmission count, determine the next transmission instruction for data transmission among the transmission instructions corresponding to other request types.

11. The method for data transmission according to claim 9 or 10, characterized in that, The method further includes: Adjust the preset request weight corresponding to the request type; If the request response time of the transmission instruction of the target request type is greater than the preset time threshold, increase the preset request weight corresponding to the target request type.

12. The method for data transmission according to claim 9, wherein The method further includes: Merge the instruction for transmitting the target data and the instruction for transmitting the storage address of the target data into a target data transmission instruction; Based on the target data transmission instruction, enable the direct memory access engine to perform data transmission.

13. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the method for data transmission according to any one of claims 1 to 12 are implemented.

14. A computer device, characterized in that, It includes: A memory for storing a computer program; A processor for implementing the steps of the method for data transmission according to any one of claims 1 to 12 when executing the computer program.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method for data transmission according to any one of claims 1 to 12 are implemented.

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