Inter-core communication method and device of multi-core system on chip, equipment and storage medium

Abstract

The embodiment of the invention discloses an inter-core communication method and device for a multi-core system on chip, equipment and a storage medium, in the method, by obtaining operation parameters of multiple dimensions when the multi-core system on chip executes a to-be-processed task, the actual situation of the multi-core system on chip can be judged more accurately, and the operation efficiency of the multi-core system on chip is improved. According to the method and the device, the target interrupt generation strategy meeting the requirements of the current to-be-processed task can be dynamically and accurately determined to generate the interrupt, so that the compatibility and the flexibility of the multi-core system on chip in processing a complex data interaction scene are realized, and the communication efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to an inter-core communication method, device, equipment, and storage medium for a multi-core system on a chip. Background Art

[0002] With the increase in the scale and complexity of SoCs, multi-core SOCs (System on Chip) have become increasingly popular. For example, a baseband chip includes an ARM (Advanced RISC Machines) processor and a DSP (Digital Signal Process) coprocessor, and even the DSP includes a scheduling DSP and a computing power DSP. Due to the increase in the input bandwidth of the chip and the increase in the amount of computation, it is difficult for a single processor to complete such a large-scale calculation. Therefore, the operation is often split into multiple steps, and each processor is responsible for a different step to reduce the load on a single processor. However, the result of multi-core operation needs to be synchronized finally. For example, two DSPs calculate A×A and B×B respectively, and finally need to add them up to get the final result. If both sides do not know whether the other has completed the calculation, the final calculation result is very likely to be incorrect. Therefore, it becomes increasingly important to achieve multi-core synchronization through inter-core communication.

[0003] Currently, in the related art, when dealing with complex data interaction scenarios, communication is usually achieved through a pre-set fixed interrupt generation mechanism. However, due to the single interrupt generation mechanism, it is easy to lead to insufficient compatibility and flexibility, and it is difficult to adapt to diverse task requirements, resulting in poor communication efficiency of the multi-core system on a chip. Summary of the Invention

[0004] To solve the above technical problems, embodiments of this application provide an inter-core communication method, device, equipment, and storage medium for a multi-core system on a chip, so as to improve the communication efficiency of the multi-core system on a chip.

[0005] According to one aspect of the embodiments of the present application, a method for inter-core communication of a multi-core system-on-chip is provided, including: obtaining the operating parameters of the multi-core system-on-chip when executing a task to be processed; wherein, the operating parameters include one or more of the current load condition, data transmission volume, and real-time requirement of the multi-core system-on-chip; determining a target interrupt generation policy according to the operating parameters; wherein, the target interrupt generation policy is used to instruct a first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when writing an operation at a target address; when the write address corresponding to the task to be processed matches the target address, generating an interrupt according to the target interrupt generation policy and sending the interrupt to a second processor; wherein, the first processor and the second processor are processors that cooperate to execute the task to be processed in the multi-core system-on-chip.

[0006] In some embodiments, the target interrupt generation policy includes a first target interrupt generation policy; the determining the target interrupt generation policy according to the operating parameters includes: when the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determining the target interrupt generation policy as the first target interrupt generation policy; wherein, the target address corresponding to the first target interrupt generation policy is the address of a special register, and when writing an operation at the address of the special register, triggering a preset interrupt controller to generate multiple first-type interrupts simultaneously and sending them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning.

[0007] In some embodiments, the target interrupt generation policy includes a second target interrupt generation policy; the determining the target interrupt generation policy according to the operating parameters includes: when the current load condition is not higher than a second preset load threshold, the data transmission volume is lower than a second preset data volume threshold, and the real-time requirement is higher than a second preset requirement threshold, determining the target interrupt generation policy as the second target interrupt generation policy; wherein, the target address corresponding to the second target interrupt generation policy is the address of a shared memory, and when writing an operation at the address of the shared memory, triggering a preset interrupt controller to generate a second-type interrupt and sending it to the second processor; the meaning of the second-type interrupt is a custom meaning.

[0008] In some embodiments, the target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a circular buffer; the method further includes: obtaining the task priority corresponding to the task to be processed; caching the data to be transmitted corresponding to the task to be processed in the sub-queue corresponding to the task priority in the target address.

[0009] In some embodiments, after generating an interrupt according to the target interrupt generation policy and sending the interrupt to the second processor when the write address corresponding to the task to be processed matches the target address, the method further includes: after detecting that the second processor performs a read operation at the target address, clearing the interrupt.

[0010] In some embodiments, the method further includes: obtaining the environmental state and task requirements of the multi-core system-on-chip; adjusting the interrupt control parameters of the interrupt controller according to the environmental state and task requirements.

[0011] In some embodiments, the bus of the multi-core system-on-chip is an AMBA bus, and the target interrupt generation policy is mounted on the AMBA bus.

[0012] According to one aspect of the embodiments of the present application, there is provided an inter-core communication device for a multi-core system-on-chip, including: an acquisition module, a determination module, and a sending module; wherein, the acquisition module is configured to acquire the operation parameters of the multi-core system-on-chip when executing a task to be processed; wherein, the operation parameters include one or more of the current load condition, data transmission volume, and real-time requirement of the multi-core system-on-chip; the determination module is configured to determine a target interrupt generation policy according to the operation parameters; wherein, the target interrupt generation policy is used to instruct a first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when performing a write operation at a target address; the sending module is configured to generate an interrupt according to the target interrupt generation policy and send the interrupt to a second processor when the write address corresponding to the task to be processed matches the target address; wherein, the first processor and the second processor are processors that cooperate to execute the task to be processed in the multi-core system-on-chip.

[0013] According to one aspect of the embodiments of the present application, there is provided an electronic device, including: one or more processors; and a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enabling the electronic device to implement the inter-core communication method of the multi-core system-on-chip as described above.

[0014] According to one aspect of the embodiments of the present application, there is provided a computer-readable storage medium, on which computer-readable instructions are stored, when the computer-readable instructions are executed by a processor of a computer, enabling the computer to execute the inter-core communication method of the multi-core system-on-chip as described above.

[0015] In the technical solution provided by the embodiments of the present application, by obtaining various dimensions of operating parameters of the multi-core system-on-chip when executing a task to be processed, it is possible to more accurately judge the actual situation of the multi-core system-on-chip, and dynamically and accurately determine a target interrupt generation strategy that meets the requirements of the current task to be processed to generate an interrupt, achieving the compatibility and flexibility of the multi-core system-on-chip in processing complex data interaction scenarios, thereby improving communication efficiency.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings: Figure 1 is a schematic diagram of an implementation environment related to an inter-core communication method of a multi-core system-on-chip shown in an exemplary embodiment of the present application; Figure 2 is a flowchart of an inter-core communication method of a multi-core system-on-chip shown in an exemplary embodiment of the present application; Figure 3 is Figure 2 a flowchart of determining a target interrupt generation strategy according to operating parameters in step S220 in the shown embodiment in an exemplary embodiment; Figure 4 is Figure 2 a flowchart of determining a target interrupt generation strategy according to operating parameters in step S220 in the shown embodiment in another exemplary embodiment; Figure 5 is a flowchart of an inter-core communication method of a multi-core system-on-chip shown in another exemplary embodiment of the present application; Figure 6 is an application schematic diagram of an inter-core communication method of a multi-core system-on-chip shown in an exemplary embodiment of the present application; Figure 7 is a flowchart of an inter-core communication method of a multi-core system-on-chip shown in yet another exemplary embodiment of the present application; Figure 8 is a schematic structural diagram of an inter-core communication device shown in an exemplary embodiment of the present application; Figure 9 shows a schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments identical to the present application. On the contrary, they are merely examples of devices and methods that are the same in some aspects of the present application as detailed in the appended claims.

[0019] The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of application programs, or implemented in one or more hardware modules or integrated circuits, or implemented in different models and / or processor devices and / or microcontroller devices.

[0020] The flowcharts shown in the drawings are merely illustrative and do not necessarily include all contents and operations / steps, nor are they necessarily executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0021] It should be noted that the term "plurality" mentioned in the present application refers to two or more. The "and / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0022] To facilitate understanding of the inter-core communication method of the multi-core system-on-chip provided in the embodiments of the present application, the following Figure 1 introduces the inter-core communication scenario in combination with the Figure 1 shown implementation environment; this implementation environment is specifically a multi-core system-on-chip, as

[0023] shown, the multi-core system-on-chip includes a first processor 110, a monitoring module 120, a dedicated address register 130, a shared memory 140, an interrupt controller 150, and a second processor 160.

[0024] The monitoring module 120 is used to monitor the multi-core system-on-chip, so as to obtain the operating parameters of the multi-core system-on-chip when executing the task to be processed, and determine the target interrupt generation strategy according to the operating parameters.

[0025] The dedicated address register 130 is a set of small high-speed storage units inside the multi-core system-on-chip for quickly accessing data. Its core function is to provide zero-latency operand access for the processor. In some embodiments, the dedicated address register is a regfile (Register File), which can be an array composed of multiple registers, and each register is identified by a unique address.

[0026] The shared memory 140 can be an SRAM (Static Random Access Memory). SRAM has the advantages of low latency, low power consumption, and high reliability, and is suitable for fast inter-core data exchange in multi-core processors.

[0027] The interrupt controller 150 can be an INTC (Interrupt Controller), or can be multiple INTCs.

[0028] In the case of one interrupt controller, different types of interrupts are generated by this interrupt controller based on different interrupt generation strategies.

[0029] In the case of multiple interrupt controllers, each interrupt controller corresponds to a target interrupt generation strategy. For example, if there are a total of 2 target interrupt generation strategies and 2 interrupt controllers in the multi-core system-on-chip, the first interrupt controller generates the first type of interrupt based on the first target interrupt generation strategy, and the second interrupt controller generates the second type of interrupt based on the second target interrupt generation strategy.

[0030] In some embodiments, the interrupt controller includes an interrupt mask register and an interrupt enable register corresponding to the interrupt. The settings can be performed in the following manner: By performing set or clear operations on different bits of the interrupt mask register through software programming, specific types of interrupts can be selectively masked; by performing corresponding settings on the interrupt enable register, the interrupt function can be enabled or disabled to achieve fine control of the interrupt.

[0031] For example, by sending a masking signal MASK[31:0] to the interrupt masking controller to control the masking of corresponding interrupts; by sending an enabling signal EN[31:0] to the interrupt enabling register to control the enabling of corresponding interrupt sources, thereby generating interrupts; by sending a signal SET[31:0] to the setting register and writing 1 to set the corresponding bit to 1 for enabling interrupts; by sending a signal CLR[31:0] to the clearing register and writing 1 to set the corresponding bit to 0 for clearing interrupts.

[0032] Figure 1 The working principle of the multi-core system-on-chip shown is as follows: When the first processor 110 (CPU1) is the communication initiator, it obtains the operating parameters of the multi-core system-on-chip during the execution of the task to be processed through the monitoring module 120, and determines the target interrupt generation strategy based on the operating parameters; among them, the target interrupt generation strategy includes the first target interrupt generation strategy and the second target interrupt generation strategy.

[0033] If the target interrupt generation strategy determined according to the operating parameters is the first target interrupt generation strategy, the data (interaction data) corresponding to the task to be processed is written to the target address corresponding to the first target interrupt generation strategy (i.e., the address corresponding to the dedicated address register 130), and then the first processor 110 (CPU1) performs a write operation to cache the data corresponding to the task to be processed in the dedicated address register 130, and at the same time outputs an interrupt request signal to the interrupt controller 150 (INTC1), triggering the interrupt controller 150 (INTC1) to generate multiple first-type interrupts (including irq1, irq2, and irq3) simultaneously, and sending the multiple first-type interrupts to multiple second processors 160 (CPU3, CPU4, and CPU5); after receiving the first-type interrupts, the multiple second processors 160 read the corresponding data from the dedicated address register 130 according to the target address, and then clear the interrupt in the interrupt controller 150 (INTC1).

[0034] If the target interrupt generation strategy determined according to the operating parameters is the second target interrupt generation strategy, the data (interaction data) corresponding to the task to be processed is written to the target address corresponding to the second target interrupt generation strategy (i.e., the address corresponding to the shared memory 140), and then the first processor 110 (CPU1) performs a write operation to cache the data corresponding to the task to be processed in the shared memory 140, and at the same time outputs an interrupt request signal to the interrupt controller 150 (INTC2), triggering the interrupt controller 150 (INTC2) to generate a second-type interrupt and send it to the second processor 160 (CPU2); after receiving the second-type interrupt, the second processor 160 (CPU2) reads the corresponding data from the shared memory 140 according to the target address, and then clears the interrupt in the interrupt controller 150 (INTC2).

[0035] In addition, the bus of the multi-core system-on-chip is the AMBA bus, and the target interrupt generation strategy is mounted on the AMBA bus. By mounting the target interrupt generation strategy on an AMBA (Advanced Microcontroller Bus Architecture) bus such as AHB or AXI, the compatibility and expandability are stronger, which can adapt to the vast majority of commercial processors, be mounted on any bus interface, and support communication between any processors. Through actual tests, it can run stably in a system composed of processors with various different architectures, and the communication success rate is over 99%. The inter-core communication method in the multi-core system-on-chip in the embodiments of the present application has strong expandability. When increasing the number of processors in the SoC, only one set of inter-core communication devices needs to be added for adaptation, and there is no need to make large-scale modifications to the original architecture.

[0036] The following will detail the inter-core communication method of the multi-core system-on-chip provided by the embodiments of the present application.

[0037] Please continue to refer to Figure 2 , Figure 2 which is a flowchart of the inter-core communication method of the multi-core system-on-chip shown in an exemplary embodiment of the present application. This method can be applied to Figure 1 the implementation environment shown, and is specifically executed by the multi-core system-on-chip in this implementation environment. It should be understood that this method can also be applicable to other exemplary implementation environments and be specifically executed by the multi-core system-on-chip in other implementation environments. The embodiments of the present application do not limit the implementation environment applicable to this method.

[0038] As Figure 2 shown, in an exemplary embodiment, the inter-core communication method of the multi-core system-on-chip at least includes steps S210 to S230, which are introduced in detail as follows: Step S210, obtain the operation parameters of the multi-core system-on-chip when executing the task to be processed.

[0039] It should be understood that in the related art, only a single pre-set interrupt generation mechanism can be used to implement inter-core communication, which easily leads to insufficient compatibility and flexibility in processing complex data interaction scenarios, is difficult to adapt to diverse task requirements, and cannot be optimized and selected according to the actual situation, resulting in low communication efficiency. However, the operation parameters of the multi-core system-on-chip in the present application can simultaneously include multi-dimensional influencing factors such as the current load situation, data transmission volume, and real-time requirements, and can take into account both the task requirements and the system processing capabilities, and thus can determine a target interrupt generation strategy that not only meets the task requirements but also is within the range of the system processing capabilities.

[0040] In some embodiments, a monitoring module is provided in the multi-core system-on-chip. The multi-core system-on-chip is monitored through this monitoring module to obtain the operating parameters of the multi-core system-on-chip. In some embodiments, the operating parameters include the current load condition, data transfer volume, and real-time requirement of the multi-core system-on-chip.

[0041] Step S220: Determine a target interrupt generation policy according to the operating parameters.

[0042] It can be understood that in this application, by obtaining the operating parameters of the multi-core system-on-chip when executing a task to be processed, since the operating parameters can include multi-dimensional influencing factors such as the current load condition, data transfer volume, and real-time requirement of the multi-core system-on-chip, it is possible to consider the influencing factors of both task requirements and system processing capabilities simultaneously, improving the accuracy of the target interrupt generation policy, so that the determined target interrupt generation policy not only meets the task requirements but also is within the range of system processing capabilities, further improving communication efficiency.

[0043] In the embodiments of this application, the target interrupt generation policy is used to instruct the first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when writing an operation at a target address. An interrupt is an event handling mechanism in a computer system, and its core function is to enable the CPU to pause the current task and instead process a more urgent or high-priority task, and resume the original task to continue execution after processing. Through the target interrupt generation policy, it is possible to manage interrupt triggering, priority allocation, and processing flow, so as to achieve a balance between limited resources and real-time requirements.

[0044] In some embodiments, in combination with Figure 3 as shown Figure 3 is Figure 2 a flowchart of step S220 in the embodiment shown for determining a target interrupt generation policy according to operating parameters in an exemplary embodiment; it includes at least steps S310 to S330, which are introduced in detail as follows: Step S310: Compare the operating parameters with corresponding thresholds to obtain a comparison result; In the embodiments of this application, the operating parameters include the current load condition, data transfer volume, and real-time requirement. In some embodiments, each operating parameter corresponds to at least one threshold. In this way, by separately comparing different operating parameters with their corresponding thresholds, it is possible to determine the current actual situation of the multi-core system-on-chip (i.e., the system operating situation and task requirement situation), so as to more accurately determine a target interrupt policy that conforms to the current actual situation.

[0045] For example, the thresholds corresponding to the current load condition include a first preset load threshold and a second preset load threshold, where the first preset load threshold is greater than the second preset load requirement threshold.

[0046] The thresholds corresponding to the data transfer volume include a first preset data volume threshold and a second preset data volume threshold, where the first preset data volume threshold is greater than the second preset data volume threshold.

[0047] The thresholds corresponding to the low real-time requirement include a first preset requirement threshold and a second preset requirement threshold, where the first preset requirement threshold is greater than the second preset requirement threshold.

[0048] Step S320, in the case where the comparison result is that the current load condition is lower than the first preset load threshold, the data transfer volume is lower than the first preset data volume threshold, and the real-time requirement is lower than the first preset requirement threshold, determine that the target interrupt generation policy is the first target interrupt generation policy; In the embodiment of the present application, the target address corresponding to the first target interrupt generation policy is the address of a dedicated register. When a write operation is performed at the address of the dedicated register, a preset interrupt controller is triggered to generate multiple first-type interrupts simultaneously and send them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning.

[0049] Exemplarily, when the current load condition is lower than the first preset load threshold, it can be considered that the CPU resources required for the task to be processed are less; when the data transfer volume is lower than the first preset data volume threshold, it can be considered that the data transfer volume will not be too high; when the real-time requirement is lower than the first preset requirement threshold, it can be considered that the real-time requirement is not high. Considering all the operating parameters, the resources required to execute the task to be processed are less, the data transfer volume is not large, and the real-time requirement is not high. In this case, by adopting the first target interrupt generation policy, multiple interrupts can be generated simultaneously and sent to multiple second processors, which can achieve compatible shared memory and the most basic interrupt notification.

[0050] Step S330, in the case where the comparison result is that the current load condition is not higher than the second preset load threshold, the data transfer volume is lower than the second preset data volume threshold, and the real-time requirement is higher than the second preset requirement threshold, determine that the target interrupt generation policy is the second target interrupt generation policy.

[0051] In the embodiment of the present application, the target address corresponding to the second target interrupt generation policy is the address of the shared memory. When a write operation is performed at the address of the shared memory, a preset interrupt controller is triggered to generate a second-type interrupt and send it to the second processor; the meaning of the second-type interrupt is a custom meaning.

[0052] Exemplarily, when the current load condition is not higher than the second preset load threshold, it can be considered that the CPU resources required for the task to be processed are relatively high; when the data transmission volume is lower than the second preset data volume threshold, it can be considered that the data volume to be transmitted by the task to be processed is small, or that there is no need to transmit data; when the real-time requirement is higher than the second preset requirement threshold, it can be considered that the real-time requirement is relatively high. Considering all the operating parameters, the resources required to execute the task to be processed are relatively high, the data transmission volume is small, and the real-time requirement is relatively high. In this case, by adopting the second target interrupt generation strategy, the meaning of the second type of interrupt can be pre-customized, so as to be able to adapt to a variety of different scenarios and improve the real-time performance. In addition, since the second target interrupt generation strategy directly generates the second type of interrupt based on writing to the shared memory, and the data can be directly transmitted through the second type of interrupt, the data and the notification can be combined into one operation, that is, directly trigger the interrupt by writing to the shared memory and transmit the data at the same time, which can further improve the real-time performance.

[0053] In some embodiments, the embodiments of the present application can flexibly support the data volume carried by messages during inter-core communication, so as to be compatible with simple or complex multi-core synchronization tasks. For example, in a graphics rendering task, a large amount of texture data transmission can be efficiently processed by adopting the first target interrupt generation strategy; in a real-time control task, by adopting the second target interrupt generation strategy, a small amount of key instruction data can be accurately transmitted.

[0054] In some embodiments, in combination with Figure 4 as shown Figure 4 is Figure 2 a flowchart of step S220 in the embodiment shown in another exemplary embodiment for determining a target interrupt generation strategy according to operating parameters; at least including steps S410 to S420, which are introduced in detail as follows: Step S410, obtain the current measurement score corresponding to the multi-core on-chip system according to the operating parameters.

[0055] In the embodiments of the present application, the current measurement score corresponding to the multi-core on-chip system includes the sum of the scores corresponding to all operating parameters.

[0056] In some embodiments, the current measurement score corresponding to the multi-core on-chip system can be obtained in the following manner: obtain the weight value corresponding to the operating parameter; perform weighted summation on the operating parameter according to the weight value to obtain the current measurement score corresponding to the multi-core on-chip system.

[0057] It can be understood that different types of operating parameters can correspond to different weight ranges, and the weight values corresponding to different sizes of operating parameters are different. For example, the operating parameters include the current load condition, data transmission volume, and real-time requirement. The weight range corresponding to the current load condition is 0.3 - 0.5. The greater the current load, the greater the corresponding weight value. The weight range corresponding to the data transmission volume is 0.2 - 0.4. The greater the data transmission volume, the greater the corresponding weight value. The weight range corresponding to the real-time requirement is 0.3 - 0.6. The higher the real-time requirement, the greater the corresponding weight value.

[0058] The current load condition refers to the utilization rate of the CPU, and its value range is 0% - 100%.

[0059] Current load condition = current load / maximum load threshold × 100%.

[0060] In some embodiments, the maximum load threshold is less than 100%, for example, it is 90%. For example: when the load is 80% and the maximum load threshold is 90%, then the current load condition = 80 / 90 × 100% ≈ 88.9% The data transmission volume can refer to the bandwidth occupancy rate, and its value range is 0% - 100%.

[0061] Data transmission volume = current transmission volume / maximum bandwidth × 100%.

[0062] In some embodiments, when the current transmission volume is 600 MB / s and the maximum bandwidth is 1 GB / s, the data transmission volume is 60%.

[0063] The real-time requirement can refer to the deadline hit rate of the task to be processed (i.e., the probability that the task to be processed is completed within the deadline).

[0064] In some embodiments, if the deadline hit rate is within 90% - 100%, it is considered that the real-time requirement is high; if the deadline hit rate is within 50% - 90%, it is considered that the real-time requirement is medium; if the deadline hit rate is within 0% - 50%, it is considered that the real-time requirement is low.

[0065] In some embodiments, obtaining the current measurement score corresponding to the multi-core system-on-chip according to the operating parameters includes: by calculating Obtaining the current measurement score corresponding to the multi-core system-on-chip; where is the current measurement score corresponding to the multi-core system-on-chip, is the current load condition, is the weight corresponding to the current load condition, is the data transmission volume, is the weight corresponding to the data transmission volume, is the real-time requirement, Weights corresponding to real-time requirements. In this way, by obtaining the corresponding weight parameters to perform weighted summation on each operating parameter, it is possible to support multi-scenario adaptation, and the weight parameters can be dynamically adjusted, thereby improving reliability and facilitating the determination of a more accurate target interrupt generation strategy.

[0066] Step S420, determine the target interrupt generation strategy according to the current measurement score.

[0067] It can be understood that in the embodiments of the present application, by setting a score threshold, the current measurement score can be compared with the score threshold, and different target interrupt generation strategies can be determined according to different comparison results.

[0068] In some embodiments, the target interrupt generation strategy includes a first target interrupt generation strategy and a second target interrupt generation strategy. Among them, the target address corresponding to the first target interrupt generation strategy is the address of a dedicated register. When a write operation is performed at the address of the dedicated register, a preset interrupt controller is triggered to generate multiple first-type interrupts simultaneously and send them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning. The target address corresponding to the second target interrupt generation strategy is the address of a shared memory. When a write operation is performed at the address of the shared memory, a preset interrupt controller is triggered to generate a second-type interrupt and send it to the second processor; the meaning of the second-type interrupt is a custom meaning.

[0069] Exemplarily, in the embodiments of the present application, the target interrupt generation strategy can be determined according to the current measurement score in the following manner, including: comparing the current measurement score with a preset score threshold. If the current measurement score is less than the preset score threshold, it is determined that the target interrupt generation strategy is the first target interrupt generation strategy; if the current measurement score is greater than the preset score threshold, it is determined that the target interrupt generation strategy is the second target interrupt generation strategy.

[0070] In some embodiments, the score threshold can also be dynamically adjusted according to different task scenarios, thereby improving the compatibility and stability of the multi-core on-chip system.

[0071] In the embodiments of the present application, the target interrupt generation strategy can also be determined according to the operating parameter in the following manner: match the target interrupt generation strategy corresponding to the operating parameter from a preset database. Among them, the corresponding relationship between the operating parameter and the target interrupt generation strategy is stored in the preset database.

[0072] Step S230, when the write address corresponding to the task to be processed matches the target address, generate an interrupt according to the target interrupt generation strategy and send the interrupt to the second processor.

[0073] Among them, the first processor and the second processor are the processors that cooperate to execute the task to be processed in the multi-core on-chip system.

[0074] In the embodiments of the present application, by obtaining the operating parameters of multiple dimensions of the multi-core system-on-chip when executing a task to be processed, the actual situation of the multi-core system-on-chip can be judged more accurately, and a target interrupt generation strategy that meets the requirements of the current task to be processed can be dynamically and accurately determined to generate an interrupt, realizing the compatibility and flexibility of the multi-core system-on-chip in processing complex data interaction scenarios, thereby improving the communication efficiency.

[0075] Please continue to refer to Figure 5 , in an exemplary embodiment, when the write address corresponding to the task to be processed matches the target address, the inter-core communication method of the multi-core system-on-chip further includes at least steps S510 to S520, which are introduced in detail as follows: Step S510, obtain the task priority corresponding to the task to be processed.

[0076] It should be understood that the target address in the embodiments of the present application is the address for performing a write operation, such as the address of a dedicated address register or the address of shared memory. The target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a circular buffer. By organizing the data storage area of each sub-queue according to a circular buffer (Ring Buffer), it means that each sub-queue has a fixed-size memory area for efficiently storing and managing messages or data. The circular buffer avoids frequent memory allocation and release by circularly using the memory space, improving the efficiency of data transmission.

[0077] In some embodiments, a fixed-size memory is pre-allocated for the data area of each sub-queue to store messages or data. The sender writes data to the tail of the queue in sequence. When writing to the end of the memory, it will automatically return to the beginning of the queue to continue writing. The receiver reads data from the head of the queue and also automatically returns to the beginning to continue reading when reaching the end. Since the data in the circular buffer is written and read circularly, no memory gaps will be generated. Therefore, the circular buffer can avoid the problem of memory fragmentation. At the same time, the size of the circular buffer is dynamically adjusted according to actual needs, and the maximum can cache 1024 pieces of data to avoid data overflow or blockage and ensure the reliability of data processing. In addition, the data cached in each sub-queue is managed according to the principle of first in first out to avoid data loss. In this way, by setting up a caching mechanism, when the system is busy and cannot process messages in time, the messages can be temporarily stored in the cache area.

[0078] Step S520, cache the data to be transmitted corresponding to the task to be processed in the sub-queue corresponding to the task priority in the target address.

[0079] In the embodiments of the present application, by storing data according to task priorities, data can be automatically classified and sorted by priority based on data types and urgency levels, and high-priority data can be processed first to ensure timely response to critical tasks. At the same time, by setting up a caching mechanism, message loss during system busyness can be avoided, and the reliability of data processing can be improved.

[0080] Exemplarily, the storage area in the target address may include multiple sub-queues; for example, it is divided into three sub-queues: a high-priority queue, a medium-priority queue, and a low-priority queue. Data is stored in the corresponding sub-queue according to task priorities, and the data in each sub-queue is arranged in the first-in-first-out order; when processing data, the data in the high-priority queue is processed first, then the data in the medium-priority queue, and finally the data in the low-priority queue.

[0081] Please continue to refer to Figure 6 , Figure 6 which is a schematic application diagram of the inter-core communication method of the multi-core system-on-chip shown in an exemplary embodiment of the present application.

[0082] Step S601, the first processor writes the first shared data into the memory address A in the shared memory. First, the first processor writes the first shared data that needs to be passed to the second processor into the memory address A in the shared memory.

[0083] Step S602, the first processor writes the circular buffer and generates a request interrupt. In the embodiments of the present application, after writing the first shared data, the first processor performs a write operation in the circular buffer and generates a request interrupt to be cached at the target address, triggering the interrupt controller to generate a first interrupt and send it to the second processor. Wherein, the target address is the address corresponding to the first target interrupt generation policy or the address corresponding to the second target interrupt generation policy.

[0084] Step S603, the second processor receives the first interrupt. The first interrupt carries the pointer address A, that is, the memory address A.

[0085] Step S604, read the first shared data from the shared memory according to the pointer address A.

[0086] Step S605, the second processor reads the circular buffer and clears the request interrupt. In the embodiments of the present application, after the second processor reads the first shared data, by performing a read operation in the circular buffer and clearing the request interrupt, one-way synchronization can be achieved.

[0087] Step S606, the second processor writes the second shared data into the memory address B in the shared memory. Then the second processor writes the second shared data that needs to be passed to the first processor into the memory address B in the shared memory.

[0088] Step S607, the second processor writes to the circular buffer and generates a request interrupt. In the embodiment of the present application, after writing the second shared data, the second processor performs a write operation in the circular buffer, and then generates a request interrupt and caches it at the target address, triggering the interrupt controller to generate a second interrupt and send it to the first processor.

[0089] Step S608, the first processor receives the second interrupt; the second interrupt carries the pointer address B, that is, the memory address B.

[0090] Step S609, read the second shared data from the shared memory according to the pointer address B.

[0091] Step S610, the first processor reads the circular buffer and clears the request interrupt. In the embodiment of the present application, after the first processor reads the second shared data, by performing a read operation in the circular buffer and clearing the request interrupt, two-way synchronization can be achieved.

[0092] In the embodiment of the present application, by generating interrupts according to the corresponding interrupt generation strategy, the communication efficiency can be improved. Moreover, by setting a circular buffer to store messages, when the system is busy and unable to process messages in time, the messages can be temporarily stored in the buffer, and the buffer is managed according to the first-in-first-out principle to avoid message loss.

[0093] In some embodiments, when the write address corresponding to the task to be processed matches the target address, after generating an interrupt according to the target interrupt generation strategy and sending the interrupt to the second processor, the method further includes: after detecting that the second processor performs a read operation at the target address, clearing the interrupt. In this way, when it is detected that the second processor performs a read operation at the target address, it is considered that the second processor has obtained the data that the first processor wants to share from the shared memory at this time. At this time, by clearing the interrupt, the interrupt controller is notified that the interrupt has been processed, preventing repeated processing of the interrupt, and by clearing the interrupt status, the interrupt controller is in a state of waiting for the next interrupt event, ensuring that the system can respond to subsequent interrupt requests in time and maintaining the real-time performance and response ability of the system.

[0094] Combined with Figure 7 As shown, in an exemplary embodiment, the inter-core communication method of the multi-core system-on-chip further includes steps S710 to S720, which are introduced in detail as follows: Step S710, obtain the environmental status and task requirements of the multi-core system-on-chip.

[0095] In the embodiments of the present application, the environmental state may include the resource state, the power state, and the bus bandwidth; the task requirements may include the data transfer volume, the communication mode, the urgency level, the task deadline, and the task priority. By obtaining parameters in multiple different dimensions, it is convenient to adjust the interrupt control parameters more accurately, so as to more accurately determine the target interrupt generation strategy.

[0096] Among them, the resource state refers to the load distribution, that is, the real-time utilization rate of each core, as well as the cache and memory pressure, such as the miss rate and the memory bandwidth occupancy rate. The power state refers to whether the CPU core is in the sleep state or the overclocked state. The bus bandwidth refers to the remaining available bandwidth of the bus and the conflict probability.

[0097] The data transfer volume may be the number of messages per unit time (such as the network packet rate of 10 Gbps) or the data block size (such as 4 KB / message). The communication mode may be unicast (point-to-point) or broadcast (one-to-many) requirements.

[0098] Step S720, adjust the interrupt control parameters of the interrupt controller according to the environmental state and the task requirements.

[0099] In the embodiments of the present application, by dynamically adjusting the interrupt control parameters of the interrupt controller according to the environmental state and the task requirements, the target interrupt generation strategy can be more accurately determined, and thus higher performance and resource utilization can be achieved.

[0100] In some embodiments, the interrupt control parameters include interrupt distribution parameters and interrupt handling parameters, etc. Among them, the interrupt distribution parameters include priority (dynamically adjusting the response order of interrupts), affinity (binding interrupts to specific processors), and trigger mode (that is, selecting edge trigger or level trigger); the interrupt handling parameters include queue depth (adjusting the size of the circular buffer of the request interrupt queue), masking (temporarily disabling non-critical interrupts), and timeout threshold (adjusting the maximum allowed time for interrupt handling).

[0101] Exemplarily, adjusting the interrupt control parameters of the interrupt controller according to the environmental state and the task requirements includes: matching the parameter adjustment value corresponding to both the environmental state and the task requirements from a preset database; and correspondingly adjusting the interrupt control parameters according to the parameter adjustment value. Among them, the preset database stores the correspondence relationship between the environmental state, the task requirements, and the parameter adjustment value.

[0102] Combined with Figure 8 shown, Figure 8 is the structural diagram of the inter-core communication device shown in an exemplary embodiment of the present application. As Figure 8As shown, the exemplary inter-core communication device includes: an acquisition module 810, a determination module 820, and a transmission module 830. The acquisition module 810 is configured to acquire the operating parameters of the multi-core system-on-chip when executing a task to be processed; wherein, the operating parameters include one or more of the current load condition, data transmission volume, and real-time requirement of the multi-core system-on-chip; the determination module 820 is configured to determine a target interrupt generation strategy according to the operating parameters; wherein, the target interrupt generation strategy is used to indicate that a first processor in the multi-core system-on-chip triggers a preset interrupt controller to generate an interrupt when writing an operation at a target address; the transmission module 830 is configured to generate an interrupt according to the target interrupt generation strategy and send the interrupt to a second processor when the write address corresponding to the task to be processed matches the target address; wherein, the first processor and the second processor are processors that cooperate to execute the task to be processed in the multi-core system-on-chip.

[0103] In the embodiment of the present application, by adopting the exemplary inter-core communication device, by acquiring the operating parameters of multiple dimensions of the multi-core system-on-chip when executing a task to be processed, it is possible to more accurately judge the actual situation of the multi-core system-on-chip, and it is possible to dynamically and accurately determine a target interrupt generation strategy that meets the requirements of the current task to be processed to generate an interrupt, realizing the compatibility and flexibility of the multi-core system-on-chip in processing complex data interaction scenarios, thereby improving the communication efficiency.

[0104] In another exemplary embodiment, the target interrupt generation strategy includes a first target interrupt generation strategy; the determination module 820 is configured to determine the target interrupt generation strategy according to the operating parameters in the following manner: when the current load condition is lower than the first preset load threshold, the data transmission volume is lower than the first preset data volume threshold, and the real-time requirement is lower than the first preset requirement threshold, determine that the target interrupt generation strategy is the first target interrupt generation strategy; Wherein, the target address corresponding to the first target interrupt generation strategy is the address of a special register, and when writing an operation at the address of the special register, a preset interrupt controller is triggered to generate multiple first-type interrupts simultaneously and send them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning.

[0105] In another exemplary embodiment, the target interrupt generation strategy includes a second target interrupt generation strategy; the determination module 820 is configured to determine the target interrupt generation strategy according to the operating parameters in the following manner: determining the target interrupt generation strategy according to the operating parameters includes: when the current load condition is not higher than the second preset load threshold, the data transmission volume is lower than the second preset data volume threshold, and the real-time requirement is higher than the second preset requirement threshold, determine that the target interrupt generation strategy is the second target interrupt generation strategy; Among them, the target address corresponding to the second target interrupt generation policy is the address of the shared memory. When a write operation is performed at the address of the shared memory, a preset interrupt controller is triggered to generate a second type of interrupt and send it to the second processor; the meaning of the second type of interrupt is a custom meaning.

[0106] In another exemplary embodiment, the inter-core communication device further includes a cache module. The target address includes multiple sub-queues, and different sub-queues correspond to different task priorities. The data storage area of each sub-queue is a circular buffer; the cache module is configured to obtain the task priority corresponding to the task to be processed in the following manner; buffer the data to be transmitted corresponding to the task to be processed in the sub-queue corresponding to the task priority in the target address.

[0107] In another exemplary embodiment, after generating an interrupt according to the target interrupt generation policy and sending the interrupt to the second processor when the write address corresponding to the task to be processed matches the target address, the sending module 830 is further configured to clear the interrupt after detecting that the second processor performs a read operation at the target address.

[0108] In another exemplary embodiment, the inter-core communication device further includes an adjustment module. The adjustment module is configured to obtain the environmental state and task requirements of the multi-core system-on-chip; adjust the interrupt control parameters of the interrupt controller according to the environmental state and task requirements.

[0109] In another exemplary embodiment, the bus of the multi-core system-on-chip is an AMBA bus, and the target interrupt generation policy is mounted on the AMBA bus.

[0110] It should be noted that the inter-core communication device provided in the above embodiments and the inter-core communication method of the multi-core system-on-chip provided in the above embodiments belong to the same concept. The specific manners in which each module and unit perform operations have been described in detail in the method embodiments and will not be elaborated here. In practical applications, the inter-core communication device provided in the above embodiments can, according to needs, allocate the above functions to different functional modules, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above. This is not limited here.

[0111] An embodiment of the present application further provides an electronic device, including: one or more processors; a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device implements the inter-core communication method of the multi-core system-on-chip provided in each of the above embodiments.

[0112] Figure 9 A schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application is shown. It should be noted that Figure 9The computer system 900 of the illustrated electronic device is merely an example and shall not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0113] As Figure 9 shown, the computer system 900 includes a Central Processing Unit (CPU) 901, which can perform various appropriate actions and processes according to the program stored in the Read-Only Memory (ROM) 902 or the program loaded from the storage section 908 into the Random Access Memory (RAM) 903, such as executing the method described in the above embodiments. In the RAM 903, various programs and data required for system operation are also stored. The CPU 901, ROM 902, and RAM 903 are connected to each other via a bus 904. An Input / Output (I / O) interface 905 is also connected to the bus 904.

[0114] The following components are connected to the I / O interface 905: an input section 906 including a keyboard, a mouse, etc.; an output section 907 including, for example, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc. and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a model interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 909 performs communication processing via a model such as the Internet. A drive 910 is also connected to the I / O interface 905 as required. A removable medium 911, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 910 as required so that the computer program read from it can be installed into the storage section 908 as required.

[0115] Specifically, according to the embodiments of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments of the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the model via the communication section 909, and / or installed from the removable medium 911. When the computer program is executed by the Central Processing Unit (CPU) 901, various functions defined in the system of the present application are executed.

[0116] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the above two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program included on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0117] Another aspect of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the inter-core communication method of the multi-core system-on-chip as described above. The computer-readable storage medium can be included in the electronic device described in the above embodiments, or can exist separately without being assembled into the electronic device.

[0118] Another aspect of the present application also provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the inter-core communication method of the multi-core system-on-chip provided in the above various embodiments.

[0119] The above content is only a preferred exemplary embodiment of the present application and is not used to limit the implementation of the present application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope required by the claims.

[0120] It should be noted that when the embodiments of the present application are applied to specific products or technologies, such as when obtaining sample data, it is inevitable to obtain the operating parameters of the multi-core system-on-chip. Then, permission or consent from relevant parties is required, and the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions.

Claims

1. An inter-core communication method for a multi-core system-on-chip, characterized in that Including: Obtaining the running parameters of a multi-core system-on-chip when executing a task to be processed; wherein, the running parameters include one or more of the current load condition, data transmission volume, and real-time requirement of the multi-core system-on-chip; Determining a target interrupt generation policy according to the running parameters; wherein, the target interrupt generation policy is used to instruct a first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when writing an operation at a target address; When the write address corresponding to the task to be processed matches the target address, generating an interrupt according to the target interrupt generation policy and sending the interrupt to a second processor; wherein, the first processor and the second processor are processors that cooperate to execute the task to be processed in the multi-core system-on-chip.

2. The method according to claim 1, wherein The target interrupt generation policy includes a first target interrupt generation policy; the determining the target interrupt generation policy according to the running parameters includes: When the current load condition is lower than a first preset load threshold, the data transmission volume is lower than a first preset data volume threshold, and the real-time requirement is lower than a first preset requirement threshold, determining the target interrupt generation policy as the first target interrupt generation policy; Wherein, the target address corresponding to the first target interrupt generation policy is the address of a special register, and when writing an operation at the address of the special register, triggering a preset interrupt controller to generate multiple first-type interrupts simultaneously and sending them to multiple second processors; the meaning of the first-type interrupt is a fixed meaning.

3. The method according to claim 1, wherein The target interrupt generation policy includes a second target interrupt generation policy; the determining the target interrupt generation policy according to the running parameters includes: When the current load condition is not higher than a second preset load threshold, the data transmission volume is lower than a second preset data volume threshold, and the real-time requirement is higher than a second preset requirement threshold, determining the target interrupt generation policy as the second target interrupt generation policy; Wherein, the target address corresponding to the second target interrupt generation policy is the address of a shared memory, and when writing an operation at the address of the shared memory, triggering a preset interrupt controller to generate a second-type interrupt and sending it to the second processor; the meaning of the second-type interrupt is a custom meaning.

4. The method according to any one of claims 1 to 3, characterized in that The target address includes multiple sub-queues, different sub-queues correspond to different task priorities, and the data storage area of each sub-queue is a circular buffer; the method further includes: Obtaining the task priority corresponding to the task to be processed; Caching the data to be transmitted corresponding to the task to be processed in the sub-queue corresponding to the task priority in the target address.

5. The method according to claim 1, wherein After generating an interrupt according to the target interrupt generation policy and sending the interrupt to the second processor when the write address corresponding to the task to be processed matches the target address, the method further includes: Clearing the interrupt after detecting that the second processor reads an operation at the target address.

6. The method according to claim 1, characterized in that The method further includes: Obtaining the environmental state and task requirements of the multi-core system-on-chip; Adjust the interrupt control parameters of the interrupt controller according to the environmental status and task requirements.

7. The method according to claim 1, wherein The bus of the multi-core system-on-chip is an AMBA bus, and the target interrupt generation strategy is mounted on the AMBA bus.

8. An inter-core communication device for a multi-core system-on-chip, characterized in that, Comprising: An acquisition module configured to acquire the operating parameters of the multi-core system-on-chip when executing a to-be-processed task; wherein, the operating parameters include one or more of the current load condition, data transfer volume, and real-time requirement of the multi-core system-on-chip. A determination module configured to determine a target interrupt generation strategy according to the operating parameters; wherein, the target interrupt generation strategy is used to instruct a first processor in the multi-core system-on-chip to trigger a preset interrupt controller to generate an interrupt when writing an operation at a target address. A sending module configured to generate an interrupt according to the target interrupt generation strategy and send the interrupt to a second processor when the write address corresponding to the to-be-processed task matches the target address; wherein, the first processor and the second processor are processors that cooperate to execute the to-be-processed task in the multi-core system-on-chip.

9. An electronic device, characterized in that, Comprising: One or more processors; A storage device for storing one or more programs, which when executed by the one or more processors, cause the electronic device to implement the inter-core communication method of the multi-core system-on-chip according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer-readable instruction is stored thereon, which when executed by a processor of a computer, causes the computer to execute the inter-core communication method of the multi-core system-on-chip according to any one of claims 1 to 7.

Images