FPGA function reconstruction method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an FPGA (Field Programmable Gate Array) function reconstruction method and device, electronic equipment and a storage medium, relates to the technical field of hardware, is applied to an FPGA node controller, and comprises the following steps: receiving a function reconstruction instruction sent by a management server; from a plurality of vFPGAs in the FPGA, a target vFPGA for which the function reconstruction instruction aims is determined, and each vFPGA comprises a part of logic resource blocks in the FPGA; and controlling the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and enabling the target vFPGA to perform function reconstruction based on the target function parameter file. By applying the scheme provided by the embodiment of the invention, FPGA function reconstruction can be realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of hardware technologies, and particularly to an FPGA function reconfiguration method, apparatus, electronic device, and storage medium. Background Art

[0002] In the related art, there may be a need for function reconfiguration during the operation of an FPGA (Field-Programmable Gate Array), that is, it is necessary to update the function of the FPGA. For example, it is necessary to change the function of the FPGA from outputting a square wave to outputting a sine wave, etc. Therefore, a method for reconfiguring the FGPA function needs to be provided. Summary of the Invention

[0003] The purpose of the embodiments of the present invention is to provide an FPGA function reconfiguration method, apparatus, electronic device, and storage medium to achieve FPGA function reconfiguration. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of the present invention provide an FPGA function reconfiguration method, which is applied to an FPGA node controller. The method includes:

[0005] Receiving a function reconfiguration instruction sent by a management server;

[0006] Determining a target vFPGA in multiple vFPGAs in the FPGA that the function reconfiguration instruction is directed to. Each vFPGA includes a part of the logic resource blocks in the FPGA;

[0007] Controlling the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, and causing the target vFPGA to perform function reconfiguration based on the target function parameter file.

[0008] In an embodiment of the present invention, the controlling the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction includes:

[0009] Sending a function reconfiguration instruction to the target vFPGA controller corresponding to the target vFPGA, so that the target vFPGA controller controls the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction. Each vFPGA corresponds to a vFPGA controller.

[0010] In an embodiment of the present invention, the target vFPGA controller is used to parse the function reconfiguration instruction, determine the target vFPGA, and control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction.

[0011] In one embodiment of the present invention, the above-mentioned FPGA node controller and / or the above-mentioned target vFPGA controller are included in the above-mentioned FPGA.

[0012] In one embodiment of the present invention, the parameters of the above-mentioned FPGA node controller are non-adjustable and / or the parameters of the above-mentioned vFPGA are adjustable.

[0013] In one embodiment of the present invention, the above-mentioned FPGA includes a static logic area and a dynamic logic area. The function of the static logic area cannot be dynamically configured, and the function of the dynamic logic area can be dynamically configured.

[0014] In one embodiment of the present invention, before receiving the function reconstruction instruction sent by the above-mentioned receiving management server, the above-mentioned FPGA has been initialized and has an initial function.

[0015] In one embodiment of the present invention, the above-mentioned method further includes:

[0016] In the case of receiving the completion confirmation information sent after the above-mentioned target vFPGA completes function reconstruction, it is determined that the above-mentioned target vFPGA has completed function reconstruction.

[0017] In one embodiment of the present invention, after determining that the above-mentioned target vFPGA has completed function reconstruction in the case of receiving the completion confirmation information sent after the above-mentioned target vFPGA completes function reconstruction, it further includes:

[0018] Send a completion confirmation information to the above-mentioned management server so that the above-mentioned management server determines that the above-mentioned target vFPGA has completed function reconstruction.

[0019] In a second aspect, an embodiment of the present invention provides an FPGA function reconstruction method applied to a management server. The above-mentioned method includes:

[0020] Send a function reconstruction instruction to the FPGA node controller, so that the above-mentioned FPGA node controller determines the target vFPGA targeted by the above-mentioned function reconstruction instruction from multiple vFPGAs in the FPGA, and makes the above-mentioned FPGA node controller control the above-mentioned target vFPGA to read the target function parameter file indicated by the above-mentioned function reconstruction instruction, and makes the above-mentioned target vFPGA perform function reconstruction based on the above-mentioned target function parameter file; wherein, each vFPGA includes a part of the logic resource blocks in the above-mentioned FPGA;

[0021] Receive the completion confirmation information sent by the above-mentioned FPGA node controller, and determine that the above-mentioned target vFPGA has completed function reconstruction.

[0022] In one embodiment of the present invention, the above-mentioned FPGA node controller is included in the above-mentioned FPGA.

[0023] Thirdly, an embodiment of the present invention provides an FPGA function reconstruction device, which is applied to an FPGA node controller. The device includes:

[0024] A receiving module, configured to receive a function reconstruction instruction sent by a management server;

[0025] A determining module, configured to determine a target vFPGA in multiple vFPGAs in the FPGA for the function reconstruction instruction, and each vFPGA includes a part of the logic resource blocks in the FPGA;

[0026] A control execution module, configured to control the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and enable the target vFPGA to perform function reconstruction based on the target function parameter file.

[0027] In an embodiment of the present invention, the control execution module is specifically configured to:

[0028] Send a function reconstruction instruction to a target vFPGA controller corresponding to the target vFPGA, so that the target vFPGA controller controls the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, and perform function reconstruction based on the target function parameter file. Each vFPGA corresponds to a vFPGA controller.

[0029] In an embodiment of the present invention, the target vFPGA controller is configured to parse the function reconstruction instruction, determine the target vFPGA, and control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction.

[0030] In an embodiment of the present invention, the FPGA node controller and / or the target vFPGA controller is included in the FPGA.

[0031] In an embodiment of the present invention, the parameters of the FPGA node controller are non-adjustable and / or the parameters of the vFPGA are adjustable.

[0032] In an embodiment of the present invention, the FPGA includes a static logic area and a dynamic logic area. The function of the static logic area cannot be dynamically configured, and the function of the dynamic logic area can be dynamically configured.

[0033] In an embodiment of the present invention, before receiving the function reconstruction instruction sent by the management server, the FPGA has been initialized and has an initial function.

[0034] In an embodiment of the present invention, the device further includes:

[0035] A completion confirmation module, configured to determine that the target vFPGA has completed functional reconstruction when receiving the completion confirmation information sent after the above-mentioned target vFPGA has completed functional reconstruction.

[0036] In an embodiment of the present invention, the above-mentioned device further includes:

[0037] A completion confirmation information sending module, configured to send completion confirmation information to the above-mentioned management server, so that the above-mentioned management server determines that the target vFPGA has completed functional reconstruction.

[0038] Fourthly, an embodiment of the present invention provides an FPGA functional reconstruction device, which is applied to a management server. The above-mentioned device includes:

[0039] A functional reconstruction instruction sending module, configured to send a functional reconstruction instruction to an FPGA node controller, so that the above-mentioned FPGA node controller determines a target vFPGA targeted by the functional reconstruction instruction from multiple vFPGAs in the FPGA, and enables the above-mentioned FPGA node controller to control the target vFPGA to read a target function parameter file indicated by the functional reconstruction instruction, and enables the target vFPGA to perform functional reconstruction based on the target function parameter file; wherein, each vFPGA includes a part of the logic resource blocks in the FPGA.

[0040] A receiving and confirmation module, configured to receive the completion confirmation information sent by the above-mentioned FPGA node controller and determine that the target vFPGA has completed functional reconstruction.

[0041] In an embodiment of the present invention, the above-mentioned FPGA node controller is included in the above-mentioned FPGA.

[0042] Fifthly, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the above-mentioned processor, communication interface, and memory complete communication with each other through the communication bus;

[0043] The memory is used to store a computer program;

[0044] The processor is configured to implement the method steps of any one of the first aspect when executing the program stored on the memory.

[0045] Sixthly, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the above-mentioned processor, communication interface, and memory complete communication with each other through the communication bus;

[0046] The memory is used to store a computer program;

[0047] A processor, when executing a program stored in a memory, implements the method steps of any one of the second aspect.

[0048] In a seventh aspect, an embodiment of the present invention provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method steps of any one of the first aspect or the second aspect are implemented.

[0049] Beneficial effects of the embodiments of the present invention:

[0050] An embodiment of the present invention provides an FPGA function reconfiguration method, which is applied to an FPGA node controller. The method includes: receiving a function reconfiguration instruction sent by a management server; determining a target vFPGA (Virtual Field-Programmable Gate Array) in multiple vFPGAs in the FPGA that the function reconfiguration instruction targets, and each vFPGA includes a part of the logic resource blocks in the FPGA; controlling the target vFPGA to read a target function parameter file indicated by the function reconfiguration instruction, and enabling the target vFPGA to perform function reconfiguration based on the target function parameter file.

[0051] As can be seen from the above, in the solution provided by the embodiment of the present invention, after receiving the function reconfiguration instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, and then the target vFPGA can perform function reconfiguration based on the target function parameter file, and the entire function reconfiguration process is rapid. Moreover, when applying the solution provided by the embodiment of the present invention for FPGA function reconfiguration, there is no need to perform function reconfiguration on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA as needed, that is, flexible configuration of the function reconfiguration area in the FPGA can be achieved. In addition, when applying the solution provided by the embodiment of the present invention for FPGA function reconfiguration, there is no need to use professional tools such as PlanAhead required in related technologies, the process of implementing function reconfiguration is simple, and the application range is wide. Description of the Drawings

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0053] Figure 1 It is a schematic flowchart of the first FPGA function reconfiguration method provided by the embodiment of the present invention;

[0054] Figure 2 Schematic diagram of the timing for functional reconfiguration of the target vFPGA in the embodiments of the present invention;

[0055] Figure 3 Schematic flow diagram of the second FPGA functional reconfiguration method provided by the embodiments of the present invention;

[0056] Figure 4 Schematic flow diagram of the third FPGA functional reconfiguration method provided by the embodiments of the present invention;

[0057] Figure 5 Schematic flow diagram of the fourth FPGA functional reconfiguration method provided by the embodiments of the present invention;

[0058] Figure 6 Schematic diagram of the system architecture design for FPGA functional reconfiguration provided by the embodiments of the present invention;

[0059] Figure 7 Schematic diagram of the logical architecture of an FPGA node controller provided by the embodiments of the present invention;

[0060] Figure 8 Schematic flow diagram of the signaling interaction in FPGA functional reconfiguration provided by the embodiments of the present invention;

[0061] Figure 9 Schematic flow diagram of the fifth FPGA functional reconfiguration method provided by the embodiments of the present invention;

[0062] Figure 10 Schematic diagram of the structure of the first FPGA functional reconfiguration device provided by the embodiments of the present invention;

[0063] Figure 11 Schematic diagram of the structure of the second FPGA functional reconfiguration device provided by the embodiments of the present invention;

[0064] Figure 12 Schematic diagram of the structure of the third FPGA functional reconfiguration device provided by the embodiments of the present invention;

[0065] Figure 13 Schematic diagram of the structure of the fourth FPGA functional reconfiguration device provided by the embodiments of the present invention;

[0066] Figure 14 Schematic diagram of the structure of an electronic device provided by the embodiments of the present invention;

[0067] Figure 15 Schematic diagram of the structure of another electronic device provided by the embodiments of the present invention. Detailed implementation manners

[0068] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art based on the present invention belong to the scope of protection of the present invention.

[0069] In the process of FPGA function reconfiguration based on the EAPR (Early Access Partial Reconfiguration) design in related technologies, not only conventional FPGA development tools are used, but also PlanAhead professional tools are required, making the process of FPGA function reconfiguration relatively complex; and the use of related professional tools makes the FPGA function reconfiguration based on the EAPR design have certain limitations and the application scope is restricted.

[0070] To solve the above problems, the embodiments of the present invention provide an FPGA function reconfiguration method, device, electronic device and storage medium, which will be specifically described below.

[0071] First, an FPGA function reconfiguration method provided by the embodiments of the present invention will be described.

[0072] See Figure 1 , which is a schematic flowchart of the first FPGA function reconfiguration method provided by the embodiments of the present invention. This method is applied to an FPGA node controller, and the above method includes the following steps S101 to step S103.

[0073] Step S101: Receive a function reconfiguration instruction sent by a management server.

[0074] In the embodiments of the present invention, the function reconfiguration instruction is sent from other electronic devices outside the FPGA node controller to the FPGA node controller. In one example, the above other electronic device that sends the function reconfiguration instruction can be called a management server, and the management server can be an electronic device with computing capabilities, such as a computer, etc.

[0075] Step S102: Determine the target vFPGA in the multiple vFPGAs in the FPGA for which the above function reconfiguration instruction is directed.

[0076] Wherein, each vFPGA includes some logic resource blocks in the above FPGA.

[0077] In an embodiment of the present invention, the logic resource blocks in an FPGA chip are pre-divided, so as to form at least one vFPGA in one FPGA. In one example, a plurality of vFPGAs are formed by partitioning in one FPGA chip, and the memories between the vFPGAs are isolated from each other, and each vFPGA can be configured and used separately.

[0078] The FPGA node controller analyzes the received function reconfiguration instruction, so as to determine the logical address of the target vFPGA, that is, determine the target vFPGA targeted by the above function reconfiguration instruction.

[0079] Step S103: Control the above target vFPGA to read the target function parameter file indicated by the above function reconfiguration instruction, and cause the above target vFPGA to perform function reconfiguration based on the above target function parameter file.

[0080] After the FPGA node controller determines the target vFPGA, it forwards the above function reconfiguration instruction, so that the target vFPGA receives the above function reconfiguration instruction. The target vFPGA reads the target function parameter file according to the received function reconfiguration instruction, and performs corresponding function reconfiguration according to the read information.

[0081] In one example, the pre-set function parameter file is stored in the configuration memory in advance. The configuration memory can be located inside the FPGA or outside the FPGA. The target vFPGA accesses the configuration memory according to the received function reconfiguration instruction to apply for obtaining the target function parameter file in the function parameter file; then, the configuration memory sends the target function parameter file to the target vFPGA, and the target vFPGA reads the content of the target function parameter file and performs relevant settings based on the target function parameter file to complete the function reconfiguration.

[0082] In an embodiment of the present invention, before the above step S101, the above FPGA has been initialized and has an initial function. Therefore, the above target vFPGA has been initialized and has an initial function before performing function reconfiguration.

[0083] Exemplarily, before performing function reconfiguration, the initial function of the target vFPGA is to output a sine wave waveform. After completing the function reconfiguration, the target vFPGA outputs a square wave waveform; in addition, after completing the function reconfiguration, the parameters and files related only to the output of the sine wave waveform used by the target vFPGA will be cleared.

[0084] Of course, the initial function of the target vFPGA before functional reconfiguration is not limited to outputting a sine wave waveform. The initial function of the target vFPGA can also be to output other types of waveforms, such as a sawtooth wave. Moreover, if based on other target function parameter files containing different information, after completing the functional reconfiguration, the target vFPGA can also have other types of functions, such as being able to output other types of waveforms. The embodiments of the present invention do not limit this.

[0085] In one embodiment of the present invention, the above-mentioned FPGA includes a static logic area and a dynamic logic area. The function of the above-mentioned static logic area cannot be dynamically configured, and the function of the above-mentioned dynamic logic area can be dynamically configured.

[0086] Specifically, for an FPGA chip, before actually using the FPGA chip, first make a plan to divide the hardware resources of the FPGA chip into a static logic area and a dynamic logic area. Among them, the function of the static logic area cannot be dynamically configured, including data interfaces, configuration interfaces, peripheral interfaces, soft cores, etc. The function of the dynamic logic area can be dynamically configured, including modulation and demodulation processes, signal processing processes, etc. Specifically, the above-mentioned FPGA node controller is in the above-mentioned static logic area, and the vFPGA is in the above-mentioned dynamic logic area.

[0087] Since the above-mentioned FPGA node controller is in the above-mentioned static logic area and the vFPGA is in the above-mentioned dynamic logic area, in one embodiment of the present invention, the parameters of the above-mentioned FPGA node controller cannot be adjusted and / or the parameters of the above-mentioned vFPGA can be adjusted, that is, in one case, the parameters of the above-mentioned FPGA node controller cannot be adjusted or the parameters of the above-mentioned vFPGA can be adjusted; in another case, the parameters of the above-mentioned FPGA node controller cannot be adjusted and the parameters of the above-mentioned vFPGA can be adjusted. Specifically, since the vFPGA is divided from the logic resource blocks in the FPGA chip, the vFPGA can be configured as needed, so the parameters of the vFPGA can be adjusted.

[0088] Specifically, taking the target vFPGA as an example, which outputs a sine wave waveform before functional reconfiguration and a square wave waveform after functional reconfiguration, it can be as Figure 2 shown, which is the timing schematic diagram of the target vFPGA performing functional reconfiguration in the embodiments of the present invention. From Figure 2 it can be seen that the process of the target vFPGA performing functional reconfiguration can be divided into the following stages:

[0089] (1) During the time from T0 to T1, the target vFPGA is initialized. During this period, the target vFPGA is in the initialization function stage.

[0090] (2) During the time period from T1 to T2, the target vFPGA configures a sine wave waveform file, that is, the initial function of the target vFPGA is to output a sine wave waveform. During this period, the relevant parameters and files of the functions previously used by the target vFPGA will be cleared, and other parts of the FPGA chip except the target vFPGA are not affected.

[0091] (3) During the time period from T2 to T3, the target vFPGA outputs a sine wave waveform. During this period, the functions of other parts of the FPGA chip except the target vFPGA remain unchanged.

[0092] (4) During the time period from T3 to T4, the target vFPGA configures a square wave waveform file, that is, the function reconstruction of the target vFPGA is to make the target vFPGA output a square wave waveform. The target function parameter file obtained by the target vFPGA contains the square wave waveform file. Thus, the target vFPGA can configure the square wave waveform file. During this period, the relevant parameters and files of the functions previously used by the target vFPGA before stage (4) will be cleared, and other parts of the FPGA chip except the target vFPGA are not affected.

[0093] (5) During the time period from T4 to T5, the target vFPGA outputs a square wave waveform. During this period, the functions of other parts of the FPGA chip except the target vFPGA remain unchanged.

[0094] As can be seen from the above, in the solution provided by the embodiment of the present invention, after receiving the function reconstruction instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, so that the target vFPGA can perform function reconstruction based on the target function parameter file, and the whole process of function reconstruction is rapid. Moreover, when applying the solution provided by the embodiment of the present invention to perform FPGA function reconstruction, there is no need to perform function reconstruction on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconstruction area in the FPGA can be realized. In addition, when applying the solution provided by the embodiment of the present invention to perform FPGA function reconstruction, there is no need to use professional tools such as PlanAhead required in related technologies, and the process of realizing function reconstruction is simple and the application range is wide.

[0095] In an embodiment of the present invention, a vFPGA controller is used to directly control the vFPGA. Refer to Figure 3 , which is a schematic flowchart of the second FPGA function reconstruction method provided by the embodiment of the present invention. This method is applied to the FPGA node controller. Compared with the embodiment shown in Figure 1 , the above step S103 can be implemented by the following step S103A.

[0096] Step S103A: Send a function reconfiguration instruction to the target vFPGA controller corresponding to the above-mentioned target vFPGA, so that the above-mentioned target vFPGA controller controls the above-mentioned target vFPGA to read the target function parameter file indicated by the above-mentioned function reconfiguration instruction, and perform function reconfiguration based on the above-mentioned target function parameter file.

[0097] In the embodiments of the present invention, each vFPGA corresponds to a vFPGA controller. Exemplarily, if there are 5 vFPGAs, there will be 5 vFPGA controllers, and in this case, there is a one-to-one correspondence between the vFPGA and the vFPGA controller. The FPGA node controller parses the received function reconfiguration instruction, determines the logical address of the target vFPGA controller corresponding to the target vFPGA, and sends the function reconfiguration instruction to the target vFPGA controller.

[0098] In an embodiment of the present invention, the above-mentioned target vFPGA controller is used to parse the above-mentioned function reconfiguration instruction, determine the target vFPGA, and control the above-mentioned target vFPGA to read the target function parameter file indicated by the above-mentioned function reconfiguration instruction. Specifically, after receiving the function reconfiguration instruction, the target vFPGA controller parses the function reconfiguration instruction, confirms the logical address of the target vFPGA, and sends the function reconfiguration instruction to the target vFPGA. Then the target vFPGA can read the target function parameter file according to the received function reconfiguration instruction, and perform function reconfiguration based on the read target function parameter file.

[0099] As can be seen from the above, in the solution provided by the embodiments of the present invention, the vFPGA controller is used to directly control the vFPGA. The FPGA node controller sends the function reconfiguration instruction to the target vFPGA controller, and then the target vFPGA controller sends the function reconfiguration instruction to the target vFPGA, enabling the target vFPGA to finally complete the function reconfiguration.

[0100] In an embodiment of the present invention, the above-mentioned FPGA node controller and / or the above-mentioned target vFPGA controller are included in the FPGA. In one case, the FPGA node controller and the target vFPGA controller are integrated on the same FPGA chip, which is convenient for device deployment in actual applications; in another case, one of the above-mentioned target vFPGA controller and the above-mentioned FPGA node controller is included in the FPGA.

[0101] Specifically, since each vFPGA corresponds to a vFPGA controller, the parameters of the vFPGA controller can also be adjusted.

[0102] Exemplarily, there are 5 vFPGAs, numbered 1, 2, 3, 4, and 5 respectively; there are 5 vFPGA controllers, numbered a, b, c, d, and e respectively. In one case, the vFPGA numbered 1 corresponds to the vFPGA controller numbered a, and the parameters of the vFPGA and / or vFPGA controller can be adjusted as needed. For example, after adjustment, the vFPGA numbered 1 corresponds to the vFPGA controller numbered c.

[0103] After the target vFPGA completes the function reconstruction, it can return a confirmation message indicating that the function reconstruction has been completed, enabling the relevant control devices at the front end to confirm that the FPGA function reconstruction has been completed. Refer to Figure 4 , which is a schematic flowchart of the third FPGA function reconstruction method provided by the embodiments of the present invention. This method is applied to the FPGA node controller. Compared with Figure 1 the embodiment shown, it further includes the following step S104.

[0104] Step S104: When receiving the completion confirmation message sent after the above-mentioned target vFPGA completes the function reconstruction, determine that the above-mentioned target vFPGA has completed the function reconstruction.

[0105] Specifically, after the target vFPGA completes the function reconstruction based on the target function parameter file, it will return a completion confirmation message. After this completion confirmation message is received by the FPGA node controller, the FPGA node controller will confirm that the target vFPGA has completed the function reconstruction.

[0106] As can be seen from the above, in the solution provided by the embodiments of the present invention, after the target vFPGA completes the function reconstruction, it returns a completion confirmation message, and the FPGA node controller receives this completion confirmation message, and can determine that the target vFPGA has completed the function reconstruction.

[0107] Refer to Figure 5 , which is a schematic flowchart of the fourth FPGA function reconstruction method provided by the embodiments of the present invention. This method is applied to the FPGA node controller. Compared with Figure 4 the embodiment shown, it further includes the following step S105.

[0108] Step S105: Send a completion confirmation message to the above-mentioned management server to enable the above-mentioned management server to determine that the above-mentioned target vFPGA has completed the function reconstruction.

[0109] After receiving the completion confirmation message sent by the target vFPGA, the FPGA node controller will send a completion confirmation message to the above-mentioned management server. After receiving the completion confirmation message sent by the FPGA node controller, the above-mentioned management server will be able to determine that the above-mentioned target vFPGA has completed the function reconstruction.

[0110] As can be seen from the above, in the solution provided by the embodiments of the present invention, after the target vFPGA completes the function reconstruction, it returns a completion confirmation message. The FPGA node controller receives the completion confirmation message and sends the completion confirmation message to the management server, enabling the management server to confirm that the target vFPGA has completed the function reconstruction.

[0111] In one embodiment of the present invention, for FPGA function reconstruction, the above-mentioned management server, the above-mentioned FPGA node controller, and the above-mentioned vFPGA controller are used, and different levels of definitions are made for the entire system for FPGA function reconstruction. Refer to Figure 6 , which is a schematic diagram of the system architecture design for FPGA function reconstruction provided by the embodiments of the present invention.

[0112] From Figure 6 it can be seen that the system architecture for FPGA function reconstruction includes a management and control layer, a function layer, and a resource layer. Among them, the resource layer includes multiple vFPGAs. In addition, the resource layer may include multiple FPGAs; the function layer stores function files for executing different functions, such as: a demodulation function file for executing the demodulation function, a scrambling function file for executing the scrambling function, and an encoding function file for executing the encoding function. Of course, the functions that the function layer can implement are not limited to Figure 6 the three functions in the function layer shown, and the function layer may also store other function files to implement other related functions. Specifically, the function layer is located on an electronic device with computing and storage capabilities.

[0113] Figure 6 The management and control layer in [[ ]] includes a management server, an FPGA node controller, and a vFPGA controller, and the management and control layer is used to manage and control the resource layer and the function layer.

[0114] Among them, the vFPGA controller is responsible for data reading and writing of the vFPGA, including memory address data conversion, forming an FPGA resource pool, parsing and reporting function configuration data, and driving the hardware to enable the vFPGA to perform function reconstruction.

[0115] The FPGA node controller is scheduled and managed by the management server, receives and parses the function reconstruction instruction from the management server, and issues the instruction to the vFPGA controller. The FPGA node controller is also responsible for submitting the working status of the vFPGA, the resource usage of the FPGA resource pool, etc. to the management server.

[0116] The management server is responsible for the operation management of the entire FPGA function reconstruction process, such as monitoring the usage of vFPGA resources, storage resources, etc., and issuing function reconstruction instructions.

[0117] In one embodiment of the present invention, the schematic diagram of the logical architecture of the FPGA node controller can be asFigure 7 as shown. From Figure 7 As can be seen, in the logical architecture of the FPGA node controller, it includes at least one of the following components: system management client, system monitor, FPGA hardware manager, database, vFPGA resource pool, FPGA memory resource pool, FPGA queue resource pool.

[0118] Among them, the system management client is used to receive and process relevant operation requests from the management server, and implement the above-mentioned relevant operation requests through the specific hardware resources of the FPGA chip. The system management client is also used to extract the monitoring result data of the system monitor from the database and send the extracted monitoring result data to the management server.

[0119] The system monitor is used to check the working state of the FPGA, the running situation of the vFPGA, and the RoCEv2Stack traffic statistics. The system monitor stores the relevant data obtained from the check in the database for use by other components. Among them, RoCE refers to RDMA over Converged Ethernet, that is, RDMA on the converged Ethernet, which is a protocol that applies the RDMA technology to the Ethernet; and RDMA refers to Remote Direct Memory Access, that is, remote direct data access; RoCEv2 refers to the second version of RoCE, which is a network layer protocol that can implement routing functions and allows hosts in different broadcast domains to access. In the embodiment of the present invention, RoCEv2 can enable the vFPGA to access the configuration memory; Stack is a basic data structure, characterized by last in first out.

[0120] The hardware resource pools including the vFPGA resource pool, the FPGA memory resource pool, and the FPGA queue resource pool are used to manage and record the usage of the FPGA hardware resources. The FPGA hardware resources mentioned here include: the reconfigurable area in the FPGA, the QP (Queue Pair) resources in the RoCEv2Stack, and the FPGA physical memory resources. Among them, QP adopts a queue structure and is a virtual interface between hardware and software, which stores the tasks sent by software to hardware in sequence.

[0121] The FPGA hardware manager is used to interact with the underlying driver and implement the allocated hardware resources on the specific hardware through the driver. Specifically, the above-mentioned underlying drivers include: vFPGA controller driver, RoCEv2Stack driver, Xilinx PCAP (Packet Capeure) driver, where Xilinx is the manufacturer name: Xilinx.

[0122] In an embodiment of the present invention, the process of FPGA function reconstruction is divided into the following three stages:

[0123] (1) Planning stage: For the FPGA chip to be reconfigured for FPGA functions, the FPGA hardware resources are divided into a static logic area and a dynamic logic area. Among them, the functions of the static logic area cannot be dynamically configured, that is, the parameters of the static logic area cannot be adjusted, including data interfaces, configuration interfaces, peripheral interfaces, soft cores, etc. The functions of the dynamic logic area can be dynamically configured, that is, the parameters of the dynamic logic area can be adjusted, including modulation and demodulation processes, signal processing processes, etc. Specifically, the FPGA node controller is in the static logic area, and the vFPGA controller and vFPGA are in the dynamic logic area.

[0124] (2) Initialization stage: For the FPGA chip to be reconfigured for FPGA functions, both the static logic area and the dynamic logic area in the FPGA are configured to enable the target vFPGA to have a preset initial function. Exemplarily, the initial function of the target vFPGA is to output a sine wave waveform.

[0125] (3) Operation stage: The management server issues a function reconfiguration instruction, enabling the target vFPGA to finally complete the function reconfiguration. Specifically, for the signaling interaction situation in the operation stage, please refer to Figure 8 , which is a schematic diagram of the signaling interaction in FPGA function reconfiguration provided by an embodiment of the present invention. As can be seen from Figure 8 , the above-mentioned signaling interaction process can be described as follows:

[0126] (a) The management server sends a function reconfiguration instruction to the FPGA node controller.

[0127] (b) The FPGA node controller parses the function reconfiguration instruction, determines the logical address of the target vFPGA controller, and sends the function reconfiguration instruction to the target vFPGA controller.

[0128] (c) The target vFPGA controller parses the function reconfiguration instruction, determines the logical address of the target vFPGA, and sends the function reconfiguration instruction to the target vFPGA.

[0129] (d) The target vFPGA parses the function reconfiguration instruction and sends a request for obtaining the target function parameter file to the configuration memory.

[0130] (e) The configuration memory sends the target function parameter file to the target vFPGA.

[0131] (f) After the target vFPGA completes the target function configuration and realizes the function reconfiguration, it sends a completion confirmation message to the target vFPGA controller.

[0132] (g) The target vFPGA controller sends a completion confirmation message to the FPGA node controller.

[0133] (h) The FPGA node controller sends a completion confirmation message to the management server.

[0134] Specifically, during the process of functional reconstruction of the target vFPGA described above, the functions of other vFPGAs and the static logic area remain unchanged and operate normally.

[0135] Corresponding to the foregoing FPGA functional reconstruction method applied to the FPGA node controller, an embodiment of the present invention further provides an FPGA functional reconstruction method applied to the management server.

[0136] See Figure 9 , which is a schematic flowchart of the fifth FPGA functional reconstruction method provided by the embodiment of the present invention. This method is applied to the management server and includes the following steps S901 and S902.

[0137] Step S901: Send a functional reconstruction instruction to the FPGA node controller, so that the above-mentioned FPGA node controller determines the target vFPGA targeted by the functional reconstruction instruction from multiple vFPGAs in the FPGA, and enables the above-mentioned FPGA node controller to control the target vFPGA to read the target function parameter file indicated by the functional reconstruction instruction, and enables the target vFPGA to perform functional reconstruction based on the target function parameter file.

[0138] Wherein, each vFPGA includes a part of the logic resource blocks in the FPGA.

[0139] Step S902: Receive the completion confirmation message sent by the above-mentioned FPGA node controller, and determine that the target vFPGA has completed functional reconstruction.

[0140] Wherein, the above-mentioned confirmation message is sent by the above-mentioned FPGA node controller when receiving the completion confirmation message sent by the target vFPGA, and the above-mentioned completion confirmation message is sent by the target vFPGA after completing functional reconstruction. According to the received above-mentioned completion confirmation message, the management server can determine that the target vFPGA has completed functional reconstruction.

[0141] As can be seen from the above, in the solution provided by the embodiments of the present invention, after receiving the function reconfiguration instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, so that the target vFPGA can perform function reconfiguration based on the target function parameter file, and the entire function reconfiguration process is rapid. Moreover, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to perform function reconfiguration on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconfiguration area in the FPGA can be realized. In addition, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to use professional tools such as PlanAhead required in related technologies. The process of realizing function reconfiguration is simple and has a wide application range.

[0142] In one embodiment of the present invention, the above FPGA node controller is included in the above FPGA, so that device deployment can be conveniently carried out in practical applications.

[0143] Specifically, for the description of each embodiment in the FPGA function reconfiguration method applied to the management server, reference can be made to the content in the foregoing FPGA function reconfiguration method applied to the FPGA node controller, which will not be elaborated here.

[0144] Corresponding to the foregoing FPGA function reconfiguration method applied to the FPGA node controller, an embodiment of the present invention further provides an FPGA function reconfiguration device applied to the FPGA node controller.

[0145] See Figure 10 , which is a schematic structural diagram of the first FPGA function reconfiguration device provided by the embodiment of the present invention. The device is applied to the FPGA node controller. The above device includes:

[0146] A receiving module 1001, configured to receive a function reconfiguration instruction sent by the management server.

[0147] A determining module 1002, configured to determine, from multiple vFPGAs in the FPGA, the target vFPGA targeted by the function reconfiguration instruction, and each vFPGA includes a part of the logic resource blocks in the FPGA.

[0148] A control execution module 1003, configured to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, and cause the target vFPGA to perform function reconfiguration based on the target function parameter file.

[0149] As can be seen from the above, in the solution provided by the embodiment of the present invention, after receiving the function reconfiguration instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, so that the target vFPGA can perform function reconfiguration based on the target function parameter file, and the entire function reconfiguration process is rapid. Moreover, when applying the solution provided by the embodiment of the present invention for FPGA function reconfiguration, it is not necessary to perform function reconfiguration on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA as needed, that is, flexible configuration of the function reconfiguration area in the FPGA can be achieved. In addition, when applying the solution provided by the embodiment of the present invention for FPGA function reconfiguration, it is not necessary to use professional tools such as PlanAhead required in related technologies. The process of realizing function reconfiguration is simple and has a wide application range.

[0150] In one embodiment of the present invention, the above control execution module 1003 is specifically configured to:

[0151] Send a function reconfiguration instruction to the target vFPGA controller corresponding to the above target vFPGA, so that the above target vFPGA controller controls the above target vFPGA to read the target function parameter file indicated by the above function reconfiguration instruction, and perform function reconfiguration based on the above target function parameter file. Each vFPGA corresponds to a vFPGA controller.

[0152] As can be seen from the above, in the solution provided by the embodiment of the present invention, the vFPGA controller is used to directly control the vFPGA. The FPGA node controller sends the function reconfiguration instruction to the target vFPGA controller, and then the target vFPGA controller sends the function reconfiguration instruction to the target vFPGA, which can enable the target vFPGA to finally complete the function reconfiguration.

[0153] In one embodiment of the present invention, the above target vFPGA controller is used to parse the above function reconfiguration instruction, determine the target vFPGA, and control the above target vFPGA to read the target function parameter file indicated by the above function reconfiguration instruction.

[0154] In one embodiment of the present invention, the above FPGA node controller and / or the above target vFPGA controller are included in the above FPGA, which can facilitate device deployment in practical applications.

[0155] In one embodiment of the present invention, the parameters of the above FPGA node controller are not adjustable and / or the parameters of the above vFPGA are adjustable.

[0156] In one embodiment of the present invention, the above FPGA includes a static logic area and a dynamic logic area. The function of the above static logic area cannot be dynamically configured, and the function of the above dynamic logic area can be dynamically configured.

[0157] In one embodiment of the present invention, before receiving the function reconstruction instruction sent by the above receiving management server, the above FPGA has completed initialization and has an initial function.

[0158] See Figure 11 , which is a schematic structural diagram of a second FPGA function reconstruction device provided by an embodiment of the present invention. This device is applied to an FPGA node controller. Compared with the device shown in Figure 10 , it further includes:

[0159] A completion confirmation module 1004, configured to determine that the target vFPGA has completed function reconstruction when receiving the completion confirmation information sent after the target vFPGA has completed function reconstruction.

[0160] As can be seen from the above, in the solution provided by the embodiment of the present invention, after the target vFPGA completes function reconstruction, it returns a completion confirmation information, and the FPGA node controller receives this completion confirmation information, and can determine that the target vFPGA has completed function reconstruction.

[0161] See Figure 12 , which is a schematic structural diagram of a third FPGA function reconstruction device provided by an embodiment of the present invention. This device is applied to an FPGA node controller. Compared with the device shown in Figure 11 , it further includes:

[0162] A completion confirmation information sending module 1005, configured to send a completion confirmation information to the above management server, so that the above management server determines that the target vFPGA has completed function reconstruction.

[0163] As can be seen from the above, in the solution provided by the embodiment of the present invention, after the target vFPGA completes function reconstruction, it returns a completion confirmation information, the FPGA node controller receives this completion confirmation information, and sends a completion confirmation information to the management server, so that the management server can confirm that the target vFPGA has completed function reconstruction.

[0164] Corresponding to the above-mentioned FPGA function reconstruction method applied to the management server, an embodiment of the present invention further provides an FPGA function reconstruction device applied to the management server.

[0165] See Figure 13 , which is a schematic structural diagram of a fourth FPGA function reconstruction device provided by an embodiment of the present invention. This device is applied to the management server and includes:

[0166] The function reconstruction instruction sending module 1301 is configured to send a function reconstruction instruction to the FPGA node controller, so that the FPGA node controller determines a target vFPGA in multiple vFPGAs in the FPGA for the function reconstruction instruction, and enables the FPGA node controller to control the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and enables the target vFPGA to perform function reconstruction based on the target function parameter file; wherein each vFPGA includes some logic resource blocks in the FPGA.

[0167] The receiving and confirmation module 1302 is configured to receive a completion confirmation message sent by the FPGA node controller and determine that the target vFPGA has completed function reconstruction.

[0168] As can be seen from the above, in the solution provided in the embodiment of the present invention, after receiving the function reconstruction instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, and then the target vFPGA can perform function reconstruction based on the target function parameter file, and the entire function reconstruction process is rapid. Moreover, when performing FPGA function reconstruction by applying the solution provided in the embodiment of the present invention, there is no need to perform function reconstruction on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA as needed, that is, flexible configuration of the function reconstruction area in the FPGA can be achieved. In addition, when performing FPGA function reconstruction by applying the solution provided in the embodiment of the present invention, there is no need to use professional tools such as PlanAhead required in related technologies, the process of realizing function reconstruction is simple, and the application range is wide.

[0169] In an embodiment of the present invention, the FPGA node controller is included in the FPGA.

[0170] See Figure 14 , which is a schematic structural diagram of an electronic device provided in an embodiment of the present invention. The electronic device includes: a processor 1401, a communication interface 1402, a memory 1403, and a communication bus 1404. Among them, the processor 1401, the communication interface 1402, and the memory 1403 communicate with each other through the communication bus 1404.

[0171] The memory 1403 is used to store a computer program.

[0172] When the processor 1401 is configured to execute the program stored on the memory 1403, it implements the steps of any one of the foregoing FPGA function reconstruction methods applied to the FPGA node controller.

[0173] As can be seen from the above, in the solution provided by the embodiments of the present invention, after receiving the function reconfiguration instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, so that the target vFPGA can perform function reconfiguration based on the target function parameter file, and the entire function reconfiguration process is rapid. Moreover, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to perform function reconfiguration on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconfiguration area in the FPGA can be achieved. In addition, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to use professional tools such as PlanAhead required in related technologies, and the process of realizing function reconfiguration is simple and has a wide application range.

[0174] See Figure 15 , which is a schematic structural diagram of another electronic device provided by the embodiments of the present invention. The above electronic device includes: a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504. Among them, the processor 1501, the communication interface 1502, and the memory 1503 complete mutual communication through the communication bus 1504.

[0175] The memory 1503 is used to store computer programs.

[0176] When the processor 1501 is used to execute the program stored on the memory 1503, it realizes the steps of any one of the foregoing FPGA function reconfiguration methods applied to the management server.

[0177] As can be seen from the above, in the solution provided by the embodiments of the present invention, after receiving the function reconfiguration instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconfiguration instruction, so that the target vFPGA can perform function reconfiguration based on the target function parameter file, and the entire function reconfiguration process is rapid. Moreover, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to perform function reconfiguration on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconfiguration area in the FPGA can be achieved. In addition, when applying the solution provided by the embodiments of the present invention to perform FPGA function reconfiguration, it is not necessary to use professional tools such as PlanAhead required in related technologies, and the process of realizing function reconfiguration is simple and has a wide application range.

[0178] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0179] The communication interface is used for communication between the above electronic device and other devices.

[0180] The memory may include a Random Access Memory (RAM), and may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0181] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an FPGA or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0182] In another embodiment provided by the present invention, there is also provided a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above FPGA function reconstruction methods applied to the FPGA node controller or the management server are implemented.

[0183] When performing FPGA function reconstruction using the computer program stored in the computer-readable storage medium provided by the embodiments of the present invention, after receiving the function reconstruction instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, so that the target vFPGA can perform function reconstruction based on the target function parameter file, and the entire function reconstruction process is rapid. Moreover, when performing FPGA function reconstruction using the solution provided by the embodiments of the present invention, there is no need to perform function reconstruction on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconstruction area in the FPGA can be achieved. In addition, when performing FPGA function reconstruction using the solution provided by the embodiments of the present invention, there is no need to use professional tools such as PlanAhead required in related technologies, the process of implementing function reconstruction is simple, and the application range is wide.

[0184] In another embodiment provided by the present invention, there is also provided a computer program product containing instructions, which when running on a computer, causes the computer to execute any of the FPGA function reconstruction methods applied to the FPGA node controller or the management server in the above embodiments.

[0185] When performing FPGA function reconstruction using the computer program product provided by the embodiments of the present invention, after receiving the function reconstruction instruction, the FPGA node controller only needs to control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, so that the target vFPGA can perform function reconstruction based on the target function parameter file, and the entire function reconstruction process is rapid. Moreover, when performing FPGA function reconstruction using the solution provided by the embodiments of the present invention, there is no need to perform function reconstruction on the entire FPGA. Only one or more target vFPGAs can be flexibly selected from multiple vFPGAs in the FPGA according to needs, that is, flexible configuration of the function reconstruction area in the FPGA can be achieved. In addition, when performing FPGA function reconstruction using the solution provided by the embodiments of the present invention, there is no need to use professional tools such as PlanAhead required in related technologies, the process of implementing function reconstruction is simple, and the application range is wide.

[0186] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0187] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0188] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the embodiments of the device, electronic device, computer-readable storage medium, and computer program product, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments.

[0189] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included within the protection scope of the present invention.

Claims

1. A method for FPGA functional reconfiguration, characterized in that, Applied to a field programmable gate array (FPGA) node controller, the method includes: Receiving a function reconstruction instruction sent by a management server; Determining, from multiple virtual field programmable gate arrays (vFPGAs) in the FPGA, the target vFPGA targeted by the function reconstruction instruction, where each vFPGA includes a part of the logic resource blocks in the FPGA; Controlling the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, and causing the target vFPGA to perform function reconstruction based on the target function parameter file.

2. The method according to claim 1, wherein The controlling the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction includes: Sending a function reconstruction instruction to the target vFPGA controller corresponding to the target vFPGA, so that the target vFPGA controller controls the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, and each vFPGA corresponds to a vFPGA controller.

3. The method according to claim 2, wherein The target vFPGA controller is used to parse the function reconstruction instruction, determine the target vFPGA, and control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction.

4. The method according to claim 2 or 3, characterized in that, The FPGA node controller and / or the target vFPGA controller is included in the FPGA.

5. The method according to any one of claims 1-3, characterized in that, The parameters of the FPGA node controller are non-adjustable and / or the parameters of the vFPGA are adjustable.

6. The method according to any one of claims 1-3, characterized in that The FPGA includes a static logic area and a dynamic logic area. The function of the static logic area cannot be dynamically configured, and the function of the dynamic logic area can be dynamically configured.

7. The method according to any one of claims 1-3, characterized in that Before receiving the function reconstruction instruction sent by the management server, the FPGA has been initialized and has an initial function.

8. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Determining that the target vFPGA has completed function reconstruction when receiving the completion confirmation information sent after the target vFPGA has completed function reconstruction.

9. The method according to claim 8, characterized in that, After determining that the target vFPGA has completed function reconstruction when receiving the completion confirmation information sent after the target vFPGA has completed function reconstruction, it further includes: Sending a completion confirmation information to the management server, so that the management server determines that the target vFPGA has completed function reconstruction.

10. A method for FPGA functional reconstruction, characterized in that Applied to a management server, the method includes: Sending a function reconstruction instruction to a field programmable gate array (FPGA) node controller, so that the FPGA node controller determines, from multiple virtual field programmable gate arrays (vFPGAs) in the FPGA, the target vFPGA targeted by the function reconstruction instruction, and causes the FPGA node controller to control the target vFPGA to read the target function parameter file indicated by the function reconstruction instruction, and cause the target vFPGA to perform function reconstruction based on the target function parameter file; where each vFPGA includes a part of the logic resource blocks in the FPGA; Receiving the completion confirmation information sent by the FPGA node controller, and determining that the target vFPGA has completed function reconstruction.

11. The method according to claim 10, wherein The FPGA node controller is included in the FPGA.

12. An FPGA function reconfiguration device, characterized in that, Applied to a field programmable gate array (FPGA) node controller, the device includes: A receiving module, configured to receive a function reconstruction instruction sent by a management server; A determining module, configured to determine a target virtual FPGA (vFPGA) in multiple vFPGAs in the FPGA for which the function reconstruction instruction is targeted, each vFPGA including a part of the logic resource blocks in the FPGA; A control execution module, configured to control the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and cause the target vFPGA to perform function reconstruction based on the target function parameter file.

13. An FPGA function reconfiguration device, characterized in that, Applied to a management server, the device includes: A function reconstruction instruction sending module, configured to send a function reconstruction instruction to an FPGA node controller, so that the FPGA node controller determines a target vFPGA in multiple vFPGAs in the FPGA for which the function reconstruction instruction is targeted, and causes the FPGA node controller to control the target vFPGA to read a target function parameter file indicated by the function reconstruction instruction, and cause the target vFPGA to perform function reconstruction based on the target function parameter file; wherein, each vFPGA includes a part of the logic resource blocks in the FPGA; A receiving and confirmation module, configured to receive a completion confirmation message sent by the FPGA node controller and determine that the target vFPGA has completed function reconstruction.

14. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used for storing a computer program; The processor, when executing the program stored on the memory, implements the method steps of any one of claims 1-9.

15. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used for storing a computer program; The processor, when executing the program stored on the memory, implements the method steps of any one of claims 10-11.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the method steps of any one of claims 1-9 or 10-11.

Images