High-speed signal wiring structure and method of chip

Abstract

The invention provides a high-speed signal wiring structure and method of a chip, and relates to the field of chip design. The structure comprises the steps that a first plate capacitor is arranged on any side of a target dielectric layer in a target internal wiring layer where a first high-speed signal line and a second high-speed signal line are located, so that a target capacitance value meeting the requirement is formed; the first plate capacitor comprises a first metal conductor pole plate, a second metal conductor pole plate and a first dielectric layer located between the first metal conductor pole plate and the second metal conductor pole plate. According to the invention, AC capacitance coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line can be realized through the first plate capacitor, placement of layer-changing via holes, surface wiring and capacitors is avoided, impedance consistency of high-speed signal links is increased, utilization rate of PCB layout space is improved, and cost is reduced. And an effective guarantee is provided for high-speed and high-density PCB design.

Description

Technical Field

[0001] This application relates to the field of chip design, and particularly to a high-speed signal routing structure and method for a chip. Background Art

[0002] High-speed signals refer to signals that are transmitted at extremely high speeds in electronic communications, data transmission, and digital systems. Among them, when routing the signal lines for transmitting high-speed signals, internal layer routing is usually adopted to avoid the uncertainty of the surface solder mask and production processing, and the transmission of high-speed signals often adopts a point-to-point method. Among them, according to the requirements of chip characteristics, high-speed signal transmission can be divided into two methods: DC coupling and AC coupling. Among them, AC coupling requires a capacitor with a certain capacitance value to be placed between two interconnected points to ensure normal signal transmission.

[0003] In the prior art, if the high-speed signals interconnected between chips adopt the AC capacitor coupling method, then when routing the signals, the signals need to be led out to the surface layer through via holes for layer change in the internal layer of the stack structure to place the capacitors, and then return to the internal layer through via holes for layer change.

[0004] It can be seen that the composition structure of the existing AC capacitor coupling method is complex. Therefore, designers mainly focus more on the optimization of via holes for layer change and coupling capacitors, and the optimized AC capacitor coupling method still has problems of impedance discontinuity and large occupied space. Summary of the Invention

[0005] The purpose of this application is to provide a high-speed signal routing structure and method for a chip in view of the above deficiencies in the prior art. The layout of the first planar capacitor can avoid via holes for layer change, surface layer routing, and capacitor placement, increase the impedance consistency of the high-speed signal link, improve the utilization rate of the PCB layout space, and provide an effective guarantee for high-speed and high-density PCB design.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, the present invention provides a high-speed signal routing structure for a chip, including: Layout a first planar capacitor on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements; Wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0007] In an alternative embodiment, the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate. The first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

[0008] In an alternative embodiment, a first spacing between the first sub-metal conductor plate and the first signal lines on adjacent two sides meets a first preset spacing requirement; A second spacing between the second sub-metal conductor plate and the second signal lines on adjacent two sides meets the first preset spacing requirement.

[0009] In an alternative embodiment, a second projection area of the second metal conductor plate includes: a first sub-projection area of the first sub-metal conductor plate and a second sub-projection area of the second sub-metal conductor plate, and an area of the second projection area is larger than a sum of areas of the first sub-projection area and the second sub-projection area.

[0010] In an alternative embodiment, the second metal conductor plate is obtained by etching a second metal conductor layer provided on either side of a target dielectric layer in a target internal trace layer.

[0011] In an alternative embodiment, a third spacing between the second metal conductor plate and the third signal lines on adjacent two sides meets a third preset spacing requirement.

[0012] In an alternative embodiment, a thickness and a dielectric constant of the first dielectric layer are determined according to the target capacitance value.

[0013] In an alternative embodiment, the target internal trace layer further includes: a third high-speed signal line and a fourth high-speed signal line. The third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line; Layout a second planar capacitor on either side of a target dielectric layer in the target internal trace layer where the third high-speed signal line and the fourth high-speed signal line are located; Wherein, the second planar capacitor is arranged in a staggered manner with the first planar capacitor. The second planar capacitor includes: a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0014] In an alternative embodiment, the first planar capacitor is arranged on an upper side of the target dielectric layer, and the second planar capacitor is arranged on a lower side of the target dielectric layer; or, the first planar capacitor is arranged on the lower side of the target dielectric layer, and the second planar capacitor is arranged on the upper side of the target dielectric layer.

[0015] In an alternative embodiment, the first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

[0016] Second, the present invention provides a method for high-speed signal routing of a chip, the method comprising: Determine a target internal routing layer where a first high-speed signal line and a second high-speed signal line for arranging a first planar capacitor in a target circuit are located according to an initial stack structure corresponding to the target circuit; Arrange a first planar capacitor on either side of a target dielectric layer in the target internal routing layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements; Wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0017] The beneficial effects of the present application are: In the high-speed signal routing structure and method of a chip provided by an embodiment of the present application, the high-speed signal routing structure includes: arranging a first planar capacitor on either side of a target dielectric layer in a target internal routing layer where a first high-speed signal line and a second high-speed signal line are located to form a target capacitance value that meets the requirements; wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate, realizing an AC capacitance coupling design of high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through the first planar capacitor, avoiding via holes for layer change, surface routing, and placement of capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization rate of the PCB layout space, and providing an effective guarantee for high-speed and high-density PCB design. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic diagram of an existing AC capacitance coupling provided by an embodiment of the present application; Figure 2 It is one of the schematic diagrams of a high-speed signal routing structure of a chip provided by an embodiment of the present application; Figure 3Schematic diagram II of a high-speed signal routing structure for a chip provided by an embodiment of the present application; Figure 4 Schematic diagram III of a high-speed signal routing structure for a chip provided by an embodiment of the present application; Figure 5 Schematic diagram IV of a high-speed signal routing structure for a chip provided by an embodiment of the present application; Figure 6 Schematic diagram V of a high-speed signal routing structure for a chip provided by an embodiment of the present application; Figure 7 A high-speed signal routing method for a chip provided by an embodiment of the present application. Detailed implementation manners

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0022] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0023] To avoid the uncertainties of the surface solder mask and production and processing, high-speed signal routing usually adopts internal layer routing, and the transmission of high-speed signals often adopts a point-to-point method. According to the requirements of chip characteristics, high-speed signal transmission can be divided into two methods: DC coupling and AC coupling. In DC coupling, the signals are directly connected, and no other devices are required between the two interconnected points. In AC coupling, a capacitor with a certain capacitance value (for example, 220 nF) is required to be placed between the two interconnected points to ensure the normal transmission of the signal. Many high-speed signal designs require AC coupling capacitors. For example, PCIe signals require a 220 nF capacitor to be placed at the sending end. If the high-speed signals between chips adopt the AC capacitor coupling method, then when routing the signals, the signals need to be led out to the surface layer through via holes for capacitor placement from the internal layer of the stack structure, and then returned to the internal layer through via holes.

[0024] It can be seen that in the related art, if the high-speed signals for interconnection between chips adopt the AC capacitance coupling method, when routing the signals, it is necessary to lead the signals out to the surface layer through via holes for layer change from the internal layer of the stack structure to place the capacitors, and then return to the internal layer through via holes for layer change.

[0025] Figure 1 This is a schematic diagram of an existing AC capacitance coupling provided by an embodiment of the present application. As Figure 1 shown, in the prior art, if it is necessary to establish an AC coupling capacitor C0 between the first internal layer trace L_1 and the second internal layer trace L_2, it is necessary to set a first via hole for layer change Q1 at the position of the first internal layer trace L_1, and set a first surface layer trace S_1 at the other end of the first via hole for layer change Q1; set a second via hole for layer change Q2 at the position of the second internal layer trace L_2, and set a second surface layer trace S_2 at the other end of the second via hole for layer change Q2, and an AC coupling capacitor C0 can be set between the first surface layer trace S_1 and the second surface layer trace S_2.

[0026] It can be seen that the existing AC capacitance coupling method has the following disadvantages: First, the transmission method is complex, and the signals need to be led out to the surface layer through two-level vias, increasing the number of vias and resulting in an increase in signal transmission discontinuity points; Second, the introduction of vias for layer change will interfere with the utilization rate of other signal layers, and the signal routing on other signal layers must bypass the area of vias for layer change; Third, vias for layer change require a large PCB space to avoid the interference effect in the vertical area of the vias; Fourth, the placement of capacitors on the surface layer increases the layout space of the PCB, wasting the layout space of the PCB and making it impossible to achieve high-density routing.

[0027] Based on the existing AC capacitance coupling method, in order to cope with the increased impedance discontinuity and design risks of the AC coupling method, PCB designers mainly focus more on the optimization of vias for layer change and coupling capacitors, but the optimized AC capacitance coupling method still has problems of impedance discontinuity and large space occupation.

[0028] In view of this, an embodiment of the present application provides a high-speed signal routing structure for a chip, and a first planar capacitor is arranged in the target internal layer where the first high-speed signal line and the second high-speed signal line are located. Through this first planar capacitor, the AC capacitance coupling design of the high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line can be realized, avoiding the placement of vias for layer change, surface layer traces and capacitors, increasing the impedance consistency of the high-speed signal link, improving the utilization rate of the PCB layout space, and providing an effective guarantee for high-speed and high-density PCB design.

[0029] Figure 2 This is one of the schematic diagrams of the high-speed signal routing structure for a chip provided by an embodiment of the present application. Figure 3This is the second schematic diagram of the high-speed signal routing structure of a chip provided by an embodiment of the present application. Among them, as Figure 2 and Figure 3 shown, the high-speed signal routing structure may include: Layout a first planar capacitor on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located to form a target capacitance value that meets the requirements; wherein, the first planar capacitor includes: a first metal conductor plate A, a second metal conductor plate B, and a first dielectric layer D located between the first metal conductor plate A and the second metal conductor plate B.

[0030] Among them, the first high-speed signal line L1 and the second high-speed signal line L2 may be high-speed signal lines in the target circuit, and the target circuit may be a part of the integrated circuit corresponding to the chip.

[0031] Optionally, the first high-speed signal line L1 and the second high-speed signal line L2 may be signal lines that require AC capacitance coupling design, such as high-speed serial signals, high-speed parallel signals, high-speed network signals, differential signal lines, etc. in the target circuit. Of course, it should be noted that if there are two signal lines that require AC capacitance coupling design, for example, the first differential signal line and the second differential signal line, then a corresponding first planar capacitor may be set for each differential signal line.

[0032] The target internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located is also the internal routing layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located in the stacked structure corresponding to the target circuit. To better understand the present application, the following will be described in conjunction with a partial initial stacked structure of the chip.

[0033] Table 1 is a schematic diagram of a partial stacked structure of a chip before adjustment provided by an embodiment of the present application. Table 2 is a schematic diagram of a partial stacked structure of a chip after adjustment provided by an embodiment of the present application. Among them, referring to Table 1, from top to bottom, there are 5 layers, which are in turn: TOP (surface layer), GND02 (inner ground plane), ART03 (signal layer), GND04, ART05. It should be noted that the setting of the stacked structure is not limited to this, and more PCB layers can be laid out according to the complex functions to be realized actually.

[0034] Among them, for the TOP layer, it can be seen that the base copper of the TOP layer is 0.3 oz (about 10 μm), and it may finally reach 1 oz through electroplating (such as copper plating). Moreover, a PP (model 1080) prepreg material with a thickness of 2.632 mil is provided between the TOP layer and the GND02 layer; for ART03, above the ART03 layer is a PP medium with a thickness of 4.688 mil, and the ART03 layer includes: a 1-oz copper foil and a target dielectric layer CoreA with a thickness of 3 mil under the copper foil. Descriptions of other layers can be found in this part of the description and will not be elaborated here. Among them, PP(1035*2) represents 2 prepreg materials of model 1035.

[0035] Optionally, the target internal trace layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located can be the ART03 layer shown in Table 1, but it is not limited thereto.

[0036] Of course, it should be noted that this application does not limit the specific arrangement of the initial stack structure corresponding to the chip here, and it can be flexibly set according to the actual application scenario.

[0037] Table 1

[0038] Table 2

[0039] Based on the above, it should also be noted that for the specific layout of the first planar capacitor, it can be arranged on the upper side of the target dielectric layer in the target internal trace layer or on the lower side of the target dielectric layer in the target internal trace layer, which is not limited here and can be flexibly set according to the actual application scenario. Among them, the target dielectric layer in the target internal trace layer, that is, the existing core material in the target internal trace layer, as shown in Table 2, the target dielectric layer can be CoreA in the ART03 layer.

[0040] In some embodiments, if the target internal trace layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located is the ART03 layer shown in Table 1, optionally, a 0.5-oz copper foil and a first dielectric layer CoreB with a thickness of 1 mil on the copper foil can be added on the upper side of the CoreA core material in the ART03 layer, and the adjusted partial stack structure shown in Table 2 can be obtained.

[0041] Of course, in some embodiments, a 0.5-oz copper foil and a first dielectric layer CoreB with a thickness of 1 mil on the copper foil can also be added on the lower side of the CoreA core material, which is not limited here and can be flexibly set according to the actual available layout space.

[0042] In addition, it should be noted that when specifically laying out the first planar capacitor with a target capacitance value, it should be laid out in the target coupling region of the first high-speed signal line L1 and the second high-speed signal line L2 (where an electrical connection between the first high-speed signal line L1 and the second high-speed signal line L2 needs to be achieved for coupling with the first dielectric layer D and the second metal conductor plate B to form the first planar capacitor), so that the DC component transmitted between the first high-speed signal line L1 and the second high-speed signal line L2 can be blocked through this first planar capacitor, and only the AC signal can be transmitted. It can be seen that the design method of the first planar capacitor provided in the embodiments of the present application can not only achieve the AC capacitance coupling design of the high-speed signals transmitted by the first high-speed signal line L1 and the second high-speed signal line L2, avoid the use of layer-changing vias, surface traces, and the placement of capacitors, increase the impedance consistency of the high-speed signal link, but also improve the utilization rate of the PCB layout space, providing an effective guarantee for the high-speed and high-density PCB design.

[0043] In summary, the embodiments of the present application provide a high-speed signal wiring structure of a chip. The high-speed signal wiring includes: laying out a first planar capacitor on either side of the target dielectric layer in the target internal wiring layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements; wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate, realizing the AC capacitance coupling design of the high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line through this first planar capacitor, avoiding the use of layer-changing vias, surface traces, and the placement of capacitors, increasing the impedance consistency of the high-speed signal link, and improving the utilization rate of the PCB layout space, providing an effective guarantee for the high-speed and high-density PCB design.

[0044] Figure 4 This is the third schematic diagram of the high-speed signal wiring structure of a chip provided by the embodiments of the present application. In an alternative embodiment, the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate. The first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

[0045] Optionally, the target coupling region of the first high-speed signal line L1 and the second high-speed signal line L2 is used for coupling with the first dielectric layer D and the second metal conductor plate B to form the first planar capacitor. In some embodiments, the target coupling region may include a first sub-coupling region and a second sub-coupling region.

[0046] Correspondingly, as Figures 2 to 4As shown, the first metal conductor plate A may include two independent first sub-metal conductor plates A1 and second sub-metal conductor plates A2. Among them, the first sub-metal conductor plate A1 can be electrically connected to the first high-speed signal line L1 to form a first sub-coupling region, and the second sub-metal conductor plate A2 can be electrically connected to the second high-speed signal line L2 to form a second sub-coupling region.

[0047] Optionally, the signal lines on two adjacent sides of the first sub-metal conductor plate A1 can be denoted as the first signal line LA1, and the signal lines on two adjacent sides of the second sub-metal conductor plate A2 can be denoted as the second signal line LA2.

[0048] In an optional embodiment, the first spacing between the first sub-metal conductor plate A1 and the first signal lines LA1 on its two adjacent sides meets the first preset spacing requirement; the second spacing between the second sub-metal conductor plate A2 and the second signal lines LA2 on its two adjacent sides meets the first preset spacing requirement.

[0049] It can be understood that the larger-sized first metal conductor plate A enhances the coupling area with the second metal conductor plate B. However, due to the relatively dense layout of high-speed signal lines, if the size of the first metal conductor plate A is large, it may affect the layout of other adjacent signals on the same layer. Optionally, in order to avoid the influence of the setting of the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2 on the adjacent signal lines in the target internal wiring layer (for example, to avoid crosstalk problems), optionally, it can be set such that the first spacing between the first sub-metal conductor plate A1 and the first signal lines LA1 on its two adjacent sides should meet the first preset spacing requirement, and the second spacing between the second sub-metal conductor plate A2 and the second signal lines LA2 on its two adjacent sides meets the first preset spacing requirement.

[0050] Optionally, the first preset spacing requirement can be determined according to the preset line width of the signal line. For example, in a certain implementation scenario, the preset line width is required to be W, then the first preset spacing requirement can be less than N times the preset line width W. In some embodiments, the value of N can be 3, that is, the first preset spacing requirement is greater than 3W. Of course, it should be noted that the specific setting method is not limited to this, and the value of N can be determined according to the signal rate. Among them, the higher the signal rate, the larger the value of N.

[0051] Refer to Figure 4As shown, taking the first high-speed signal line L1 and the second high-speed signal line L2 as single signal lines as an example for illustration, denote the first spacing as S1 and the second spacing as S2. The first signal lines on the two adjacent sides of the first sub-metal conductor plate A1 are LA1, and the second signal lines on the two adjacent sides of the second sub-metal conductor plate A2 are LA2. The first preset spacing requirement is that it should be greater than 3W. Specifically, when setting the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2, it should be ensured that S1 > 3W and S2 > 3W. Of course, it should be noted that the specific setting method is not limited to this.

[0052] It should be noted that in some embodiments, the first signal line LA1 and the second signal line LA2 on the same side of the first high-speed signal line L1 may be the same signal line. If they are the same signal line, the above layout rules should also be satisfied.

[0053] In an alternative embodiment, the second projection area SD of the second metal conductor plate B includes: the first sub-projection area SA1 of the first sub-metal conductor plate A1 and the second sub-projection area SA2 of the second sub-metal conductor plate A2, and the area of the second projection area SD is greater than the sum of the areas of the first sub-projection area SA1 and the second sub-projection area SA2.

[0054] Among them, for a better understanding of the present application, the relationship between the second metal conductor plate B, the first sub-metal conductor plate A1, and the second sub-metal conductor plate A2 is described from the perspective of the projection area.

[0055] Continue to refer to Figure 4 As shown, it can be seen that the set sizes of the first sub-metal conductor plate A1 and the first sub-metal conductor plate A1 are the same, and the overlapping area of the second projection area SD and the first sub-projection area SA1 is the first sub-projection area SA1, the overlapping area of the second projection area SD and the second sub-projection area SA2 is the second sub-projection area SA2, and the area of the second projection area SD is greater than the sum of the areas of the first sub-projection area SA1 and the second sub-projection area SA2, so as to form a first planar capacitor M1 with a target capacitance value between the first high-speed signal line L1 and the second high-speed signal line L2. Through this first planar capacitor M1, the DC component transmitted between the first high-speed signal line L1 and the second high-speed signal line L2 can be blocked, and only the AC signal can be transmitted.

[0056] In addition, it should be noted that although the effective coupling area of the coupling capacitor formed by the first metal conductor plate A and the second metal conductor plate B is the projection area corresponding to the first metal conductor plate A, in some embodiments, the second projection area of the second projection area SD can still be set to be larger than the first projection area of the first metal conductor plate A, so that the parasitic capacitive effect at high frequencies can be better utilized, and the target capacitance value of the coupling can be more easily achieved.

[0057] For better understanding, the size relationship between the second projection region SD of the second metal conductor plate B and the first projection region of the first metal conductor plate A, the sizes of the first sub-metal conductor plate A1 and the second sub-metal conductor plate A2 can be 0.25 mm * 0.25 mm respectively, and the size of the second metal conductor plate B can be 0.3 mm * 0.8 mm. Of course, the specific setting method is not limited thereto.

[0058] In an alternative embodiment, the second metal conductor plate B is obtained by etching a second metal conductor layer provided on either side of the target dielectric layer in the target internal wiring layer.

[0059] Optionally, the second metal conductor plate B can be generated by an etching operation. For example, a second metal conductor layer can be laid below the first metal conductor plate A (i.e., above the target dielectric layer), and a region with a specific shape is etched to form. This region with a specific shape can be regarded as the second metal conductor plate B. In other words, only the size of the second metal conductor plate B is retained for the second metal conductor layer, and the remaining copper cladding is etched away to avoid affecting the impedance consistency of the signal line. Among them, the specific shape can be a rectangle. Of course, the size of this region is not limited in this application and can be flexibly set according to the actual application scenario.

[0060] In some embodiments, the laid second metal conductor layer can be copper cladding. Of course, it can also be other conductive materials, which can be flexibly set according to the actual application scenario. Optionally, the thickness of the set copper cladding can be 0.5 Oz or 1 / 3 Oz, which is not limited herein.

[0061] Figure 5 This is the fourth schematic diagram of the high-speed signal wiring structure of a chip provided by the embodiments of the present application. In an alternative embodiment, the third spacing between the second metal conductor plate B and the third signal lines on the adjacent two sides meets the requirements of the third preset spacing.

[0062] Among them, as can be seen from the above, the size of the second metal conductor plate should be greater than the sum of the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate. In some embodiments, the third spacing between the second metal conductor plate B and the third signal lines on the adjacent two sides should be greater than half of the preset wiring spacing to avoid affecting other adjacent signals. Among them, the preset wiring spacing can be set according to the preset line width. For example, if W is the preset line width of the signal line, the preset wiring spacing can be 3W.

[0063] Refer to Figure 5As shown, taking the first high-speed signal line L1 and the second high-speed signal line L2 as a pair of signal lines (for example, differential signal lines) for illustration, where the first high-speed signal line L1 includes a first high-speed sub-signal line L1_1 and a second high-speed sub-signal line L1_2, and the second high-speed signal line L2 includes a third high-speed sub-signal line L2_1 and a fourth high-speed sub-signal line L2_2. There is a first sub-coupling region between the first high-speed sub-signal line L1_1 and the third high-speed sub-signal line L2_1, and a second sub-coupling region between the second high-speed sub-signal line L1_2 and the fourth high-speed sub-signal line L2_2. Then, referring to the above embodiments, a first sub-planar capacitor H1 is respectively arranged in the first sub-coupling region, and a second sub-planar capacitor H2 is arranged in the second sub-coupling region. Moreover, the first distance between the first metal conductor plate in each sub-planar capacitor and the adjacent first signal line LA1 meets the requirements of the first preset distance, and the second distance between the second metal conductor plate and the adjacent second signal line LA2 meets the requirements of the first preset distance.

[0064] Optionally, the signal lines on both adjacent sides of the second metal conductor plate B can be denoted as the third signal lines. In some embodiments, as Figure 5 shown, taking the first sub-planar capacitor H1 as an example for illustration, the third distance S3 between the second metal conductor plate in the first sub-planar capacitor H1 and the third signal line LC1 should be greater than half of the preset routing distance (for example, 3W / 2). For the description of other third signal lines (LC2, LC3, LC4), reference can be made to the description of the third signal line LC1, and details will not be repeated here.

[0065] In addition, it should be noted that for Figure 5 the embodiment shown, if the first high-speed signal line L1 and the second high-speed signal line L2 are differential signal lines, the fourth distance S4 between the second metal conductor plate in the first sub-planar capacitor H1 and the second metal conductor plate in the second sub-planar capacitor H2 needs to be consistent with the differential signal line distance (for example, the distance between the first high-speed sub-signal line and the second high-speed sub-signal line).

[0066] In an alternative embodiment, the thickness and dielectric constant of the first dielectric layer D are determined according to the target capacitance value.

[0067] It should be noted that when specifically laying the first dielectric layer, the laid thickness should be relatively small, so that a larger equivalent capacitance can be formed in the coupling region, and the impedance consistency of the signal routing outside the coupling region will not be affected. For example, in some scenarios, although the dielectric constant of the first dielectric layer is relatively large, due to the small thickness, the impact on the signal line impedance will also be very small.

[0068] Among them, the target capacitance value of the first planar capacitor M1 can be determined according to the thickness and dielectric constant of the first dielectric layer D. The purpose of increasing the first dielectric layer D is to generate an insulating cavity for the capacitor, that is, to enable the first metal conductor plate A, the second metal conductor plate B, and the first dielectric layer D to jointly form a capacitor cavity, forming a target capacitance value that meets the requirements, so as to achieve the coupling design.

[0069] It should be noted that the smaller the thickness of the first dielectric layer D and the larger the dielectric constant, the larger the generated target capacitance value.

[0070] For example, if a target capacitance value of 220 nF needs to be generated, optionally, the thickness of the increased first dielectric layer D needs to be less than 1 mil, and the dielectric constant of the first dielectric layer D needs to reach about 30. Of course, the specific setting method is not limited to this.

[0071] Figure 6 This is the fifth schematic diagram of the high-speed signal wiring structure of a chip provided by an embodiment of the present application. In an alternative embodiment, the target internal wiring layer further includes: a third high-speed signal line L3 and a fourth high-speed signal line L4. The third high-speed signal line L3 is adjacent to the first high-speed signal line L1, and the fourth high-speed signal line L4 is adjacent to the second high-speed signal line L2; a second planar capacitor M2 is arranged on either side of the target dielectric layer in the target internal wiring layer where the third high-speed signal line L3 and the fourth high-speed signal line L4 are located.

[0072] Among them, the second planar capacitor M2 is arranged in a staggered manner with the first planar capacitor M1. The second planar capacitor includes: a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0073] Among them, for the specific composition of the second planar capacitor M2, reference can be made to the relevant content of the above-mentioned first planar capacitor W1, which will not be elaborated here.

[0074] It should be noted that the position of the second planar capacitor M2 in the target internal wiring layer can be flexibly set. In some embodiments, the second planar capacitor M2 can be arranged on the upper side of the target dielectric layer in the target internal wiring layer, or can be arranged on the lower side of the target dielectric layer in the target internal wiring layer. This is not limited here and can be flexibly set according to the actual application scenario.

[0075] In some embodiments, the first planar capacitor M1 and the second planar capacitor M2 can be arranged on the same side or different sides of the target dielectric layer in the target internal wiring layer. This is not limited here and can be flexibly described according to the actual application scenario.

[0076] Furthermore, as Figure 6As shown, in some embodiments, when the first planar capacitor M1 and the second planar capacitor M2 are arranged on the same side of the target dielectric layer in the target internal trace layer, the second planar capacitor can be arranged in a staggered manner with respect to the first planar capacitor M1, that is, the adjacent signal coupling regions are arranged in a staggered manner, thereby increasing the space utilization rate.

[0077] In an alternative embodiment, the first planar capacitor M1 and the second planar capacitor M2 can be arranged on opposite sides of the target dielectric layer in the target internal trace layer, the first planar capacitor M1 is arranged on the upper side of the target dielectric layer, and the second planar capacitor M2 is arranged on the lower side of the target dielectric layer; or, the first planar capacitor M1 is arranged on the lower side of the target dielectric layer, and the second planar capacitor M2 is arranged on the upper side of the target dielectric layer.

[0078] It can be understood that by arranging on different sides, the applicability and flexibility of the method of the present application can be increased, providing more choice space for the design of high-speed and high-density PCBs.

[0079] Of course, it should be noted that the present application does not limit the specific layout manner herein, and can be flexibly set according to the actual application scenario.

[0080] In an alternative embodiment, the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate are the same.

[0081] Optionally, in some embodiments, the following method can be referred to determine the coupling area S, the dielectric constant E, and the thickness F of the first dielectric layer D in the first planar capacitor.

[0082] First, according to the application scenarios of the first high-speed signal line L1 and the second high-speed signal line L2, determine the target capacitance value C of the first planar capacitor. Denote the coupling area formed by the first metal conductor plate A and the second metal conductor plate B as S, the dielectric constant of the first dielectric layer D as E, and the thickness as D. During the optimization process, keep the thickness F unchanged, adjust the coupling area D and the dielectric constant E, calculate the capacitance value C0 of the first planar capacitor, and compare whether C0 is equal to the target capacitance value C. If not, the effective coupling area D and the dielectric constant E can be readjusted, and the capacitance value C0 of the first planar capacitor can be calculated until C0 is equal to the target capacitance value C. At this time, the structure of the first planar capacitor that meets the target capacitance value can be obtained. Further, according to the adjusted dielectric constant E at this time, the type of the first dielectric layer D and the coupling area requirements can be determined. Subsequently, according to the determined coupling area S, the dielectric constant E, and the thickness F of the first dielectric layer D, the corresponding first planar capacitor can be arranged on either side of the target dielectric layer in the target internal trace layer where the first high-speed signal line L1 and the second high-speed signal line L2 are located.

[0083] It can be understood that after determining the coupling area of the first planar capacitor, the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate can be set accordingly. For example, the sizes of the first sub-metal conductor plate and the second sub-metal conductor plate can be set to half of the coupling area to achieve rapid setting. Of course, the specific setting method is not limited thereto.

[0084] Figure 7 A high-speed signal routing method for a chip provided by an embodiment of the present application. Among them, the execution subject of this method can be a high-speed signal routing device. The basic principle and the technical effects generated by this method are the same as those of the corresponding structural embodiments described above. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the method embodiment. As Figure 7 shown, this method includes: Step 101: Determine the target internal routing layer where the first high-speed signal line and the second high-speed signal line for laying out the first planar capacitor in the target circuit are located according to the initial stack structure corresponding to the target circuit.

[0085] Among them, the target circuit can be a part of the integrated circuit corresponding to the chip. Optionally, the target internal routing layer can be any routing layer in the initial stack structure corresponding to the target circuit where high-speed signal lines are laid out and AC coupling capacitors need to be implemented between the high-speed signal lines, and there is no limitation here.

[0086] Step 102: Layout the first planar capacitor on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements.

[0087] Among them, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

[0088] For the specific setting method of the first planar capacitor, reference can be made to the relevant content of the foregoing embodiments, and details are not described herein again.

[0089] In an optional implementation manner, the first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate. The first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

[0090] In an optional implementation manner, the first distance between the first sub-metal conductor plate and the first signal lines on adjacent sides meets the first preset distance requirement; The second distance between the second sub-metal conductor plate and the second signal lines on adjacent sides meets the first preset distance requirement.

[0091] In an alternative embodiment, the second projection area of the second metal conductor plate includes: the first sub-projection area of the first sub-metal conductor plate and the second sub-projection area of the second sub-metal conductor plate, and the area of the second projection area is greater than the sum of the areas of the first sub-projection area and the second sub-projection area.

[0092] In an alternative embodiment, the second metal conductor plate is obtained by etching a second metal conductor layer provided on either side of the target dielectric layer in the target internal trace layer.

[0093] In an alternative embodiment, a third spacing between the second metal conductor plate and the third signal lines on adjacent two sides meets a third preset spacing requirement.

[0094] In an alternative embodiment, the thickness and dielectric constant of the first dielectric layer are determined according to the target capacitance value.

[0095] In an alternative embodiment, the target internal trace layer further includes: a third high-speed signal line and a fourth high-speed signal line, the third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line; A second planar capacitor is arranged on either side of the target dielectric layer in the target internal trace layer where the third high-speed signal line and the fourth high-speed signal line are located; Wherein, the second planar capacitor is arranged in a staggered manner with the first planar capacitor, and the second planar capacitor includes: a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

[0096] In an alternative embodiment, the first planar capacitor is arranged on the upper side of the target dielectric layer, and the second planar capacitor is arranged on the lower side of the target dielectric layer; or, the first planar capacitor is arranged on the lower side of the target dielectric layer, and the second planar capacitor is arranged on the upper side of the target dielectric layer.

[0097] In an alternative embodiment, the first sub-metal conductor plate and the second sub-metal conductor plate have the same size.

[0098] Applying the embodiments of the present application, the AC capacitive coupling design of the high-speed signals transmitted by the first high-speed signal line and the second high-speed signal line can be realized through the first planar capacitor, the via holes for layer change, the surface traces and the placement of capacitors are avoided, the impedance consistency of the high-speed signal link is increased, the utilization rate of the PCB layout space is improved, and an effective guarantee is provided for the high-speed and high-density PCB design.

[0099] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0100] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0102] The above integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above software functional units stored in a storage medium include several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute some steps of the methods in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (English: Read-Only Memory, abbreviated as: ROM), random access memories (English: Random Access Memory, abbreviated as: RAM), magnetic disks or optical discs that can store program codes.

[0103] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application. It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A high-speed signal wiring structure for a chip, characterized in that, Including: Layout a first planar capacitor on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements; Wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

2. The high-speed signal wiring structure according to claim 1, wherein The first metal conductor plate includes: a first sub-metal conductor plate and a second sub-metal conductor plate. The first sub-metal conductor plate is electrically connected to the first high-speed signal line, and the second sub-metal conductor plate is electrically connected to the second high-speed signal line.

3. The high-speed signal wiring structure according to claim 2, characterized in that, The first spacing between the first sub-metal conductor plate and the first signal lines on adjacent two sides meets the first preset spacing requirement; The second spacing between the second sub-metal conductor plate and the second signal lines on adjacent two sides meets the first preset spacing requirement.

4. The high-speed signal wiring structure according to claim 2, wherein The second projection area of the second metal conductor plate includes: the first sub-projection area of the first sub-metal conductor plate and the second sub-projection area of the second sub-metal conductor plate, and the area of the second projection area is greater than the sum of the areas of the first sub-projection area and the second sub-projection area.

5. The high-speed signal wiring structure according to claim 1, characterized in that, The second metal conductor plate is obtained by etching a second metal conductor layer provided on either side of the target dielectric layer in the target internal routing layer.

6. The high-speed signal wiring structure according to claim 1, wherein The third spacing between the second metal conductor plate and the third signal lines on adjacent two sides meets the third preset spacing requirement.

7. The high-speed signal wiring structure according to claim 1, characterized in that The thickness and dielectric constant of the first dielectric layer are determined according to the target capacitance value.

8. The high-speed signal wiring structure according to claim 2, characterized in that The sizes of the first sub-metal conductor plate and the second sub-metal conductor plate are the same.

9. The high-speed signal wiring structure according to any one of claims 1-8, characterized in that The target internal routing layer further includes: a third high-speed signal line and a fourth high-speed signal line. The third high-speed signal line is adjacent to the first high-speed signal line, and the fourth high-speed signal line is adjacent to the second high-speed signal line; Layout a second planar capacitor on either side of the target dielectric layer in the target internal routing layer where the third high-speed signal line and the fourth high-speed signal line are located; Wherein, the second planar capacitor is arranged in a staggered manner with the first planar capacitor. The second planar capacitor includes: a third metal conductor plate, a fourth metal conductor plate, and a second dielectric layer located between the third metal conductor plate and the fourth metal conductor plate.

10. The high-speed signal wiring structure according to claim 9, wherein The first planar capacitor is arranged on the upper side of the target dielectric layer, and the second planar capacitor is arranged on the lower side of the target dielectric layer; or, The first planar capacitor is arranged on the lower side of the target dielectric layer, and the second planar capacitor is arranged on the upper side of the target dielectric layer.

11. A high-speed signal routing method for a chip, characterized in that, The method includes: Determine the target internal routing layer where the first high-speed signal line and the second high-speed signal line, which need to layout the first planar capacitor, are located in the target circuit according to the initial stack structure corresponding to the target circuit; Layout a first planar capacitor on either side of the target dielectric layer in the target internal routing layer where the first high-speed signal line and the second high-speed signal line are located to form a target capacitance value that meets the requirements; Wherein, the first planar capacitor includes: a first metal conductor plate, a second metal conductor plate, and a first dielectric layer located between the first metal conductor plate and the second metal conductor plate.

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