Display panel, integrated chip and display device

Abstract

The invention provides a display panel, an integrated chip and a display device.The display panel comprises a first display area and a second display area; the pixel circuit comprises a first pixel circuit and a second pixel circuit, the first pixel circuit is connected with the light-emitting element of the first display area, and the second pixel circuit is connected with the light-emitting element of the second display area; the pixel circuit comprises a driving transistor and a first preset module. One end of the first preset module is connected with the driving transistor. Wherein the control end of a first preset module in the first pixel circuit is used for receiving a first control signal, and the control end of a first preset module in the second pixel circuit is used for receiving a second control signal; in at least one stage of the working process of the display panel, the pulse change frequency of the first control signal is F1, the pulse change frequency of the second control signal is F2, and F1 is not equal to F2. The frequency of receiving the preset signal by different display areas can be adjusted, so that the power consumption is reduced.

Description

[0001] This application is a divisional application of the application with the application number 202211020971.3, the application date of August 24, 2022, and the invention title of "Display Panel, Integrated Chip and Display Device". Technical Field

[0002] The present invention relates to the field of display technologies, and in particular, to a display panel, an integrated chip for providing signals to the display panel, and a display device including the display panel. Background Art

[0003] With the continuous development of display technologies and the increasing requirements of consumers for display panels, the functions integrated in display panels are becoming increasingly numerous. In some scenarios, for the same display panel, different regions are required to have different display functions. For example, the requirements for display regions for games, movie playback, etc. are different from those for display regions for text, time information, etc. By differentiating the design of these different regions, it is possible to achieve better user experience while reducing power consumption and other effects.

[0004] The pixel circuit is a key component in the display panel, which determines the driving current received by the light-emitting elements of the display panel, and thus determines the light-emitting effect of the display panel. When differentiating the design of different regions of the display panel, it is often necessary to separately adjust the respective corresponding pixel circuits for different display regions, so that different display regions can have a good display effect while realizing their respective functions. Summary of the Invention

[0005] In view of this, the present application provides a display panel, an integrated chip for providing signals to the display panel, and a display device including the display panel, which are used to perform regional differential design on different display regions according to their respective functions to realize the functions of different display regions.

[0006] One aspect of the embodiments of the present application provides a display panel, including:

[0007] A first display region and a second display region;

[0008] A pixel circuit, the pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit is connected to the light-emitting elements of the first display region, and the second pixel circuit is connected to the light-emitting elements of the second display region;

[0009] The pixel circuit includes a driving transistor and a first preset module, one end of the first preset module is connected to the driving transistor; wherein,

[0010] The control end of the first preset module in the first pixel circuit is used to receive a first control signal, and the control end of the first preset module in the second pixel circuit is used to receive a second control signal;

[0011] During at least one stage of the operation of the display panel, the pulse change frequency of the first control signal is F1, and the pulse change frequency of the second control signal is F2, where F1≠F2.

[0012] Another aspect of the embodiments of the present application provides an integrated chip for providing signals to the above-mentioned display panel.

[0013] Another aspect of the embodiments of the present application provides a display device including the above-mentioned display panel.

[0014] As can be seen from the above description, the display panel, integrated chip, and display device provided by the embodiments of the present application. The display panel includes a first pixel circuit connected to the light-emitting elements in the first display area and a second pixel circuit connected to the light-emitting elements in the second display area. The control terminal of the first preset module in the first pixel circuit is used to receive the first control signal, and the control terminal of the first preset module in the second pixel circuit is used to receive the second control signal. During at least one stage of the operation of the display panel, the pulse change frequency F1 of the first control signal is not equal to the pulse change frequency F2 of the second control signal. Since one end of the first preset module is connected to the driving transistor for transmitting a preset signal to the driving transistor, when F1≠F2, the frequency at which the first control signal controls the first preset module to turn on and off will be different from the frequency at which the second control signal controls the first preset module to turn on and off. Thus, the frequency at which the first pixel circuit receives the preset signal will be different from the frequency at which the second pixel circuit receives the preset signal. Through such a design, the present application realizes the frequency differentiation of the preset signals received by the first pixel circuit and the second pixel circuit, so as to control the transmission of the preset signal for the first display area and the second display area according to their respective functions, while achieving their respective functions, fully reducing power consumption. Description of the Drawings

[0015] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of another display panel provided by an embodiment of the present application;

[0017] Figure 3 is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of still another display panel provided by an embodiment of the present application;

[0019] Figure 5 is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0020] Figure 6 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0021] Figure 7 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0022] Figure 8 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0023] Figure 9 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0024] Figure 10 It is a comparative schematic diagram of a transistor provided by an embodiment of the present application;

[0025] Figure 11 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0026] Figure 12 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0027] Figure 13 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0028] Figure 14 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0029] Figure 15 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0030] Figure 16 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0031] Figure 17 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0032] Figure 18 It is a schematic diagram of another display panel provided by an embodiment of the present application;

[0033] Figure 19 It is a schematic diagram of yet another display panel provided by an embodiment of the present application;

[0034] Figure 20 It is a schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0036] It should be noted that specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0037] One aspect of the embodiments of the present application provides a display panel, which can be an organic light emitting diode (OLED) display panel, a micro light emitting diode (micro LED) display panel, or other types of display panels. This embodiment does not make special limitations on this.

[0038] Reference Figures 1 - 8 , Figure 1 is a schematic diagram of a display panel provided by the embodiments of the present application, Figure 2 is a schematic diagram of another display panel provided by the embodiments of the present application, Figure 3 is a schematic diagram of yet another display panel provided by the embodiments of the present application, Figure 4 is a schematic diagram of still another display panel provided by the embodiments of the present application, Figure 5 is a schematic diagram of yet another display panel provided by the embodiments of the present application, Figure 6 is a schematic diagram of still another display panel provided by the embodiments of the present application, Figure 7 is a schematic diagram of yet another display panel provided by the embodiments of the present application, Figure 8 is a schematic diagram of still another display panel provided by the embodiments of the present application, wherein the display panel includes: a first display area 100 and a second display area 200; a pixel circuit, the pixel circuit includes a first pixel circuit 101 and a second pixel circuit 102, the first pixel circuit 101 is connected to the light emitting element 20 of the first display area 100, and the second pixel circuit 102 is connected to the light emitting element 20 of the second display area 200; the pixel circuit 10 includes a driving transistor T0 and a first preset module 11, and one end of the first preset module 11 is connected to the driving transistor T0; wherein, the control end of the first preset module 11 in the first pixel circuit 101 is used to receive a first control signal Vc1, and the control end of the first preset module 11 in the second pixel circuit 102 is used to receive a second control signal Vc2; during at least one stage of the working process of the display panel, the pulse change frequency of the first control signal Vc1 is F1, and the pulse change frequency of the second control signal Vc2 is F2, wherein, F1≠F2.

[0039] In this embodiment, one end of the first preset module 11 is connected to the driving transistor T0. Optionally, as Figure 1As shown, one end of the first preset module 11 is connected to the first pole of the driving transistor T0, that is, the N2 node. In the first pixel circuit 101, the first preset module 11 is used to provide a signal to the first pole of the driving transistor T0 under the control of the first control signal Vc1. In the second pixel circuit 102, the first preset module 11 is used to provide a signal to the first pole of the driving transistor T0 under the control of the second control signal Vc2. Optionally, as Figure 2 As shown, one end of the first preset module 11 is connected to the second pole of the driving transistor T0, that is, the N3 node. In the first pixel circuit 101, the first preset module 11 is used to provide a signal to the second pole of the driving transistor T0 under the control of the first control signal Vc1. In the second pixel circuit 102, the first preset module 11 is used to provide a signal to the second pole of the driving transistor T0 under the control of the second control signal Vc2. Optionally, as Figure 3 As shown, one end of the first preset module 11 is connected to the gate of the driving transistor T0, that is, the N1 node. In the first pixel circuit 101, the first preset module 11 is used to provide a signal to the gate of the driving transistor T0 under the control of the first control signal Vc1. In the second pixel circuit 102, the first preset module 11 is used to provide a signal to the gate of the driving transistor T0 under the control of the second control signal Vc2. Optionally, as Figure 4 As shown, one end of the first preset module 11 is connected to the gate of the driving transistor T0, that is, the N1 node, and the other end is connected to the first pole or the second pole of the driving transistor T0, that is, the N2 node or the N3 node. In the first pixel circuit 101, the first preset module 11 is used to selectively provide a signal path between the gate of the driving transistor T0 and the first pole or the second pole under the control of the first control signal Vc1. In the second pixel circuit 102, the first preset module 11 is used to selectively provide a signal path between the gate of the driving transistor T0 and the first pole or the second pole under the control of the second control signal Vc2.

[0040] From the above description, it can be seen that one end of the first preset module 11 is connected to the driving transistor T0 and is used to provide a signal to the gate or the first pole or the second pole of the driving transistor T0. In this embodiment, due to the different functional requirements for the first display area 100 and the second display area 200, therefore, the frequency requirements for the first pixel circuit 101 and the second pixel circuit 102 to receive the preset signal are also different. This makes the pulse change frequency requirements for the control signal of the first preset module 11 different, that is, the pulse change frequency F1 of the first control signal Vc1 is different from the pulse change frequency F2 of the second control signal Vc2, so as to separately control the frequency of the preset signal received by the gate or the first pole or the second pole of the driving transistor T0 in the first pixel circuit 101 and the second pixel circuit 102, and further realize the respective functions of the first display area 100 and the second display area 200.

[0041] In this embodiment, optionally, as Figures 5 - 8 shown, the first preset module 11 is a data writing module 111. The data writing module 111 is connected to the first pole of the driving transistor T0 and is used to provide a data signal Vdata for the driving transistor T0; alternatively, the first preset module 11 is a compensation module 112. The compensation module 112 is connected between the gate and the second pole of the driving transistor T0 and is used to compensate for the threshold voltage deviation of the driving transistor T0; alternatively, the first preset module 11 is a reset module 113. The reset module 113 is connected to the gate or the second pole of the driving transistor T0 and is used to provide a reset signal Vref for the driving transistor T0; alternatively, the first preset module 11 is a bias adjustment module 114. The bias adjustment module 114 is connected to the first pole or the second pole of the driving transistor T0 and is used to provide a bias adjustment signal V0 for the driving transistor T0.

[0042] It should be noted that, as Figure 5 and Figure 6 shown, the driving transistor T0 is a PMOS transistor. Among them, Figure 5 in the bias adjustment module 114 is connected to the first pole of the driving transistor T0, Figure 6 in the bias adjustment module 114 is connected to the second pole of the driving transistor T0. As Figure 7 and Figure 8 shown, the driving transistor T0 is an NMOS transistor. Among them, Figure 7 in the bias adjustment module 114 is connected to the first pole of the driving transistor T0, Figure 8The middle bias adjustment module 114 is connected to the second pole of the driving transistor T0. When the driving transistor T0 is a PMOS transistor, during the light-emitting stage, the signal applied to the gate of the driving transistor T0 is the data signal Vdata, the signal applied to the first pole is the first power supply signal PVDD, and the signal of the second pole may be a relatively low potential. At this time, there may be a situation where the gate potential of the driving transistor T0 is higher than the potential of the second pole. At this time, the PMOS driving transistor T0 is in the on state. At this time, there will be a reverse electric field between the gate and the second pole, resulting in the polarization of the carriers in the active layer of the driving transistor T0, thereby causing the threshold voltage of the driving transistor T0 to shift, and further affecting the generation of the driving current. To improve this phenomenon, a relatively high-level bias adjustment signal is input to the first pole or the second pole of the driving transistor T0 through the bias adjustment module 114, so that the potential of the first pole or the second pole is higher than the gate potential, thereby offsetting the aforementioned threshold voltage shift problem. When the driving transistor T0 is an NMOS transistor, the situation is similar. During the light-emitting stage, there may be a situation where the gate potential of the NMOS driving transistor T0 is lower than the potential of the second pole. At this time, a reverse electric field will also be formed, so the threshold voltage of the driving transistor T0 shifts. Therefore, a relatively low-level bias adjustment signal is input to the first pole or the second pole of the driving transistor T0 through the bias adjustment module 114, so that the potential of the first pole or the second pole is lower than the gate potential, thereby offsetting the aforementioned threshold voltage shift problem.

[0043] In this embodiment, in some cases, for the functional requirements of the first display area 100 and the second display area 200, it is reflected in the difference in the data refresh frequency. For example, if the first display area 100 is an area for playing movies, games and other pictures, a higher data refresh frequency is required to ensure fast picture refresh and improve the user experience. The second display area 200 is an area for displaying text, time information, etc., and does not require a high data refresh frequency. Under a low data refresh frequency, the requirements can be met. In this case, the first pixel circuit 101 and the second pixel circuit 102 receive data signals at different frequencies. Then, to achieve this purpose, the control signal frequencies of the modules involved in the data signal input paths of the first pixel circuit 101 and the second pixel circuit 102 need to be designed differently.

[0044] The module located on the data signal input path described above can be the data writing module 111. One end of the data writing module 111 is connected to the data signal terminal for receiving the data signal Vdata, and the other end is connected to the first pole of the driving transistor T0 for providing the data signal Vdata to the first pole of the driving transistor T0. Therefore, if the first preset module 11 is the data writing module 111, by making the pulse change frequencies of the first control signal Vc1 and the second control signal Vc2 different, the data refresh frequencies of the first display area 100 and the second display area 200 can be controlled to be different. Refer to Figures 5 - 8 , when the first preset module 11 is the data writing module 111, the control signal S11 of the data writing module 111 in the first pixel circuit 101 is the first control signal Vc1, and the control signal S21 of the data writing module 111 in the second pixel circuit 102 is the second control signal Vc2. Optionally, the data writing module 111 includes a data writing transistor T1. The gate of the data writing transistor T1 in the first pixel circuit 101 receives the control signal S11, that is, the first control signal Vc1, and the gate of the data writing transistor T1 in the second pixel circuit 102 receives the control signal S21, that is, the second control signal Vc2.

[0045] In addition, the module located on the data signal input path described above can also be the compensation module 112. One end of the compensation module 112 is connected to the gate of the driving transistor T0, and the other end is connected to the second pole of the driving transistor T0 for compensating for the threshold voltage deviation of the driving transistor T0. Since the data signal Vdata needs to be input to the gate of the driving transistor T0 to generate a driving current, therefore, after the data signal Vdata is input from the data writing module 111 to the first pole of the driving transistor T0, it will pass through the driving transistor T0 to the second pole of the driving transistor T0, and then pass through the compensation module 112 to the gate of the driving transistor T0. Therefore, if the first preset module 11 is the compensation module 112, by making the pulse change frequencies of the first control signal Vc1 and the second control signal Vc2 different, the data refresh frequencies of the first display area 100 and the second display area 200 can be controlled to be different. Refer to Figures 5 - 8 , when the first preset module 11 is the compensation module 112, the control signal S12 of the compensation module 112 in the first pixel circuit 101 is the first control signal Vc1, and the control signal S22 of the compensation module 112 in the second pixel circuit 102 is the second control signal Vc2. Optionally, the compensation module 112 includes a compensation transistor T2. The gate of the compensation transistor T2 in the first pixel circuit 101 receives the control signal S21, that is, the first control signal Vc1, and the gate of the compensation transistor T2 in the second pixel circuit 102 receives the control signal S22, that is, the second control signal Vc2.

[0046] In addition, during the operation of the pixel circuit, generally, the data writing stage often needs to be accompanied by the reset stage. Because, before the data signal Vdata is written to the gate of the driving transistor T0, generally, the gate of the driving transistor T0 needs to be reset. After resetting the data signal of the previous frame to a fixed potential, the data signal Vdata is written, so as to avoid the interference of the data signal of the previous frame on the data signal Vdata of the current frame. Therefore, generally speaking, for the frames that do not need to write data signals, the reset stage is not required either. Therefore, the first preset module 11 can also be the reset module 113. One end of the reset module 113 is connected to the gate or the second pole of the driving transistor T0, and the other end is connected to the reset signal terminal, and is used to provide the reset signal Vref for the driving transistor T0. At this time, by making the pulse change frequencies of the first control signal Vc1 and the second control signal Vc2 different, the reset frequencies of the first display area 100 and the second display area 200 can be controlled to be different, so as to match the requirements of different data refresh frequencies of the first display area 100 and the second display area 200. Refer to Figures 5 - 8 , when the first preset module 11 is the reset module 113, the control signal S13 of the reset module 113 in the first pixel circuit 101 is the first control signal Vc1, and the control signal S23 of the reset module 113 in the second pixel circuit 102 is the second control signal Vc2. Optionally, the reset module 113 includes a reset transistor T3. The gate of the reset transistor T3 in the first pixel circuit 101 receives the control signal S13, that is, the first control signal Vc1, and the gate of the reset transistor T3 in the second pixel circuit 102 receives the control signal S23, that is, the second control signal Vc2.

[0047] In some other cases, the first preset module 11 can also be the bias adjustment module 114. Because the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, and as described above, different data refresh frequencies will result in different signal change frequencies of the gate of the driving transistor T0 in different light emitting stages, and the bias degree of the driving transistor T0 is related to the potential of the gate of the driving transistor T0. Therefore, there may be differences in the bias conditions of the first pixel circuit 101 and the second pixel circuit 102. Based on this, the frequencies of the input bias adjustment signals in the first pixel circuit 101 and the second pixel circuit 102 can also be different. Therefore, the first preset module 11 can be the bias adjustment module 114. At this time, refer to Figures 5 - 8, the control signal S14 of the bias adjustment module 114 in the first pixel circuit 101 is the first control signal Vc1, and the control signal S24 of the bias adjustment module 114 in the second pixel circuit 102 is the second control signal Vc2. Optionally, the bias adjustment module 114 includes a bias adjustment transistor T4. The gate of the bias adjustment transistor T4 in the first pixel circuit 101 receives the control signal S14, which is the first control signal Vc1, and the gate of the bias adjustment transistor T4 in the second pixel circuit 102 receives the control signal S24, which is the second control signal Vc2.

[0048] Optionally, in this embodiment, during at least one stage of the display panel working process, the data refresh frequency of the first pixel circuit 101 is greater than the data refresh frequency of the second pixel circuit 102; wherein, when the first preset module 11 is the data writing module 111 or the compensation module 112 or the reset module 113, F1 > F2; or, when the first preset module 11 is the bias adjustment module 114, F1 > F2, or, F1 ≤ F2.

[0049] In the display panel, generally, the frame refresh frequency is the change frequency of the minimum unit sub-frame for screen refresh, and the data refresh frequency refers to the frequency at which the data signal Vdata is written to the gate of the driving transistor T0. Taking a panel with a frame refresh frequency of 120 HZ as an example, when the data refresh frequency is 60 HZ, it means that within one data refresh cycle, there is 1 data writing frame and 1 holding frame. The data writing frame refers to the sub-frame in which the data signal Vdata is written to the gate of the driving transistor T0, and the holding frame refers to the sub-frame in which no data signal Vdata is written to the gate of the driving transistor T0; when the data refresh frequency is 30 HZ, it means that within one data refresh cycle, there is 1 data writing frame and 3 holding frames, and so on. The data refresh frequency of the first pixel circuit 101 is greater than the data refresh frequency of the second pixel circuit 102. For example, the data refresh frequency of the first pixel circuit 101 is 60 HZ, and the data refresh frequency of the second pixel circuit 102 is 30 HZ, etc. This is only an example. In other cases, the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 can be set according to actual needs.

[0050] As described above, since the data writing module 111 and the compensation module 112 are located on the path of the gate of the driving transistor T0 of the data signal Vdata input, therefore, when the first preset module 11 is the data writing module 111 or the compensation module 112, and the data refresh frequency of the first pixel circuit 101 is greater than that of the second pixel circuit 102, then there will be F1 > F2. That is to say, the switching frequency of the module that controls the transmission of the data signal Vdata on the first pixel circuit 101 is greater than that of the module that controls the transmission of the data signal Vdata on the second pixel circuit 102. Only in this way can the data refresh frequency of the first pixel circuit 101 be greater than that of the second pixel circuit 102.

[0051] In addition, as also described above, since the reset stage often occurs along with the data writing stage, therefore, when the first preset module 11 is the reset module 113 and the data refresh frequency of the first pixel circuit 101 is greater than that of the second pixel circuit 102, then there will be F1 > F2. That is to say, in the pixel circuit with a higher data refresh frequency, the switching frequency of the reset module 113 is also higher.

[0052] In addition, when the first preset module 11 is the bias adjustment module 114, the situation is somewhat different from the above situation because the bias adjustment module 114 is not on the path of the data signal Vdata input to the gate of the driving transistor T0, nor on the writing path of the reset signal Vref. That is, the bias adjustment module 114 is not used to control the data refresh frequency. Therefore, when the data refresh frequency of the first pixel circuit 101 is greater than that of the second pixel circuit 102, the switching frequency of the bias adjustment module 114 needs to be designed according to its function. In some cases, when the data refresh frequency is higher, it means that the change frequency of the gate potential of the driving transistor T0 is also higher. As described above, the bias problem of the driving transistor T0 is closely related to the gate potential of the driving transistor T0 during the light-emitting stage. When the change frequency of the gate potential of the driving transistor T0 is relatively high, the driving transistor T0 does not have the same reverse electric field for a long time. That is, it does not stay under the same bias problem for a long time. When the change frequency of the gate potential of the driving transistor T0 is relatively low, if a bias problem occurs, the bias problem may exist for a relatively long time. Therefore, when the data refresh frequency of the pixel circuit is low, it may cause the bias problem to be more serious. To solve this problem, it may be necessary to increase the frequency of the bias adjustment stage and correct the bias problem through multiple bias adjustments. When the data refresh frequency of the pixel circuit is high, the bias problem is relatively less severe, and the frequency of the bias adjustment stage can be appropriately reduced. Therefore, in this case, there may be a situation where F1 ≤ F2. Of course, in some other cases, for example, when the data refresh frequencies of both the first pixel circuit 101 and the second pixel circuit 102 are relatively low, but the data refresh frequency of the first pixel circuit 101 is relatively higher, at this time, both the first pixel circuit 101 and the second pixel circuit 102 require multiple bias adjustment stages to correct the bias problem of the driving transistor T0. And if the display effect requirement for the first display area 100 corresponding to the first pixel circuit 101 is better, there may also be a situation where F1 > F2.

[0053] In this embodiment, optionally, referring to Figure 9 , Figure 9 is a schematic diagram of another display panel provided by an embodiment of the present application. Among them, the pixel circuit further includes a second preset module 12; the control end of the second preset module 12 in the first pixel circuit 101 is used to receive a fourth control signal Vc4, and the control end of the second preset module 12 in the second pixel circuit 102 is used to receive a fifth control signal Vc5; among them, during at least one stage of the operation of the display panel, the pulse change frequency of the fourth control signal Vc4 is F4, and the pulse change frequency of the fifth control signal Vc5 is F5; |F1 - F2| > |F4 - F5| ≥ 0.

[0054] In a display panel, a module data writing module 111, a compensation module 112 located on the gate path of a driving transistor T0 for writing a data signal Vdata, and a reset module 113 for providing a reset signal Vref to the gate of the driving transistor T0 are all closely related to changes in the data refresh frequency. Therefore, these modules can all be referred to as the first preset module 11. When the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, the pulse change frequency of the first control signal Vc1 is F1, and the pulse change frequency of the second control signal Vc2 is F2. The difference between F1 and F2 represents the data refresh frequency difference between the first pixel circuit 101 and the second pixel circuit 102. There are often some modules in the pixel circuit that are not related to changes in the data refresh frequency. The on and off transitions of these modules are not necessarily restricted by the data refresh frequency. This type of module is the second preset module 12. In some cases, as long as the pixel circuit performs sub-frame refreshing, then the second preset module 12 needs to perform on and off transitions. At this time, the on and off frequencies of the second preset module 12 in the first pixel circuit 101 and the second pixel circuit 102 can be the same, that is, the pulse change frequency F4 of the fourth control signal is equal to the pulse change frequency F5 of the fifth control signal. In some other cases, the on and off frequencies of the second preset module 12 in the first pixel circuit 101 and the second pixel circuit 102 can be different, but there may be a small difference and it is not set exactly according to the difference in the data refresh frequency. At this time, there may be a situation where F4 is not equal to F5, but |F1 - F2| > |F4 - F5|. Therefore, generally speaking, |F1 - F2| > |F4 - F5| ≥ 0.

[0055] It should be noted that Figure 9 Only the connection manner of the second preset module 12 is schematically shown and should not be understood that the second preset module 12 can only be connected to the N2 node. In other embodiments, the second preset module 12 can also be connected to the N1 node or the N3 node, and can also be connected to the light-emitting element, and can also be connected to other positions.

[0056] Optionally, referring to Figures 5 - 8 , the second preset module 12 can be a light-emitting control module 115. The light-emitting control module 115 is connected between the first power signal terminal and the driving transistor T0, or the light-emitting control module 115 is connected between the driving transistor T0 and the light-emitting element 20, and is used to selectively allow the light-emitting element 20 to enter the light-emitting stage. Optionally, the light-emitting control module 115 includes a first light-emitting control module 1151 and a second light-emitting control module 1152. The first light-emitting control module 1151 is connected to the first power signal terminal and the first pole (such as Figure 5 and Figure 6 shown) or the second pole of the driving transistor T0 (such asFigure 7 and Figure 8 as shown in between) for providing a first power signal Vdata to the driving transistor T0, and the second light emission control module 1152 is connected to the first pole of the driving transistor T0 (such as Figure 7 and Figure 8 as shown in) or the second pole (such as Figure 5 and Figure 6 as shown in) and the light emitting element 20 for selectively allowing a driving current to enter the light emitting element 20. Since the turning on and off of the light emission control module 115 controls whether the light emitting element emits light, and within the period of a sub-frame, that is, there is a process of turning on and off the light emitting element, generally speaking, the turning on and off of the light emission control module 115 needs to be consistent with the frequency of the sub-frame. Therefore, the change in the frequency of the control signal of the light emission control module 115 is different from the change in the data refresh frequency. In this embodiment, in the first pixel circuit 101, the control signal of the light emission control module 115 is EM1, that is, the fourth control signal Vc4, and in the second pixel circuit 102, the control signal of the light emission control module 115 is EM2, that is, the fifth control signal Vc5. Optionally, the first light emission control module 1151 includes a first light emission control transistor T5, the second light emission control module 1152 includes a second light emission control transistor T6. In the first pixel circuit 101, the gates of the first light emission control transistor T5 and the second light emission control transistor T6 are used to receive the control signal EM1, that is, the fourth control signal Vc4; in the second pixel circuit 102, the gates of the first light emission control transistor T5 and the second light emission control transistor T6 are used to receive the control signal EM2, that is, the fifth control signal Vc5.

[0057] Optionally, the second preset module 12 may also be an initialization module 117. One end of the initialization module 117 is connected to the initialization signal terminal, and the other end is connected to the light-emitting element 20, for providing an initialization signal Vini to the light-emitting element 20. Since after the light emission of the light-emitting element 20 in the previous frame ends, generally the driving current information of the previous frame still remains, it is necessary to apply an initialization signal Vini to the light-emitting element 20 to initialize the driving current information of the previous frame, and then write the driving current of the current frame. Therefore, the turn-on and turn-off of the initialization module 117 also do not have a direct corresponding relationship with the data refresh frequency. In some cases, when the display panel goes through a light-emitting stage, an initialization stage needs to be carried out once. Therefore, there are differences in the pulse change frequencies of the control signals of the initialization modules 117 of the first pixel circuit 101 and the second pixel circuit 102 compared to the data refresh frequency differences. At this time, the control signal S15 of the initialization module 117 in the first pixel circuit 101 is the fourth control signal Vc4, and the control signal S25 of the initialization module 117 in the second pixel circuit 102 is the fifth control signal Vc5. Optionally, the initialization module 117 includes an initialization transistor T7. The gate of the initialization transistor T7 in the first pixel circuit 101 receives the control signal S15, that is, the fourth control signal Vc4, and the gate of the initialization transistor T7 in the second pixel circuit 102 receives the control signal S25, that is, the fifth control signal Vc5.

[0058] In addition, optionally, in some embodiments, the second preset module 12 may also be a bias adjustment module 114. The bias adjustment module 114 is connected to the first pole or the second pole of the driving transistor T0, for providing a bias adjustment signal to the driving transistor T0. Since the bias adjustment module 114 is not directly on the path of writing the data signal Vdata or the reset signal Vref, the turn-on and turn-off frequencies of the bias adjustment module 114 may be different from the change of the data refresh frequency. Therefore, the bias adjustment module 114 may also be the second preset module 12. Since the bias adjustment module 114 is mainly used to provide a bias adjustment signal to the driving transistor T0, in some cases, after a frame of the picture ends, a bias adjustment stage needs to be carried out to correct the bias problem of the driving transistor T0 in a timely manner. At this time, the control signal S14 of the bias adjustment module 114 in the first pixel circuit 101 is the fourth control signal Vc4, and the control signal S24 of the bias adjustment module 114 in the second pixel circuit 102 is the fifth control signal Vc5. Optionally, the bias adjustment module 114 includes a bias adjustment transistor T4. The gate of the bias adjustment transistor T4 in the first pixel circuit 101 receives the control signal S14, which is the fourth control signal Vc4, and the gate of the bias adjustment transistor T4 in the second pixel circuit 102 receives the control signal S24, which is the fifth control signal Vc5.

[0059] Optionally, in this embodiment, (F1 - F2) × (F4 - F5) ≥ 0. As described above, F1 may determine the data refresh frequency of the first pixel circuit 101, F2 may determine the data refresh frequency of the second pixel circuit 102, and F4 and F5 have little relation with the data refresh frequency. In this case, it is possible that F4 = F5, that is, the on and off frequencies of the second preset module 12 are the same in the first pixel circuit 101 and the second pixel circuit 102. In this case, (F1 - F2) × (F4 - F5) = 0. In other cases, there may be situations where when the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, the on and off frequencies of the second preset module 12 also change accordingly, but the change amplitude is not as large as that between F1 and F2. For example, if the data refresh frequency of the second pixel circuit 102 is relatively low, then for one data refresh cycle, since the data signal remains unchanged, that is, the driving current remains unchanged, correspondingly, the change frequency of the initialization module 117 can be appropriately reduced, and it can be refreshed again after several frames. Therefore, the situation that may occur at this time is F4 > F5, and (F1 - F2) × (F4 - F5) > 0.

[0060] In some special cases, it is also possible that (F1 - F2) × (F4 - F5) < 0. For example, when the second preset module 12 is the bias adjustment module 114, as described above, there may be a situation where when the data refresh frequency of the first pixel circuit 101 is relatively high and the data refresh frequency of the second pixel circuit 102 is relatively low, in order to prevent the second pixel circuit 102 from remaining in the same bias state for a long time, it may be necessary to perform relatively high-frequency bias adjustment on the second pixel circuit 102 with low-frequency data refresh to fully adjust the bias problem of the second pixel circuit 102. At this time, it is possible that F4 < F5, making (F1 - F2) × (F4 - F5) < 0.

[0061] Optionally, in this embodiment, referring to Figure 10 , Figure 10It is a comparative schematic diagram of a transistor provided by an embodiment of the present application. Among them, on a substrate 3000, a first preset module 11 of a first pixel circuit 101 includes a first transistor T10, and a first preset module 11 of a second pixel circuit 102 includes a second transistor T20. The active layers of the first transistor T10 and the second transistor T20 both contain an oxide semiconductor. The first transistor T10 includes an active layer 3011, a gate 3012a and / or a gate 3012b, a source 3013, and a drain 3014, where the active layer 3011 contains an oxide semiconductor; the second transistor T20 includes an active layer 3021, a gate 3022a and / or a gate 3022b, a source 3023, and a drain 3024, where the active layer 3021 contains an oxide semiconductor; it should be noted that the gate 3012a in the first transistor T10 can be a bottom gate, and the gate 3012b can be a top gate. Through the design of the top and bottom double gates, the stability of the first transistor T10 is improved. Similarly, the gate 3022a in the second transistor T20 can be a bottom gate, and the gate 3022b can be a top gate, thereby improving the stability of the second transistor T20. A second preset module 12 of the first pixel circuit 101 includes a third transistor T30, and a second preset module 12 of the second pixel circuit 102 includes a fourth transistor T40. The active layers of the third transistor T30 and the fourth transistor T40 both contain silicon. The third transistor T30 includes an active layer 3031, a gate 3032, a source 3033, and a drain 3034, and the fourth transistor T40 includes an active layer 3041, a gate 3042, a source 3043, and a drain 3044.

[0062] Since oxide semiconductor transistors have the advantage of low leakage current, in a pixel circuit, the transistors connected to the driving transistor T0, especially the transistors connected to the gate of the driving transistor T0, are preferably oxide semiconductor transistors. Because the gate of the driving transistor T0 undertakes the function of storing the data signal Vdata, and the generation of the driving current is closely related to the data signal Vdata. Therefore, the stability of the gate potential of the driving transistor T0 directly affects the stability of the driving current. Therefore, an oxide semiconductor transistor with a smaller leakage current is selected to be connected to the gate of the driving transistor T0, so as to fully ensure the stability of the gate potential of the driving transistor T0 during the light-emitting stage. In this embodiment, one end of the first preset module 11 is connected to the driving transistor T0, and it is generally located on the writing path of the data signal Vdata or the writing path of the reset signal Vref. This requires that the first preset module 11 has a small off-state leakage current to ensure the potential stability of the driving transistor T0. Therefore, it is preferred that the first preset module 11 in the first pixel circuit 101 and the second pixel circuit 102 both include oxide semiconductor transistors. For the second preset module 12, since it is not directly located on the input path of the data signal Vdata or the reset signal Vref, and is not directly connected to the gate of the driving transistor T0, it needs to have a faster response speed. Therefore, a silicon transistor with a faster response speed is generally used.

[0063] Optionally, in this embodiment, as Figures 5 - 8 shown, the pixel circuit includes a bias adjustment module 114. The bias adjustment module 114 is connected to the first pole or the second pole of the driving transistor T0 and is used to provide a bias adjustment signal for the driving transistor T0. The bias adjustment module in the first pixel circuit 101 is used to receive the first bias adjustment signal Vb1, and the bias adjustment module in the second pixel circuit 102 is used to receive the second bias adjustment signal Vb2.

[0064] In some embodiments, when F1≠F2, Vb1 = Vb2. That is, the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, but the bias adjustment signal Vb1 received by the first pixel circuit 101 is the same as the bias adjustment signal Vb2 received by the second pixel circuit 102. When the difference in data refresh frequencies between the first pixel circuit 101 and the second pixel circuit 102 is not large and the difference in bias problems is not obvious, the same bias adjustment signal can be used for adjustment. In this way, it helps to simplify the panel process.

[0065] In some other embodiments, when F1≠F2, Vb1≠Vb2, that is, the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, and the bias adjustment signals received by them are also different. In some cases, the difference in the data refresh frequencies between the first pixel circuit 101 and the second pixel circuit 102 is large, and the bias problems are quite different. Or, when the requirements for correcting the bias problem of the first pixel circuit 101 are different from those for correcting the bias problem of the second pixel circuit 102, the bias adjustment signals that are more suitable for the first pixel circuit 101 and the second pixel circuit 102 will be selected respectively, so as to ensure the display functions of the first display area 100 and the second display area 200 respectively.

[0066] Optionally, in some embodiments, F1>F2, Vb1<Vb2, or F1<F2, Vb1>Vb2, that is, (F1 - F2)×(Vb1 - Vb2)<0, and the change in the data refresh frequency is negatively correlated with the change in the voltage value of the bias adjustment signal. For the case where the driving transistor T0 is a PMOS transistor, the bias problem of the driving transistor T0 is mainly caused by the fact that the potential of the gate may be higher than the potential of the second pole during the light-emitting stage. Therefore, in order to offset the bias problem, the bias adjustment signal is often a relatively high potential. When the data refresh frequency is low, the light-emitting stage under the same data signal lasts for a longer time. Therefore, the bias problem will be relatively more serious. In this case, in order to fully offset the bias problem in a shorter time, a higher bias adjustment signal may be required, so that when the data refresh frequency is low, the bias adjustment signal is instead high, resulting in the situation of F1>F2, Vb1<Vb2, or F1<F2, Vb1>Vb2, that is, (F1 - F2)×(Vb1 - Vb2)<0. Of course, when the driving transistor T0 is a PMOS transistor, in some other cases, the situation of (F1 - F2)×(Vb1 - Vb2)>0 may also occur, that is, the change in the data refresh frequency is positively correlated with the change in the voltage value of the bias adjustment signal. For example, when the first pixel circuit 101 has a high data refresh frequency and the second pixel circuit 102 has a low refresh frequency, the first display area 100 is used to play a high-refresh-frequency picture, while the second display area 200 is used to play a relatively static picture. In this way, the requirement for improving the bias problem of the first pixel circuit 101 is much greater than the requirement for improving the bias problem of the second pixel circuit 102, because whether the bias problem is improved will affect problems such as flicker and brightness instability during the gray-scale change process. In this case, it may be possible to provide a higher bias adjustment signal for the first pixel circuit 101 to ensure that the bias problem is fully improved, while providing a relatively lower bias adjustment signal for the second pixel circuit 102 to meet the display requirements of the relatively static second display area 200.

[0067] When the driving transistor T0 is an NMOS transistor, the biasing problem of the driving transistor T0 is mainly caused by the gate potential being lower than the second potential during the light-emitting stage. At this time, a relatively low-level biasing adjustment signal needs to be provided for the driving transistor T0 to offset the biasing problem. When the data refresh frequency is lower, the driving transistor T0 maintains the light-emitting stage for a longer time under the same data signal, so the biasing problem may be more serious. Therefore, a lower-level biasing adjustment signal is required to fully offset the biasing problem in a shorter time. In this case, there will be a situation where F1 > F2, Vb1 > Vb2, or F1 < F2, Vb1 < Vb2, that is, (F1 - F2) × (Vb1 - Vb2) > 0. Of course, similar to the previous description, when the requirements for improving the biasing problems of the first display area 100 and the second display area 200 are different, there may also be a situation where (F1 - F2) × (Vb1 - Vb2) < 0. That is, for the area with a higher data refresh frequency, no problems such as flicker are required, so a lower biasing adjustment signal is needed, while for a relatively static picture, only a certain biasing adjustment signal needs to be set to meet the display requirements of the relatively static picture.

[0068] Optionally, in this embodiment, F1 > F2, and |F1 / F2| > |Vb1 / Vb2|. When F1 > F2 and |Vb1| < |Vb2|, this formula holds naturally; when F1 > F2 and |Vb1| > |Vb2|, as described above, since F1 and F2 often determine the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102. For example, when the data refresh frequency of the first pixel circuit 101 is 60HZ and the data refresh frequency of the second pixel circuit 102 is 30HZ, F1 / F2 = 2. The function of the bias adjustment signal is to raise the potential of the second pole of the driving transistor T0 (the driving transistor T0 is a PMOS transistor) or lower the potential of the second pole of the driving transistor T0 (the driving transistor T0 is an NMOS transistor), and reverse the potential difference between the gate and the second pole of the driving transistor T0. If the gate potential of the driving transistor T0 is Vg and the second pole potential is Vd, then the adjusted potential difference is |Vd - Vg|. Generally speaking, the potential of the bias adjustment signal is between 5V and 6V, and a 1V change in the potential of the bias adjustment signal can cause a large change in |Vd - Vg|. If the bias adjustment signal changes in proportion to F1 / F2, then the change amplitude of the bias adjustment signal will be large. However, if the change of the bias adjustment signal is too large, for example, for a PMOS driving transistor, when the bias adjustment signal is low, it cannot play a good bias adjustment role; when the bias adjustment signal is too high, it will cause an increase in power consumption. For an NMOS driving transistor, when the bias adjustment signal is high, it cannot play a good bias adjustment role; when the bias adjustment signal is too low, it will also cause an increase in power consumption. Therefore, generally speaking, the change amplitude of the bias adjustment signal will be set to be less than the change amplitude of the data refresh frequency, that is, when F1 > F2, |F1 / F2| > |Vb1 / Vb2|.

[0069] Further, in this embodiment, F01 is set as the separation frequency. When F1 > F2 > F01, |F1 / F2| < |Vb1 / Vb2|; when F01 > F1 > F2, |F1 / F2| > |Vb1 / Vb2|. Because as the data refresh frequency increases, F1 / F2 gradually decreases. For example, when F1 is 120HZ and F2 is 100HZ, at this time, |F1 / F2| = 1.2. And if the first bias adjustment signal Vb1 is 5V and the second bias adjustment signal Vb2 is 4V, then |Vb1 / Vb2| = 1.25. At this time, |F1 / F2| < |Vb1 / Vb2|, that is, when the data refresh frequency increases to a certain extent, F1 / F2 decreases, and |F1 / F2| < |Vb1 / Vb2| will not cause a large change in the bias adjustment signal. When F01 > F1 > F2, as the data refresh frequency decreases, F1 / F2 gradually increases. For example, when F1 is 30HZ and F2 is 1HZ, at this time, |F1 / F2| = 30. At this time, if the first bias adjustment signal Vb1 is 5V, and if the second bias adjustment signal Vb2 is 30 times or 1 / 30 of Vb1, then the second bias adjustment signal Vb2 will be too large or too small, and neither can play a good bias adjustment role. Therefore, in this case, |F1 / F2| > |Vb1 / Vb2|. Generally, F01 can take the middle value of the data refresh frequency range. For example, for the case where the data refresh frequency varies within the range of 1HZ - 120HZ, F01 is the frequency value in the middle region, such as 40HZ - 80HZ. Specifically, it can be 80HZ, 60HZ, 40HZ, etc.

[0070] Optionally, in this embodiment, the working process of the display panel includes a first stage and a second stage; the difference between the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the first stage and the pulse change frequency of the first control signal Vc2 received by the first pixel circuit 101 in the second stage is ΔF1; the difference between the first bias adjustment signal Vb1 received by the first pixel circuit 101 in the first stage and the first bias adjustment signal Vb1 received by the first pixel circuit 101 in the second stage is ΔVb; where ΔF1 ≠ 0, and ΔVb ≠ 0.

[0071] In this embodiment, there may be some situations where the data refresh frequency of the first display area 100 of the display panel may change, for example, from 60HZ to 30HZ. Because the pulse change frequency of the first control signal Vc1 determines the data refresh frequency, therefore, as the data refresh frequency changes, the change amplitude of the pulse change frequency of the first control signal Vc1 is ΔF1. As described above, when the data refresh frequencies are different, the bias problems of the driving transistor T0 are also different. Therefore, it can be set that ΔVb ≠ 0, that is, different bias adjustment signals are set for different data refresh frequencies for separate adjustment.

[0072] Optionally, in this embodiment, ΔF1×ΔVb<0. Referring to the foregoing, for the case where the driving transistor T0 is a PMOS transistor, when the data refresh frequency becomes lower, the driving transistor T0 maintains the light-emitting stage for a longer time under the same data signal, so the bias problem may be more serious. At this time, a higher bias adjustment signal needs to be set to fully adjust the bias state of the driving transistor T0. Therefore, when the data refresh frequency becomes lower, the bias adjustment signal increases, making ΔF1×ΔVb<0. In other embodiments, there may also be a case where ΔF1×ΔVb>0. For example, when the bias problem in the high data refresh frequency region is required to be more stringent, there may be a situation where the data refresh frequency is higher and the bias adjustment signal also becomes higher, that is, ΔF1×ΔVb>0.

[0073] For the case where the driving transistor T0 is an NMOS transistor, when the data refresh frequency becomes lower and the bias problem may be more serious, a lower bias adjustment signal is required to adjust the bias state. At this time, ΔF1×ΔVb>0. When the bias problem in the high data refresh frequency region is required to be more stringent, there may be a situation where the data refresh frequency is higher and the bias adjustment signal becomes lower, that is, ΔF1×ΔVb<0.

[0074] Optionally, in this embodiment, the absolute value of the ratio of the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the first stage to the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the second stage is R11; the absolute value of the ratio of the first bias adjustment signal Vb1 received by the first pixel circuit 101 in the first stage to the first bias adjustment signal Vb1 received by the first pixel circuit 101 in the second stage is R12; where ΔF1>0 and R11>R12.

[0075] Referring to the foregoing, generally speaking, the pulse change frequency of the first control signal Vc1 generally changes by several times or even dozens of times. For example, it changes from 60HZ to 1HZ, a 60-fold change. And the bias adjustment signal is generally between 0V - 5V, and the change of the bias adjustment signal is generally in the region of 0 - 2V, which can affect the degree of bias adjustment. Therefore, the change amplitude of the bias adjustment signal is smaller than the change amplitude of the pulse change frequency of the first control signal Vc1, that is, when ΔF1>0, R11>R12.

[0076] Optionally, in this embodiment, referring to Figure 11 , Figure 11It is a schematic diagram of another display panel provided by an embodiment of the present application. The display panel includes a bias adjustment signal bus 40. The bias adjustment signal bus 40 provides a first bias adjustment signal Vb1 for the first pixel circuit 101 and a second bias adjustment signal Vb2 for the second pixel circuit 102 through bias adjustment signal lines 400. When the control signal S14 controls the bias adjustment module 114 in the first pixel circuit 101 to turn on, the control signal S24 controls the bias adjustment module 114 in the second pixel circuit 102 to turn off, and the signal on the bias adjustment signal bus 40 is the first bias adjustment signal Vb1. When the control signal S14 controls the bias adjustment module 114 in the first pixel circuit 101 to turn off, the control signal S24 controls the bias adjustment module 114 in the second pixel circuit 102 to turn on, and the signal on the bias adjustment signal bus 40 is the second bias adjustment signal Vb2.

[0077] In this embodiment, since the first pixel circuit 101 and the second pixel circuit 102 are located in different display areas, in order to fully save the number of bias adjustment signal buses and thus save the border area of the display panel, the same bias adjustment signal bus can be used to provide bias adjustment signals for the first pixel circuit 101 and the second pixel circuit 102. In this case, in order to prevent signal crosstalk, it is necessary to ensure that when the bias adjustment module 114 in the first pixel circuit 101 is turned on, the bias adjustment module 114 in the second pixel circuit 102 is turned off. At this time, the signal on the bias adjustment signal bus 40 is the first bias adjustment signal Vb1, which is used to provide a bias adjustment signal for the first pixel circuit 101. When the bias adjustment module 114 in the first pixel circuit 101 is turned off, the bias adjustment module 114 in the second pixel circuit 102 is turned on. At this time, the signal on the bias adjustment signal bus 40 is the second bias adjustment signal Vb2, which is used to provide a bias adjustment signal for the second pixel circuit 102.

[0078] In addition, optionally, in this embodiment, referring to Figure 12 , Figure 12It is a schematic diagram of another display panel provided by an embodiment of the present application. The display panel includes a first bias adjustment signal bus 41 and a second bias adjustment signal bus 42. The first bias adjustment signal bus 41 provides a first bias adjustment signal Vb1 for the first display area 100 through a first bias adjustment signal line 401. The second bias adjustment signal bus 42 provides a second bias adjustment signal Vb2 for the second display area 200 through a second bias adjustment signal line 402. When permitted by the border of the display panel, the first bias adjustment signal bus 41 and the second bias adjustment signal bus 42 can exist simultaneously, providing bias adjustment signals for the first pixel circuit 101 and the second pixel circuit 102 respectively. In this case, the signals on the first bias adjustment signal bus 41 and the second bias adjustment signal bus 42 can remain unchanged. Moreover, when the first pixel circuit 101 receives the first bias adjustment signal Vb1, the second pixel circuit 102 can also receive the second bias adjustment signal Vb2, and the two processes can occur simultaneously without affecting each other.

[0079] Optionally, in this embodiment, during at least one stage of the operation process of the display panel, the operation process of the first pixel circuit 101 includes a first data writing frame and a first holding frame, and the operation process of the second pixel circuit 102 includes a second data writing frame and a second holding frame. Among them, within the first data writing frame, the first bias adjustment signal is Vb11, and within the first holding frame, the first bias adjustment signal is Vb12. Within the second data writing frame, the second bias adjustment signal is Vb21, and within the second holding frame, the second bias adjustment signal is Vb22. Among them, Vb11≠Vb21, and / or, Vb12≠Vb22.

[0080] As described above, the data writing frame represents a sub-frame with a data signal Vdata input, and the holding frame represents a sub-frame without a data signal Vdata input. When the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, within one data refresh cycle, the number of data writing frames and holding frames of the first pixel circuit 101 is also different from that of the second pixel circuit 102. For the same pixel circuit, the bias adjustment signals of the data writing frame and the holding frame can be the same or different. Therefore, on the basis of the foregoing, when the bias adjustment signals received by the first pixel circuit 101 and the second pixel circuit 102 are different, it is reflected in the difference in the bias adjustment signals in the data writing frame, and / or, the difference in the bias adjustment signals in the holding frame, that is, Vb11≠Vb21, and / or, Vb12≠Vb22.

[0081] In some embodiments, the difference between the first bias adjustment signal Vb11 in the first data write frame and the second bias adjustment signal Vb21 in the second data write frame is the same as the difference between the first bias adjustment signal Vb12 in the first hold frame and the second bias adjustment signal Vb22 in the second data write frame, that is, |Vb11 - Vb21| = |Vb12 - Vb22|. In this case, the variation amplitudes of the bias adjustment signals in the data write frame and the hold frame with respect to the data refresh frequency are the same, which is conducive to the unified adjustment of the data write frame and the hold frame and simplifies the process.

[0082] In some other embodiments, there may also be cases where |Vb11 - Vb21| > |Vb12 - Vb22|, or |Vb11 - Vb21| < |Vb12 - Vb22|. For example, when the data refresh frequency of the first pixel circuit 101 is relatively high, at 120 HZ, and the data refresh frequency of the second pixel circuit 102 is relatively low, at 1 HZ, the number of second hold frames is much larger than the number of first hold frames at this time. And the more the number of hold frames, the longer the driving transistor T0 holds under the same data signal, and the more serious the bias problem may be. Therefore, the difference between the bias adjustment signal in the second hold frame and the bias adjustment signal in the first hold frame can be set to be relatively large. For the data write frame, one data refresh cycle includes one or several data write frames. Therefore, the difference in the number of data write frames is relatively small compared to the difference in the number of hold frames. Therefore, the difference between the bias adjustment signal of the first data write frame and the bias adjustment signal of the second data write frame can be set to be relatively small, that is, |Vb11 - Vb21| < |Vb12 - Vb22|. In some other cases, when the relative difference in the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 is not too large, or when the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are both relatively high, for example, when the data refresh frequency of the first pixel circuit 101 is 120 HZ and the data refresh frequency of the second pixel circuit 102 is 90 HZ, at this time, the number of first data write frames is relatively large, and the number of second data write frames is relatively large. The difference in the bias adjustment problem is mainly reflected by the difference in the bias adjustment signals of the data write frames. Then, the difference between the first bias adjustment signal Vb1 received by the first data write frame and the second bias adjustment signal Vb2 received by the second data write frame can be set to be relatively large, while the difference in the bias adjustment signals of the hold frames is relatively small, that is, |Vb11 - Vb21| > |Vb12 - Vb22|.

[0083] Optionally, referring to Figure 13 , Figure 13It is a schematic diagram of another display panel provided by an embodiment of the present application. The display panel further includes a third display area 300. The pixel circuit includes a third pixel circuit 103, and the third pixel circuit 103 is connected to the light-emitting element 20 of the third display area 300. The control terminal of the first preset module 11 in the third pixel circuit 103 is used to receive a third control signal Vc3. During at least one stage of the operation of the display panel, the pulse change frequency of the first control signal Vc1 is F1, the pulse change frequency of the second control signal Vc2 is F2, and the pulse change frequency of the third control signal Vc3 is F3, where F1≠F3 and F2≠F3.

[0084] In this embodiment, the display panel may include more than two display areas with different data refresh frequencies, and may include three or more display areas with different data refresh frequencies. For example, the first display area 100 is a display area for playing game screens, the second display area 200 is a display area for playing text information, and the third display area 300 is a display area for playing time information. Then, in the case of including three or more display areas with different data refresh frequencies, the pulse change frequencies of the control signals of the first preset module 11 in these three display areas are all different.

[0085] Optionally, the bias adjustment module 114 in the third pixel circuit 103 is used to receive a third bias adjustment signal Vb3. Where F1>F2>F3, and at least two of Vb1, Vb2, and Vb3 are not equal. As described above, when the data refresh frequencies are different, according to the display requirements of the display panel, bias adjustment signals suitable for different display areas can be designed respectively. Therefore, at least two of Vb1, Vb2, and Vb3 are not equal. For example, when both F1 and F2 are high frequencies and F3 is a low frequency, Vb1 = Vb2≠Vb3 can be designed, which can simplify the process. In particular, when stricter requirements are imposed on the bias adjustment effects of the first display area 100, the second display area 200, and the third display area 300, then Vb1≠Vb2≠Vb3 is designed.

[0086] Optionally, in this embodiment, F1 > F2 > F3, and |F2 / F3 - F1 / F2| > ||Vb2 / Vb3| - |Vb1 / Vb2|| ≥ 0. As shown above, generally speaking, the change in the data refresh frequency is generally several times or even dozens of times. Therefore, F2 / F3 and / or F1 / F2 may both be relatively large values. Especially for F2 / F3, the smaller F3 is, the larger F2 / F3 is. And because the change range of the bias adjustment signal is generally within the range of 0V - 2V, therefore, |Vb2 / Vb3| and |Vb1 / Vb2| are generally relatively small values, and the absolute value of the difference between the two is even smaller. Therefore, generally speaking, |F2 / F3 - F1 / F2| > ||Vb2 / Vb3| - |Vb1 / Vb2|| ≥ 0. In this way, it not only ensures the change in the data refresh frequency of different display areas but also ensures that the bias adjustment signals of different display areas can meet their respective bias adjustment requirements.

[0087] Optionally, referring to Figures 14 - 17 , Figure 14 is a schematic diagram of another display panel provided by an embodiment of the present application, Figure 15 is a schematic diagram of yet another display panel provided by an embodiment of the present application, Figure 16 is a schematic diagram of another display panel provided by an embodiment of the present application, Figure 17 is a schematic diagram of yet another display panel provided by an embodiment of the present application. Among them, the display panel includes an initialization module 117, and the initialization module 117 is connected between the initialization signal terminal and the light-emitting element 20. Among them, the initialization module 117 in the first pixel circuit 101 is used to provide a first initialization signal Vi1 for the light-emitting element 10 in the first display area 100, and the initialization module 117 in the second pixel circuit 102 is used to provide a second initialization signal Vi2 for the light-emitting element 20 in the second display area 200.

[0088] It should be noted that, as shown in Figure 14 and Figure 15 , the driving transistor T0 is a PMOS transistor, and the bias adjustment module 114 is connected to the first pole ( Figure 14 ) of the driving transistor T0 or connected to the second pole ( Figure 15 ) of the driving transistor T0; as shown in Figure 16 and Figure 17 , the driving transistor T0 is an NMOS transistor, and the bias adjustment module 114 is connected to the first pole ( Figure 16 ) of the driving transistor T0 or connected to the second pole ( Figure 17 ) of the driving transistor T0. In addition, when the pixel circuit does not include the bias adjustment module 114 and the setting of the initialization signal also meets the aforementioned limitations, it also belongs to the scope protected by this embodiment.

[0089] Optionally, in some embodiments, when F1≠F2, Vi1 = Vi2. That is, the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, but the initialization signal Vi1 received by the first pixel circuit 101 is the same as the initialization signal Vi2 received by the second pixel circuit 102. Since the role of the initialization signal is to initialize the light-emitting element, and the light-emitting times and voltages of the pixel circuits are different, it is necessary to determine whether different initialization signals are required. Generally, when the difference in the light-emitting times of the pixel circuits at different data refresh frequencies is not too large and the same initialization signal can meet the requirements, then the same initialization signal can be used to initialize the light-emitting element. That is, when F1≠F2, Vi1 = Vi2.

[0090] Optionally, in some embodiments, when F1≠F2, Vi1≠Vi2. That is, the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 are different, and their respective received initialization signals are also different. In some cases, the difference in the data refresh frequencies of the first pixel circuit 101 and the second pixel circuit 102 is relatively large, resulting in a relatively large difference in the light-emitting stage times of the first pixel circuit 101 and the second pixel circuit 102. For example, when the first data refresh frequency is relatively high, the light-emitting element maintains a short time at the same driving current. That is, the voltage on the light-emitting element is changing during the maintenance, and when the second data refresh frequency is relatively low, the light-emitting element maintains a long time at the same driving current. That is, the voltage on the light-emitting element may remain unchanged for a long time. For the above two situations, the initialization requirements for the light-emitting element may be different. Especially when the gray levels of the light-emitting element in the previous and subsequent refresh cycles differ greatly, if the maintenance time at the same driving current is long at this time, a more sufficient initialization process is required. Therefore, for different data refresh frequencies, different initialization voltages may be required for separate initialization adjustments, that is, when F1≠F2, Vi1≠Vi2.

[0091] Optionally, in this embodiment, in some cases, (F1 - F2)×(|Vi1| - |Vi2|) < 0. That is, F1 > F2, |Vi1| < |Vi2|, or F1 < F2, |Vi1| > |Vi2|. When the pulse change frequency of the control signal is faster, that is, the data refresh frequency is larger, the absolute value of the voltage value of the initialization signal is larger. Generally, as Figures 14 - 17As shown, in the display panel, the light-emitting element includes an anode and a cathode. The anode is connected to the first power signal terminal through a pixel circuit for receiving the first power signal PVDD, and the cathode is connected to the second power signal terminal for receiving the second power signal PVEE. Generally, the PVEE voltage is a low-level signal, a negative voltage value, and the PVEE voltage is a high-level signal, a positive voltage value. In this embodiment, the first initialization signal Vi1 or the second initialization signal Vi2 is generally applied to the anode of the light-emitting element. During the light-emitting stage, the potential of the anode of the light-emitting element is higher than that of the cathode, so that a voltage difference is generated between the cathode and the anode. When initializing the anode of the light-emitting element, generally, the anode voltage is initialized to a certain value, and then other anode voltages are input in the next frame. Therefore, in this case, the initialization signal is generally a negative voltage. At this time, if |Vi1| > |Vi2|, the voltage value of Vi1 is lower than that of Vi2, and if |Vi1| < |Vi2|, the voltage value of Vi2 is lower than that of Vi1. When F1 > F2 and |Vi1| < |Vi2|, the data refresh frequency of the first pixel circuit is greater than that of the second pixel circuit. As described above, when the data refresh frequency is smaller, the time that the light-emitting element maintains at the same driving current is longer, that is, the anode of the light-emitting element maintains at the same voltage for a longer time. Then, in order to fully initialize the light-emitting element, an initialization voltage with a relatively large absolute value and a lower negative voltage can be set, so that the light-emitting element can be fully initialized in a shorter time. Moreover, because the smaller the data refresh frequency is, the longer the anode voltage of the light-emitting element remains unchanged relatively, therefore, a relatively low initialization voltage can be set to make the initialization process sufficient. When the data refresh frequency is larger, the time that the light-emitting element maintains at the same driving current is shorter, then, a negative voltage value with a relatively small absolute value can be set. In this way, after the initialization stage ends, the anode signal can be applied to the anode of the light-emitting element relatively quickly, facilitating the high-frequency conversion of the anode signal.

[0092] Optionally, in this embodiment, in other cases, there may also be a situation where (F1 - F2) × (|Vi1| - |Vi2|) > 0, that is, F1 > F2 and |Vi1| > |Vi2|. When the display requirements for the first display area 100 and the second display area 200 are different, resulting in different initialization requirements for the light-emitting elements, there may be a situation where when the data refresh frequency is larger, the absolute value of the initialization signal is larger and the voltage is lower. For example, when it is required to avoid the flicker problem as much as possible in the area with a large data refresh frequency to achieve high-quality picture switching, it may be required that |Vi1| > |Vi2|, so that the area with a large data refresh frequency can be fully initialized through the initialization signal with a lower voltage value, and the flicker problem in the picture switching caused by the insufficient initialization of the anode voltage in the previous frame and the inaccurate anode voltage signal in the next frame can be fully avoided.

[0093] Optionally, in this embodiment, F1 > F2 and |F1 / F2| > |Vi1 / Vi2|. When F1 > F2 and |Vi1| < |Vi2|, this formula holds naturally. When F1 > F2 and |Vi1| > |Vi2|, since F1 is the pulse change frequency of the first control signal and F2 is the pulse change frequency of the second control signal, to a certain extent, they represent the data refresh frequency. In actual operation, the data refresh frequency generally changes by several times or dozens of times. For example, when F1 is 60HZ and F2 is 30HZ, |F1 / F2| = 2; when F1 is 120HZ and F2 is 1HZ, |F1 / F2| = 120. The initialization signal is generally between -5V and 0V, and the difference between the first initialization signal Vi1 and the second initialization signal Vi2 is generally between 0V and 2V. Generally, a difference of 1V can generate the required effect difference in the initialization stage. Therefore, |Vi1 / Vi2| is generally small, and in this embodiment, |F1 / F2| > |Vi1 / Vi2| is set.

[0094] Optionally, in this embodiment, F02 is set as the separation frequency. When F1 > F2 > F02, |F1 / F2| < |Vi1 / Vi2|; when F02 > F1 > F2, |F1 / F2| > |Vi1 / Vi2|. Because as the data refresh frequency increases, F1 / F2 gradually decreases. For example, when F1 is 120HZ and F2 is 100HZ, |F1 / F2| = 1.2. If the first initialization signal Vi1 is -3V and the second initialization signal Vi2 is -2V, |Vi1 / Vi2| = 1.5. At this time, |F1 / F2| < |Vi1 / Vi2|, that is, when the data refresh frequency increases to a certain extent, F1 / F2 decreases, and |F1 / F2| < |Vi1 / Vi2| will not cause a large change in the initialization signal. When F02 > F1 > F2, as the data refresh frequency decreases, F1 / F2 gradually increases. For example, when F1 is 30HZ and F2 is 1HZ, |F1 / F2| = 30. At this time, if the first initialization signal Vi1 is -3V, and if the second initialization signal Vi2 is 30 times or 1 / 30 of the first initialization signal Vi1, it will cause the second initialization signal Vi2 to be too large or too small, and neither can play a good initialization role. Therefore, in this case, |F1 / F2| > |Vi1 / Vi2|. Generally, F02 can take the middle value of the data refresh frequency range. For example, for the case where the data refresh frequency varies in the range of 1HZ - 120HZ, F01 is the frequency value in the middle region, such as 40HZ - 80HZ, specifically, it can be 80HZ, 60HZ, 40HZ, etc.

[0095] Optionally, in this embodiment, the working process of the display panel includes a third stage and a fourth stage. The difference between the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the third stage and the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the fourth stage is ΔF2; the difference between the first initialization signal received by the first pixel circuit 101 in the third stage and the first initialization signal received by the first pixel circuit 101 in the fourth stage is ΔVi; where ΔF2≠0 and ΔVi≠0.

[0096] In this embodiment, there may be some situations where the data refresh frequency of the first display area 100 of the display panel may change, for example, from 60HZ to 30HZ. Since the pulse change frequency of the first control signal Vc1 determines the data refresh frequency, therefore, with the change of the data refresh frequency, the change amplitude of the pulse change frequency of the first control signal Vc1 is ΔF2. As described above, when the data refresh frequencies are different, the requirements for the initialization signal of the light-emitting element are different, or the requirements for the initialization degree of the light-emitting element are different when the data refresh frequencies are different. Therefore, it can be set that ΔVi≠0, that is, different initialization signals are set for different data refresh frequencies for separate adjustment.

[0097] Optionally, in this embodiment, ΔF2×ΔVi>0. Referring to the foregoing, when the initialization signal is a negative voltage, when the pulse change frequency of the first control signal decreases, the data refresh frequency decreases. At this time, because the anode of the light-emitting element stays at the same voltage for a longer time, in order to make the initialization process more sufficient, a lower initialization voltage can be set, that is, when the data refresh frequency decreases, the initialization signal decreases. At this time, if the initialization signal is negative, then the absolute value of the voltage value of the initialization signal increases instead. When the pulse change frequency of the first control signal increases, the data refresh frequency increases. At this time, because the anode voltage of the light-emitting element changes greatly, in order to meet the requirement of maintaining the change of the anode voltage, a relatively high initialization voltage value can be set, which is conducive to the rapid input of the anode voltage, that is, when the data refresh frequency increases, the initialization signal increases. At this time, if the initialization signal is negative, then the absolute value of the voltage value of the initialization signal decreases instead.

[0098] In some other situations, there may also be a situation where ΔF2×ΔVi<0. When the pulse change frequency of the first control signal increases and the data refresh frequency increases, in order to avoid the flicker problem during the switching between different frames as much as possible and ensure the display effect, at this time, a lower voltage value of the initialization signal can also be set, that is, when the data refresh frequency increases, the initialization signal decreases. Since the initialization signal is negative, its absolute value increases instead.

[0099] Optionally, in this embodiment, the absolute value of the ratio of the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the third stage to the pulse change frequency of the first control signal Vc1 received by the first pixel circuit 101 in the fourth stage is R21; the absolute value of the ratio of the first initialization signal received by the first pixel circuit 101 in the third stage to the first initialization signal received by the first pixel circuit 101 in the fourth stage is R22; where ΔF2 > 0 and R21 > R22.

[0100] Referring to the foregoing, generally speaking, the pulse change frequency of the first control signal Vc1 generally changes by several times or even dozens of times. For example, it changes from 60HZ to 1HZ, a 60-fold change. The initialization signal is generally between -5V and 0V, and the change of the initialization signal is generally in the range of 0 - 2V, which can affect the initialization degree. Therefore, the change amplitude of the initialization signal is smaller than the change amplitude of the pulse change frequency of the first control signal Vc1, that is, ΔF2 > 0 and R21 > R22.

[0101] Reference Figure 18 , Figure 18 FIG. is a schematic diagram of another display panel provided by an embodiment of the present application. The display panel includes an initialization signal bus 50. The initialization signal bus 50 provides a first initialization signal Vi1 for the first pixel circuit 101 and a second initialization signal Vi2 for the second pixel circuit 102 through an initialization signal line 500. When the control signal S15 controls the initialization module 117 in the first pixel circuit 101 to turn on, the control signal S25 controls the initialization module 117 in the second pixel circuit 102 to turn off, and the signal on the initialization signal bus 50 is the first initialization signal Vi1. When the control signal S15 controls the initialization module 117 in the first pixel circuit 101 to turn off, the control signal S25 controls the initialization module 117 in the second pixel circuit 102 to turn on, and the signal on the initialization signal bus 50 is the second initialization signal Vi2.

[0102] In this embodiment, since the first pixel circuit 101 and the second pixel circuit 102 are located in different display areas, in order to fully save the number of initialization signal buses and thus save the border area of the display panel, the same initialization signal bus can be used to provide initialization signals for the first pixel circuit 101 and the second pixel circuit 102. In this case, in order to prevent signal crosstalk, it is necessary to ensure that when the initialization module 117 in the first pixel circuit 101 is turned on, the initialization module 117 in the second pixel circuit 102 is turned off. At this time, the signal on the initialization signal bus 50 is the first initialization signal Vi1, which is used to provide an initialization signal for the first pixel circuit 101. When the initialization module 117 in the first pixel circuit 101 is turned off, the initialization module 117 in the second pixel circuit 102 is turned on. At this time, the signal on the initialization signal bus 50 is the second initialization signal Vi2, which is used to provide an initialization signal for the second pixel circuit 102.

[0103] In addition, optionally, in this embodiment, referring to Figure 19 , Figure 19 is a schematic diagram of another display panel provided by an embodiment of the present application. Among them, the display panel includes a first initialization signal bus 51 and a second initialization signal bus 52. The first initialization signal bus 51 provides a first initialization signal Vi1 for the first display area 100 through a first initialization signal line 501; the second initialization signal bus 52 provides a second initialization signal Vi2 for the second display area 200 through a second initialization signal line 502. When the border of the display panel permits, the first initialization signal bus 51 and the second initialization signal bus 52 can exist simultaneously, providing initialization signals for the first pixel circuit 101 and the second pixel circuit 102 respectively. In this case, the signals on the first initialization signal bus 51 and the second initialization signal bus 52 can remain unchanged. Moreover, when the first pixel circuit 101 receives the first initialization signal Vi1, the second pixel circuit 102 can also receive the second initialization signal Vi2, and the two processes can occur simultaneously without affecting each other.

[0104] Optionally, in this embodiment, during at least one stage of the operation process of the display panel, the light-emitting elements 20 in the first display area 100 operate in a first brightness mode, and the light-emitting elements 20 in the second display area 200 operate in a second brightness mode. The brightness of the first brightness mode is L1, and the brightness of the second brightness mode is L2, where L1 ≠ L2.

[0105] In this embodiment, the data refresh frequencies of different display areas are different to implement different display functions. Different display areas have different requirements for data refresh frequencies, which are often accompanied by different light emission brightness modes. For example, for areas where games, movies, etc. are played, a relatively high brightness mode is generally required to achieve a better user experience. For areas where time information, text, etc. are played, an eye protection mode with a relatively low brightness mode can generally be set to save power at the same time. Therefore, in this embodiment, it is further limited that the first display area 100 and the second display area 200 operate in different brightness modes. Optionally, the brightness of the first display area 100 is greater than that of the second display area 200, that is, L1 > L2. In some other embodiments, it can also be L1 < L2, depending on the specific application situation. This application does not make special limitations on this.

[0106] Another aspect of the embodiments of the present application provides an integrated chip. Refer to Figures 11 - 12 , and Figures 18 - 19 , wherein the integrated chip 600 is used to provide a first bias adjustment signal Vb1 for the first pixel circuit 101 of the first display area 100, and / or, used to provide a second bias adjustment signal Vb2 for the second pixel circuit 102 of the second display area 200; and / or, used to provide a first initialization signal Vi1 for the first pixel circuit 101 of the first display area 100, and / or, used to provide a second initialization signal Vi2 for the second pixel circuit 102 of the second display area 200.

[0107] Since different display areas are included in the present application, the bias adjustment signals received by different display areas may be different, and / or, the initialization signals received by different display areas may be different. These different bias adjustment signals or initialization signals can all be provided by the integrated chip 600.

[0108] Optionally, as Figure 11 shown, when the display panel includes a bias adjustment signal bus 40, when the bias adjustment module 114 in the first pixel circuit 101 is turned on and the bias adjustment module 114 in the second pixel circuit 102 is turned off, the integrated chip 600 provides a first bias adjustment signal Vb1 for the bias adjustment signal bus 40; when the bias adjustment module 114 in the first pixel circuit 101 is turned off and the bias adjustment module 114 in the second pixel circuit 102 is turned on, the integrated chip 600 provides a second bias adjustment signal Vb2 for the bias adjustment signal bus 40.

[0109] Optionally, as Figure 12 shown, when the display panel includes a first bias adjustment signal bus 41 and a second bias adjustment signal bus 42, the integrated chip 600 provides a first bias adjustment signal Vb1 for the first bias adjustment signal bus 41 and provides a second bias adjustment signal Vb2 for the second bias adjustment signal bus 42.

[0110] Optionally, as Figure 18 shown, when the display panel includes the initialization signal bus 50, when the initialization module 117 in the first pixel circuit 101 is turned on and the initialization module 117 in the second pixel circuit 102 is turned off, the integrated chip 600 provides the first initialization signal Vi1 for the initialization signal bus 50; when the initialization module 117 in the first pixel circuit 101 is turned off and the initialization module 117 in the second pixel circuit 102 is turned on, the integrated chip 600 provides the second initialization signal Vi2 for the initialization signal bus 50.

[0111] Optionally, as Figure 19 shown, when the display panel includes the first initialization signal bus 51 and the second initialization signal bus 52, the integrated chip 600 provides the first initialization signal Vi1 for the first initialization signal bus 41 and provides the second initialization signal Vi2 for the second initialization signal bus 42.

[0112] Another aspect of the embodiments of the present application provides a display device, including the display panel in any of the foregoing embodiments, and may also include the integrated chip in any of the foregoing embodiments.

[0113] Referring to Figure 20 , Figure 20 is a schematic diagram of a display device provided by the embodiments of the present application. Among them, the display device 800 includes a display panel 700. The display panel 700 may be the display panel described in any of the foregoing embodiments. The display device may be a mobile phone, a television, a laptop computer, a flat panel display device, a smart wearable display device, etc. The present application does not make special limitations on this.

[0114] Through the above description, the present application provides a display panel, an integrated chip, and a display device. The display panel includes a first pixel circuit 101 connected to the light-emitting element 20 of the first display area 100 and a second pixel circuit 102 connected to the light-emitting element 20 of the second display area 200. The control end of the first preset module 11 in the first pixel circuit 101 is used to receive a first control signal Vc1, and the control end of the first preset module 11 in the second pixel circuit 102 is used to receive a second control signal Vc2. During at least one stage of the operation of the display panel, the pulse change frequency F1 of the first control signal Vc1 is not equal to the pulse change frequency F2 of the second control signal Vc2. Since one end of the first preset module 11 is connected to the driving transistor T0 and is used to transmit a preset signal to the driving transistor T0, when F1≠F2, the frequency at which the first control signal Vc1 controls the first preset module 11 to turn on and off will be different from the frequency at which the second control signal Vc2 controls the first preset module 11 to turn on and off. Thus, the frequency at which the first pixel circuit 101 receives the preset signal will be different from the frequency at which the second pixel circuit 102 receives the preset signal. The preset signal can be a data signal Vdata, a reset signal Vref, a bias adjustment signal, etc. Through such a design, the present application realizes the frequency differentiation of the preset signals received by the first pixel circuit 101 and the second pixel circuit 102, so as to control the transmission of the preset signal for the first display area 100 and the second display area 200 according to their respective functions, and fully reduce power consumption while realizing their respective functions.

[0115] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is limited only to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Comprising: A first display area and a second display area; A pixel circuit, the pixel circuit including a first pixel circuit and a second pixel circuit, the first pixel circuit being connected to a light-emitting element in the first display area, and the second pixel circuit being connected to a light-emitting element in the second display area; During at least one stage of the operation of the display panel, the light-emitting elements in the first display area operate in a first brightness mode, and the light-emitting elements in the second display area operate in a second brightness mode. The brightness of the first brightness mode is L1, and the brightness of the second brightness mode is L2, where L1 ≠ L2; The pixel circuit includes a driving transistor and a bias adjustment module. The bias adjustment module is connected to a first pole or a second pole of the driving transistor and is used to provide a bias adjustment signal for the driving transistor; The bias adjustment module in the first pixel circuit is used to receive a first bias adjustment signal Vb1, and the bias adjustment module in the second pixel circuit is used to receive a second bias adjustment signal Vb2; wherein, Vb1 ≠ Vb2; And / or, The pixel circuit includes an initialization module. The initialization module is connected between an initialization signal terminal and the light-emitting element and is used to provide an initialization signal for the light-emitting element; the initialization module in the first pixel circuit is used to receive a first initialization signal Vi1, and the initialization module in the second pixel circuit is used to receive a second initialization signal Vi2; wherein, Vi1 ≠ Vi2.

2. The display panel according to claim 1, wherein The display panel includes a bias adjustment signal bus. The bias adjustment signal bus provides the first bias adjustment signal Vb1 for the first pixel circuit and the second bias adjustment signal Vb2 for the second pixel circuit through bias adjustment signal lines; wherein, When the bias adjustment module in the first pixel circuit is turned on, the bias adjustment module in the second pixel circuit is turned off, and the signal on the bias adjustment signal bus is the first bias adjustment signal Vb1; When the bias adjustment module in the first pixel circuit is turned off, the bias adjustment module in the second pixel circuit is turned on, and the signal on the bias adjustment signal bus is the second bias adjustment signal Vb2.

3. The display panel according to claim 1, wherein The display panel includes a first bias adjustment signal bus and a second bias adjustment signal bus; The first bias adjustment signal bus provides the first bias adjustment signal Vb1 for the first display area through a first bias adjustment signal line; The second bias adjustment signal bus provides the second bias adjustment signal Vb2 for the second display area through a second bias adjustment signal line.

4. The display panel according to claim 1, wherein The display panel includes an initialization signal bus. The initialization signal bus provides the first initialization signal Vi1 for the first pixel circuit and the second initialization signal Vi2 for the second pixel circuit through initialization signal lines; wherein, When the initialization module in the first pixel circuit is turned on, the initialization module in the second pixel circuit is turned off, and the signal on the initialization signal line is the first initialization signal Vi1; When the initialization module in the first pixel circuit is turned off, the initialization module in the second pixel circuit is turned on, and the signal on the initialization signal line is the second initialization signal Vi2.

5. The display panel according to claim 1, wherein: The display panel includes a first initialization signal bus and a second initialization signal bus; The first initialization signal bus provides the first initialization signal Vi1 for the first display area through a first initialization signal line; The second initialization signal bus provides the second initialization signal Vi2 for the second display area through a second initialization signal line.

6. The display panel according to claim 1, wherein: During at least one stage of the operation of the display panel, the operation process of the first pixel circuit includes a first data writing frame and a first holding frame, and the operation process of the second pixel circuit includes a second data writing frame and a second holding frame; wherein, Within the first data writing frame, the first bias adjustment signal is Vb11, and within the first holding frame, the first bias adjustment signal is Vb12; Within the second data writing frame, the second bias adjustment signal is Vb21, and within the second holding frame, the second bias adjustment signal is Vb22; wherein, Vb11≠Vb21, and / or, Vb12≠Vb22.

7. The display panel according to claim 6, wherein: |Vb11 - Vb21| = |Vb12 - Vb22|.

8. The display panel according to claim 6, wherein: |Vb11 - Vb21| > |Vb12 - Vb22|, or, |Vb11 - Vb21| < |Vb12 - Vb22|.

9. The display panel according to claim 1, wherein: The pixel circuit includes: A data writing module, the data writing module is connected to the first pole of the driving transistor and is used to provide a data signal for the driving transistor; and / or, A compensation module, the compensation module is connected between the gate and the second pole of the driving transistor; and / or, A reset module, the reset module is connected to the gate or the second pole of the driving transistor and is used to provide a reset signal for the driving transistor; and / or, A light emission control module, the light emission control module is connected between the first power signal terminal and the driving transistor, or the light emission control module is connected between the driving transistor and the light emitting element, and is used to selectively allow the light emitting element to enter the light emission stage.

10. The display panel according to claim 1, wherein: The pixel circuit includes a first preset module, and one end of the first preset module is connected to the driving transistor; The control terminal of the first preset module in the first pixel circuit is used to receive a first control signal, and the control terminal of the first preset module in the second pixel circuit is used to receive a second control signal; During at least one stage of the operation of the display panel, the pulse change frequency of the first control signal is F1, and the pulse change frequency of the second control signal is F2, where F1 ≠ F2.

11. The display panel according to claim 10, wherein F1 > F2; and, |F1 / F2| > |Vb1 / Vb2|, and / or, |F1 / F2| > |Vi1 / Vi2|.

12. The display panel according to claim 10, wherein When F1 > F2 > F01, |F1 / F2| < |Vb1 / Vb2|; When F01 > F1 > F2, |F1 / F2| > |Vb1 / Vb2|.

13. The display panel according to claim 10, wherein When F1 > F2 > F02, |F1 / F2| < |Vi1 / Vi2|; When F02 > F1 > F2, |F1 / F2| > |Vi1 / Vi2|.

14. The display panel according to claim 10, wherein The operation process of the display panel includes a first stage and a second stage; The difference between the pulse change frequency of the first control signal received by the first pixel circuit in the first stage and the pulse change frequency of the first control signal received by the first pixel circuit in the second stage is ΔF1; The difference between the first bias adjustment signal received by the first pixel circuit in the first stage and the first bias adjustment signal received by the first pixel circuit in the second stage is ΔVb; where ΔF1 × ΔVb < 0, or, ΔF1 × ΔVb > 0.

15. The display panel according to claim 14, wherein The absolute value of the ratio of the pulse change frequency of the first control signal received by the first pixel circuit in the first stage to the pulse change frequency of the first control signal received by the first pixel circuit in the second stage is R11; The absolute value of the ratio of the first bias adjustment signal received by the first pixel circuit in the first stage to the first bias adjustment signal received by the first pixel circuit in the second stage is R12; where ΔF1 > 0, and R11 > R12.

16. The display panel according to claim 10, wherein The operation process of the display panel includes a third stage and a fourth stage; The difference between the pulse change frequency of the first control signal received by the first pixel circuit in the third stage and the pulse change frequency of the first control signal received by the first pixel circuit in the fourth stage is ΔF2; The difference between the first initialization signal received by the first pixel circuit in the third stage and the first initialization signal received by the first pixel circuit in the fourth stage is ΔVi; where ΔF2 × ΔVi > 0, or, ΔF2 × ΔVi < 0.

17. The display panel according to claim 16, wherein the absolute value of the ratio of the pulse change frequency of the first control signal received by the first pixel circuit in the third stage to the pulse change frequency of the first control signal received by the first pixel circuit in the fourth stage is R21; the absolute value of the ratio of the first initialization signal received by the first pixel circuit in the third stage to the first initialization signal received by the first pixel circuit in the fourth stage is R22; wherein, ΔF2 > 0, and R21 > R22.

18. The display panel according to claim 10, wherein the first preset module is a data writing module, and the data writing module is connected to the first pole of the driving transistor for providing a data signal to the driving transistor; or, the first preset module is a compensation module, and the compensation module is connected between the gate and the second pole of the driving transistor; or, the first preset module is a reset module, and the reset module is connected to the gate or the second pole of the driving transistor for providing a reset signal to the driving transistor; or, the first preset module is the bias adjustment module.

19. An integrated chip, wherein it is configured to provide the first bias adjustment signal Vb1 and / or the second bias adjustment signal Vb2 for the display panel according to any one of claims 1-18; or, it is configured to provide the first initialization signal Vi1 and / or the second initialization signal Vi2 for the display panel according to any one of claims 1-18.

20. A display device, characterized in that, It includes the display panel according to any one of claims 1-18.

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