Memory testing device, three-dimensional stacked memory chip, and memory testing method and system

Abstract

The present invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method, and a testing system. A built-in self-test (BIST) test process and first to third configuration registers are embedded in the memory testing device. Therefore, only a prescribed test stimulus needs to be applied on a test host to automatically implement testing of corresponding functional parameters of the three-dimensional stacked memory chip. During testing, switching of functional parameters, test directions, and test modes only needs to be implemented by adjusting configuration values in the first to third configuration registers. Thus, the test process of the functional parameters of the memory is optimized, greatly saving test time and test costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a memory testing device, a three-dimensional stacked memory chip, and a memory testing method and system. Background Art

[0002] With the development of artificial intelligence (AI), the demand for computing power is increasing, and DRAM (dynamic random access memory) chips are being used in a growing number of scenarios. Efficiently testing the timing parameters and functionality of DRAM chips has become a key issue for those skilled in the art.

[0003] Currently, DRAM chip testing mainly relies on corresponding machines. These machines use robots to grab and sort chips. They can test 128 to 256 DRAM chips at a time under high temperature conditions (for example, 88°C). However, the testing methods of these machines are costly and inflexible.

[0004] At the same time, since some delays are inevitable when accessing DRAM chips, the bandwidth utilization of the data interface in system integration is greatly limited. Summary of the Invention

[0005] The object of the present invention is to provide a memory testing device, a three-dimensional stacked memory chip, and a memory testing method and system, which can efficiently test the corresponding functional parameters of the three-dimensional stacked memory chip and save testing time and cost.

[0006] To achieve the above objectives, the present invention provides a memory testing device embedded in a three-dimensional stacked memory chip or disposed outside the three-dimensional stacked memory chip, wherein the three-dimensional stacked memory chip includes multiple layers of memory dies stacked together, and the memory testing device is embedded with:

[0007] A first configuration register is used to configure a test gear of a current functional parameter to be tested;

[0008] A second configuration register is used to configure a test mode corresponding to the current function parameter;

[0009] a third configuration register, configured to configure a test instruction for the current function parameter, wherein different test instructions indicate different at least one of a test direction and an operation type;

[0010] a built-in self-test module, having a built-in self-test process embedded therein, and configured to receive a corresponding test stimulus and, in the test gear configured in the first configuration register and the test mode configured in the second configuration register, activate a corresponding word line or bit line in the three-dimensional stacked memory chip according to a test instruction configured in the third configuration register, so as to execute the built-in self-test process and test the current functional parameters of the three-dimensional stacked memory chip;

[0011] The configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register is adjusted according to a test result of the built-in self-test module.

[0012] Optionally, the built-in self-test process includes:

[0013] Writing test vector data into the three-dimensional stacked memory chip;

[0014] Reading corresponding data from the three-dimensional stacked memory chip and comparing the read data with the written data to see whether they are consistent;

[0015] If they are consistent, the configuration value in the first configuration register is adjusted to reduce the test level, thereby causing the built-in self-test module to retest the current functional parameters of the 3D stacked memory chip under the reduced test level.

[0016] Optionally, if the read data is inconsistent with the written data, the built-in self-test module is further configured to perform Shmoo chart analysis on the test result to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter.

[0017] Optionally, after the built-in self-test module completes the test of the current functional parameter, the configuration value of at least one of the first configuration register, the second configuration register and the third configuration register is adjusted so that the built-in self-test module performs the next functional parameter test on the three-dimensional stacked memory chip.

[0018] Optionally, when the test direction indicated by the test instruction in the third configuration register is the word line direction, after activating the corresponding word line and writing a predetermined number of test vector data, the address in the bit line direction automatically points to the next bit line; when the test direction indicated by the test instruction in the third configuration register is the bit line direction, after writing a predetermined number of test vector data, the address in the word line direction automatically points to the next word line.

[0019] Optionally, when the test direction is the word line direction, different configuration values in the second configuration register can implement a basic mode and an extended mode, the basic mode including at least one of an all-0 mode, an all-1 mode, and a checkerboard mode, and the extended mode including at least one of an inter-row alternating mode and a word line adjustable step mode;

[0020] And / or, when the test direction is the bit line direction, different configuration values in the second configuration register can implement an odd and even column alternating activation test mode and a diagonal column interference test mode.

[0021] Optionally, the built-in self-test process performed in the word line direction further includes at least one of the following operations (1) to (4):

[0022] (1) performing voltage gradient scanning on corresponding word lines in the three-dimensional stacked memory chip using corresponding voltage step sizes;

[0023] (2) negatively overdriving corresponding word lines in the three-dimensional stacked memory chip to detect leakage by reverse biasing;

[0024] (3) updating the reference voltage once each time a preset number of writes are completed in the three-dimensional stacked memory chip;

[0025] (4) Adding a row interference test enhancement instruction to the current functional parameter test, wherein the row interference test enhancement instruction is used to implement coupling testing and / or refresh interval insertion of adjacent word lines in the three-dimensional stacked memory chip.

[0026] Optionally, the built-in self-test process performed in the bit line direction further includes at least one of the following operations (1) to (3):

[0027] (1) dynamically adjusting a bias voltage of a readout amplifier for reading corresponding data in the three-dimensional stacked memory chip;

[0028] (2) injecting enable timing jitter into a sense amplifier for reading corresponding data in the three-dimensional stacked memory chip;

[0029] (3) Apply high-speed data transitions and measure the bit line voltage build-up time to implement bit line slew rate testing.

[0030] Optionally, the current functional parameter includes at least one timing parameter, and the timing parameter includes at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, and tFAW.

[0031] Optionally, the three-dimensional stacked memory chip also includes a memory controller, the memory testing device is embedded in the memory controller, the memory controller is arranged in the buffer bare core, and the multi-layer memory bare cores and between the multi-layer memory bare cores and the buffer bare cores are hybrid bonded together through silicon vias; or, the memory testing device is arranged in a main control chip outside the three-dimensional stacked memory chip.

[0032] Based on the same inventive concept, the present invention also provides a three-dimensional stacked memory chip, which includes a memory controller and multiple layers of memory bare cores stacked together, wherein the memory controller is embedded with the memory testing device as described in the present invention.

[0033] Based on the same inventive concept, the present invention also provides a memory testing system, which includes: a three-dimensional stacked memory chip, a test host and a memory testing device as described in the present invention; wherein, the three-dimensional stacked memory chip includes a memory controller and multiple layers of memory bare cores stacked together, the memory controller is embedded with the memory testing device, or the memory testing device is arranged in a test chip outside the three-dimensional stacked memory chip, the test host applies corresponding test stimulus to the memory testing device, so that the memory testing device activates the corresponding word line or bit line in the three-dimensional stacked memory chip, and then performs corresponding functional parameter testing on the three-dimensional stacked memory chip.

[0034] Based on the same inventive concept, the present invention also provides a memory testing method, which includes the following steps:

[0035] Provided are a memory testing device and a three-dimensional stacked memory chip to be tested according to the present invention, wherein the memory testing device is disposed outside the three-dimensional stacked memory chip or embedded in a memory controller within the three-dimensional stacked memory chip, and wherein the memory testing device embeds a corresponding built-in self-test process, a first configuration register, a second configuration register, and a third configuration register;

[0036] Determining a current functional parameter to be tested and its test direction, and configuring a test gear of the current functional parameter by writing a corresponding configuration value into the first configuration register, configuring a test mode corresponding to the current functional parameter by writing a corresponding configuration value into the second configuration register, and configuring a test instruction corresponding to the current functional parameter by writing a corresponding configuration value into the third configuration register, where different test instructions indicate different at least one of a test direction and an operation type;

[0037] A corresponding test stimulus is applied to the memory test device through a test host. The memory test device receives the test stimulus and activates the corresponding word lines or bit lines in the three-dimensional stacked memory chip in accordance with the test instructions configured in the third configuration register under the test gear configured in the first configuration register and the test mode configured in the second configuration register, so as to execute the built-in self-test process and test the current functional parameters of the three-dimensional stacked memory chip.

[0038] Optionally, the built-in self-test process includes:

[0039] receiving the test stimulus sent by the test host, and writing test vector data into the three-dimensional stacked memory chip;

[0040] Reading corresponding data from the three-dimensional stacked memory chip and comparing the read data with the written data to see whether they are consistent;

[0041] If they are consistent, adjusting the configuration value in the first configuration register to reduce the test gear, and then re-executing the built-in self-test process under the reduced test gear until the read data is inconsistent with the written data;

[0042] If there is inconsistency, a Shmoo chart analysis is performed on the current test result to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter;

[0043] After completing the test of the current functional parameter, determine whether the current functional parameter is the last functional parameter to be tested. If so, end the test; if not, adjust the configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register to perform the next current functional parameter test on the three-dimensional stacked memory chip.

[0044] Compared with the prior art, the memory testing device, three-dimensional stacked memory chip, and memory testing method and system provided by the present invention embed a built-in self-test (BIST) test process and first to third configuration registers in the memory testing device. Therefore, only the specified test stimulus needs to be applied on the test host to automatically implement the testing of the corresponding functional parameters of the three-dimensional stacked memory chip. During the test, the switching of functional parameters, test direction, and test mode only needs to be achieved by adjusting the configuration values in the first to third configuration registers. Therefore, the test process of the functional parameters of the memory is optimized, greatly saving test time and test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0046] Figure 1 and Figure 2 1 is a schematic diagram of a memory testing device and a testing system architecture according to an embodiment of the present invention.

[0047] Figure 3 Schematic diagram of the structure of a memory unit in a three-dimensional stacked memory chip according to an embodiment of the present invention.

[0048] Figure 4 A schematic diagram of a packaging structure of a three-dimensional stacked memory chip according to an embodiment of the present invention.

[0049] Figure 5 FIG. 1 is a schematic diagram of some configuration values in the third configuration register of a memory testing device according to an embodiment of the present invention.

[0050] Figure 6 This is a schematic diagram of establishing Shmoo diagram parameters based on measurement results when a memory testing device according to an embodiment of the present invention is used for testing.

[0051] Figure 7 FIG. 4 is a flow chart of a memory testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] An embodiment of the present invention provides a memory testing device 10a, which can be embedded in a three-dimensional stacked memory chip 1, such as Figure 1 The memory test device 10a can also be placed outside the three-dimensional stacked memory chip 1, as shown; Figure 2 shown.

[0054] In one example, combine Figure 2 The memory testing device 10a is set in a main control chip outside the three-dimensional stacked memory chip 1. The main control chip serves as a test host 2 for the three-dimensional stacked memory chip 1 after leaving the factory. It can include a main control processor 20 and the memory testing device 10a, etc. The main control processor can include any type of processing device with computing processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processing device can be configured to execute instructions or software (including code, operating system or application, etc.) that can be executed by one or more computers, firmware or a combination thereof.

[0055] Based on this, please refer to Figure 1 and Figure 4 This embodiment further provides a three-dimensional stacked memory chip 1, which includes a memory controller 10 and n+1 layers of stacked memory dies D0~Dn. The memory controller 10 is embedded with a memory test device 10a as described in this embodiment.

[0056] The memory stack 11 is formed by stacking n+1 layers of memory die D0-Dn. Each memory die D0-Dn can be a DRAM or any other suitable type of memory die. The DRAM can be any suitable type, such as synchronous DRAM (SDRAM) or wide I / O DRAM. The memory stack 11 can be implemented as an unbuffered dual in-line memory module (UDIMM), registered DIMM (RDIMM), load-reduced DIMM (LRDIMM), fully buffered DIMM (FBDIMM), small outline DIMM (SODIMM), etc. The memory test device 10a is embedded in the memory controller 10, which is provided in the buffer die 105. The n+1 layers of memory die D0-Dn and the buffer die 105 are connected together by through-silicon via (TSV) hybrid bonding.

[0057] Please refer to Figure 3Each memory die D0-Dn may include multiple memory units (also called "data units"). Each memory unit may have a memory array determined by the intersection of multiple word lines WL (each word line can be considered a row) and multiple bit lines BL (each bit line can be considered a column). The memory array has multiple cells. Each cell is located at the intersection of a word line WL and a bit line BL corresponding to the memory unit, that is, corresponds to a memory address determined by the root word line WL and the root bit line BL. The word line WL (wordline) is addressed by the row address (RA) in the memory address, and the bit line BL (bitline) is addressed by the column address (CA) in the memory address. A memory unit can be a memory block, a sector, a page, or any other suitable management unit above the cell level in the memory stack 11. Among them, a page contains multiple bytes (whose address range can be determined by multiple word lines and multiple bit lines), a sector contains multiple pages, a storage block contains multiple sectors, and multiple storage units can form a storage unit (Bank).

[0058] It should be understood that in the example where the memory test device 10a is embedded in the memory controller 10 of the three-dimensional stacked memory chip 1, the memory controller 10, in addition to the memory test device 10a, may also have other logic modules (not shown) such as an input / output interface 100 to implement other functions. For example, the other logic modules in the memory controller 1 may include circuits for performing error correction (e.g., ECC correction) on the memory, circuits for clock and frequency control (e.g., a phase-locked loop (PLL)), circuits for managing power consumption and temperature, first-in, first-out queue registers (FIFOs), and any other required circuits. These circuits are not the focus of the present invention and are therefore not described in detail here. The input / output interface 100 may be any suitable parallel communication protocol interface that supports multiple IOs, such as any suitable high-bandwidth protocol interface such as an AXI (Advanced eXtensible Interface) interface or a CHI (Coherent Hub Interface) interface, but the present invention is not limited thereto. Among them, the AXI interface is an on-chip bus interface for high-performance, high-bandwidth, and low-latency master-slave architecture. Its address, instruction, and data phases are separated, supporting unaligned data transmission. At the same time, in burst transmission, only the first address is required. At the same time, the read and write data channels are separated, and it supports transmission access and out-of-order access with a large number of outstanding instructions to be executed (for example, the number of unfinished transactions such as read and write instructions), and is easier to perform timing convergence, making it suitable for high-speed memory access.

[0059] Please continue to refer to Figure 1 and Figure 2 、 Figure 4 The memory test device 10 a is embedded with a first configuration register 101 , a second configuration register 102 , a third configuration register 103 and a built-in self-test module 104 .

[0060] Among them, the first configuration register 101 is used to configure the test gear of the current functional parameter to be tested, the second configuration register 102 is used to configure the test mode corresponding to the current functional parameter, and the third configuration register 103 is used to configure the test instruction of the current functional parameter. Different test instructions indicate at least one of different test directions and operation types.

[0061] Furthermore, the configuration value of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 is adjusted based on the test results of the built-in self-test module 104. This adjustment can be performed by a test program on the test host 2, or the memory test device 10a can automatically perform the adjustment based on the test results (i.e., the memory test device 10a automatically adjusts the corresponding configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103 based on the test results).

[0062] In one example, the test instruction cmd_t configured in the third configuration register 103 is as follows: Figure 5 In this example, the upper 4 bits of the third configuration register MR2 can be used to represent the test instruction cmd_t, and the upper 4 bits can be configured to be equal to different values to represent the corresponding test direction and the type of operation implemented in the test direction, for example:

[0063] cmd_t[3:0]=h1=0001, represents the write operation in the direction of word line WL (write, Figure 5 abbreviated as "WR" in Chinese);

[0064] cmd_t[3:0]=h2=0010, represents the read operation in the direction of word line WL (read, Figure 5 abbreviated as "RD" in Chinese);

[0065] cmd_t[3:0]=h3=0011, represents the read-before-write operation in the word line WL direction ( Figure 5 abbreviated as "RD-WR" in Chinese);

[0066] cmd_t[3:0]=h4=0100, represents the write-before-read operation in the word line WL direction ( Figure 5 abbreviated as "WR-RD" in Chinese);

[0067] cmd_t[3:0]=h5=0101, representing the refresh operation in the word line WL direction;

[0068] ...(other operations in the word line WL direction);

[0069] cmd_t[3:0]=ha=1010, representing a write operation in the direction of the bit line BL;

[0070] cmd_t[3:0]=hb=1011, represents the read operation in the direction of bit line BL;

[0071] cmd_t[3:0]=hc=1100, indicating a read-before-write operation in the bit line BL direction;

[0072] cmd_t[3:0]=hd=1101, represents the write-before-read operation in the direction of bit line BL;

[0073] cmd_t[3:0]=he=1110, represents the refresh operation in the direction of bit line BL;

[0074] ...(other operations in the bit line WL direction).

[0075] It should be understood that the value of the test instruction configured in the third configuration register 103 is not limited to the above-mentioned h0~h8, and there may be other configuration values to indicate other operation types and test directions, such as a write-first-read-then operation in the word line direction, a write-first-read-then operation in the bit line direction, etc. The present invention does not make specific limitations on this.

[0076] In addition, when the test direction indicated by the test instruction cmd_t in the third configuration register 103 is the word line WL direction, after activating the corresponding word line WL in the three-dimensional stacked memory chip 1 and writing a predetermined number (for example, 1 burst) of test vectors (test pattern, 1 test pattern, for example, including 1 byte of data) of data, the address in the bit line BL direction (i.e., the column address) automatically points to the next bit line BL (i.e., the column address automatically increments); when the test direction indicated by the test instruction cmd_t in the third configuration register 103 is the bit line direction, after writing a predetermined number (for example, 1 burst) of test vectors (1 test pattern, for example, including 1 byte of data) of data, the address in the word line direction (i.e., the row address) automatically points to the next word line (i.e., the row address automatically increments). Thus, when testing a functional parameter of a 3D stacked memory chip 1 using the memory test apparatus of this embodiment, the entire memory array of a corresponding memory cell in the 3D stacked memory chip 1 can be read / written / read-first-then-write / write-first-then-read / refreshed. The specific operation depends on which test instructions cmd_t are configured in the third configuration register 103. A burst refers to the number of data blocks that the 3D stacked memory chip 1 (e.g., a DRAM) can transfer in a single access. The length of a burst is, for example, 8 / 34 / 64 bytes.

[0077] For another example, when the test direction indicated by the test instruction in the third configuration register 103 is the word line direction, different configuration values in the second configuration register 102 can achieve:

[0078] (1) Basic mode; the basic mode includes at least one of any appropriate test patterns such as all-0 (0x00) mode, all-1 (0xFF) mode, checkerboard (0xAA / 0x55) mode (or the test pattern is 0x00, 0xFF, 0xAA, 0x55);

[0079] (2) Extended mode; the extended mode includes at least one of an inter-row alternating mode (complementary data is written to adjacent rows) and a word line adjustable step mode (for example, the step number can be 0 / 1 / 2 / 4 / 8 / 16 / 32), and the step jump method is adjustable by the configuration of the second configuration register 102 (for example, when activating row x, pre-charge row x ±1 / 2 / 4 / 8).

[0080] For another example, when the test direction indicated by the test instruction in the third configuration register 103 is the bit line direction, different configuration values in the second configuration register 102 can achieve:

[0081] (1) Odd and even columns are activated alternately in test mode: even columns are written with 0x00, odd columns are written with 0xFF;

[0082] (2) Diagonal column interference test mode: When column y is activated, reverse data is applied to columns y+1 / 2 / 4 / 8 by configuration.

[0083] In this embodiment, a built-in self-test (BIST) process is embedded in the built-in self-test module 104. The built-in self-test module 104 is configured to receive a test stimulus applied by a test host and, in accordance with the test instructions configured in the third configuration register 103, activate the corresponding word lines WL or bit lines BL in the three-dimensional stacked memory chip 1 under the test level configured in the first configuration register 101 and the test mode configured in the second configuration register 102, thereby executing the corresponding built-in self-test process and testing the current functional parameters of the three-dimensional stacked memory chip 1. The configuration value of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 can be adjusted based on the test results of the built-in self-test module 104. This adjustment can be implemented by a test program of the test host 2 or automatically by the memory testing device 10a.

[0084] In one example, the built-in self-test process in the built-in self-test module 104 includes:

[0085] Writing test vector data into the three-dimensional stacked memory chip 1, for example, writing all "0" (for example, data 0x00) or all "1" (for example, data 0xFF) to the entire storage array of the corresponding storage unit, or writing "0" or "1" in a checkerboard manner (for example, data 0xAA and 0x55 interlaced), etc.;

[0086] Read the corresponding data in the three-dimensional stacked memory chip 1 and compare the read data with the written data to see if they are consistent (e.g. Figure 7 (as shown in step S4 in FIG);

[0087] If they are consistent, the configuration value in the first configuration register 101 is adjusted to reduce the test level, thereby causing the built-in self-test module 104 to retest the current functional parameters of the three-dimensional stacked memory chip 1 at the reduced test level.

[0088] If they are inconsistent, perform Shmoo chart analysis on the current test results (such as Figure 6 As shown in the figure, the final value of the current function parameter is determined, and the test of the current function parameter is completed (as shown in the figure). Figure 7The Shmoo plot is a key analysis method in semiconductor manufacturing and integrated circuit testing. During testing, the current functional parameters of the three-dimensional stacked memory chip 1 are repeatedly tested within a specific parameter range (for example, the bit line voltage margin), and the pass / fail results are recorded. A two-dimensional visualization chart can be generated between the current functional parameter and the specific parameter.

[0089] Optionally, after the built-in self-test module 104 completes the test of the current functional parameters, the configuration value of at least one of the first configuration register 101, the second configuration register 102 and the third configuration register 103 is adjusted so that the built-in self-test module 104 performs the next functional parameter test on the three-dimensional stacked memory chip 1.

[0090] When switching to the next functional parameter test, the test mode and test instructions (i.e., the configuration values of the second configuration register 102 and the third configuration register 103) may need to be adjusted. In this case, the test program of the test host 2 or the built-in self-test module 104 of the memory test device 10a can be used to select the functional parameters whose required configuration values are closest to the configuration values when the previous functional parameter test is completed as the functional parameters for the next test.

[0091] In one example, the built-in self-test process performed by the built-in self-test module 104 in the word line WL direction further includes at least one of the following operations (1) to (4):

[0092] (1) A voltage gradient scan is performed on the corresponding word lines in the three-dimensional stacked memory chip 1 using a corresponding voltage step size. For example, the step range of the applied excitation voltage VPP is: 2.5V~3.3V, and the voltage step size is 50mV.

[0093] (2) The corresponding word lines WL in the three-dimensional stacked memory chip 1 are negatively overdriven to detect leakage by applying a reverse bias voltage (eg, −100 mV).

[0094] (3) After a preset number of writes (for example, 32 times) in the three-dimensional stacked memory chip 1 are completed, the reference voltage VREF is updated once, thereby achieving dynamic reference voltage VREF calibration.

[0095] (4) Adding a row interference test enhancement instruction to the current functional parameter test, wherein the row interference test enhancement instruction is used to implement coupling testing and / or refresh interval insertion of adjacent word lines in the three-dimensional stacked memory chip.

[0096] In one example, the built-in self-test process performed by the built-in self-test module 104 in the direction of the bit line BL further includes at least one of the following operations (1) to (3):

[0097] (1) Dynamically adjust the bias voltage VBL (also the bit line voltage) of the read amplifier used to read the corresponding data in the three-dimensional stacked memory chip, for example, in normal mode: VBL=0.5VDDQ; in extreme test mode: VBL=0.45VDDQ~0.55VDDQ scan, wherein the voltage VDDQ is the power supply voltage of the input and output interface circuit of the three-dimensional stacked memory chip 1, which is mainly used to drive the data transmission between the memory controller 10 of the three-dimensional stacked memory chip 1 and an external device (such as a CPU).

[0098] (2) Injecting enable timing jitter into the sense amplifier (SA) used to read the corresponding data in the three-dimensional stacked memory chip 1, for example, adding a ±20ps timing disturbance within the tRCD window, where tRCD (RAS to CAS Delay) is the row-to-column delay time, that is, the delay time from row address strobe (RAS) to column address strobe (CAS). In the operation of the three-dimensional stacked memory chip 1, tRCD is an important timing parameter of the three-dimensional stacked memory chip 1, which determines the minimum time interval required from activating a row address of the three-dimensional stacked memory chip 1 to reading or writing a column address in the row.

[0099] (3) Apply high-speed data transitions (e.g., alternating between 0→1 and 1→0) and measure the bit line voltage setup time to implement a bit line slew rate test. During the bit line slew rate test, an on-chip time-voltage converter (TVC) can be used to sample the bit line, with a sampling point density of, for example, one measurement point every 10 ps.

[0100] The memory testing device 10a of this embodiment can test any appropriate one or more functional parameters of the three-dimensional stacked memory chip 1. These functional parameters include at least one timing parameter, which can include at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW, etc. Each timing parameter can be measured in the word line WL direction or in the bit line BL direction. That is, when writing test vector data, write / read / read first then write / write first then read / refresh operations can be performed in the order of self-incrementing row addresses (testing direction is the bit line BL direction), or write / read / read first then write / write first then read / refresh operations can be performed in the order of self-incrementing column addresses (testing direction is the word line WL direction).

[0101] Among them, tRAS (Active to Precharge Delay) represents the minimum time interval between issuing a row activation command and being able to issue a row precharge command. This interval is also measured in units of clock cycles tck. In the operation of three-dimensional stacked memory chips 1 such as DRAM, each data access begins with row activation, and the required data row is activated through a specific row selection command. Subsequently, the system accesses a specific column address in the row to read or write data. Once the data access is completed, in order to free up resources and prepare for the next access, the system issues a row precharge command to close the current row. tRAS strictly stipulates the shortest time interval from row activation to row precharge. In terms of system performance, a smaller tRAS value means that the three-dimensional stacked memory chip 1 can complete the transition from row activation to row precharge more quickly, thereby improving the speed of data access and overall system performance.

[0102] tRCD (Row Command Delay) refers to the minimum time interval between issuing a row activation (Active) command and being able to issue a column address selection command (it is also the time it takes for data to be transmitted from the storage cell of a three-dimensional stacked memory chip 1 such as DRAM to the read amplifier (SA) after a row is activated). This interval is measured in units of clock cycles tck. In the addressing process of the three-dimensional stacked memory chip 1, the memory bank address and the memory unit address are generally determined first, followed by the row address, and finally the specific cell is located by the column address. In actual operation, the memory bank address, the memory unit address and the corresponding row address are issued synchronously. This process is called "row activation". After the row activation is completed, the column address addressing command and the corresponding operation instruction are issued to indicate whether a read operation or a write operation is to be performed. These two commands can be collectively referred to as "read / write commands."

[0103] ‌tCOLOFF2WLOFF (column off to WL off delay) is the minimum time interval between the deactivation of the column address strobe command and the deactivation of the row activate command. This interval is measured in clock cycles, tck.

[0104] tRP (Row Precharge Time) represents the minimum time interval between issuing a row precharge command and being able to issue a row activation command again. This interval is also measured in units of clock cycles tck. In the operation of three-dimensional stacked memory chips 1 such as DRAM, each data access requires activating a row first, and then reading or writing data through the column address. When a row of data is accessed, in order to free up resources and prepare for the next access, a row precharge command needs to be issued to close the current row. tRP defines the shortest time required for a row to be closed and another row to be activated. In terms of performance impact, a smaller tRP value means that the three-dimensional stacked memory chip 1 can complete row switching in a shorter time, thereby improving access speed and overall performance.

[0105] tWR (Write Recovery Time) is the minimum interval between the last write command and the next row precharge command. This interval is also measured in clock cycles. In DDR memory, after a data write operation is completed, a certain recovery time is required to ensure that the data is correctly stored in the memory cell. tWR exists precisely to define this recovery time interval. It ensures sufficient time for data recovery after the write operation is complete, thus avoiding potential data errors.

[0106] tCAS (Column Access Time) is the minimum time the CAS signal must remain active to latch the column address and initiate a read or write operation. This time is measured in clock cycles, tck. For most memory operations, including those on three-dimensional stacked memory chips like DRAM, the CAS signal must remain inactive for at least tCP before being activated again.

[0107] tCL (CAS Latency) is the time interval from when the memory controller 10 issues a read command to when the first data is available, measured in clock cycles (tck). A smaller tCAS value means faster memory response time.

[0108] tWTR (Write to Read Delay) represents the minimum time interval between executing a write command and being able to issue a read command. This interval is also measured in clock cycles, tck. In three-dimensional stacked memory chips such as DRAM, it reflects the number of clock cycles that must pass between the last valid write operation and the next read operation of the same cell. During the operation of three-dimensional stacked memory chips such as DRAM, a certain time interval must be maintained between write and read operations to ensure that the newly written data is correctly stored and does not interfere with subsequent read operations. tWTR exists precisely to define this necessary time interval, ensuring sufficient recovery time after the write operation is completed, thereby avoiding possible data errors.

[0109] tRC (Row Cycle Time) is the minimum time interval between issuing an activate command for a row and issuing another activate command for the same row. This interval is measured in clock cycles (tck) and is calculated using the formula: tRC = tRAS + tRP. The size of tRC directly affects the memory row switching speed, and thus the overall system performance. The smaller tRC, the faster the memory row switching speed and the better the system performance.

[0110] tRFC (Row Refresh Cycle Time) represents the minimum time between the issuance of one row refresh command and the issuance of the next. This interval, measured in nanoseconds, ensures that all rows of memory data are refreshed within the predetermined period.

[0111] tCCD (CAS to CAS Delay) refers to the time interval between CAS commands and CAS commands, representing the timing of the minimum burst duration, or the minimum column to column command timing

[0112] tRTP (Read to Precharge Delay) refers to the time interval between the completion of a read operation and the start of precharge.

[0113] tFAW (Four Activation Window) refers to the minimum time interval between row strobe commands issued in the same refresh cycle.

[0114] These timing parameters together determine the performance and stability of three-dimensional stacked memory chips 1 such as DRAM, and are crucial for the design and optimization of memory systems.

[0115] Based on the same invention concept, please refer to Figures 1 to 4 This embodiment further provides a memory testing system, comprising: a three-dimensional stacked memory chip 1, a test host 2, and a memory testing device 10a as described in this embodiment. The three-dimensional stacked memory chip 1 includes a memory controller 10 and n+1 stacked layers of memory die D0-Dn. The memory testing device 10a is embedded in the memory controller 10, or alternatively, the memory testing device 10a is disposed in a main control chip external to the three-dimensional stacked memory chip 1.

[0116] In an example, see Figure 1 As shown, the test host 2 can be a test machine for the three-dimensional stacked memory chip 1 before leaving the factory. It can be coupled to the memory test device 10a through a probe card to apply corresponding test stimulus to the memory test device 10a, so that the memory test device 10a can activate the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1, and then perform corresponding functional parameter tests on the three-dimensional stacked memory chip 1.

[0117] In another example, see Figure 1 and Figure 2 The test host 2 can also be the main control chip of the three-dimensional stacked memory chip 1 after leaving the factory. The memory test device 10a can be integrated in the memory controller 10 of the three-dimensional stacked memory chip 1, or it can be integrated outside the main control chip to apply corresponding test stimulus to the memory test device 10a, so that the memory test device 10a can activate the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1, and then perform corresponding functional parameter tests on the three-dimensional stacked memory chip 1.

[0118] Based on the same invention concept, please refer to Figure 7 , and combined with Figures 1 to 6 , this embodiment also provides a memory testing method, which includes the following steps:

[0119] S1. Provide a memory test device 10a as described in this embodiment and a three-dimensional stacked memory chip 1 to be tested. The memory test device 10a can be disposed outside the three-dimensional stacked memory chip 1 or embedded in a memory controller 10a within the three-dimensional stacked memory chip 1. The memory test device 10a has embedded therein a corresponding built-in self-test (BIST) process (e.g., a test process including adjustable timing parameter ranges such as tRP, tRCD, and tRAS), a first configuration register 101, a second configuration register 102, and a third configuration register 103.

[0120] S2, determining the current functional parameters to be tested and its test direction;

[0121] S3, configuring a test gear of the current function parameter by writing a corresponding configuration value into the first configuration register 101, configuring a test mode corresponding to the current function parameter by writing a corresponding configuration value into the second configuration register 102, and configuring a test instruction of the current function parameter by writing a corresponding configuration value into the third configuration register 103, wherein at least one of a test direction and an operation type indicated by different test instructions is different;

[0122] S4, applying a corresponding test stimulus to the memory test device 10a through the test host 3, the memory test device 10a receives the test stimulus, and in the test gear configured by the first configuration register 101 and the test mode configured in the second configuration register 102, according to the test instruction configured in the third configuration register 103, activates the corresponding word line WL or bit line BL in the three-dimensional stacked memory chip 1 to execute the corresponding built-in self-test process, and tests the current functional parameters of the three-dimensional stacked memory chip 1, wherein test vector data can be written into the three-dimensional stacked memory chip 1, for example, writing all "0" (for example, data is 0x00) or all "1" (for example, data is 0xFF) to the entire storage array array of the corresponding memory unit unit, or writing "0" or "1" in a checkerboard manner (for example, data is 0xAA and 0x55 interlaced), etc.;

[0123] S5, reading the corresponding data in the three-dimensional stacked memory chip 1, and comparing the read data with the written data to see if they are consistent (i.e., comparing the read value with the expected value to see if they are consistent);

[0124] If they are consistent, the process returns to S3 to adjust the configuration value in the first configuration register 101, thereby reducing the test range (for example, by one level), and repeating the operations of S4 to S5 to re-execute the above-mentioned built-in self-test process at the reduced test range to re-test the current functional parameters of the three-dimensional stacked memory chip 1, until it is determined in S5 that the read data is inconsistent with the written data.

[0125] If they are inconsistent, execute S6 to perform Shmoo chart analysis on the current test results, such as Figure 6 As shown, to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter;

[0126] S7, determines whether the current functional parameter is the last functional parameter to be tested. If so, the test ends. If not, the process returns to S2 and repeats the operations of S3 to S7 to test the next functional parameter of the three-dimensional stacked memory chip 1. In step S3, the configuration value of at least one of the first configuration register 101, the second configuration register 102, and the third configuration register 103 is adaptively adjusted based on the result of S2 to meet the requirements of the next functional parameter test.

[0127] Therefore, through the above-mentioned testing method, various functional parameters required for testing can be completed and the final values of various functional parameters can be determined, thereby adjusting the three-dimensional stacked memory chip 1 to the optimal performance.

[0128] It should be understood that, among the various functional parameters that can be tested by the memory testing device 10a, some are suitable for testing in the word line direction, and some are suitable for testing in the bit line direction. The above-mentioned testing process can dynamically adjust the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103 according to the test requirements, so as to perform tests on the corresponding functional parameters in the word line WL direction or the bit line BL direction. That is, after configuring the first configuration register 101, the second configuration register 102, and the third configuration register 103, and preparing the test gear, test mode, and test instructions (the test instructions can indicate the test direction and operation type), etc., the memory testing device 10 can realize automatic testing of the corresponding functional parameters of the three-dimensional stacked memory chip.

[0129] These functional parameters may include at least one timing parameter, which may include at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, tFAW, etc.

[0130] For example, when testing timing parameters such as tRP, tRCD, and tRAS, in step S1, a BIST test process for these timing parameters is pre-embedded in the memory test device 10a, and in step S2, it is determined that the timing parameters such as tRP, tRCD, and tRAS are suitable for testing in the word line WL direction. In step S3, by configuring the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103, the test gear, test mode, and test direction are prepared. Then, in step S4, under the configured test mode and test direction, the three-dimensional stacked memory chip 1 is activated row by row and voltage is applied (i.e., test stimulus is applied) to write data into the corresponding storage cells of the three-dimensional stacked memory chip 1, and the read data is compared with the written data. If the data are consistent, the process returns to step S3, and by adjusting the configuration value of the first configuration register, the test gear of the timing parameter is adjusted down by one gear. The above operation is repeated until the written data is inconsistent with the read data. Then, in step S5, the test results are analyzed using a Shmoo diagram. In step S6, the tightest timing of the timing parameter is determined based on the analysis results.

[0131] The wordline test mode can be configured as either a basic or extended mode. The basic mode can be any suitable pattern, such as all 0s (0x00), all 1s (0xFF), or a checkerboard pattern (0xAA / 0x55). The extended mode can be an inter-row alternating mode (complementary data is written to adjacent rows), an adjustable wordline step mode, and a configurable jump mode (precharging row n ±1 / 2 / 4 / 8 when activating row n). During the test, any suitable operation can be performed, such as voltage control and adding row interference test enhancement instructions. For example, operations such as wordline voltage gradient scanning, negative overdrive, and dynamic VREF calibration can be performed, as described above.

[0132] For another example, timing parameters such as tRCD, tCOLOFF2WLOFF, and tRP are suitable for testing in the bit line BL direction. In step S1, a BIST test flow for these timing parameters is pre-embedded in the memory test device 10a. In step S2, it is determined that the timing parameters such as tRCD, tCOLOFF2WLOFF, and tRP are suitable for testing in the bit line BL direction. In step S3, by configuring the configuration values in the first configuration register 101, the second configuration register 102, and the third configuration register 103, the test gear, test mode, and test direction are prepared. Then, in step S4, under the configured test mode and test direction, the three-dimensional stacked memory chip 1 is activated row by row and voltage is applied (i.e., test stimulus is applied) to write data into the corresponding storage cells of the three-dimensional stacked memory chip 1, and the read data is compared with the written data. If the data are consistent, the process returns to step S3, and by adjusting the configuration value of the first configuration register, the test gear of the timing parameter is adjusted down by one gear. The above operation is repeated until the written data is inconsistent with the read data. Then, in step S5, the test results are analyzed using a Shmoo diagram. In step S6, the tightest timing of the timing parameter is determined based on the analysis results.

[0133] The test mode in the bit line direction can be configured as any suitable mode, such as an odd-even column alternating activation mode (writing 0x00 to even columns and 0xFF to odd columns) or a diagonal column interference test mode (when activating column m, reverse data is applied to columns m+1 / 2 / 4 / 8 by configuration).

[0134] During testing, the sense amplifier (SA) bias voltage (VBL) can be dynamically adjusted, for example, in normal mode: VBL = 0.5VDDQ; in stress test mode: VBL = 0.45VDDQ to 0.55VDDQ sweep. The sense amplifier enable timing jitter injection can also be performed, for example, by adding ±20ps timing perturbations within the tRCD window. Bitline slew rate testing can also be performed, for example, by applying high-speed data transitions (alternating between 0→1 and 1→0) and measuring the bitline BL voltage settling time using an on-chip time-to-voltage converter (TVC) at a sampling density of one measurement point every 10ps. Shmoo plots are then generated based on the measurement results. Shmoo plot analysis can then be used to determine the final values of the timing parameters being tested. After completing the testing of each timing parameter, the 3D stacked memory chip can be tuned for optimal performance.

[0135] For example, in one example, the Shmoo diagram established based on the measurement results is as follows: Figure 6As shown in the table, the Shmoo diagram generates a two-dimensional visualization chart showing the relationship between the two variables of bit line voltage VBL margin and tRCD. During testing, the memory test device 1 repeatedly tests the three-dimensional stacked memory chip 1 under the corresponding bit line voltage VBL margin, records the pass (PASS) / fail (FAIL) test results, and then determines the final value of the timing parameter tRCD of the current test.

[0136] In summary, the memory testing device, three-dimensional stacked memory chip, memory testing method, and testing system provided by the present invention embed a built-in self-test (BIST) test process and first to third configuration registers in the memory testing device. Therefore, only the prescribed test stimulus needs to be applied on the test host to automatically implement the testing of the corresponding functional parameters of the three-dimensional stacked memory chip. Moreover, the switching of functional parameters, test direction, and test mode only needs to be achieved by adjusting the configuration values in the first to third configuration registers. Thus, the test process of the functional parameters of the memory is optimized, greatly saving test time and test costs.

[0137] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A memory test device, embedded in a three-dimensional stacked memory chip or disposed outside the three-dimensional stacked memory chip, wherein the three-dimensional stacked memory chip comprises multiple layers of memory bare cores stacked together, characterized in that: The memory test device is embedded with: A first configuration register is used to configure a test gear of a current functional parameter to be tested; A second configuration register is used to configure a test mode corresponding to the current function parameter; a third configuration register, configured to configure a test instruction for the current function parameter, wherein different test instructions indicate different at least one of a test direction and an operation type; a built-in self-test module, having a built-in self-test process embedded therein, and configured to receive a corresponding test stimulus and, in the test gear configured in the first configuration register and the test mode configured in the second configuration register, activate a corresponding word line or bit line in the three-dimensional stacked memory chip according to a test instruction configured in the third configuration register, so as to execute the built-in self-test process and test the current functional parameters of the three-dimensional stacked memory chip; wherein the configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register is adjusted according to the test result of the built-in self-test module; And the built-in self-test process includes: Writing test vector data into the three-dimensional stacked memory chip; Reading corresponding data from the three-dimensional stacked memory chip and comparing the read data with the written data to see whether they are consistent; If they are consistent, the configuration value in the first configuration register is adjusted to reduce the test level, thereby causing the built-in self-test module to retest the current functional parameters of the 3D stacked memory chip under the reduced test level.

2. The memory testing device according to claim 1, wherein: If the read data is inconsistent with the written data, the built-in self-test module is further used to perform Shmoo chart analysis on the test result to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter.

3. The memory testing device according to claim 1 or 2, wherein: After the built-in self-test module completes the test of the current functional parameter, the configuration value of at least one of the first configuration register, the second configuration register and the third configuration register is adjusted so that the built-in self-test module performs a next functional parameter test on the three-dimensional stacked memory chip.

4. The memory testing device according to claim 1 or 2, wherein: When the test direction indicated by the test instruction in the third configuration register is the word line direction, after activating the corresponding word line and writing a predetermined number of test vector data, the address in the bit line direction automatically points to the next bit line; When the test direction indicated by the test instruction in the third configuration register is the bit line direction, after a predetermined number of test vector data are written, the address in the word line direction automatically points to the next word line.

5. The memory testing device according to claim 4, wherein: When the test direction is the word line direction, different configuration values in the second configuration register can realize a basic mode and an extended mode, the basic mode includes at least one of an all-0 mode, an all-1 mode, and a checkerboard mode, and the extended mode includes at least one of an inter-row alternating mode and a word line adjustable step mode; And / or, when the test direction is the bit line direction, different configuration values in the second configuration register can implement an odd and even column alternating activation test mode and a diagonal column interference test mode.

6. The memory testing device according to claim 4, wherein: The built-in self-test process performed in the word line direction further includes at least one of the following operations (1) to (4): (1) performing voltage gradient scanning on corresponding word lines in the three-dimensional stacked memory chip using corresponding voltage step sizes; (2) negatively overdriving corresponding word lines in the three-dimensional stacked memory chip to detect leakage by reverse biasing; (3) updating the reference voltage once each time a preset number of writes are completed in the three-dimensional stacked memory chip; (4) Adding a row interference test enhancement instruction to the current functional parameter test, wherein the row interference test enhancement instruction is used to implement coupling testing and / or refresh interval insertion of adjacent word lines in the three-dimensional stacked memory chip.

7. The memory testing device according to claim 4, wherein: The built-in self-test process performed in the bit line direction further includes at least one of the following operations (1) to (3): (1) dynamically adjusting a bias voltage of a readout amplifier for reading corresponding data in the three-dimensional stacked memory chip; (2) injecting enable timing jitter into a sense amplifier for reading corresponding data in the three-dimensional stacked memory chip; (3) Apply high-speed data transitions and measure the bit line voltage build-up time to implement bit line slew rate testing.

8. The memory testing device according to any one of claims 1 to 2 and 5 to 7, wherein: The current functional parameter includes at least one timing parameter, and the timing parameter includes at least one of tRAS, tRCD, tCOLOFF2WLOFF, tRP, tWR, tCL, tCAS, tWTR, tRC, tRFC, tCCD, tRTP, and tFAW.

9. The memory testing device according to any one of claims 1 to 2 and 5 to 7, wherein: The three-dimensional stacked memory chip also includes a memory controller, the memory testing device is embedded in the memory controller, the memory controller is arranged in a buffer bare core, and the multi-layer memory bare cores and the memory bare cores are hybrid bonded together through silicon vias; or, the memory testing device is arranged in a main control chip outside the three-dimensional stacked memory chip.

10. A three-dimensional stacked memory chip, characterized in that: The invention comprises a memory controller and multiple layers of memory bare cores stacked together, wherein the memory controller is embedded with the memory testing device according to any one of claims 1 to 9.

11. A memory testing system, characterized in that: include: A three-dimensional stacked memory chip, a test host, and a memory test device as described in any one of claims 1 to 9; wherein the three-dimensional stacked memory chip includes a memory controller and multiple layers of memory bare cores stacked together, the memory controller is embedded with the memory test device, or the memory test device is arranged in a test chip outside the three-dimensional stacked memory chip, the test host applies corresponding test stimulus to the memory test device so that the memory test device activates the corresponding word line or bit line in the three-dimensional stacked memory chip, and then performs corresponding functional parameter testing on the three-dimensional stacked memory chip.

12. A memory testing method, characterized in that: The following steps are involved: Provided are a memory testing device and a three-dimensional stacked memory chip to be tested according to any one of claims 1 to 9, wherein the memory testing device is disposed outside the three-dimensional stacked memory chip or embedded in a memory controller within the three-dimensional stacked memory chip, and wherein the memory testing device embeds a corresponding built-in self-test process, a first configuration register, a second configuration register, and a third configuration register; Determining a current functional parameter to be tested and its test direction, and configuring a test gear of the current functional parameter by writing a corresponding configuration value into the first configuration register, configuring a test mode corresponding to the current functional parameter by writing a corresponding configuration value into the second configuration register, and configuring a test instruction corresponding to the current functional parameter by writing a corresponding configuration value into the third configuration register, where different test instructions indicate different at least one of a test direction and an operation type; Applying a corresponding test stimulus to the memory test device through a test host, the memory test device receiving the test stimulus and, in the test gear configured in the first configuration register and the test mode configured in the second configuration register, activating a corresponding word line or bit line in the three-dimensional stacked memory chip according to the test instruction configured in the third configuration register, so as to execute the built-in self-test process and test the current functional parameters of the three-dimensional stacked memory chip; The built-in self-test process includes: Writing test vector data into the three-dimensional stacked memory chip; Reading corresponding data from the three-dimensional stacked memory chip and comparing the read data with the written data to see whether they are consistent; If they are consistent, the configuration value in the first configuration register is adjusted to reduce the test gear, and then the built-in self-test process is re-executed under the reduced test gear until the read data is inconsistent with the written data.

13. The memory testing method according to claim 12, wherein: The built-in self-test process also includes: If the read data is inconsistent with the written data, a Shmoo chart analysis is performed on the current test result to determine the final value of the current functional parameter, thereby completing the test of the current functional parameter; After completing the test of the current functional parameter, determine whether the current functional parameter is the last functional parameter to be tested. If so, end the test; if not, adjust the configuration value of at least one of the first configuration register, the second configuration register, and the third configuration register to perform the next current functional parameter test on the three-dimensional stacked memory chip.

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