Memory chip, probe card and electronic equipment
By integrating serialization/deserializer in the memory chip, serialization of data is realized and test ports is reduced, the problem of insufficient probe card channel resources is solved, the efficiency and flexibility of wafer testing is improved, and the cost is reduced.
Patent Information
- Application Number
- CN202510324013.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, the number of signal channels of the probe card is limited, resulting in high wafer testing costs and low efficiency, making it difficult to take into account both the testing costs and the testing efficiency.
Integrate serialization/deserializer in memory chips to process test data through serialization and provide a small number of test ports to reduce the number of channels on the probe card while supporting multiple test modes to improve testing flexibility.
It reduces the channel resource usage of probe cards, shortens testing time, improves testing efficiency and flexibility, and reduces testing costs.
Smart Images
Figure CN120260660A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular, to a storage chip, a probe card, and an electronic device. Background Art
[0002] For Dynamic Random Access Memory (DRAM), Design for Testability (DFT) and Chip Probing (CP) are design strategies adopted to improve the testability of DRAM chips during the manufacturing and testing phases. The core objective is to ensure that the chips can be efficiently and accurately tested after production, thereby improving the yield and reliability. DFT is to add specific circuits and structures during the chip design phase to improve the testability of the chip. CP is a process of electrically testing each chip on the wafer through a Probe Card after the wafer manufacturing is completed. Currently, since there are multiple chips on the wafer, but the number of signal channels in the Probe Card is limited, multiple probe cards or batch testing are required to test the wafer. The former has a high cost, and the latter will take a long time, resulting in the inability to balance the test cost and test efficiency, and the test flexibility is relatively low. Summary of the Invention
[0003] The present disclosure provides a storage chip, a probe card, and an electronic device, which can reduce the resource occupation of the signal channels on the probe card, reduce the test cost, and improve the test efficiency.
[0004] The technical solution of the present disclosure is implemented as follows:
[0005] In a first aspect, an embodiment of the present disclosure provides a storage chip, which includes a main storage module, a serializer / deserializer connected to the main storage module, and a plurality of first test ports connected to the serializer / deserializer;
[0006] The plurality of first test ports are configured to receive test input data and transmit the test input data to the serializer / deserializer;
[0007] The serializer / deserializer is configured to perform deserialization processing on the test input data to generate data to be written, and send the data to be written to the data input / output end of the main storage module; wherein, the number of the first test ports is less than the number of the data input / output ends of the main storage module;
[0008] The main storage module is configured to store the data to be written.
[0009] In some embodiments, the main storage module is further configured to generate data to be read out, and send the data to be read out to the serializer / deserializer via the data input / output terminal of the main storage module; the serializer / deserializer is further configured to select the data to be read out, perform serial processing on the selected data to be read out, generate test output data, and send the test output data to a plurality of the first test ports for output.
[0010] In some embodiments, the storage chip further includes data ports, the number of the data ports is the same as the number of the data input / output terminals of the main storage module, and a plurality of the data ports are respectively and correspondingly connected to the plurality of data input / output terminals of the main storage module; the plurality of data ports are configured to receive data to be written, and transmit the data to be written to the plurality of data input / output terminals of the main storage module; the plurality of data ports are further configured to receive the data to be read out from the main storage module and output the data to be read out.
[0011] In some embodiments, the serializer / deserializer includes:
[0012] a selection unit configured to receive a test mode signal, select and transmit the data to be read out based on the test mode signal, and generate first intermediate data; a latch unit configured to receive an internally generated clock signal, latch the first intermediate data based on the clock signal, and generate second intermediate data; a conversion unit configured to perform serial processing on the second intermediate data to generate the test output data.
[0013] In some embodiments, the conversion unit is further configured to perform deserialization processing on the test input data and output third intermediate data; the latch unit is further configured to receive an externally input clock signal, latch the third intermediate data based on the clock signal, and output fourth intermediate data; the selection unit is further configured to receive and select and output the fourth intermediate data based on the test mode signal to generate the data to be written.
[0014] In some embodiments, the serializer / deserializer further includes a transmitter; the transmitter is configured to perform drive enhancement and transmission on the test input data or the test output data.
[0015] In some embodiments, the serializer / deserializer performs serial processing based on the Serdes protocol; the test output data includes some or all of the information carried by the data to be read out and the information carried by the internally generated clock signal; the latch unit is specifically configured to receive the internally generated clock signal, latch the clock signal, and latch the first intermediate data based on the clock signal to generate the second intermediate data.
[0016] In some embodiments, the serializer / deserializer performs deserialization processing based on the Serdes protocol; the test input data includes the information corresponding to the data to be written and the information of the externally input clock signal.
[0017] In some embodiments, the storage chip further includes a second test port; the second test port is configured to output the internally generated clock signal; or input the externally transmitted clock signal.
[0018] In some embodiments, the serializer / deserializer further includes a third test port: the third test port is configured to output the internally generated data strobe signal; or input the externally transmitted data strobe signal; wherein, the data strobe signal is at least used to indicate the start of the test input data or the test output data.
[0019] In some embodiments, the number of input / output terminals of the main storage module is M, where M is a positive integer greater than 1; the selection unit includes M transmission gates; the first end of the i-th transmission gate is connected to the i-th data input / output terminal of the main storage module, the second end of the i-th transmission gate is connected to the latch unit, the enable end of the i-th transmission gate receives the i-th enable signal, and the inverted enable end of the i-th transmission gate receives the i-th enable signal; the i-th transmission gate is configured to electrically connect the i-th data input / output terminal of the main storage module to the latch unit when the i-th enable signal is in the enabled state; and electrically isolate the i-th data input / output terminal of the main storage module from the latch unit when the i-th enable signal is in the non-enabled state; wherein, the test mode signal is used to indicate the state of each enable signal.
[0020] In some embodiments, M = 8, and the number of the first test ports is 1; if the test mode signal is the first value, the first enable signal and the eighth enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the second value, the second enable signal and the seventh enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the third value, the third enable signal and the sixth enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the fourth value, the fourth enable signal and the fifth enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the fifth value, the first enable signal, the third enable signal, the fifth enable signal, and the seventh enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the sixth value, the second enable signal, the fourth enable signal, the sixth enable signal, and the eighth enable signal are in the enabled state, and the rest of the enable signals are in the disabled state; if the test mode signal is the seventh value, all the enable signals are in the enabled state.
[0021] In some embodiments, the main storage module includes: a storage array including a plurality of storage units; an input / output unit configured to store the data to be written into the corresponding storage unit; and an input / output unit further configured to obtain the data to be read out from the corresponding storage unit.
[0022] In a second aspect, an embodiment of the present disclosure provides a probe card for testing a wafer including a plurality of storage chips, where the storage chips are as described in the first aspect; each of the storage chips occupies only N signal channels on the probe card, and N refers to the total number of the first test port, the second test port, and the third test port in the storage chip.
[0023] In a third aspect, an embodiment of the present disclosure provides an electronic device including the storage chip as described in the first aspect.
[0024] The embodiments of the present disclosure provide a storage chip, a probe card, and an electronic device. By means of DFT, a serializer / deserializer is integrated in the storage chip, and data serialization processing in the test mode is implemented through the serializer / deserializer. In addition, a smaller number of test ports are provided for data transmission during the test process, thereby saving the channel number on the probe card. At the same time, the data can be screened in the serializer / deserializer, and different test modes are provided, so that the storage units meeting the requirements can be selectively and separately read and written for testing, improving the flexibility and pertinence of the test. Description of the Drawings
[0025] Figure 1 Structural schematic diagram of a storage chip provided by an embodiment of the present disclosure Figure 1 ;
[0026] Figure 2 A schematic diagram of a partial structure of a storage chip provided by an embodiment of the present disclosure;
[0027] Figure 3 A schematic diagram of the structure of a storage chip provided by an embodiment of the present disclosure Figure 2 ;
[0028] Figure 4 A schematic diagram of a partial structure of a storage chip provided by an embodiment of the present disclosure Figure 3 ;
[0029] Figure 5 A schematic diagram of signal timing provided by an embodiment of the present disclosure Figure 4 ;
[0030] Figure 6 A schematic diagram of the structure of a serializer / deserializer provided by an embodiment of the present disclosure;
[0031] Figure 7A A schematic diagram of the working process of a serializer / deserializer provided by an embodiment of the present disclosure Figure 1 ;
[0032] Figure 7B A schematic diagram of the working process of a serializer / deserializer provided by an embodiment of the present disclosure Figure 2 ;
[0033] Figure 8 A schematic diagram of signal timing provided by an embodiment of the present disclosure;
[0034] Figure 9 A schematic diagram of the structure of a selection unit provided by an embodiment of the present disclosure;
[0035] Figure 10 A schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners
[0036] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the application. Additionally, it should be noted that for ease of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" related to the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
[0037] Dynamic Random Access Memory (DRAM);
[0038] Synchronous Dynamic Random Access Memory (SDRAM);
[0039] Double Data Rate SDRAM (DDR);
[0040] Low Power DDR (LPDDR);
[0041] Metal-Oxide-Semiconductor MOS.
[0042] Next, each embodiment of the present disclosure will be described in detail in conjunction with the drawings.
[0043] In an embodiment of the present disclosure, refer to Figure 1 , which shows a schematic structural diagram of a storage chip 10 provided by the embodiment of the present disclosure. As Figure 1 shown, the storage chip 10 includes a main storage module 11, a serializer / deserializer 12 connected to the main storage module 11, and a plurality of first test ports PAD_TX1 connected to the serializer / deserializer 12.
[0044] A plurality of first test ports PAD_TX1 are configured to receive test input data and transmit the test input data to serializer / deserializer 12;
[0045] The serializer / deserializer 12 is configured to deserialze the test input data to generate data to be written DQ[0-7], and send the data to be written DQ[0-7] to the data input / output terminal 111 of the main storage module 11;
[0046] The main storage module 11 is configured to store the data to be written DQ[0-7].
[0047] It should be noted that the storage chip 10 of the present disclosure embodiment can be applied to but not limited to electronic devices, specifically, it can be DRAM, SDRAM, DDR, LPDDR, etc.
[0048] During the CP test phase, the storage unit is frequently read and written, and the data is input and output through the data port DQ_PAD by means of the data signal DQ. Please refer to Figure 2 , the number of data ports DQ_PAD is the same as the number of channels of the data signal DQ (which can also be called the parallel number, number of bits), and the probe card must also provide the same number of signal channels. For example, if the number of channels of the data signal DQ is 8 bits, then there are 8 data ports DQ_PAD, and each storage chip needs to occupy 8 signal channels in the probe card.
[0049] It should be understood that certain mature circuit design functions can be integrated into the DFT area of the chip through DFT to increase the error correction function of the chip. In the embodiment of the present disclosure, through the DFT method, the serializer / deserializer 12 is integrated in the storage chip 10, and the data serialization process in the test mode is realized through the serializer / deserializer 12, and a smaller number of first test ports are additionally provided for data transmission during the test process, thereby saving the number of channels on the probe card.
[0050] Specifically, as Figure 1 shown, the number of data input / output terminals 111 is equal to the number of channels of the data to be written DQ[0-7], so as to perform transmission in a one-to-one correspondence, and the number of first test ports is equal to the number of channels of the test input data, so as to perform transmission in a one-to-one correspondence.
[0051] Figure 1Eight data input / output terminals 111 are shown, that is, the number of channels for data to be written is 8, specifically represented as DQ[0-7]. However, this is only an example, and the number of data input / output terminals 111 of the main storage module 11 in storage chips 10 of different specifications can be adjusted. In addition, the data input / output terminals 111 refer to the ports of the main storage module 11 for outputting / inputting data DATA. In addition to this, the main storage module 11 may also have ports for transmitting other types of information. For example, the main storage module 11 at least also needs to have ports for transmitting command address signals.
[0052] In addition, although the number of channels for data to be written is 8, some channels of the data to be written can be invalid signals. For example, only DQ[0] and DQ[7] transmit valid data, and other channels do not transmit valid data, so as to achieve compressed (Compress) transmission of the data signal DQ and improve test flexibility.
[0053] Figure 1 One first test port PAD_TX1 is shown, but this also does not constitute a relevant limitation. However, the number of the first test ports PAD_TX1 is less than the number of data input / output terminals 111 of the main storage module 11. In this way, when performing CP testing, taking Figure 1 as an example, one storage chip 10 only occupies 1 signal channel in the probe card (Probe Card), thus saving the channel resources in the probe card and reducing the test cost; at the same time, one probe card can also test a larger number of chips on the wafer, and the test time is also significantly shortened, and the test efficiency is improved.
[0054] In some embodiments, please refer to Figure 1 , the main storage module 11 is further configured to generate the data DQ[0-7] to be read out, and send the data DQ[0-7] to be read out to the serializer / deserializer 12 via the data input / output terminals 111 of the main storage module 11;
[0055] The serializer / deserializer 12 is further configured to select the data DQ[0-7] to be read out, and perform serial processing on the selected data DQ[0-7] to be read out to generate test output data, and send the test output data to a plurality of first test ports PAD_TX1 for output.
[0056] It should be noted that the data to be written and the data to be read out are only used to distinguish the data signals in the writing process / readout process. Essentially, they are transmitted on the same signal line, only the transmission directions are different. Therefore, in Figure 1 they are both referred to as DQ[0-7].
[0057] In this way, whether in the reading or writing process, the number of ports required for data transmission is reduced through serial processing / deserialization processing, saving the channel resources in the probe card, reducing the test cost and improving the test efficiency.
[0058] It should be understood that in CP testing, certain features in DFT are often used, and it is carried out by compressing (Compress) or normalizing the data signal DQ data, so as to improve the test flexibility. In the embodiments of the present disclosure, the serializer / deserializer 12 can select the data to be read out, and the selected data to be read out includes part or all of the information of the original data to be read out. For example, if the data to be read out refers to DQ[0~7], the selected data to be read out is DQ[0], DQ[2], DQ[4] and DQ[6]. Thus, the test output signal contains the specified information in the data to be read out, and the test can be selectively carried out, improving the flexibility and pertinence of the test.
[0059] In the above example, as Figure 1 shown, the data to be read out / written DQ[0-7] has 8 bits, and the number of the first test ports PAD_TX 1 is 1. At this time, DQ[0-7] is serialized into one-bit data.
[0060] In another example, the data to be read out / written DQ[0-7] has 8 bits, and the number of the first test ports PAD_TX 1 is 2. At this time, DQ[0-3] is serialized into one-bit data for output, and DQ[4-7] is serialized into another one-bit data for output.
[0061] In yet another example, the data to be read out / written DQ[0-15] has 16 bits, and the number of the first test ports PAD_TX1 is 4. At this time, DQ[0-3] is serialized into the first one-bit data for output, DQ[4-7] is serialized into the second one-bit data for output, DQ[8-11] is serialized into the third one-bit data for output, and DQ[12-15] is serialized into the fourth one-bit data for output.
[0062] In some embodiments, please refer to Figure 3 , the storage chip 10 further includes a plurality of data ports DQ_PAD[0-7], and the number of the data ports DQ_PAD[0-7] is the same as the number of the data input / output terminals 111 of the main storage module 11. The plurality of data ports DQ_PAD[0-7] are connected to the plurality of data input / output terminals 111 of the main storage module 11 in one-to-one correspondence.
[0063] The plurality of data ports DQ_PAD[0-7] are configured to receive the data DQ[0-7] to be written and transmit the data DQ[0-7] to be written to the plurality of data input / output terminals 111 of the main storage module 11;
[0064] Multiple data ports DQ_PAD[0-7], which are also configured to receive data to be read out DQ[0-7] from the main storage module 11 and output the data to be read out DQ[0-7].
[0065] Here, the number of data ports DQ_PAD[0-7] is the same as the number of channels of the data to be written / data to be read out DQ[0-7], so as to transmit the data to be written / data to be read out DQ[0-7] in a one-to-one correspondence.
[0066] That is to say, as Figure 3 shown, in different modes, the storage chip 10 transmits data through different ports. Specifically, in the first mode (such as the working mode), the storage chip 10 transmits the data to be written / data to be read out DQ[0-7] through the data ports DQ_PAD[0-7], the data port DQ_PAD[0] transmits DQ[0], the data port DQ_PAD[1] transmits DQ[1]... the data port DQ_PAD[7] transmits DQ[7]. In the second mode (such as the test mode), the storage chip 10 transmits the data to be written / data to be read out DQ[0-7] through the first test port PAD_TX1 in cooperation with the serializer / deserializer 12.
[0067] In some embodiments, as Figure 3 shown, the main storage module 11 includes:
[0068] A storage array 112, including a plurality of storage cells Cell;
[0069] An input / output unit 113, configured to store the data to be written DQ[0-7] into the corresponding storage cells;
[0070] The input / output unit 113 is also configured to obtain the data to be read out DQ[0-7] from the corresponding storage cells.
[0071] Here, the structural type of the storage cell is not limited, such as 1T1C, 2T1C structures, etc.
[0072] In a specific embodiment, as Figure 3 shown, the input / output unit 113 specifically includes a data interface unit 201 and a receiver 202. The data interface unit 201 includes a plurality of data interfaces, and the data interfaces are respectively coupled to the storage array 112 and the receiver 202, and the receiver 202 is coupled to a plurality of input / output terminals 111.
[0073] In this way, taking Figure 3For example, in the first mode (e.g., the working mode), for a write operation, the data ports DQ_PAD[0-7] receive 8-bit data to be written DQ[0-7]. The receiver 202 transmits the data to be written DQ[0-7] to the storage array 112 via the data interface unit 201 for storage in the corresponding storage cell. In the second mode (e.g., the test mode), for a write operation, the first test port PAD_TX1 receives 1-bit test write data. The serializer / deserializer 12 converts the 1-bit test write data into 8-bit data to be written DQ[0-7]. The receiver 202 transmits the data to be written DQ[0-7] to the storage array 112 via the data interface unit 201, and the storage array stores it in the corresponding storage cell according to the corresponding command address signal (Command and Address, CA).
[0074] As Figure 3 shown, the input / output unit 113 further includes a read queue unit 203 (Read FIFO&MUX) and a driver unit 204. Here, the read queue unit 203 includes a first-in, first-out read queue (Read First-In, First-Out, ReadFIFO) and a multiplexer (MUX). The driver unit 204 can also be referred to as an output driver stage (ODS). The read queue unit 203 is respectively coupled to the storage array 112 and the driver unit 204, and the driver unit 204 is coupled to a plurality of input / output terminals 111.
[0075] In this way, taking Figure 3 as an example, in the first mode (e.g., the working mode), for a read operation, the storage array 112 reads data from the corresponding storage cell according to the corresponding command address signal. The read data enters the read queue unit 203 and is output in sequence to generate the data to be read DQ[0-7], which is transmitted to 8 data ports (DQ_PAD[0-7]) via the driver unit 204 for output. In the second mode (e.g., the test mode), for a read operation, the storage array 112 reads data from the corresponding storage cell according to the corresponding command address signal. The read data enters the read queue unit 203 and is output in sequence as the data to be read DQ[0-7]. The data to be read DQ[0-7] is transmitted to the serializer / deserializer 12 via the driver unit 204. The serializer / deserializer 12 selects and serially processes the data to be read DQ[0-7] to generate 1-bit test output data, which is then output from the first test port PAD_TX1.
[0076] In some embodiments, the serializer / deserializer 12 performs serial processing or deserialization based on the Serdes protocol.
[0077] It should be noted that the Serdes (Serializer / Deserializer) protocol is a key technology for converting parallel data into serial data (or converting serial data into parallel data) for transmission, and is widely used in the field of high-speed data transmission. Its core advantages lie in reducing wiring conflicts, enhancing anti-interference ability, reducing power consumption and packaging costs, and can improve data transmission rate and bandwidth. In the embodiments of the present disclosure, by utilizing the characteristics of the Serdes communication protocol, a serializer / deserializer 12 is integrated inside the storage chip 10 through DFT to select the data DQ[0-7] to be read out output by the storage array 112, and perform parallel-to-serial conversion, improving the flexibility of testing in the CP test stage and at the same time reducing the resource occupancy of the probe card.
[0078] It should be noted that the Serdes protocol can be divided into several types: parallel clock Serdes, embedded clock bit Serdes, and 8b10b Serdes.
[0079] In a specific embodiment, taking the embedded clock bit Serdes as an example, please refer to Figure 8 , the test output data D_OUT includes some or all of the information carried by the data to be read out and the information carried by the internally generated clock signal (C0, C1). Specifically, Figure 8 shows three test modes. In the test mode Tmode3, the test output data D_OUT includes clock information (C0, C1) and data information (DQ[0-7]); in the test mode Tmode2_1, the test output data D_OUT includes clock information (C0, C1) and data information (DQ[0], DQ[2], DQ[4], DQ[6]); in the test mode Tmode0_1, the test output data D_OUT includes clock information (C0, C1) and data information (DQ[0] and DQ[7]).
[0080] Correspondingly, the test input data includes the information corresponding to the data to be written and the information of the clock signal input from the outside, and can be understood with reference to Figure 8 .
[0081] In this way, by serializing data information and clock information onto a single line to form a single-channel serial information, two clock bits, one low (C0) and one high (C1), are embedded in the data stream and placed once every one cycle, generating a periodic rising edge in the serial data stream to define the start and end points of each word. The advantage of this architecture is that the width of the data payload does not need to be restricted to multiples of bytes and can be set as agreed, such as 10 bits, 16 bits, 18 bits, etc. During deserialization, the rising edge of the clock signal can be searched for to synchronize the serial data. The data bits may change randomly over time, while the clock rising edge always remains unchanged. Therefore, the serializer / deserializer 12 can recover the data based on this.
[0082] Correspondingly, the storage chip 10 can specifically adopt an architecture as shown in Figure 3 , that is, by only setting one first test port PAD_TX1, the functions of data input and output during the test can be achieved. Correspondingly, only one signal channel in the probe card is required for one chip, saving the number of signal channels in the probe card, reducing the test cost. When testing a large number of chips on a wafer, the number of chips tested at one time increases, thereby shortening the test time. In addition, different test modes can be flexibly selected to perform read and write tests on different memory cells, improving the flexibility and pertinence of the test and enhancing the test efficiency.
[0083] In some other embodiments, please refer to Figure 4 , the storage chip 10 further includes a second test port PAD_TX2; the second test port PAD_TX2 outputs the internally generated clock signal CLK; or inputs the externally transmitted clock signal CLK.
[0084] Specifically, in the second mode (such as the test mode), for a read operation, the second test port PAD_TX2 outputs the clock signal CLK, so that the test machine can directly sample and deserialize the signal of the first test port PAD_TX1 according to the clock signal CLK to obtain the required data information; for a write operation, the second test port PAD_TX2 receives the clock signal CLK sent by the test machine, and the storage chip 10 samples and deserialize the signal of the first test port PAD_TX1 according to the clock signal CLK to obtain the required data information.
[0085] In this way, as shown in Figure 8As shown, clock information is output separately through the second test port PAD_TX2, and clock information and data information are serially output through the first test port PAD_TX1. The clock information is more stable, while reducing the complexity of clock recovery and improving system reliability; it is easy to be compatible with the test machine, and can also simplify the system design and reduce power consumption; the interface type of the entire system changes little compared with the original system, and the compatibility with the test machine is better.
[0086] In still other embodiments, please refer to Figure 5 , the serializer / deserializer 12 further includes a third test port PAD_TX3; the third test port PAD_TX3 is configured to output the internally generated data strobe signal DQS; or, input the externally transmitted data strobe signal DQS; wherein, the data strobe signal DQS is at least used to indicate the start of test input data or test output data.
[0087] It should be noted that the serializer / deserializer 12 can also be implemented by other serial-parallel conversion architectures except the Serdes protocol. For example, data information is output / input through the first test port PAD_TX1 (that is, the test input data and test output data no longer include clock information, but only include data information), the second test port PAD_TX2 outputs / inputs the clock signal, and the third test port PAD_TX3 outputs / inputs the data strobe signal DQS respectively. Thereby, the complexity of decoding is reduced.
[0088] Taking Figure 4 the storage chip 10 shown as an example, a feasible structure of the serializer / deserializer 12 is provided.
[0089] In some embodiments, as Figure 6 shown, the serializer / deserializer 12 includes a selection unit 121, a latch unit 122, and a conversion unit 123.
[0090] As Figure 7A shown, for the read operation, the working process of the serializer / deserializer 12 is as follows:
[0091] The selection unit 121 is connected to a plurality of input / output terminals 111, and is configured to receive the test mode signal TM enable, select and transmit the data to be read out DQ[0-7] based on the test mode signal TM enable, and generate first intermediate data;
[0092] The latch unit 122 is connected to the selection unit 121, and is configured to receive the clock signal clk, latch the first intermediate data based on the clock signal clk, and generate second intermediate data;
[0093] The conversion unit 123, connected to the latch unit 122, is configured to perform serial processing on the second intermediate data to generate test output data.
[0094] It should be noted that the clock signal clk received by the latch unit 122 and the clock signal CLK at the second test port PAD_TX2 are essentially the same signal with the same waveform (although there may be a delay between them), but they are in different circuit positions. Therefore, the same noun is used to refer to them for the read operation. Specifically, for the read operation, the internally generated clock signal clk is transmitted to the latch unit 122 to implement the latching function and is output via the second test port PAD_TX2.
[0095] It should be noted that the latch unit 122 can be implemented by a latch, and / or a D flip-flop (Dff), etc., and the conversion unit 123 can be implemented by a multiplexer (Mux), etc.
[0096] It should be noted that the first intermediate data carries all or part of the information of the aforementioned data to be read DQ[0-7]. Exemplarily, please refer to Table 1, which provides multiple test modes, and the test mode signal TM enable is used to indicate the selected test mode. In test mode TMode0_1, the first intermediate data includes DQ[0] and DQ[7]; in test mode TMode0_2, the first intermediate data includes DQ[1] and DQ[6]... In test mode TMode3, the first intermediate data includes DQ[0] and DQ[7].
[0097] Table 1
[0098] Test mode Enable signal in the enabled state First intermediate data TMode0_1 TM0, TM7 D[0], D[7] TMode0_2 TM1, TM6 D[1], D[6] TMode0_3 TM2, TM5 D[2], D[5] TMode0_4 TM3, TM4 D[3], D[4] TMode2_1 TM0, TM2, TM4, TM6 D[0], D[2], D[4], D[6] TMode2_2 TM1, TM3, TM5, TM7 D[1], D[3], D[5], D[7] TMode3 TM0~TM7 D[0]~D[7]
[0099] In some embodiments, for Figure 4 the architecture shown, the test output data also needs to include clock information. Therefore, the latch unit 122 is specifically configured to receive the internally generated clock signal, latch the clock signal, and latch the first intermediate data based on the clock signal to generate the second intermediate data.
[0100] Please refer to Figure 8 , in different test modes, the corresponding data DQ is latched by the latch unit 122, and the waiting time t_l complies with the corresponding timing sequence; at the same time, the internally generated clock signal clk is also latched, and finally the test readout data D_OUT is generated according to the embedded clock Serdes protocol; and the internally generated clock signal clk will also be transmitted through the second test port, and the clock signal at the second test port is denoted as CLK.
[0101] In this way, the storage chip 10 provided by the embodiments of the present disclosure also supports flexible test mode selection. In different test modes, reading tests can be performed on different storage units, improving test efficiency and saving test resources.
[0102] In some embodiments, as Figure 7B shown, the conversion unit 123 is further configured to perform deserialization processing on the test input data D_IN and output third intermediate data;
[0103] The latch unit 122 is further configured to receive an externally input clock signal and latch the third intermediate data based on the clock signal to output fourth intermediate data;
[0104] The selection unit 121 is further configured to selectively output the fourth intermediate data to generate data to be written.
[0105] As described above, the clock signal clk received by the latch unit 122 and the clock signal CLK at the second test port PAD_TX2 are essentially the same signal. Briefly speaking, for the write operation, the externally generated clock signal CLK is input via the second test port PAD_TX2 and continues to be transmitted to the latch unit 122 to implement the latching function.
[0106] It should be understood that the third intermediate data and the second intermediate data are respectively used to indicate the data in the read process and the write process, and are transmitted via the same physical signal, only the transmission directions are different; the first intermediate data and the fourth intermediate data are respectively used to indicate the data in the read process and the write process, and are transmitted via the same physical signal, only the transmission directions are different.
[0107] In this way, the storage chip provided by the embodiments of the present disclosure also supports flexible test mode selection. In different test modes, write tests are performed on different storage units, improving test efficiency and saving test resources.
[0108] In some embodiments, as Figure 6 shown, the serializer / deserializer 12 further includes a transmitter 124; the transmitter 124 is configured to perform drive enhancement and transmission on the test input data D_IN or the test output data D_OUT.
[0109] In some embodiments, the number of input / output terminals 111 of the main storage module 11 is M, where M is a positive integer greater than 1. The selection unit 121 includes M transmission gates; the first end of the i-th transmission gate is connected to the i-th data input / output terminal 111 of the main storage module 11, the second end of the i-th transmission gate is connected to the latch unit 122, the enable end of the i-th transmission gate receives the i-th enable signal TM(i - 1), and the inverted enable end of the i-th transmission gate receives the i-th enable signal / TM(i - 1).
[0110] Here, each transmission gate includes a pair of complementary MOS transistors (PMOS and NMOS in parallel), which are controlled by a pair of complementary signals TM(i - 1), / TM(i - 1). Specifically, the i-th transmission gate is configured to electrically connect the i-th data input / output terminal 111 of the main storage module 11 to the latch unit 122 when the i-th enable signal TM(i - 1) is in the enabled state; and to electrically isolate the i-th data input / output terminal 111 of the main storage module 11 from the latch unit 122 when the i-th enable signal TM(i - 1) is in the non-enabled state; wherein, the test mode signal TM enable is used to indicate the state of each enable signal.
[0111] Here, the enabled state is one of logic 0 and logic 1, and the non-enabled state is the other of logic 0 and logic 1.
[0112] Taking M = 8 as an example, please refer to Figure 9 , the selection unit 121 includes 8 transmission gates, and the enable signals TM0 to TM7 respectively control the 8 transmission gates one by one.
[0113] As shown in Table 1, if the test mode signal TM enable is the first value (i.e., the test mode is TMode0_1), then the first enable signal TM0 and the eighth enable signal TM7 are in the enabled state, and the remaining enable signals are in the non-enabled state;
[0114] If the test mode signal TM enable is the second value (i.e., the test mode is TMode0_2), then the second enable signal TM1 and the seventh enable signal TM6 are in the enabled state, and the remaining enable signals are in the non-enabled state;
[0115] If the test mode signal TM enable is the third value (i.e., the test mode is TMode0_3), then the third enable signal TM2 and the sixth enable signal TM5 are in the enabled state, and the remaining enable signals are in the non-enabled state;
[0116] If the test mode signal TM enable is the fourth value (i.e., the test mode is TMode0_4), then the fourth enable signal TM3 and the fifth enable signal TM4 are in the enabled state, and the remaining enable signals are in the non-enabled state;
[0117] If the test mode signal TM enable is the fifth value (i.e., the test mode is TMode2_1), then the first enable signal TM0, the third enable signal TM2, the fifth enable signal TM4, and the seventh enable signal TM6 are in the enabled state, and the remaining enable signals are in the non-enabled state;
[0118] If the test mode signal TM enable is the sixth value (i.e., the test mode is TMode2_2), then the second enable signal TM1, the fourth enable signal TM3, the sixth enable signal TM5, and the eighth enable signal TM7 are in the enabled state, and the remaining enable signals are in the disabled state;
[0119] If the test mode signal TM enable is the seventh value (i.e., the test mode is TMode3), then all enable signals are in the enabled state.
[0120] Here, the test mode signal TM enable can be a three-bit signal. For example, the first value is 000, the second value is 001... and it can be defined by yourself.
[0121] In a specific embodiment, taking the test mode TM0_1 as an example, the test input data actually carries the information of DQ[0] to DQ[7]. The effective channels of the third intermediate data are 8 bits (i.e., DQ[0] to DQ[7]). At this time, since only the enable signals TM0 and TM7 are in the enabled state, DQ[0] and DQ[7] in the third intermediate data are transmitted to the corresponding input / output terminals 111, and DQ[1] to DQ[6] are masked.
[0122] In a specific embodiment, taking the test mode TM0_1 as an example, the test input data only carries the information of DQ[0] and [7]. At this time, the effective channels of the third intermediate data are only DQ[0] and DQ[7], and DQ[1] to DQ[6] are filled with 0 or no signal is transmitted.
[0123] In particular, the hardware structure of the storage chip 10 is provided above. For this hardware structure, a supporting test software needs to be provided for use. Briefly speaking, the above-mentioned serial / deserializer 12 (integrated with the Serdes protocol) is integrated in the DFT area of the storage chip 10, and corresponding test ports are designed; secondly, according to the structure of the storage chip 10, a corresponding probe card is provided, and each storage chip 10 only occupies the channel resources in the probe card with the number of test ports; finally, corresponding ENGINE instructions and PATTEN instructions are developed. The function of the ENGINE instruction is to arbitrarily select and switch between the Compress or Normal mode to select the output data of DQ, and configure the corresponding enable signal. Through the PATTEN instruction, specific instructions can be operated on the chip, so as to realize the specific operation of each function of the chip and obtain the feedback of the chip. In the Normal mode during the test process, data is transmitted through the normal data ports DQ_PAD[0-7], and the multiplexing of the data ports DQ_PAD[0-7] is also realized; in the Compress mode during the test process, data is transmitted through the serial / deserializer 12 and the first / second / third test ports, reducing the channel resources of the probe card. In different CP test stages, the above different modes can be adopted, and the corresponding probe cards are also different.
[0124] In summary, the embodiments of the present disclosure relate to the fields of chip DFT and CP testing, and particularly to modules in the field of chip circuit design in microelectronics. In the entire design, production, and manufacturing of chips, the testing of wafers in the CP stage, verifying the functions on the wafers and the testing costs are very important factors. At the same time, there are many DFT circuits on the chips on the wafers to support the corresponding functions of the wafers in the CP stage. Therefore, adding reasonable DFT circuits to meet the various requirements of CP stage testing can reduce the testing costs and increase flexibility.
[0125] Therefore, in order to fully verify the design functions and testing costs of the chips on the wafers, the Serdes protocol with extended DFT integration function is utilized in the storage chips. When verifying the functions, the serial-to-parallel characteristics of the Serdes protocol are used to reduce the number of signal channels in the design of the probe card; at the same time, making full use of the characteristics of the Serdes protocol, when the data in the storage array is transmitted through DQ, transmission gates are used to select the DQ path to increase the flexibility of testing, and arbitrary combination processing of data in the compression or normal mode can be realized. In this way, since the Serdes protocol with extended function is integrated in the die on the wafer, the cost of the probe card can be reduced, thereby improving the scalability of the probe card design.
[0126] In another embodiment of the present disclosure, a probe card is provided, which is used to test a wafer including a plurality of memory chips 10; each memory chip 10 only occupies N signal channels on the probe card, where N refers to the total number of the first test port, the second test port, and the third test port in the memory chip.
[0127] For example, for Figure 3 the memory chip 10 shown, one memory chip 10 only occupies 1 signal channel on the probe card; for another example, for Figure 4 the memory chip 10 shown, one memory chip 10 only occupies 2 signal channels on the probe card; for still another example, for Figure 5 the memory chip 10 shown, one memory chip 10 only occupies 3 signal channels on the probe card.
[0128] In this way, since the memory chip 10 integrates a serializer / deserializer 12 to implement parallel-to-serial conversion based on the Serdes protocol, the signal channels connecting the solder pads on the chip under test to the probe card are reduced, and the cost of the probe card is reduced; in addition, multiple test modes are provided to realize normal output or compressed output of the DQ data of the chip, thereby improving the flexibility of testing.
[0129] In another embodiment of the present disclosure, refer to Figure 10 , which shows a schematic structural diagram of an electronic device 50 provided by an embodiment of the present disclosure. As Figure 10 shown, the electronic device 50 at least includes the aforementioned memory chip 10.
[0130] In the compression read / write (Compress mode) during the CP test phase, due to resource issues of the signal channels of the probe card, it is necessary to compress the DQ data to reduce the use of resources on the machine or the probe card. In the CP engineering verification phase, in order to verify the chip design function, it is necessary to test all DQs, and a probe card supporting full DQ input / output will be designed. In this way, more machine and probe card resources will be used for testing, and it is necessary to test a wafer in multiple times, which will cause the test time to increase exponentially.
[0131] In the embodiments of the present disclosure, a serializer / deserializer 12 is integrated in the storage chip 10, and serial output of data is achieved through the Serdes protocol, which can reduce the number of signal channel resources in the design of the probe card and lower the cost of the probe card. By integrating the Serdes protocol with extended functions, that is, using transmission gates to implement different data signal selections and supporting different test modes, the scalability of the probe card design is improved. Finally, by using the Serdes protocol with extended functions, the Compress or Normal modes can be arbitrarily combined to arbitrarily select the output data of DQ, so as to meet various test requirements, reduce the test cost and increase flexibility.
[0132] The above are only the preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element. The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims
1. A storage chip, characterized in that, The storage chip includes a main storage module, a serializer / deserializer connected to the main storage module, and a plurality of first test ports connected to the serializer / deserializer; The plurality of first test ports are configured to receive test input data and transmit the test input data to the serializer / deserializer; The serializer / deserializer is configured to perform deserialization processing on the test input data to generate data to be written, and send the data to be written to the data input / output terminal of the main storage module; wherein, the number of the first test ports is less than the number of the data input / output terminals of the main storage module; The main storage module is configured to store the data to be written.
2. The storage chip according to claim 1, wherein The main storage module is further configured to generate data to be read out, and send the data to be read out to the serializer / deserializer via the data input / output terminal of the main storage module; The serializer / deserializer is further configured to select the data to be read out, perform serialization processing on the selected data to be read out to generate test output data, and send the test output data to the plurality of first test ports for output.
3. The storage chip according to claim 2, wherein The storage chip further includes data ports, the number of the data ports is the same as the number of the data input / output terminals of the main storage module, and the plurality of data ports are respectively connected to the plurality of data input / output terminals of the main storage module in one-to-one correspondence; The plurality of data ports are configured to receive data to be written and transmit the data to be written to the plurality of data input / output terminals of the main storage module; The plurality of data ports are further configured to receive the data to be read out from the main storage module and output the data to be read out.
4. The storage chip according to claim 2, wherein, The serializer / deserializer includes: A selection unit configured to receive a test mode signal and selectively transmit the data to be read out based on the test mode signal to generate first intermediate data; A latch unit configured to receive an internally generated clock signal and latch the first intermediate data based on the clock signal to generate second intermediate data; A conversion unit configured to perform serialization processing on the second intermediate data to generate the test output data.
5. The storage chip according to claim 4, wherein The conversion unit is further configured to perform deserialization processing on the test input data and output third intermediate data; The latch unit is further configured to receive an externally input clock signal and latch the third intermediate data based on the clock signal to output fourth intermediate data; The selection unit is further configured to receive and selectively output the fourth intermediate data based on the test mode signal to generate the data to be written.
6. The storage chip according to claim 4, wherein The serializer / deserializer further includes a transmitter; The transmitter is configured to drive and enhance and transmit the test input data or the test output data.
7. The storage chip according to claim 5, characterized in that The serializer / deserializer performs serialization processing based on the Serdes protocol; The test output data includes part or all of the information carried by the data to be read out and the information carried by the internally generated clock signal; The latch unit is specifically configured to receive the internally generated clock signal, latch the clock signal, and latch the first intermediate data based on the clock signal to generate the second intermediate data.
8. The storage chip according to claim 5, wherein The serializer / deserializer performs deserialization processing based on the Serdes protocol; The test input data includes the information corresponding to the data to be written and the information of the clock signal input from the outside.
9. The storage chip according to claim 5, wherein The storage chip further includes a second test port; The second test port is configured to output the internally generated clock signal; or input the clock signal sent from the outside.
10. The storage chip according to claim 2, characterized in that, The serializer / deserializer further includes a third test port; The third test port is configured to output the internally generated data strobe signal; or input the data strobe signal sent from the outside; Wherein, the data strobe signal is at least used to indicate the start of the test input data or the test output data.
11. The storage chip according to claim 4, wherein The number of input / output terminals of the main storage module is M, and M is a positive integer greater than 1; The selection unit includes M transmission gates; The first end of the i-th transmission gate is connected to the i-th data input / output terminal of the main storage module, the second end of the i-th transmission gate is connected to the latch unit, the enable end of the i-th transmission gate receives the i-th enable signal, and the inverted enable end of the i-th transmission gate receives the i-th enable signal; The i-th transmission gate is configured to electrically connect the i-th data input / output terminal of the main storage module to the latch unit when the i-th enable signal is in the enabled state; and electrically isolate the i-th data input / output terminal of the main storage module from the latch unit when the i-th enable signal is in the non-enabled state; Wherein, the test mode signal is used to indicate the state of each enable signal.
12. The storage chip according to claim 11, wherein, M = 8, and the number of the first test ports is 1; If the test mode signal is the first value, the first enable signal and the eighth enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the second value, the second enable signal and the seventh enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the third value, the third enable signal and the sixth enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the fourth value, the fourth enable signal and the fifth enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the fifth value, the first enable signal, the third enable signal, the fifth enable signal, and the seventh enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the sixth value, the second enable signal, the fourth enable signal, the sixth enable signal, and the eighth enable signal are in the enabled state, and the remaining enable signals are in the non-enabled state; If the test mode signal is the seventh value, all enable signals are in the enabled state.
13. The storage chip according to claim 2, wherein The main storage module includes: A storage array including a plurality of storage units; An input / output unit configured to store the data to be written into the corresponding storage unit; The input / output unit is further configured to obtain the data to be read out from the corresponding storage unit.
14. A probe card, characterized in that, The probe card is used to test a wafer including a plurality of memory chips, and the memory chips are as described in claims 1-13; Each of the memory chips occupies only N signal channels on the probe card, where N refers to the total number of the first test port, the second test port, and the third test port in the memory chip.
15. An electronic device, characterized in that, The electronic device includes a memory chip as described in any one of claims 1-13.