Power device terminal area passivation method and power device

Abstract

The invention provides a passivation method for a terminal area of a power device and the power device, and finally forms a composite passivation layer structure consisting of a silicon nitride thin film, an amorphous silicon carbide thin film and a silicon nitride thin film by improving a traditional passivation layer only formed by a single silicon nitride thin film, the silicon nitride films on the two sides can provide good insulation performance and chemical stability, atoms in the amorphous silicon carbide in the middle are arranged disorderly, stress can be better absorbed and dispersed when the amorphous silicon carbide is subjected to external stress, stress transfer between the silicon nitride films on the two sides is effectively reduced, and the performance of the silicon nitride film is improved. Therefore, the problem that the passivation layer is prone to cracking and moisture permeation due to mechanical stress accumulation caused by difference of thermal expansion coefficients is solved, in addition, the reliability and the stability of the power device in a high-temperature and high-humidity environment are improved, and the service life of the power device is prolonged.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power device fabrication, and relates to a passivation method for the terminal region of a power device and a power device. Background Art

[0002] A power device refers to a power electronic device that encapsulates a power semiconductor chip (such as an IGBT, MOSFET, etc.) in an insulating housing according to a certain circuit structure. Its main function is to achieve power electronic power conversion, and it is the core component of energy conversion, and is widely used in fields such as rail transit, smart grid, industrial energy conservation, new energy vehicles, and new energy equipment. However, the working environments faced by the above application fields are usually harsh environments with high temperature, high humidity, and chemical corrosive medium erosion. Under such harsh conditions, the reliability and stability of power devices in high-temperature and high-humidity environments face severe challenges. In particular, the problem of passivation layer failure in the terminal region at the edge of the chip has become a key bottleneck restricting the life and stability of power devices.

[0003] In traditional processes, generally, a passivation layer is added to the surface of the terminal region at the edge of the chip to prevent water vapor in the environment from invading and reduce the impact on the reliability and life of the power device. Since silicon nitride thin film has the characteristics of stable chemical properties, not easy to corrode, dense structure, especially good hydrophobicity, and extremely low pinhole density, and water vapor cannot penetrate, traditional passivation layers are mostly prepared using silicon nitride materials. However, it has been found that the thermal expansion coefficients between the silicon nitride material and the metal on the surface of the power device do not match. Once the power device works in a high-temperature and high-humidity environment for a long time, the mechanical stress generated due to the difference in thermal expansion coefficients will gradually accumulate, eventually causing the passivation layer formed by the silicon nitride thin film to generate microcracks or even delamination. Once the crack penetrates the passivation layer, moisture in the environment will invade the chip interior along the crack path, thus seriously affecting the reliability and life of the power device.

[0004] Therefore, there is an urgent need to find a passivation method for the terminal region of a power device to solve the problem that the traditional single silicon nitride thin film passivation layer works in a high-temperature and high-humidity environment for a long time, and the stress accumulation caused by the difference in thermal expansion coefficients results in the generation of cracks in the passivation layer, thereby affecting the reliability, stability, and service life of the power device. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a passivation method for the terminal region of a power device and a power device, which are used to solve the problem that in the prior art, the traditional single silicon nitride thin film passivation layer works in a high-temperature and high-humidity environment for a long time, and the stress accumulation caused by the difference in thermal expansion coefficients results in the generation of cracks in the passivation layer, thereby affecting the reliability, stability, and service life of the power device.

[0006] To achieve the above and other related objectives, the present invention provides a passivation method for the terminal region of a power device, comprising the following steps:

[0007] Provide a power device, and sequentially form a bottom passivation layer, an intermediate passivation layer, and a top passivation layer on the surface of the terminal region of the power device by using a plasma-enhanced chemical vapor deposition process to form a composite passivation layer;

[0008] Anneal the composite passivation layer and perform local lithography to form lead holes, and the bottom of the lead holes exposes the pads of the power device.

[0009] Optionally, the material for forming the bottom passivation layer includes silicon nitride, and the thickness of the bottom passivation layer is 100-500 nm.

[0010] Optionally, the material for forming the top passivation layer includes silicon nitride, and the thickness of the top passivation layer is 100-500 nm.

[0011] Optionally, the process parameters for forming the bottom passivation layer and the top passivation layer are that the plasma atmosphere ratio is SiH4:NH3 = 1:5-1:8, and the deposition temperature is 300-400 °C.

[0012] Optionally, the thickness of the top passivation layer is greater than or equal to the thickness of the bottom passivation layer.

[0013] Optionally, the intermediate passivation layer includes a first amorphous silicon carbide layer, wherein the thickness of the first amorphous silicon carbide layer is 50-200 nm.

[0014] Optionally, before forming the intermediate passivation layer, it further includes the steps of plasma cleaning and passivation treatment of the bottom passivation layer, and the process parameters for forming the intermediate passivation layer are that the plasma atmosphere ratio is CH4:SiH4 = 2:1-4:1, and the deposition temperature is 200-400 °C.

[0015] Optionally, the intermediate passivation layer includes a second amorphous silicon carbide layer and a second silicon nitride layer arranged in a stacked manner, wherein the total thickness of the second amorphous silicon carbide layer and the second silicon nitride layer is 50-200 nm.

[0016] Optionally, the process temperature for annealing the composite passivation layer is 300-400 °C, and the time is 30-60 minutes.

[0017] The present invention also provides a power device, which is obtained after being passivated by using the above-mentioned passivation method for the terminal region of the power device.

[0018] As described above, the passivation method for the terminal region of the power device of the present invention and the power device form a composite passivation layer structure composed of a silicon nitride thin film, an amorphous silicon carbide thin film, and a silicon nitride thin film by improving the passivation layer formed by only a single silicon nitride thin film in the conventional art. Among them, the silicon nitride thin film can provide good insulation performance and chemical stability, while the atoms in the amorphous silicon carbide are disorderly arranged, and can better absorb and disperse stress when subjected to external stress, effectively reducing the stress transfer between the bottom passivation layer and the top passivation layer, thus fundamentally solving the problem that the passivation layer formed by only a single silicon nitride thin film in the conventional art is prone to cracks and causes moisture penetration. In addition, the reliability and stability of the power device in high-temperature and high-humidity environments are improved, and the service life of the power device is extended. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It shows a schematic cross-sectional structure diagram of forming a bottom passivation layer on the terminal region of the power device in an embodiment of the present invention.

[0020] Figure 2 It shows a schematic cross-sectional structure diagram of forming an intermediate passivation layer in an embodiment of the present invention.

[0021] Figure 3 It shows a schematic cross-sectional structure diagram of forming a top passivation layer in an embodiment of the present invention.

[0022] Figure 4 It shows a schematic cross-sectional structure diagram of forming a via hole in an embodiment of the present invention.

[0023] DESCRIPTION OF THE REFERENCE NUMERALS IN THE DRAWINGS

[0024] 10. Terminal region; 11. Interlayer dielectric layer; 12. Metal layer; 13. Bottom passivation layer; 14. Intermediate passivation layer; 15. Top passivation layer; 16. Via hole. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0027] For ease of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the drawings.

[0028] In the context of the present application, the structure in which the first feature described is "above" the second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0029] Please refer to Figures 1 to 4 Note that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the layout type of the components may also be more complex.

[0030] Next, with reference to the accompanying drawings, a passivation method for the terminal region of a power device provided by an embodiment of the present invention will be described.

[0031] In this embodiment, a composite passivation layer is formed by sequentially forming a bottom passivation layer 13, an intermediate passivation layer 14, and a top passivation layer 15 on the surface of the terminal region 10 of the semiconductor power device. The bottom passivation layer 13 and the top passivation layer 15 in the composite passivation layer provide good insulation performance and chemical stability for the power device, blocking the penetration of moisture. The intermediate passivation layer 14 can reduce lattice stress and prevent cracks from occurring in the composite passivation layer, thereby improving the reliability and stability of the semiconductor power device in harsh environments such as high temperature and high humidity.

[0032] Furthermore, in this embodiment, the deposition and formation of the composite passivation layer on the surface of the power device terminal region 10 includes the following implementation steps.

[0033] 1. Grow a bottom passivation layer 13 on the surface of the power device terminal region 10.

[0034] Figure 1Schematic cross-sectional structure diagram of forming a bottom passivation layer 13 on the terminal region 10 of a power device in an embodiment of the present invention. In this embodiment, the material of the bottom passivation layer 13 is silicon nitride, and before depositing silicon nitride, it also includes the step of cleaning the terminal region 10 of the power device. Specifically: putting the power device chip into an ultrasonic cleaning machine for cleaning, the liquid in the ultrasonic cleaning machine is an acetone solution with a volume fraction of 60% - 75%, and the ultrasonic cleaning time is 5 min - 15 min, so as to ensure that the stains on the surface of the power device chip can be effectively removed, then rinsing with deionized water, controlling the water temperature at 25°C - 45°C, and then performing multi-angle blowing and drying treatment on the power device chip. On the surface of the terminal region 10 of the power device chip, silicon nitride is grown by plasma-enhanced chemical vapor deposition process to form the bottom passivation layer 13 as shown in Figure 1 shown. Among them, the process parameters of the plasma-enhanced chemical vapor deposition process are to control the plasma atmosphere ratio at SiH4:NH3 = 1:5 - 1:8, the deposition temperature is 300 - 400°C, the thickness of the bottom passivation layer 13 is 100 - 500 nm. For example: the thickness of the bottom passivation layer 13 is 100 nm, 300 nm or 500 nm, and the bottom passivation layer 13 covers the interlayer dielectric layer 11 and the metal layer 12 of the power device.

[0035] 2. Grow an intermediate passivation layer 14 on the bottom passivation layer 13.

[0036] Figure 2 Schematic cross-sectional structure diagram of growing an intermediate passivation layer 14 on the bottom passivation layer 13 in an embodiment of the present invention. In this embodiment, the intermediate passivation layer 14 only includes a first amorphous silicon carbide layer. Specifically, before forming the intermediate passivation layer 14 on the bottom passivation layer 13, it is also necessary to clean the bottom passivation layer 13 with Ar / O2 plasma and passivate the bottom passivation layer 13 with H2 to improve the interfacial adhesion to the bottom passivation layer 13, so that when the intermediate passivation layer 14 is formed subsequently, the bottom passivation layer 13 and the intermediate passivation layer 14 have better bonding strength.

[0037] Specifically, the process of forming the intermediate passivation layer 14 is a plasma-enhanced chemical vapor deposition process. Among them, the process parameters of the plasma-enhanced chemical vapor deposition process are to control the plasma atmosphere ratio at CH4:SiH4 = 2:1 to 4:1, the deposition temperature is 200 to 400 °C, and the thickness of the intermediate passivation layer 14 is 50 to 200 nm. For example, the thickness of the intermediate passivation layer 14 is 50 nm, 100 nm, 150 nm, or 200 nm. The material for forming the intermediate passivation layer 14 is amorphous silicon carbide. The amorphous silicon carbide material has a disordered atomic arrangement, and the relative displacement between atoms is more free. When subjected to external stress, it can better absorb and disperse stress, effectively reducing the stress transfer between the underlying passivation layer 13 and the top passivation layer 15 materials, and can form a relatively tight interface with silicon nitride.

[0038] In another embodiment, the intermediate passivation layer 14 can also be a stacked arrangement of a second amorphous silicon carbide layer and a second silicon nitride layer, where the total thickness of the second amorphous silicon carbide layer and the second silicon nitride layer is 50 to 200 nm. For example, the intermediate passivation layer 14 can be a 7-layer structure with a thickness of 140 nm. Its specific composition is the second amorphous silicon carbide layer / the second silicon nitride layer / the second amorphous silicon carbide layer / the second silicon nitride layer / the second amorphous silicon carbide layer / the second silicon nitride layer / the second amorphous silicon carbide layer, and the thickness of each layer is 20 nm. Compared with the intermediate passivation layer 14 formed only by amorphous silicon carbide, the stacked structure formed by amorphous silicon carbide and silicon nitride has higher thermal matching.

[0039] 3. Form a top passivation layer on the intermediate passivation layer 14.

[0040] Figure 3 This is a schematic cross-sectional structure diagram of forming a top passivation layer on the intermediate passivation layer 14 in an embodiment of the present invention. In this embodiment, the material of the top passivation layer is silicon nitride. Specifically, before forming the top passivation layer on the intermediate passivation layer 14, it is also necessary to clean the intermediate passivation layer 14 using Ar / O2 plasma and passivate the underlying passivation layer 13 using H2 to improve the interfacial adhesion of the intermediate passivation layer 14, so that the subsequently formed top passivation layer and the intermediate passivation layer 14 have better bonding strength.

[0041] Specifically, silicon nitride is grown on the surface of the intermediate passivation layer 14 using a plasma-enhanced chemical vapor deposition process to form the top passivation layer as shown in Figure 3 wherein, the process parameters of the plasma-enhanced chemical vapor deposition process are to control the plasma atmosphere ratio at SiH4:NH3 = 1:5 to 1:8, the deposition temperature is 300 to 400 °C, and the thickness of the top passivation layer is 100 to 500 nm. For example, the thickness of the top passivation layer is 100 nm, 300 nm, or 500 nm.

[0042] As an example, the thickness of the top passivation layer 15 is greater than or equal to the thickness of the bottom passivation layer 13.

[0043] Specifically, the thickness of the top passivation layer 15 can be equal to the thickness of the bottom passivation layer 13, or the thickness of the top passivation layer 15 can be greater than the thickness of the bottom passivation layer 13, without special limitation here. However, it should be noted that when the thickness of the top passivation layer 15 is greater than the thickness of the bottom passivation layer 13, an asymmetric composite passivation layer structure is formed, which can better optimize the mechanical stress generated due to the difference in thermal expansion coefficients.

[0044] 4. Anneal the composite passivation layer.

[0045] Specifically, anneal the deposited composite passivation layer structure, where the annealing temperature is 300 - 400 °C and the time is 30 - 60 minutes. The annealing treatment helps to improve the density and adhesion of the composite passivation layer structure, promotes the internal structure reorganization of the intermediate passivation layer 14, and further reduces the accumulation of mechanical stress generated due to the difference in thermal expansion coefficients.

[0046] 5. Perform local lithography on the composite passivation layer to form a via hole 16, and the bottom of the via hole 16 exposes the pad of the power device.

[0047] Specifically, deposit a photoresist on the top passivation layer to form a photoresist masking layer, expose and develop the photoresist masking layer. As Figure 4 shown, perform local lithography on the patterned photoresist masking layer to obtain a via hole 16, and the bottom of the via hole 16 exposes the pad of the power device (i.e., the metal layer 12 of the power device). Then, remove the photoresist masking layer through an ashing process.

[0048] The present invention also provides a semiconductor power device. The terminal region 10 of the semiconductor power device is passivated by the above passivation method, which can significantly improve the sealing performance of the semiconductor power device and fundamentally solve the problem that the passivation layer formed by only a single silicon nitride film in the prior art is prone to cracks and causes moisture penetration.

[0049] In summary, the passivation method for the terminal region of the power device and the power device of the present invention improve the traditional passivation layer formed only by a single silicon nitride thin film, and finally form a composite passivation layer structure composed of a silicon nitride thin film, an amorphous silicon carbide thin film, and a silicon nitride thin film. Among them, the silicon nitride thin films on both sides can provide good insulation performance and chemical stability, while the atoms in the middle amorphous silicon carbide are disorderly arranged, and can better absorb and disperse stress when subjected to external stress, effectively reducing the stress transfer between the silicon nitride thin films on both sides, thus solving the problem that the passivation layer is prone to cracks and moisture penetration caused by the accumulation of mechanical stress due to the difference in thermal expansion coefficients. In addition, the reliability and stability of the power device in high-temperature and high-humidity environments are improved, and the service life of the power device is extended. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0050] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A passivation method for the terminal region of a power device, characterized in that The passivation method includes the following steps: Provide a power device, and sequentially form a bottom passivation layer, an intermediate passivation layer, and a top passivation layer on the surface of the terminal region of the power device by using a plasma-enhanced chemical vapor deposition process to form a composite passivation layer. The intermediate passivation layer includes a second amorphous silicon carbide layer and a second silicon nitride layer arranged in a stacked manner. Among them, the total thickness of the second amorphous silicon carbide layer and the second silicon nitride layer is 50-200 nm; Anneal the composite passivation layer and perform local lithography to form lead holes, and the bottom of the lead holes exposes the pads of the power device.

2. The passivation method for the terminal region of the power device according to claim 1, characterized in that: The material for forming the bottom passivation layer includes silicon nitride, and the thickness of the bottom passivation layer is 100-500 nm.

3. The passivation method for the terminal region of the power device according to claim 1, characterized in that, The material for forming the top passivation layer includes silicon nitride, and the thickness of the top passivation layer is 100-500 nm.

4. The passivation method for the terminal region of a power device according to any one of claims 2 to 3, characterized in that: The process parameters for forming the bottom passivation layer and the top passivation layer are that the plasma atmosphere ratio is SiH4:NH3 = 1:5-1:8, and the deposition temperature is 300-400 °C.

5. The passivation method for the terminal region of a power device according to claim 4, characterized in that: The thickness of the top passivation layer is greater than or equal to the thickness of the bottom passivation layer.

6. The passivation method for the terminal region of a power device according to claim 4, characterized in that, Before forming the intermediate passivation layer, it also includes the steps of plasma cleaning and passivation treatment of the bottom passivation layer, and the process parameters for forming the intermediate passivation layer are that the plasma atmosphere ratio is CH4:SiH4 = 2:1-4:1, and the deposition temperature is 200-400 °C.

7. The passivation method for the terminal region of a power device according to claim 1, characterized in that: The process temperature for annealing the composite passivation layer is 300-400 °C, and the time is 30-60 minutes.

8. A power device, characterized in that, The power device is obtained after passivation by using the passivation method for the terminal region of the power device according to any one of claims 1-7.

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