Chip packaging method and chip

Abstract

The present application discloses a chip packaging method and chip, which belongs to the field of chip packaging technology. The chip packaging method includes: performing wafer testing on a first target wafer to determine the power consumption test value of each chip to be packaged on the first target wafer; dividing each chip to be packaged into multiple chip groups according to the size of the power consumption test value, and calculating the allowable packaging thermal resistance of each chip group according to the power consumption range of each chip group; determining the packaging optimization structure corresponding to the packaging thermal resistance of each chip group; and packaging each chip to be packaged on the first target wafer using the corresponding packaging optimization structure. Group the chips to be packaged on the wafer according to the power consumption of each chip to be packaged, and select the corresponding packaging optimization scheme for packaging according to the packaging thermal resistance of each chip group, so that high-power consumption chips use high-heat dissipation packaging and low-power consumption chips use low-heat dissipation packaging. Under the premise of meeting the chip performance, the problems of thermal redundancy and insufficient heat dissipation are solved, and low-cost and high-performance packaging is achieved.

Description

Technical Field

[0001] The present application belongs to the field of chip packaging technology, and in particular relates to a chip packaging method and a chip. Background Art

[0002] As chip integration increases, the heat generated by the chips also continues to increase. If this heat cannot be dissipated in a timely manner, the chip temperature will rise. Excessive temperatures can lead to a sharp increase in the failure rate and malfunction rate of semiconductor devices. Therefore, before chip processing, package thermal design is required. This involves rationally designing the chip's packaging structure, materials, and heat dissipation methods to ensure that the heat generated during chip operation can be effectively dissipated, preventing overheating from causing a decrease in chip performance and reliability.

[0003] Process deviations are inevitable during chip manufacturing. Chips from different wafer batches, and chips located at different locations on the same wafer, have inconsistent process parameters such as effective channel length and critical dimensions. This results in differences in leakage current across chips. These differences in leakage current further lead to differences in static power consumption and total power consumption between chips. Therefore, during chip development, even if the same package thermal design is used for each chip, differences in static power consumption between chips can lead to excessive heat dissipation in the chip package, resulting in high packaging costs and the risk of thermal redundancy. Alternatively, insufficient heat dissipation can lead to performance degradation and thermal runaway. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip packaging method and chip that utilizes different packaging thermal optimization structures for chips in different power consumption ranges. While maintaining chip performance, this method solves the problems of thermal redundancy and insufficient heat dissipation, achieving low-cost, high-performance packaging.

[0005] In a first aspect, the present application provides a chip packaging method, comprising:

[0006] Performing a wafer test on the first target wafer to determine a power consumption test value of each chip to be packaged on the first target wafer;

[0007] Dividing the chips to be packaged into multiple chip groups according to the power consumption test values, and calculating the corresponding allowable packaging thermal resistance of each chip group according to its power consumption range;

[0008] Determine a package optimization structure corresponding to the package thermal resistance for each of the chipsets;

[0009] Each chip to be packaged on the first target wafer is packaged using a corresponding packaging optimization structure.

[0010] According to one embodiment of the present application, each chip to be packaged is divided into multiple chip groups according to the size of the power consumption test value, and the allowable package thermal resistance of each chip group pair is calculated according to the power consumption range of each chip group pair, including:

[0011] Divide the total power consumption interval defined by each power consumption test value into a target number of sub-intervals, and the chips to be packaged corresponding to the sub-intervals are a chipset;

[0012] Calculate the allowable package thermal resistance based on the power consumption range corresponding to each sub-interval.

[0013] According to one embodiment of the present application, the package thermal resistance corresponding to each sub-interval is calculated based on the maximum power consumption test value of the sub-interval, and the package thermal resistance is determined according to the following formula:

[0014] R=(TJ-Ta) / P

[0015] Where R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value within the range.

[0016] According to one embodiment of the present application, the chip packaging method further includes:

[0017] Generating a wafer power consumption distribution map according to the distribution of chipsets on a plurality of first target wafers, wherein the wafer power consumption distribution map determines the distribution area of ​​each chip to be packaged based on the power consumption test value of the chip to be packaged;

[0018] According to the wafer power consumption distribution map, each chip to be packaged on the second target wafer is packaged using a packaging optimization structure corresponding to the distribution area, and the second target wafer has the same structure as the first target wafer.

[0019] According to one embodiment of the present application, the wafer power consumption distribution map includes a power consumption distribution area, in which chips to be packaged of the same chipset are distributed;

[0020] The method includes packaging each chip to be packaged on the second target wafer using a packaging optimization structure corresponding to the distribution area according to the wafer power consumption distribution map, including:

[0021] Determining a package thermal resistance corresponding to a power consumption distribution area on a second target wafer according to the wafer power consumption distribution map;

[0022] Each chip to be packaged in each power distribution area is packaged according to the package optimization structure corresponding to the package thermal resistance.

[0023] According to one embodiment of the present application, the wafer power consumption distribution map further includes a critical test area, which is located between the multiple power consumption distribution areas and has multiple chips to be packaged of the chipset distributed therein;

[0024] The method further includes packaging each to-be-packaged chip on the second target wafer using a packaging optimization structure corresponding to the distribution area according to the wafer power consumption distribution map.

[0025] Testing the power consumption of each chip to be packaged in the corresponding critical test area on the second target wafer;

[0026] The chips to be packaged in the critical test area are packaged using the corresponding packaging optimization structure according to the power consumption test value.

[0027] According to one embodiment of the present application, the power consumption distribution areas and critical test areas are alternately arranged in sequence from the inside to the outside on the wafer, the outer area surrounds the inner area, and the critical test area is distributed with the chips to be packaged of the chip group corresponding to the two adjacent power consumption distribution areas. The power consumption test value of the chip to be packaged located in the outer power consumption distribution area is greater than the power consumption test value of the chip to be packaged located in the inner power consumption distribution area.

[0028] According to one embodiment of the present application, the packaging optimization structure involves at least one of material optimization, substrate optimization, packaging form optimization, and external heat dissipation optimization.

[0029] According to one embodiment of the present application, material optimization involves the thermal conductivity coefficient of the packaging material, and involves at least one of the following: carrier material optimization, plastic packaging material optimization, patch adhesive material optimization, bottom filling adhesive material optimization, and interface thermal conductive adhesive material optimization.

[0030] According to one embodiment of the present application, substrate optimization involves at least one of whether a window is opened in the green oil of the packaging substrate, the window area, the window shape, and the copper coverage rate of the substrate.

[0031] According to one embodiment of the present application, the package form optimization involves at least one of a ball grid array package, a land grid array package, and a flip chip ball grid array package.

[0032] According to one embodiment of the present application, external heat dissipation optimization involves at least one of radiator optimization, fan cooling optimization, and liquid cooling optimization.

[0033] In a second aspect, the present application provides a chip, which is manufactured according to the aforementioned chip packaging method.

[0034] According to the chip packaging method and chip of the present application, by grouping the chips to be packaged on the wafer according to their power consumption and selecting the corresponding packaging optimization scheme for the packaging thermal resistance of each chip group, high-power consumption chips use high-heat dissipation packaging and low-power consumption chips use low-heat dissipation packaging. While meeting the chip performance, the problems of thermal redundancy and insufficient heat dissipation are solved, thereby achieving low-cost and high-performance packaging.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 This is one of the flow charts of the chip packaging method provided in the embodiment of the present application;

[0038] Figure 2 This is the second flow chart of the chip packaging method provided in the embodiment of the present application;

[0039] Figure 3 This is the third flow chart of the chip packaging method provided in the embodiment of the present application;

[0040] Figure 4 This is one of the structural diagrams of the chip packaging structure provided in the embodiment of the present application;

[0041] Figure 5 This is the second structural diagram of the chip packaging structure provided in the embodiment of the present application;

[0042] Figure 6 This is the third structural diagram of the chip packaging structure provided in the embodiment of the present application;

[0043] Figure 7 This is the fourth flow chart of the chip packaging structure provided in the embodiment of the present application;

[0044] Figure 8 This is a schematic diagram of the power consumption distribution diagram after wafer testing provided in an embodiment of the present application.

[0045] Reference numerals:

[0046] Chip to be packaged 1, plastic packaging material 2, interconnect bonding wires 3, packaging substrate 4, patch adhesive 5, solder balls 6, pads 7, and chip heat sink 8. DETAILED DESCRIPTION

[0047] Embodiments of the present application are described in detail below, with examples of the embodiments illustrated in the accompanying drawings. In the accompanying drawings, the sizes of layers, regions, and components, as well as their relative sizes, may be exaggerated for clarity. Throughout, the same or similar reference numerals represent the same or similar components or components having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and intended only to explain the present application, and are not to be construed as limiting the present application.

[0048] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0049] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0050] In related technologies, chip packaging needs to be thermally designed based on factors such as the chip's power consumption, working environment, and heat dissipation requirements. Usually, a certain chip power consumption value is first obtained through power consumption simulation, and then thermal simulation is performed in the simulation software based on this power consumption value, and finally the packaging structure and material that meet the chip's heat dissipation requirements are determined. Therefore, if the chip's packaging structure, material parameters, and packaging processing parameters are all consistent, then its heat dissipation performance is basically the same, that is, the package thermal resistance of all chips is basically the same. For chips with high heat dissipation requirements, the thermal design of their packaging is very difficult, especially in high temperature environments. The thermal resistance of the package is required to be small enough to meet the normal heat dissipation of the chip at high temperatures, thereby ensuring that the chip's maximum temperature, that is, the junction temperature, does not exceed the specified temperature. Therefore, accurate evaluation of chip power consumption plays an important role in package thermal design.

[0051] Chip power consumption includes dynamic power consumption and static power consumption. Dynamic power consumption refers to the power consumption generated during circuit operation and can be further divided into switching power consumption and short-circuit power consumption. Switching power consumption is the power consumption caused by charging and discharging the load capacitance when the circuit switches. Short-circuit power consumption refers to the short-circuit power consumption between the NMOS and PMOS transistors during the circuit state switching process. A chip's dynamic power consumption is primarily determined by the circuit's capacitive load, chip voltage, operating frequency, and signal toggle rate. Therefore, for a group of chips in the same operating state, their dynamic power consumption is generally consistent.

[0052] Static power consumption is the power consumption generated when the circuit state does not flip, that is, when the chip circuit is in an inactive or static state. It mainly includes subthreshold leakage current, gate leakage current, drain current caused by the gate, and power consumption caused by junction reverse bias current. Static power consumption is related to the chip's leakage current, which is affected by the chip's manufacturing process. Due to the inevitable process deviations in the chip manufacturing process, the effective channel length, key dimensions and other process parameters of chips on different wafer batches and chips at different locations on the same wafer are inconsistent, resulting in differences in leakage current between different chips. The difference in leakage current further leads to differences in static power consumption and total power consumption between chips.

[0053] At the same time, as the temperature rises, the leakage current tends to increase exponentially. When the chip runs at high temperature, the proportion of static power consumption in the total power consumption of the chip increases sharply.

[0054] In summary, during conventional chip development, even if chips with the same dynamic power consumption share the same package thermal design, variations in static power consumption can still lead to inconsistent chip junction temperatures during operation. When a low-power chip uses a package with a fixed thermal resistance, the package's heat dissipation easily meets the chip's requirements, resulting in high packaging costs and the risk of thermal redundancy. However, when a high-power chip uses a package with the same thermal resistance, the package's heat dissipation struggles to meet the chip's requirements, leading to performance degradation and thermal runaway.

[0055] This application proposes a chip packaging method and chip, which groups the chips to be packaged on a wafer according to their power consumption and selects a corresponding packaging optimization solution for the packaging thermal resistance of each chip group for packaging. This allows high-power consumption chips to use high-heat dissipation packaging and low-power consumption chips to use low-heat dissipation packaging. While meeting chip performance, it solves the problems of thermal redundancy and insufficient heat dissipation, achieving low-cost and high-performance packaging.

[0056] In this application, the "first target wafer" and "second target wafer" mentioned refer to different individual wafers produced with the same wafer structure in wafer mass production. For example, among a large number of wafers produced in a mass production, a portion is used as the "first target wafer" and another portion is used as the "second target wafer". Alternatively, in multiple mass production batches of a wafer, the "first target wafer" is the first batch or batches of wafers produced at the beginning, and the "second target wafer" is the wafer produced in subsequent batches.

[0057] Reference Figure 1 , Figure 1 The flow chart of a chip packaging method is shown. An embodiment of the present application provides a chip packaging method. In this embodiment, the chip packaging method includes steps 10, 20, 30, and 40.

[0058] Step 10: performing a wafer test on the first target wafer to determine a power consumption test value of each chip to be packaged on the first target wafer;

[0059] Step 20: Divide the chips to be packaged into multiple chipsets according to the power consumption test values, and calculate the allowable corresponding package thermal resistance of each chipset according to the power consumption range of each chipset;

[0060] Step 30: Determine the package optimization structure corresponding to the package thermal resistance of each chipset;

[0061] Step 40: Package each chip to be packaged on the first target wafer using a corresponding optimized packaging structure.

[0062] It should be noted that the wafer test can include multiple first target wafers, and each wafer can also include multiple chips to be packaged, with each chip to be packaged being a bare die. In this embodiment, all chips to be packaged have the same circuit architecture, which is equivalent to all chips to be packaged on the first target wafer having the same dynamic power consumption. Furthermore, the "second target wafer" mentioned later has the same circuit architecture as the chips to be packaged on the "first target wafer."

[0063] Wafer probing (CP) is a crucial step in the integrated circuit (IC) manufacturing process. It occurs after the wafer fabrication process and aims to ensure the quality of chips entering the packaging stage. Wafer probing can be performed using a probe station and a tester. During the test, basic electrical parameters such as connectivity (DC failing, power short), leakage current (Ileakage), power consumption (SIDD), and functional test items can be obtained.

[0064] This embodiment is mainly used to obtain power consumption test values. Due to different characteristics such as actual leakage current of each chip to be packaged, the power consumption test values ​​obtained by the test are different. Therefore, the power consumption test values ​​can reflect the static power consumption differences between the chips to be packaged.

[0065] During the wafer test, the test temperature of the first target wafer is any value within the temperature range in which the chip to be packaged can operate. For example, the operating range of the chip to be packaged is between -50° and 120°, and the test temperature can be any value within this range, such as 0°, 50° or 100°. In addition, the test temperature of all chips to be packaged is the same during the wafer test process to avoid distortion of the power consumption difference due to the test temperature difference. Of course, the temperature range in which the chip to be packaged can operate is determined based on the specific circuit architecture and material selection of the chip to be packaged.

[0066] The chips to be packaged are sorted in ascending order according to their power consumption test values ​​and then grouped, so that the power consumption differences between the chips to be packaged in the chipset are small. Therefore, after packaging with the same packaging optimization structure, there will not be much redundancy while ensuring that the heat dissipation requirements are met.

[0067] Reference Figure 2 , Figure 2 A chip packaging process is shown. As an example, after the wafer manufacturing is completed, the wafer CP test is carried out, and the power consumption values ​​of all chips are obtained according to the test. Chips with different power consumption ranges are limited to different Bins, and low power consumption a~b is obtained as Bin1, medium power consumption b~c is obtained as Bin2, high power consumption c~d is obtained as Bin3, and ultra-high power consumption d~e is obtained as Bin4. At the same time, under the specified ambient operating temperature and chip junction temperature threshold conditions, the package thermal resistance range corresponding to different Bins can be obtained by formula calculation. The upper limit of thermal resistance in interval Bin1 is defined as B, the upper limit of thermal resistance in interval Bin2 is defined as C, the upper limit of thermal resistance in interval Bin3 is defined as D, and the upper limit of thermal resistance in interval Bin4 is defined as E. In terms of package thermal design, there are usually four major ways to optimize package thermal resistance, namely, package material optimization, package substrate optimization, package form optimization, and external heat dissipation optimization to form four optimization schemes. The chip corresponding to interval Bin1 is packaged using optimization solution 1 to obtain product 1 with low heat dissipation packaging, the chip corresponding to interval Bin2 is packaged using optimization solution 2 to obtain product 2 with medium heat dissipation packaging, the chip corresponding to interval Bin3 is packaged using optimization solution 3 to obtain product 3 with high heat dissipation packaging, and the chip corresponding to interval Bin4 is packaged using optimization solution 4 to obtain product 4 with ultra-high heat dissipation packaging.

[0068] Reference Figure 3 , Figure 3A process of a chip packaging method is shown. In some embodiments, each chip to be packaged is divided into multiple chip groups according to the size of the power consumption test value, and the allowable packaging thermal resistance of each chip group is calculated according to the power consumption range of each chip group, including:

[0069] Step 21: Divide the total power consumption interval defined by each power consumption test value into a target number of sub-intervals, and the chips to be packaged corresponding to the sub-intervals constitute a chipset;

[0070] Step 22: Calculate the allowable package thermal resistance according to the power consumption range corresponding to each sub-interval.

[0071] One way to divide the target number of intervals is to determine a total power consumption interval based on the minimum and maximum power consumption test values, and then divide the total power consumption interval into a target number of equal-span intervals. Each chip to be packaged within the equal-span interval constitutes a chipset.

[0072] Another way to divide the chipset is to divide the total number of chips to be packaged into a target number of groups, where the number of chips in each group is the total number divided by the target number; and then select the chips to be packaged in the group with the same number of chips as a chipset based on the order of power consumption test value from small to large.

[0073] As an example, the minimum power consumption test value for all chips to be packaged is 1.73W, and the maximum is 2.82W. For example, the power range for Bin1, Bin2, Bin3, and Bin4, from smallest to largest, is [1.73W, 2W], Bin2 [2W, 2.27W], Bin3 [2.27W, 2.55W], and Bin4 [2.55W, 2.82W].

[0074] In some embodiments, the number of chipsets is determined according to the number of solutions for the package optimization structure, and the number of chipsets is equal to the number of solutions.

[0075] It is understood that different chipsets will be packaged using different packaging optimization structures. Therefore, the number of chipsets should be less than or equal to the number of achievable packaging optimization structure solutions. To fully utilize different packaging optimization structures, the number of chipsets can be equal to the number of solutions. The relevant content of packaging optimization structures will be discussed later.

[0076] In another example, the power consumption test values ​​of all chips to be packaged have a minimum value of 1.73 W and a maximum value of 2.82 W. The power consumption is divided into five intervals, Bin1, Bin2, Bin3, Bin4, and Bin5. The power range of interval Bin1 is [1.73 W, 1.948 W), the power range of interval Bin2 is [1.948 W, 2.166 W), the power range of interval Bin3 is [2.166 W, 2.384 W), the power range of interval Bin4 is [2.384 W, 2.602 W), and the power range of interval Bin5 is [2.602 W, 2.82 W].

[0077] In some embodiments, the package thermal resistance corresponding to each sub-interval is calculated based on the maximum power consumption test value of the sub-interval, and the package thermal resistance is determined according to the following formula:

[0078] R=(TJ-Ta) / P

[0079] Where R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value within the range.

[0080] The chip junction temperature threshold is determined by the specific circuit architecture and material selection of the packaged chip. The ambient operating temperature can be the maximum value within the operating range of the product in which the packaged chip is used. For example, the packaged chip can be used in consumer electronics, industrial electronics, and automotive electronics, each with its own specific operating temperature range.

[0081] As an example, assume the ambient operating temperature is 85°C and the chip junction temperature threshold is 125°C. The package thermal resistance corresponding to each interval is calculated based on the maximum power consumption test value corresponding to the interval and according to the above formula. For example, the power consumption test values ​​of all chips to be packaged are divided into four intervals, Bin1, Bin2, Bin3, and Bin4. For example, the maximum power consumption test value in interval Bin1 is 2W, and the calculated package thermal resistance is 20°C / W; the maximum power consumption test value in interval Bin2 is 2.27W, and the calculated package thermal resistance is 17.62°C / W; the maximum power consumption test value in interval Bin3 is 2.55W, and the calculated package thermal resistance is 15.69°C / W; the maximum power consumption test value in interval Bin4 is 2.82W, and the calculated package thermal resistance is 14.18°C / W. Therefore, for the chip to be packaged in Bin1, the upper limit of its thermal resistance is defined as 20℃ / W; for the chip to be packaged in Bin2, the upper limit of its thermal resistance is defined as 17.62℃ / W; for the chip to be packaged in Bin3, the upper limit of its thermal resistance is defined as 15.69℃ / W; for the chip to be packaged in Bin4, the upper limit of its thermal resistance is defined as 14.18℃ / W.

[0082] Package optimization refers to optimizing the thermal resistance of the package structure to improve its heat dissipation capabilities. This typically involves the heat generation and heat transfer capabilities of the material and structure, as well as auxiliary heat dissipation. For example, package optimization involves at least one of material optimization, substrate optimization, package form optimization, and external heat dissipation optimization.

[0083] It should be noted that within each optimization method, the optimization parameters can be further controlled to achieve different levels of package thermal resistance optimization. Therefore, by combining various optimization methods and parameters, different optimization solutions can be formed to achieve the desired thermal resistance range.

[0084] In some embodiments, material optimization involves the thermal conductivity coefficient of the packaging material, and involves at least one of the following: carrier material optimization, plastic packaging material optimization, patch adhesive material optimization, bottom filling adhesive material optimization, and interface thermal conductive adhesive material optimization.

[0085] Substrate materials can be categorized as flexible or rigid. Flexible substrate materials include PI (polyimide), PET (polyester), and PEEK (polyetheretherketone). Rigid substrates include FR4 (Flame-Retardant 4), ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine), and ceramics. Molding materials are categorized as organic or inorganic. Inorganic materials primarily include glass and ceramic, while organic materials include epoxy resin, polyimide, and thermoplastics. Surface mount adhesives primarily include epoxy resin, acrylic, and polyurethane. Underfill materials primarily include flip-chip underfills and ball grid array underfills. Thermal interface adhesives include silicone sheets, adhesive paste, gel, double-sided tape, and grease. When optimizing materials, you can select the above-mentioned types of materials, and you can formulate corresponding optimization plans by comprehensively considering various aspects such as thermal conductivity and heat resistance.

[0086] In some embodiments, substrate optimization involves at least one of whether a window is opened in the green oil of the packaging substrate, the window area, the window shape, and the copper coverage rate of the substrate.

[0087] Substrate green paint refers to the solder mask layer on the substrate. By creating windows in the green paint, the circuitry on the substrate can be exposed, thereby improving heat dissipation. The area and shape of the window also affect the heat dissipation of the green paint window. The substrate copper coverage ratio refers to the ratio of the area covered by copper foil to the total substrate area, which directly affects the substrate's heat dissipation performance.

[0088] In some embodiments, the package optimization involves at least one of a wire bonding ball grid array (WBBGA), a wire bonding land grid array (WBLGA), and a flip chip ball grid array (FCBGA).

[0089] WBBGA uses an array of solder balls on the bottom of the package substrate as the I / O terminals of the chip to interconnect with the substrate. It is a packaging method that connects the chip to the substrate through wire bonding. WBLGA also uses wire bonding to connect to the substrate, but the contacts are in the form of a flat grid. WBLGA uses point contact technology (contacts) to achieve interconnection with the substrate. The contacts are all on the substrate. Its interconnection principle is similar to that of WBBGA, but the contacts of WBLGA can be released to replace the chip, while the solder balls of WBBGA are fixed. FCBGA uses spherical solder joints to fix the package to the substrate. It is a packaging technology that inverts the chip and connects it to the package substrate. It has the advantages of high integration, small size, high performance, and low power consumption.

[0090] In some embodiments, the external heat dissipation optimization involves at least one of a heat sink optimization, a fan cooling optimization, and a liquid cooling optimization.

[0091] External cooling optimization achieves different cooling capabilities by selecting the type of external cooling or whether to install external cooling. Radiators achieve heat dissipation by increasing the heat exchange area through the design of appropriate heat dissipation structures (such as heat sinks). Fan cooling accelerates heat dissipation through airflow, and liquid cooling utilizes liquid for heat exchange, increasing heat dissipation speed.

[0092] As an example, the power consumption test values ​​of all chips to be packaged are divided into four intervals: Bin1, Bin2, Bin3 and Bin4. For the chips to be packaged corresponding to the Bin1 interval, optimization solution 1 is adopted: based on the conventional packaging thermal design, the materials are optimized, the surface mount adhesive and plastic encapsulation material are optimized, and the thermal resistance is 20°C / W; for the chips to be packaged corresponding to the Bin2 interval, optimization solution 2 is adopted: the combination of materials and substrates is optimized, specifically, the plastic encapsulation material is optimized, and a local window is used in the substrate to make the thermal resistance 17.62°C. / W; for the chip to be packaged corresponding to the Bin3 interval, optimization solution 3 is adopted: a combined optimization of the substrate and packaging form is performed. Specifically, a full-window substrate method is adopted, and the packaging form is changed from the initial WBBGA to WBLGA, so that its thermal resistance is 15.69℃ / W; for the chip to be packaged corresponding to the Bin4 interval, optimization solution 4 is adopted: a combined optimization of the packaging form and external heat dissipation is performed. Specifically, the packaging form is changed from WBBGA to FCBGA, and a heat sink and fan are added, so that its thermal resistance is 14.18℃ / W.

[0093] Reference Figures 4 to 6 , Figures 4 to 6 The following diagrams illustrate a chip packaging structure with three different heat dissipation capabilities. The packaged chip 1 is fixed to the package substrate 4 using patch adhesive 5 and electrically connected to the package substrate 4 via interconnecting bonding wires 3. The plastic encapsulation compound 2 is used for encapsulation, securing the packaged chip 1 and isolating it from the outside world.

[0094] Figure 4 and Figure 5 The main difference is the different welding method under the package substrate. Figure 4 Solder balls 6 are used to achieve welding. Figure 5 Use pad 7 to achieve welding, Figure 5 The package structure shown has a heat dissipation capability greater than Figure 4 . Figure 4 and Figure 6 compared to, Figure 6 The addition of the auxiliary fin heat sink 8 further improves the heat dissipation capacity through external heat dissipation. Figure 5 and Figure 6 compared to, Figure 5 The welding method is optimized and welding is achieved using pad 7. Figure 6 Added auxiliary fin radiator 8 to optimize external heat dissipation. Figure 6 The package structure shown has better heat dissipation capability than Figure 5 .certainly, Figures 4 to 6 The chip packaging structure shown does not constitute a limitation on the above-mentioned packaging optimization structure, and the specific structure can be set according to requirements.

[0095] Reference Figure 7 , Figure 7 FIG. 5 shows a process flow of a chip packaging method. In this embodiment, the chip packaging method further includes steps 50 and 60.

[0096] Step 50: Generate a wafer power consumption distribution map based on the distribution of chipsets on the plurality of first target wafers, wherein the wafer power consumption distribution map determines the distribution area of ​​each chip to be packaged based on the power consumption test value of the chip to be packaged;

[0097] Step 60 : According to the wafer power consumption distribution map, each chip to be packaged on the second target wafer is packaged using a packaging optimization structure corresponding to the distribution area. The second target wafer has the same structure as the first target wafer.

[0098] The wafer power consumption distribution diagram can show the distribution areas of the chips to be packaged with different power consumption test values ​​on the first target wafer. Since the first target wafer and the second target wafer are wafers with the same structure, the wafer power consumption distribution diagram can also show the power consumption test values ​​of the chips to be packaged in each distribution area on the second target wafer.

[0099] When packaging the second target wafer according to the wafer power consumption distribution map, the corresponding packaging optimization structure can be directly determined according to the packaging thermal resistance corresponding to the chip group in each distribution area. This eliminates the need to perform power consumption testing on each chip to be packaged, thus simplifying the packaging process.

[0100] In some embodiments, the wafer power consumption distribution diagram includes power consumption distribution areas, in which chips to be packaged of the same chipset are distributed; step 60 includes: determining the packaging thermal resistance corresponding to the power consumption distribution area on the second target wafer according to the wafer power consumption distribution diagram; and packaging each chip to be packaged in each power consumption distribution area according to the packaging optimization structure corresponding to the packaging thermal resistance.

[0101] In conjunction with the above example, on the second target wafer, the distribution area may include a first power consumption distribution area and a second power consumption distribution area. The first power consumption distribution area contains the chips to be packaged corresponding to the Bin1 interval. Based on conventional packaging thermal design, material optimization can be performed on the first power consumption distribution area, optimizing the die-cast adhesive and molding compound to achieve a thermal resistance of 20°C / W. The second power consumption distribution area contains the chips to be packaged corresponding to the Bin2 interval. Material and substrate combination optimization can be performed on the second power consumption distribution area. Specifically, the molding compound can be optimized and a partial windowing method can be used to achieve a thermal resistance of 17.62°C / W.

[0102] In addition, the above example only selects two power consumption distribution areas for illustration, but the specific number of power consumption distribution areas is the same as the number of chipsets, which can be set according to the number requirements of chipsets. For details, please refer to the above embodiments.

[0103] In some embodiments, the wafer power consumption distribution diagram also includes a critical test area, which is located between multiple power consumption distribution areas and has multiple chips to be packaged from multiple chipsets distributed therein; step 60 includes: testing the power consumption of each chip to be packaged in the corresponding critical test area on the second target wafer, and packaging each chip to be packaged in the critical test area using the corresponding packaging optimization structure according to the power consumption test value.

[0104] Understandably, if the wafer preparation process has low precision control, the power consumption distribution of each chip to be packaged on the wafer may not fully conform to the established rules, resulting in a region on the prepared wafer containing chips to be packaged with a wide range of power consumption test values. The power consumption test value range corresponding to this region may cover multiple chip groups on the first target wafer.

[0105] In such cases, it is not appropriate to package the area using the packaging optimization structure corresponding to a certain chipset. Therefore, the power consumption of each chip to be packaged in the area can be tested, and the corresponding packaging optimization structure can be determined according to the power consumption test value and the packaging correspondence on the first target wafer.

[0106] In some embodiments, the power consumption distribution areas and critical test areas are alternately arranged in sequence from the inside to the outside on the wafer, the outer area surrounds the inner area, and the critical test area is distributed with the chips to be packaged of the chip group corresponding to the two adjacent power consumption distribution areas. The power consumption test value of the chip to be packaged located in the outer power consumption distribution area is greater than the power consumption test value of the chip to be packaged located in the inner power consumption distribution area.

[0107] Reference Figure 8 , Figure 8 A schematic diagram of a wafer power consumption distribution diagram is shown. As an example, the power consumption of the first batch of wafers (i.e., the first target wafer) is overlaid to obtain a wafer power consumption distribution diagram. The wafer is divided into four power consumption distribution areas and three critical test areas. The four power consumption distribution areas correspond to the power consumption test values ​​of Bin1, Bin2, Bin3, and Bin4, respectively, with power ranges of [1.73W, 2W), [2W, 2.27W), [2.27W, 2.55W), and [2.55W, 2.82W]. The first critical test area is located between Bin1 and Bin2, with a power range of [1.73W, 2.27W); the second critical test area is located between Bin1 and Bin2, with a power range of [2W, 2.55W); and the third critical test area is located between Bin1 and Bin2, with a power range of [2.27W, 2.82W].

[0108] In subsequent mass production batches of wafers (i.e., the second target wafer), for the chips to be packaged located in the Bin1, Bin2, Bin3, and Bin4 distribution areas, there is no need to perform power consumption testing, and the corresponding packaging optimization solution can be directly selected for packaging processing.

[0109] A power consumption test was performed on the chip to be packaged located in the first critical test area. When the power consumption value was within the range of [1.73W, 2W), the low heat dissipation packaging solution of optimization solution 1 was selected for packaging. When the power consumption value was within the range of [2W, 2.27W), the medium heat dissipation packaging solution of optimization solution 2 was selected for packaging. A power consumption test was performed on the chip to be packaged located in the second critical test area. When the power consumption value was within the range of [2W, 2.27W), the medium heat dissipation packaging solution of optimization solution 2 was selected for packaging. When the power consumption value was within the range of [2.27W, 2.55W), the high heat dissipation packaging solution of optimization solution 3 was selected for packaging. When the power consumption value was within the range of [2.55W, 2.82W], the ultra-high heat dissipation packaging solution of optimization solution 4 was selected for packaging.

[0110] An embodiment of the present application further provides a chip, which is manufactured according to the aforementioned chip packaging method.

[0111] The chip in this embodiment is packaged using the aforementioned chip packaging method. While meeting chip performance requirements, it is less likely to encounter thermal redundancy and insufficient heat dissipation issues, achieving low-cost, high-performance packaging. The chip packaging method is described above in detail and will not be further described in this embodiment.

[0112] In this document, the terms "comprises", "includes" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0113] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging method, characterized in that: include: Performing a wafer test on a first target wafer to determine a power consumption test value of each chip to be packaged on the first target wafer, wherein the wafer test has a test temperature range of -50°C to 120°C, the chips to be packaged on the first target wafer have the same circuit architecture, the proportion of static power consumption of the chips to be packaged in the total power consumption increases with increasing temperature, and the chips to be packaged on the first target wafer have different static power consumptions; Dividing the chips to be packaged into multiple chip groups according to the power consumption test values, and calculating the allowable package thermal resistance of each chip group according to the power consumption range of each chip group; Determining a package optimization structure corresponding to the package thermal resistance of each chipset, wherein different package optimization structures have different heat dissipation performances; Each of the chips to be packaged on the first target wafer is packaged using the corresponding packaging optimization structure, and the chips to be packaged in the same chipset are packaged using the same packaging optimization structure; generating a wafer power consumption distribution map according to the distribution of the chipsets on the plurality of first target wafers, wherein the wafer power consumption distribution map determines a distribution area of ​​each chip to be packaged based on a power consumption test value of the chip to be packaged; According to the wafer power consumption distribution map, each chip to be packaged on the second target wafer is packaged using a packaging optimization structure corresponding to the distribution area, wherein each chip to be packaged on the second target wafer has the same circuit architecture as each chip to be packaged on the first target wafer; The wafer power consumption distribution diagram includes a power consumption distribution area and a critical test area. The power consumption distribution area is distributed with chips to be packaged of the same chipset. The critical test area is located between multiple power consumption distribution areas and is distributed with chips to be packaged of multiple chipsets. The power consumption distribution areas and the critical test areas are alternately arranged in sequence from the inside to the outside on the wafer, and the outer area surrounds the inner area. The critical test area is distributed with chips to be packaged of the chipsets corresponding to two adjacent power consumption distribution areas. The power consumption test value of the chip to be packaged in the outer power consumption distribution area is greater than the power consumption test value of the chip to be packaged in the inner power consumption distribution area.

2. The chip packaging method according to claim 1, wherein: The step of dividing the chips to be packaged into a plurality of chip groups according to the power consumption test values, and calculating the allowable package thermal resistance of each chip group according to the power consumption range of each chip group includes: Dividing the total power consumption interval defined by each of the power consumption test values ​​into a target number of sub-intervals, wherein the chips to be packaged corresponding to the sub-intervals constitute a chipset; The allowable package thermal resistance is calculated according to the power consumption range corresponding to each sub-interval.

3. The chip packaging method according to claim 2, wherein: The package thermal resistance corresponding to each sub-interval is calculated based on the maximum power consumption test value of the sub-interval, and the package thermal resistance is determined according to the following formula: R=(TJ-Ta) / P Where R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value in the sub-interval.

4. The chip packaging method according to any one of claims 1 to 3, characterized in that: The step of packaging each to-be-packaged chip on the second target wafer using a packaging optimization structure corresponding to the distribution area according to the wafer power consumption distribution map includes: Determining a package thermal resistance corresponding to the power consumption distribution area on a second target wafer according to the wafer power consumption distribution map; Each chip to be packaged in each power consumption distribution area is packaged according to the package optimization structure corresponding to the package thermal resistance.

5. The chip packaging method according to claim 4, characterized in that: The step of packaging each to-be-packaged chip on the second target wafer using a packaging optimization structure corresponding to the distribution area according to the wafer power consumption distribution map further includes: Testing the power consumption of each chip to be packaged in the corresponding critical test area on the second target wafer; The chips to be packaged in the critical test area are packaged using the corresponding packaging optimization structure according to the power consumption test value.

6. The chip packaging method according to any one of claims 1 to 3, characterized in that: The packaging optimization structure involves at least one of material optimization, substrate optimization, packaging form optimization and external heat dissipation optimization.

7. The chip packaging method according to claim 6, characterized in that: The material optimization involves the thermal conductivity coefficient of the packaging material, and involves at least one of the following: optimization of the carrier material, optimization of the plastic packaging material, optimization of the patch adhesive material, optimization of the bottom filling adhesive material, and optimization of the interface thermal conductive adhesive material; The substrate optimization involves at least one of whether the green oil of the packaging substrate has a window, the window area, the window shape, and the copper coverage rate of the substrate; The packaging form optimization involves at least one of ball grid array packaging, land grid array packaging and flip chip ball grid array packaging; The external heat dissipation optimization involves at least one of radiator optimization, fan cooling optimization and liquid cooling optimization.

8. A chip, characterized in that: The chip is manufactured according to the chip packaging method according to any one of claims 1 to 7.

Images