In-situ detection method for die of small and medium-sized integrated circuits on large-size wafer

Abstract

The invention provides an in-situ detection method based on randomized sampling and dynamic adjustment, aiming at the high-efficiency detection problem of small and medium-sized integrated circuit chips on a large-size wafer. The core of the method is to dynamically adjust the randomized sampling inspection probability: the sampling inspection frequency is reduced in a region with high reliability, and the sampling inspection frequency is improved in a region with low reliability. Meanwhile, a punishment and reward mechanism is introduced, the sampling inspection frequency is increased for a region with poor reliability for punishment, the sampling inspection frequency is reduced for a region with high reliability for reward, the detection efficiency can be remarkably improved while the detection precision is ensured, the production cost is reduced, and the method is particularly suitable for efficient detection scenes of large-size wafers.

Description

Technical Field

[0001] The present invention relates to an integrated circuit testing method, and more particularly to an in-situ detection method for medium and small scale integrated circuit Dies on large-sized wafers. Background Art

[0002] Medium and small scale integrated circuits refer to integrated circuits with relatively low integration levels. They usually contain a relatively small number of components (the number of transistors in each Die ranges from dozens to thousands), and their functions are relatively simple. Medium and small scale integrated circuits are widely used in some basic audio processing, simple logic control, network communication and other fields. With the development of technology, although large scale and very large scale integrated circuits have become the mainstream, medium and small scale integrated circuits still continue to play a role in some specific fields due to their low cost and high reliability.

[0003] Producing medium and small scale integrated circuits on large-sized wafers has significant economic advantages. First, large-sized wafers (such as 300mm) have a larger area, which can accommodate more chip units (Dies), thus significantly reducing the unit chip cost. Second, the production process of large-sized wafers (such as the Czochralski method) is relatively mature and has a lower cost, which can effectively control the production cost. In addition, with the progress of technology, the production efficiency and yield of large-sized wafers are continuously improved, further optimizing the production cost. Therefore, although the integration level of medium and small scale integrated circuits is relatively low, using large-sized wafers for production can give full play to their economies of scale, reduce the manufacturing cost per unit chip, and enhance the market competitiveness.

[0004] The cost advantages of producing medium and small scale integrated circuits on large-sized wafers are mainly reflected in the following aspects: (1) Improved area utilization: The area of a large-sized wafer (such as 12 inches) is about 2.25 times that of an 8-inch wafer. Therefore, the number of chips that can be cut from a single wafer increases significantly, thus significantly reducing the production cost per unit chip.

[0005] (2) Economies of scale: The production efficiency of large-sized wafers is higher. Especially in large-scale production, the fixed costs per unit chip (such as equipment depreciation, maintenance, etc.) are shared by more chips, further reducing the cost.

[0006] (3) Process maturity: The production process of large-sized wafers is gradually maturing, and the stability of equipment and processes is improving, resulting in an increase in production yield and further optimizing the cost.

[0007] Taking 8-inch and 12-inch wafers as examples, the unit chip cost of 12-inch wafers is about 20%-30% lower than that of 8-inch wafers, depending on chip design and process complexity. Therefore, producing medium and small-scale integrated circuits on large-sized wafers can significantly reduce production costs and improve economic efficiency while meeting performance requirements.

[0008] In the semiconductor manufacturing process, the testing of chips before packaging is an important link to ensure product quality and reliability. After the chips are fabricated on the wafers, whether their performance and functions meet the design requirements need to be verified through strict testing. The testing before packaging can effectively screen out unqualified chips, avoid putting defective products into the subsequent packaging process, thereby reducing resource waste and production costs. In addition, the testing before packaging can also help engineers promptly discover process problems in the manufacturing process, feedback to the production link for optimization and adjustment, thereby improving the overall production quality. Therefore, the testing before packaging is not only a key step to ensure chip quality but also an important means to improve production efficiency and reduce production costs.

[0009] Traditional chip Die testing methods mainly adopt the method of testing one by one. Specifically, each chip (Die) on the wafer is tested individually to verify whether its function meets the design requirements. During the testing process, each Die is connected to the testing equipment through a probe card, and electrical performance testing, function testing, etc. are carried out in sequence. After the testing is completed, the qualified Dies are marked and cut for packaging, and the unqualified Dies are discarded. The advantage of this method is that it can ensure that each chip undergoes strict testing and the finished product qualification rate is extremely high. However, with the increase in wafer size and the number of chips, the traditional method of testing one by one faces huge challenges. A large-sized wafer may integrate thousands or even tens of thousands of chips, and testing one by one requires a large amount of time and testing equipment resources, seriously affecting production efficiency.

[0010] For example, when producing medium and small-scale integrated circuits on large-sized wafers (such as 12 inches), the number of Dies depends on the size of the Dies. For example, for medium-sized Dies (such as 9.5mm × 10.5mm, area 99mm²), about 622 Dies can be cut from a 12-inch wafer. For smaller-scale integrated circuits, the Die size is smaller and the number is larger, possibly reaching thousands or tens of thousands. For such a large number of Dies, the existing method of testing chip Dies one by one has significant disadvantages in terms of efficiency. The difficulties in testing are mainly reflected in the following points: (1) Long test time: A large number of Dies means a significant increase in the number of chips that need to be tested one by one, resulting in a significant extension of the test time. On large-sized wafers, with a large number of chips, the test time will increase linearly with the increase in the number of chips. For example, a wafer containing tens of thousands of chips may take several days or even weeks to complete the test, seriously affecting the production cycle and increasing the production time cost.

[0011] (2) High pressure on test equipment: A large number of Dies need to be tested within a short period, posing higher requirements for the throughput and stability of the test equipment.

[0012] (3) Rising test costs: Testing one by one requires a large amount of test equipment and human input. The increased usage frequency of test resources (such as probe cards and test machines) leads to an increase in test costs. Each Die needs to be individually connected to the test equipment and tested, which not only increases the usage time and frequency of the test equipment but also causes a significant increase in equipment depreciation and maintenance costs.

[0013] (4) Complex data processing: The analysis and processing of a large amount of test data become more difficult, posing higher requirements for the automated test system.

[0014] Therefore, although large-sized wafers have a cost advantage in the production of small and medium-scale integrated circuits, the complexity of the test link also increases accordingly, the test cost rises significantly, and the efficiency of the existing test methods is low.

[0015] In addition, traditional test methods cannot be dynamically adjusted according to the process reliability of different regions on the wafer, resulting in a waste of test resources. Regardless of the process reliability of the chips, each Die needs to go through a complete test process, which to a certain extent reduces the test efficiency. Therefore, the traditional method of testing one by one has become an important bottleneck restricting semiconductor production due to its low efficiency when facing large-sized wafers and high-density chips. Summary of the Invention

[0016] The main technical solution to achieve the object of the present invention is: To address the problem of efficient detection of medium and small-scale integrated circuit chips on large-sized wafers, an in-situ detection method based on randomized sampling and dynamic adjustment is proposed. The core of this method lies in randomly sampling and detecting some chips (Dies) on the wafer, and statistically analyzing the process reliability based on the detection results of different regions. On this basis, the sampling probability is dynamically adjusted: the sampling frequency is reduced in regions with high reliability, and increased in regions with low reliability. At the same time, a penalty and reward mechanism is introduced to "penalize" regions with poor reliability by increasing the sampling frequency and "reward" regions with high reliability by reducing the sampling frequency. Through this optimized sampling strategy and testing process, the present invention can significantly improve the detection efficiency and reduce the production cost while ensuring the detection accuracy, and is particularly suitable for the efficient detection scenario of large-sized wafers.

[0017] The technical solution of the present invention is only applicable to the testing of medium and small-scale integrated circuits on large-sized wafers, and is not applicable to small and medium-sized wafers, nor to the testing of large-scale and ultra-large-scale integrated circuits.

[0018] It should be noted that the present invention does not make specific definitions and limitations on "large-sized wafers" and does not make specific definitions and limitations on "medium and small-scale integrated circuits" either. However, it should be noted that the technical solution of the present invention is applicable to the testing of medium and small-scale integrated circuits on large-sized wafers, which is limited to: the number of Dies distributed on a wafer is numerous, and the more Dies there are, the more applicable the technical solution of the present invention is, and vice versa, the fewer Dies there are, the less applicable the technical solution of the present invention is.

[0019] Preferably, the number of Dies distributed on a wafer reaches more than one thousand.

[0020] More preferably, the number of Dies distributed on a wafer reaches more than ten thousand.

[0021] The testing method of the present invention specifically includes the following steps: 1. Randomized sampling detection: Randomly select a certain number of Dies on the large-sized wafer for functional testing. This random selection relies on a specific controlled parametric randomized function. Sampling and in-situ detecting Dies according to the aforementioned controlled parametric randomized function before wafer dicing.

[0022] The test content includes electrical performance, logical function, etc., to ensure that the Dies meet the design requirements.

[0023] 2. Statistical analysis: According to the test results, statistically analyze the process reliability of different regions on the wafer.

[0024] Divide the wafer into several regions, and calculate the pass rate and failure rate of each region; Or divide the wafer into several regions according to the yield rate.

[0025] 3. Dynamically adjust the sampling probability: For regions with high reliability (high yield rate), reduce the sampling probability and decrease the test frequency.

[0026] For regions with low reliability (low yield rate), increase the sampling probability and increase the test frequency.

[0027] By setting a reward and punishment function, dynamically adjust the sampling strategy: Punishment: For regions with a high unqualified rate, increase the sampling frequency.

[0028] Reward: For regions with a high yield rate, reduce the sampling frequency.

[0029] 4. After the test of each wafer is completed, return to step 1 and complete the in-situ test of the entire production batch of wafers one by one.

[0030] 5. In-situ test and dicing and packaging: Complete the in-situ test before wafer dicing and mark the unqualified Dies according to the test results.

[0031] After dicing, only package the qualified Dies, and directly discard the unqualified Dies.

[0032] In the present invention, the technology for in-situ testing of Dies on the wafer adopts the existing technology. For example: The core principle of in-situ testing on the wafer is to make electrical connections between the Probe Card and the Dies on the wafer, and test the electrical performance and functions of the Dies one by one or in batches. During the test process, the probes on the probe card contact the pads of the Dies, and the test equipment applies test signals to the Dies through the probe card and reads the response signals of the Dies, so as to judge whether the Dies meet the design requirements. The test equipment connects each Die in turn through the probe card to perform electrical performance tests, functional tests, etc. After the test is completed, the qualified Dies are marked and diced for packaging, and the unqualified Dies are discarded.

[0033] During the process of in-situ testing of integrated circuit Dies on the wafer, the test equipment makes electrical connections with the pads of each Die through the Probe Card, and performs electrical performance tests and functional tests in turn. The electrical performance test mainly includes measuring parameters such as voltage, current, and resistance of the Die to ensure that its electrical characteristics meet the design requirements. The functional test verifies whether its logic function is normal by inputting specific test signals to the Die. The test equipment will automatically complete these test steps according to the preset test program and record the test results of each Die.

[0034] After the test is completed, qualified Dies are marked as "passed", while unqualified Dies are marked as "failed". The marking method is usually through laser marking or ink marking on the surface of the wafer, so as to distinguish qualified and unqualified Dies during subsequent dicing and packaging processes. After the marking is completed, the wafer enters the dicing process, and each Die is separated from the wafer using precise dicing equipment. Qualified Dies will be sent into the packaging process, and steps such as wire bonding and plastic encapsulation are carried out, and finally become available chip products. While unqualified Dies will be directly discarded to avoid entering subsequent production links, thereby reducing resource waste and production costs.

[0035] Since this belongs to the prior art well-known to those skilled in the art, it will not be elaborated here.

[0036] A further improvement of the present invention lies in: combining the characteristics of semiconductor manufacturing processes, optimizing the randomized sampling inspection function, further improving the Die detection efficiency, and better balancing detection accuracy, comprehensiveness, and economy.

[0037] The technical principle thereof lies in: When producing a large number of Dies on a large-sized wafer, the defect distribution usually has certain regularity and regional characteristics, which is closely related to the complexity and variability of semiconductor manufacturing processes. The following is a specific analysis: 1. Regionality and process fluctuations: The defect distribution on the wafer often shows regional characteristics. Due to the difficulty in fully ensuring the uniformity of process steps such as lithography, etching, and deposition during the manufacturing process, the process conditions in the edge area of the wafer are usually more unstable than those in the central area, resulting in a higher defect density in the edge area. This phenomenon is called the "edge effect".

[0038] Process fluctuations (such as temperature, gas flow rate, pressure, etc.) will cause parameters such as film thickness and doping concentration in some areas of the wafer to deviate from the design values, thereby forming local high-defect areas.

[0039] 2. Random defects and systematic defects: Random defects: Caused by particle contamination, equipment failures, or material non-uniformity, the distribution is relatively random and may appear anywhere on the wafer.

[0040] Systematic defects: Caused by systematic errors or design problems of process equipment, usually showing a regular distribution. For example, defects on the lithography mask will form repetitive defects on the wafer.

[0041] 3. Defect aggregation effect: In some cases, defects exhibit an aggregated distribution, i.e., the defect density in certain areas is significantly higher than that in other areas. This phenomenon may be related to abnormal local process conditions (such as uneven photoresist coating) or equipment failures.

[0042] 4. Inter-batch differences: There may be significant differences in the defect distribution among wafers of different batches. For example, wafers of a certain batch may have defects concentrated in specific areas due to incomplete calibration after equipment maintenance.

[0043] 5. Correlation between defect types and process steps: Different process steps may introduce different types of defects. For example, the lithography step may cause pattern distortion or missing, the etching step may introduce residues or over-etching, and the ion implantation step may cause uneven doping.

[0044] In summary, the defect distribution on large-sized wafers has the characteristics of coexistence of regionality, randomness, and systematicness. By statistically analyzing the defect distribution pattern, the testing strategy can be optimized. For example, increasing the sampling probability in high-defect areas and decreasing the sampling probability in low-defect areas, specifically referring to optimizing the randomized sampling function, so as to improve the testing efficiency and reduce the missed detection rate.

[0045] The present invention has achieved significant beneficial technical effects in multiple aspects through innovative detection methods and strategies: 1. Significantly improve the detection efficiency

[0046] Traditional chip detection methods use a one-by-one testing method, and each chip needs to go through a complete testing process, resulting in a linear increase in testing time as the number of chips increases. For example, a large-sized wafer may integrate tens of thousands of chips, and one-by-one testing may take several days or even weeks. The present invention adopts a randomized sampling detection technology, only performing functional tests on some chips, and inferring the process reliability of the entire wafer through statistical analysis. This method greatly reduces the number of tests and significantly shortens the testing time. In addition, the strategy of dynamically adjusting the sampling probability enables the detection resources to be concentrated in areas with lower reliability, avoiding over-detection of high-reliability areas and further optimizing the detection efficiency.

[0047] 2. Reduce production costs

[0048] The traditional method of testing one by one is not only time-consuming, but also requires a large amount of testing equipment and human input, increasing equipment depreciation, maintenance costs, and labor costs. By reducing the number of tests and optimizing the testing process, the present invention significantly reduces the usage time and frequency of testing equipment, reducing equipment depreciation and maintenance costs. At the same time, due to the substantial reduction in testing time, labor costs are also correspondingly reduced. In addition, the present invention completes testing before dicing and packaging, which can avoid packaging unqualified chips and reduce waste during the packaging process. Through these improvements, the present invention significantly reduces production costs and improves the economic efficiency of enterprises without compromising product quality.

[0049] 3. Optimize Quality Control Although there may be a risk of missed inspections in randomized sampling inspection, the present invention controls the missed inspection rate within an acceptable range through reasonable algorithm design and process adjustment. For example, by dynamically adjusting the sampling probability and introducing a penalty and reward mechanism, it is possible to accurately locate areas with lower reliability and increase the detection intensity, thereby effectively reducing the possibility of missed inspections. At the same time, combined with the characteristics of semiconductor processes, the present invention can control the missed inspection rate at a level of one in a million or even ten million, far lower than the unqualified rate of traditional testing methods. In addition, the present invention can further reduce the potential risks brought by missed inspections through an economic compensation mechanism (such as compensating ten for one defective). This optimized quality control strategy improves the feasibility and reliability of the detection method while ensuring product quality.

[0050] 4. Enhance Process Optimization Feedback

[0051] The present invention is not only a detection method but also capable of providing important process optimization feedback for the production process. By statistically analyzing the process reliability of different regions on the wafer, problems in the manufacturing process can be promptly identified and fed back to the production process for adjustment and optimization. This real-time feedback mechanism helps engineers quickly locate process defects, reducing the chip unqualified rate caused by process problems and further improving the overall production quality. In addition, the strategy of dynamically adjusting the sampling probability can also flexibly adjust the detection focus according to real-time detection results to ensure that the detection method always matches the actual production situation.

[0052] 5. Adapt to the Requirements of Mass Production

[0053] With the development of semiconductor technology, the size of wafers continues to increase, and the integration of chips is getting higher and higher. The traditional one-by-one testing method can no longer meet the needs of large-scale production. The present invention can efficiently process a large number of chips on large-size wafers through randomized sampling detection and dynamic adjustment strategies, and is particularly suitable for high-density, large-scale production scenarios in modern semiconductor manufacturing. By optimizing the detection process and resource allocation, the present invention not only improves the detection efficiency, but also reduces the production bottleneck caused by long detection time, providing a more competitive solution for semiconductor manufacturers.

[0054] 6. Environmental friendliness and sustainability

[0055] From the perspective of sustainable development, the present invention reduces energy consumption and equipment loss by reducing the use time and frequency of test equipment. At the same time, it reduces waste in the packaging process, further reducing resource consumption and environmental impact in the production process. This environmentally friendly design not only conforms to the green development concept of modern manufacturing, but also provides support for the sustainable development of enterprises.

[0056] In summary, the present invention has achieved significant beneficial technical effects in terms of improving detection efficiency, reducing production costs, optimizing quality control, enhancing process optimization feedback, adapting to large-scale production needs, and environmental friendliness through innovative detection methods and strategies. These effects not only improve the production efficiency and economic benefits of semiconductor manufacturing companies, but also provide important support for the technological progress of the semiconductor industry.

[0057] The technical solution of the present invention also achieves significant technical effects in preventing the risk of missed detection, which is mainly reflected in the following aspects: 1. Extremely low level and acceptability of missed detection risk

[0058] The present invention controls the missed detection rate at an extremely low level by optimizing the randomized sampling function and combining the characteristics of semiconductor processes. Specifically, by dynamically adjusting the probability of random inspections and introducing a penalty and reward mechanism, it is possible to accurately locate areas with low reliability on the wafer and increase the frequency of random inspections in these areas. This strategy can reduce the missed detection rate to one in a million or even one in ten million. In large-scale production, such a low missed detection rate is much lower than the failure rate of traditional detection methods, and is almost negligible in practical applications.

[0059] From the perspective of economics, even if a few missed inspections occur, the impact on the overall quality is minimal. Through economic compensation mechanisms (such as "ten times the cost of one bad product"), customer losses can be effectively compensated. At the same time, the cost of such compensation is almost negligible in large-scale production. Therefore, the risk of missed inspections is completely acceptable.

[0060] 2. Detection strategy combined with semiconductor process characteristics

[0061] In the semiconductor manufacturing process, the quality of chips on a wafer usually has a certain distribution pattern. In some areas, a higher rejection rate may occur due to process defects or equipment problems, while other areas show higher reliability. Through statistical analysis of the process reliability in different areas, the present invention dynamically adjusts the sampling probability to ensure that the detection resources can be concentrated where they are most needed. This detection strategy based on process characteristics not only improves the detection efficiency but also further reduces the missed detection rate, ensuring product quality.

[0062] 3. Solving the missed detection risk through economic means

[0063] From an economic perspective, although the traditional one-by-one testing method has a low missed detection rate, its detection cost is extremely high and it is difficult to adapt to large-scale production. By optimizing the sampling algorithm, the present invention significantly reduces the detection cost while ensuring detection accuracy. Even at a very low missed detection rate, it is possible for individual defective chips to flow into the market, but this problem can be effectively solved through an economic compensation mechanism.

[0064] For example, assume that one defective chip is missed in one hundred thousand chips. Through a "compensate ten for one defective" compensation mechanism, the enterprise needs to compensate for the cost of ten chips. However, due to the extremely low missed detection rate, this compensation cost can be almost negligible in large-scale production. From an economic perspective, this strategy not only reduces the detection cost but also ensures the economic benefits of the enterprise through reasonable risk control.

[0065] 4. Application of semiconductor testing principles

[0066] The core of semiconductor testing lies in screening out defective chips through electrical performance testing and functional testing. Through randomized sampling detection, the present invention can complete the testing before wafer dicing, effectively screening out defective chips. This testing method not only improves the testing efficiency but also ensures that the missed detection rate is controlled within an acceptable range through reasonable algorithm design and process adjustment.

[0067] 5. Balance between technology and economy

[0068] By optimizing the detection algorithm and combining the characteristics of semiconductor processes, the present invention achieves a balance between technology and economy. On the one hand, it ensures product quality through an extremely low missed detection rate; on the other hand, it solves the possible missed detection risk through an economic compensation mechanism. This balance not only improves the detection efficiency, reduces the production cost, but also provides a more competitive solution for semiconductor manufacturing enterprises.

[0069] In summary, by optimizing the detection algorithm and combining the characteristics of semiconductor processes, the present invention controls the missed detection rate at an extremely low level and solves the possible risk of missed detection through an economic compensation mechanism. This technical solution is not only innovative technically but also feasible economically, providing an efficient, economical, and reliable detection method for semiconductor manufacturing enterprises.

[0070] The technical solution of the present invention is mainly aimed at the testing of medium and small-scale integrated circuits (ICs) on large-sized wafers, having significant economic and efficiency advantages. However, this solution is not applicable to small and medium-sized wafers, nor to the testing of large-scale and ultra-large-scale integrated circuits.

[0071] The following elaborates in detail from aspects such as technical principles, economy, and missed detection rate to illustrate the applicable scope and limitations of the present invention.

[0072] 1. Advantages of Testing Medium and Small-Scale Integrated Circuits on Large-Sized Wafers When producing medium and small-scale integrated circuits on large-sized wafers (such as 300mm wafers), a large number of Dies (chip units) can be accommodated on a single wafer. Since the Die size of medium and small-scale integrated circuits is relatively small, thousands or even tens of thousands of Dies can be cut from a single wafer. This high-density Die distribution makes the randomized sampling detection method have significant advantages: High testing efficiency: Through randomized sampling detection, only a part of the Dies need to be tested to infer the process reliability of the entire wafer, thus significantly reducing the testing time and the usage frequency of equipment.

[0073] Significant cost-effectiveness: Due to the reduction in the number of tests, the depreciation, maintenance costs of testing equipment, and labor costs are significantly reduced, being particularly suitable for large-scale production scenarios.

[0074] Dynamic adjustment strategy: By statistically analyzing the process reliability of different regions and dynamically adjusting the sampling probability, the missed detection rate can be effectively reduced to ensure product quality.

[0075] 2. Limitations of Small and Medium-Sized Wafers Small and medium-sized wafers (such as 150mm or 200mm wafers) have a relatively small area, and the number of Dies that can be produced on a single wafer is relatively small. For medium and small-scale integrated circuits, the number of Dies may be only a few hundred, far lower than the thousands or even tens of thousands of Dies on large-sized wafers. In this case, the limitations of the randomized sampling detection method are mainly reflected in the following aspects: High missed detection rate: Due to the small number of Dies, the randomized sampling detection may lead to a high missed detection rate. Even by dynamically adjusting the sampling probability, it is difficult to ensure that the missed detection rate is controlled within an acceptable range.

[0076] Limited improvement in testing efficiency: The number of Dies on medium and small-sized wafers is small, and the time cost of individual testing is relatively low. The efficiency improvement brought by randomized sampling inspection is not significant.

[0077] Lack of economy: The production scale of medium and small-sized wafers is small. Although randomized sampling inspection can reduce the number of tests, due to the small total number of Dies, the cost-saving effect is not obvious.

[0078] Therefore, for the testing of medium and small-scale integrated circuits on medium and small-sized wafers, the traditional individual testing method is still a more reliable and efficient choice.

[0079] 3. Limitations of large-scale and very large-scale integrated circuits The Die size of large-scale and very large-scale integrated circuits is usually large, and the number of Dies that can be produced on a single wafer is relatively small. For example, for large-scale integrated circuits, only hundreds of Dies may be cut out on a single wafer. In this case, the limitations of the randomized sampling inspection method are mainly reflected in the following aspects: Unacceptable missed detection rate: Large-scale and very large-scale integrated circuits usually have a high market value, and the failure of a single Die may lead to the failure of the entire system. Therefore, the missed detection rate must be controlled at an extremely low level. Due to the small number of tests, the missed detection rate of the randomized sampling inspection method is high, and it is difficult to meet the testing requirements of large-scale and very large-scale integrated circuits.

[0080] Limited improvement in testing efficiency: Due to the small number of Dies, the time cost of individual testing is relatively low, and the efficiency improvement brought by randomized sampling inspection is not significant.

[0081] Lack of economy: The production cost of large-scale and very large-scale integrated circuits is high, and the failure of a single Die may cause huge economic losses. Therefore, enterprises tend to adopt the individual testing method to ensure that each Die undergoes strict testing and avoid the risk of missed detection.

[0082] In summary, the technical solution of the present invention is mainly applicable to the testing of medium and small-scale integrated circuits on large-sized wafers. On large-sized wafers, due to the large number of Dies, randomized sampling inspection can significantly improve testing efficiency, reduce production costs, and at the same time, by dynamically adjusting the sampling probability, the missed detection rate can be controlled within an acceptable range. However, for medium and small-sized wafers and large-scale and very large-scale integrated circuits, the limitations of the randomized sampling inspection method are obvious, with a high missed detection rate, limited improvement in testing efficiency, and lack of economy, so it is not applicable to these scenarios. Specific implementation manner

[0083] To facilitate the understanding of the present invention, the technical solution of the present invention will be introduced below in combination with specific examples.

[0084] Step S0: After the chips are produced on a wafer of a certain process batch, select one wafer from this batch and detect all Dies in-situ one by one before wafer dicing; According to the above test results, statistically analyze the process reliability of different regions on the wafer. According to the statistical analysis results, initialize the parameters of the controlled parametric randomization function. It should be noted that when initializing the parameters, the initialization principle of the parameters is: For regions with high reliability (high pass rate), set a smaller density of the randomization function, that is, reduce the sampling inspection probability; For regions with low reliability (low pass rate), set a larger density of the randomization function, that is, increase the sampling inspection probability; Meanwhile, if the above statistical results show that there are significant differences in the chip defect density of different regions, and the chip defect density in a certain region or some regions is greater than a certain threshold. For example, the unqualified rate of Dies in a certain edge region of the wafer is higher than 20%, it indicates that there are intolerable defects in this production process, and subsequent inspections can be stopped, and the process parameters can be readjusted or the equipment can be repaired and maintained by returning to the process flow; If the above statistical results show that the chip defect density in each region is generally the same, but the overall Die pass rate is lower than a certain preset threshold. For example, the pass rate of all Dies on this wafer is lower than the preset target pass rate of 90%, it also indicates that there are defects in this production process and it does not meet the expected process target. Similarly, subsequent inspections can be stopped, and the process parameters can be readjusted or the equipment can be repaired and maintained by returning to the process flow; It should be pointed out that the target pass rate here can be determined by the factory according to factors such as the semiconductor production process and the tolerable pass rate in terms of economy. Different process technologies should have different target pass rates, and it is also closely related to market demand. The "unqualified rate higher than 20%" and "preset target pass rate of 90%" mentioned in the above examples are just for illustrative purposes and do not limit the technical solution.

[0085] Of course, in step S0, the following can also be achieved: regular sampling inspection of Dies. Here, regular sampling means sampling Dies at fixed intervals in the horizontal and vertical directions for testing. For example, sampling and testing one every other one, or one every other two, or one every other three. The specific interval selection can be determined according to the number of Dies on each wafer. If the number of Dies is very large, such as tens of thousands of Dies, the interval number can be appropriately increased.

[0086] When the above tests and analyses are completed on the selected wafer, and the Die pass rates in each region are within the acceptable range, then enter the next inspection step: Step S1: Set a controlled parametric randomization function, and the parameters are initialized by step S0; before wafer dicing, sample and detect Dies in-situ according to the controlled parametric randomization function. For example, If after the conventional inspection of all Dies on a certain wafer, the statistical result shows that the pass rate of an edge area is about 96%, denoted as area A; the pass rate of Dies in the remaining areas is higher than 99%, denoted as area B, then a controlled parametric randomization function can be set so that the random sampling probability of area A is 25% and the random sampling probability of area B is 10%.

[0087] Of course, the setting of the random sampling probabilities for different areas here is also just an example. The specific parameter settings can be comprehensively determined according to the tolerable undetected rate of unqualified Dies and the market compensation mechanism. If the requirement for the undetected rate of unqualified Dies is low, the random sampling probability can be appropriately reduced; conversely, it can be appropriately increased. If the market value of the final single integrated circuit product is low and the market compensation ratio is high, the random sampling probability can also be appropriately reduced.

[0088] In the above example, a controlled parametric randomization function can also be set so that the random sampling probability of area A is 40% and the random sampling probability of area B is 15%; or, set the random sampling probability of area A to 30% and the random sampling probability of area B to 5%; or, more strictly, set the random sampling probability of area A to 60% and the random sampling probability of area B to 25%; For another example, if after the conventional inspection of all Dies on a certain wafer, the statistical result is that the pass rate of area A is 97%, the pass rate of Dies in area B is 98%, and the pass rate of Dies in area C is higher than 99%, then a controlled parametric randomization function can be set so that the random sampling probability of area A is 15%, the random sampling probability of area B is 10%, and the random sampling probability of area B is 5%. These values can be selected in accordance with the principle of economy according to actual needs. Here, it is only for illustrative explanation and should not be regarded as a specific limitation 。

[0089] The controlled parametric randomization function can use various randomization functions in the prior art. Each existing programming language contains a pseudo-random function for generating a uniformly distributed random decimal between 0 and 1. In the present invention, the existing random functions can be directly borrowed and appropriately packaged and modified to meet the above requirements.

[0090] For example, the controlled parametric randomization function can be obtained by means of the random function in the Python language. The random function in the Python language can generate a random number uniformly distributed between 0 and 1. As an example: Initialize the input parameters of the controlled parameterized randomization function according to the result of step S0. For example, the yield rate of Dies in area A is about 95%, that is, the failure rate of Dies in this area is 100% - 95% = 5%. Set the random sampling probability of area A to 25%, then the input parameter of the controlled parameterized randomization function can be set to 0.25; when the random number generated by the random function each time is between 0 and 0.25, set the output value of the controlled parameterized randomization function to 1, otherwise the output value is 0. Here, "1" means to detect the current Die, and "0" means not to detect the current Die. Of course, it can also be defined conversely that "1" means not to detect the current Die and "0" means to detect the current Die. The following example shows more clearly the working mechanism / principle of the controlled parameterized randomization function:

[0091] In the present invention, the working mechanism / principle of the controlled parameterized randomization function can be summarized as follows: Since the output value of the built-in random function in the programming language is uniformly distributed between 0 and 1, therefore, when the output value of the random function is between A and B, the output value of the controlled parameterized randomization function is 1, where both A and B are numbers between 0 and 1, and the difference between A and B is the input parameter of the controlled parameterized randomization function. The proportion of the difference between A and B within 0 and 1 is the random sampling probability in the present invention.

[0092] Therefore, in the above table example, it is also possible to set the output value of the controlled parameterized randomization function to 1 when the random number generated by the random function each time is between 0.75 and 1, otherwise the output value is 0.

[0093]

[0094] Of course, it can also be: in the above table example, it is also possible to set the output value of the controlled parameterized randomization function to 1 when the random number generated by the random function each time is between 0.5 and 0.75, otherwise the output value is 0.

[0095] In the previous examples, only a few random number examples were listed. Therefore, the randomization distribution has not fully reflected the distribution characteristics of the controlled parameterized randomization function of the present invention. When the number of rows in the table increases greatly, that is, when the data sample is large enough, its characteristics can naturally be reflected. Of course, this is unnecessary, as the working principle / mechanism has been fully and clearly explained above, and there is no need to waste space here.

[0096] As a further illustration, the following also gives an example of implementing the controlled parameterized randomization function of the present invention using the Python programming language: import random def custom_random(probability): """ Custom randomization function that generates 0 or 1 based on the input probability.

[0097] :param probability: The probability that the result is 1, and the range should be between 0 and 1 (including 0 and 1).

[0098] :return: The output result is 0 or 1.

[0099] """ if not (0<= probability<= 1): raise ValueError("The probability value must be between 0 and 1!") # Generate a random floating point number between 0 and 1 random_value = random.random() # If the random number is less than the input probability, return 1, otherwise return 0 if random_value<probability: return 1 else: return 0 # Test the function if __name__ == "__main__": # Input the probability value input_probability = float(input("Please enter the probability that the result is 1 (between 0 and 1): ")) # Call the custom randomization function result = custom_random(input_probability) print(f"Based on the input probability {input_probability}, the generated result is: {result}") In this way, the predetermined set of Dies to be detected in the designated area can be randomly determined.

[0100] Similarly, the above program code is only an example and does not mean that it must or can only be designed in this way, and shall not be construed as a limitation on the protection scope of the technical solution of the present invention.

[0101] Preferably, after setting the controlled parametric randomization function and determining the set of Dice to be detected in the designated area, verify whether the Dice to be detected in the designated area are too concentrated in location. If they are too concentrated in location, further randomize the Dice to be detected in the designated area to enhance / improve the uniformity of the random distribution of the Dice to be detected.

[0102] The present invention also provides another way to implement the controlled parametric randomization function. That is, in the case where the pass rate / fail rate of the Dice in the designated area and the random sampling probability of the set area A have been determined in the previous steps, it is also possible to pre-calculate the number of Dice to be detected in the designated area according to the number of Dice in the designated area and the random sampling probability of the set area A as the input parameter of the controlled parametric randomization function, and randomly determine the set of Dice to be detected in the designated area through the controlled parametric randomization function.

[0103] Still taking an example mentioned above to explain, if the wafer is pre-divided into five areas A, B, C, D, and E, where the pass rate of the Dice in area A is about 95%, that is, the fail rate of the Dice in this area is 100% - 95% = 5%, and the number of Dice in area A is 400, and the random sampling probability of area A is set to 25%, then the number of Dice to be detected in area A can be calculated as 400×25% = 100.

[0104] Set the input parameters of the controlled parametric randomization function to 400 and 100, and randomly distribute the 100 Dice to be detected among the 400 Dice through the controlled parametric randomization function.

[0105] The division of areas on the wafer can be carried out by the following two methods: First, divide approximately evenly according to the area of the region; In the present invention, two specific division methods can be provided here: a. Taking the center of the wafer as the origin, divide each area of the wafer at equal angles, that is, divide the area at equal angles in polar coordinates; b. Taking the center of the wafer as the origin, divide each area at equal intervals of the abscissa and ordinate, that is, divide the area at equal intervals in the plane rectangular coordinate system; The so-called "approximately uniform" here is actually "uniform", and "approximate" mainly considers the particularity of the wafer edge.

[0106] Second, divide according to the process reliability level of different areas on the wafer obtained by statistical analysis in step S0; For example, it can be divided into two regions, high and low, according to the Die qualification rate in different regions on the wafer; or divided into three regions, high, medium, and low; or divided into five regions, high, relatively high, medium, relatively low, and low.

[0107] As an example, the above function can be implemented as follows: import random def custom_randomize(total_positions, num_to_select): """ Custom randomization function :param total_positions: Total number of positions :param num_to_select: Number of positions to be randomly selected :return: List of randomly selected positions """ if num_to_select>total_positions: raise ValueError("The number of selected positions cannot exceed the total number of positions") # Generate a list from 0 to total_positions - 1 all_positions = list(range(total_positions)) # Randomly select num_to_select positions selected_positions = random.sample(all_positions, num_to_select) return selected_positions # Test the function total_positions = 400 num_to_select = 100 selected_positions = custom_randomize(total_positions, num_to_select) print("Randomly selected positions:", selected_positions) print("Number of randomly selected positions:", len(selected_positions)) In this example, if the number of dies in area A is 400 and the random sampling probability of area A is set to 10%, the number of dies scheduled to be tested in area A can be calculated to be 400×10%=40. The input parameters of the controlled parameter-containing randomization function are set to 400 and 40, and the 40 dies scheduled to be tested are randomly distributed among the 400 dies through the controlled parameter-containing randomization function.

[0108] It is particularly important to point out that no matter which of the above implementations is adopted, the present invention will subsequently map the predetermined die positions to be detected in the determined pointing area to the actual positions of the wafer, so that the test device can detect the corresponding die. This is a routine skill possessed by those skilled in the art and will not be elaborated here.

[0109] After the area is divided, different reward and punishment functions are used in different areas for detection in subsequent steps.

[0110] Step S2: According to the test results of S1, statistically analyze the process reliability of different areas on the wafer.

[0111] Here, it should be noted that, although in step S0, all dies are detected one by one in situ before wafer cutting, and the process reliability of different areas on the wafer is statistically analyzed from the test results, it does not mean that the regional distribution of die reliability of all wafers of the process is completely consistent, because there are random defects and systematic defects, regional and process fluctuations, batch differences, etc. in the semiconductor process, resulting in the reliability of die areas of different wafers being not completely consistent. Since the uniformity of process steps such as lithography, etching, and deposition in the manufacturing process is difficult to fully guarantee, the process conditions in the edge area of ​​the wafer are usually more unstable than those in the center area, resulting in a higher defect density in the edge area. This phenomenon is called the "edge effect". Process fluctuations (such as temperature, gas flow, pressure, etc.) will cause parameters such as film thickness and doping concentration in certain areas of the wafer to deviate from the design values, thereby forming local high defect areas.

[0112] Therefore, in the random sampling of step S1, the distribution of defective dies obtained will be continuously included in the statistical work, the statistical sample size will be expanded, the accuracy of the statistical analysis of process reliability in different areas on the wafer will be continuously improved, and then used to fine-tune the parameters of the controlled parameter-containing randomization function called in the next sampling. That is, enter the next step S3.

[0113] Step S3: adjusting the parameters of the aforementioned randomization function according to the analysis results of step S2, dynamically adjusting the sampling probability of different areas, or dynamically adjusting the division of areas; For example, In step S0, after detecting each Die on a certain wafer one by one, through statistical analysis, it is found that the qualified rate of Dies in some areas is about 97%, and this area is defined as area A; the qualified rate of Dies in the remaining areas is higher than 99%, which is defined as area B. Based on this, the randomized sampling probability of area A is set to 30%, and the randomized sampling probability of area B is set to 10%; Based on the above settings, in step S1, randomized sampling is performed on the next wafer; In step S3, the distribution of defective Dies on this wafer is statistically obtained again, combined with the test results of the previous wafer for statistical analysis, and the overall distribution of defective Dies is obtained. Based on the overall distribution of defective Dies, area A and area B are adjusted / not adjusted; After adjustment, continue to perform randomized sampling on subsequent wafers, and statistically obtain the distribution of defective Dies on the subsequent wafers again. Combine it with the overall test results of the previous wafers, and perform statistical analysis again to obtain the new overall distribution of defective Dies. Based on the new overall distribution of defective Dies, area A and area B are adjusted / not adjusted again; Continue in this way, so that the division of area A and area B is continuously updated and continuously approaches the real situation, becoming more accurate.

[0114] In step S3, in addition to dynamically adjusting the division of areas, the sampling probabilities of different areas can also be dynamically adjusted according to the results of the re - statistical analysis.

[0115] Preferably, the division of areas and the sampling probabilities of different areas can be dynamically adjusted simultaneously.

[0116] Preferably, when the statistical analysis results of the next wafer show that the qualified rate of Dies in the adjacent area of area A has decreased, the range of area A is appropriately expanded; otherwise, the range of area A is appropriately reduced. This helps to detect wafers more accurately and efficiently, and achieve a dynamic balance between detection efficiency and detection accuracy.

[0117] Step S4: After the test of each wafer is completed, return to step S1 to complete the in - situ test of the wafers in the entire production batch one by one; Step S5: Perform wafer dicing and Die packaging according to the test results.

[0118] In step S5, mark the unqualified Dies according to the test results; then perform wafer dicing, and only package the qualified Dies, while the unqualified Dies are discarded.

[0119] In the present invention, different reward and punishment functions are used in the foregoing different areas, and the specific meanings are elaborated as follows: For areas with high reliability (high qualified rate), a smaller randomized function density is set, that is, the sampling probability is reduced; For areas with low reliability (low pass rate), a larger randomization function density is set, that is, the probability of random inspection is increased; After inspecting the next wafer again and combining the statistics to analyze the defective die distribution, if the die pass rate in a certain area increases, the randomization function density of the area is reduced, that is, the sampling probability of the area is reduced; If the Die qualified rate in a certain area decreases, the randomization function density of the area will be increased, that is, the sampling probability of the area will be increased; Optionally, a more specific implementation method is: the randomization function density (spot check probability) can be selected to be in a negative linear proportional relationship with the Die qualified rate in a certain area, that is, the randomization function density (spot check probability) is in a linear proportional relationship with the Die unqualified rate in a certain area.

[0120] That is, the reward and punishment function can be set as follows: randomization function density (sampling probability) = k·Die failure rate, where k is a preset constant coefficient. As a specific example:

[0121] Alternatively, another more specific implementation is: the randomization function density (spot check probability) can be selected to have a nonlinear proportional relationship with the Die failure rate in a certain area, such as a square relationship or an exponential relationship. For example: randomization function density (spot check probability) = k'·Die failure rate 2 , where k' is also a preset constant coefficient.

[0122] As another specific example:

[0123] Obviously, this nonlinear reward and punishment function is intended to implement more stringent sampling measures for areas with increased die rejection rates, that is, to "punish" and monitor the area more strictly, to avoid unqualified dies from entering the next production process as much as possible, and to improve detection accuracy as much as possible. For areas with a high pass rate, they will be "rewarded" to significantly reduce the probability of sampling and improve the detection efficiency of dies on large-size wafers.

[0124] The exponential relationship will not be described in detail here, and those skilled in the art should be able to understand how to implement it based on the above two examples.

[0125] It should be noted that, as can be seen from various embodiments of the present invention, even in areas with a high yield rate of Dies on the wafer, a relatively low randomization function density (sampling probability) is still implemented for them. This is considered based on the characteristics of semiconductor manufacturing processes, that is, semiconductor processes always have random defects. For example, there will still be dust with extremely low concentration and uniform distribution in the air of the clean room, which may cause Die defects on the wafer during the manufacturing process, and the positions of such defects are uniformly distributed and random. In the present invention, maintaining a lower limit of the sampling probability at all times helps to cope with such random defects and reduce the possibility of missed inspections.

[0126] In addition, when the failure rate of Dies in a certain area on the wafer is higher than a certain threshold, one of the following measures can be selected: (1) Detect each Die in this area one by one; (2) Return to the design stage and / or production stage to check for design defects or process defects.

[0127] Specifically, a reasonable choice can also be made according to the actual situation on which method to adopt.

[0128] In mature chip production processes, random defects usually manifest as extremely few and uniformly distributed micro-defects. Such defects are usually caused by factors such as particle contamination, minor equipment malfunctions, or material inhomogeneity during the manufacturing process, and their distribution is random and will not concentrate in a specific area of the wafer. Since the number of these random defects is small and the distribution is uniform, the random sampling detection method can effectively control the missed inspection rate under mature process conditions without having a significant impact on the overall product quality. The following will elaborate in detail from aspects such as technical principles, defect distribution characteristics, and the rationality of sampling detection.

[0129] 1. Characteristics of Random Defects In mature semiconductor production processes, random defects usually have the following characteristics: Small number: Due to the stability of the production process and the high precision of the equipment, the number of random defects is usually very small. For example, on a single wafer, random defects may only affect a very small number of Dies, and even in some cases, there may be no random defects on a single wafer.

[0130] Uniform distribution: The distribution of random defects is usually uniform and will not concentrate in a specific area of the wafer. This means that the probability of each Die being affected by random defects is equal, and there will be no situation where the defect density in some areas is significantly higher than that in other areas.

[0131] Minor impact: Random defects usually manifest as minor electrical performance deviations or functional abnormalities and do not cause the Die to completely fail. Therefore, even if there are a small number of random defects, their impact on the overall product quality is relatively small.

[0132] 2. Technical principle of randomized sampling inspection The randomized sampling inspection method tests some Dies randomly selected on the wafer and infers the process reliability of the entire wafer based on the test results. Its technical principle mainly includes the following aspects: Randomly select test samples: In the present invention, a certain number of Dies are randomly selected on the wafer for testing to ensure that the test samples can represent the process conditions of the entire wafer. Due to the uniform distribution of random defects, the randomly selected test samples can effectively cover all regions on the wafer, thereby reducing the missed inspection rate.

[0133] Statistically analyze process reliability: According to the test results, statistically analyze the process reliability of different regions on the wafer. By calculating the qualified rate and unqualified rate of each region, the process conditions of the entire wafer can be inferred, and the high-defect regions that may exist can be identified.

[0134] Dynamically adjust the sampling probability: According to the statistical analysis results, dynamically adjust the sampling probability of different regions. For regions with high reliability (high qualified rate), reduce the sampling probability and decrease the test frequency; for regions with low reliability (low qualified rate), increase the sampling probability and increase the test frequency. This dynamic adjustment strategy can effectively reduce the missed inspection rate and ensure product quality.

[0135] 3. Rationality of randomized sampling inspection In mature chip production processes, the rationality of the randomized sampling inspection method is mainly reflected in the following aspects: Controllable missed inspection rate: Due to the small number and uniform distribution of random defects, the randomized sampling inspection method can control the missed inspection rate at an extremely low level. For example, through reasonable sampling ratios and dynamic adjustment strategies, the missed inspection rate can be reduced to one in a million or even lower, far lower than the unqualified rate of traditional one-by-one testing methods.

[0136] High test efficiency: The randomized sampling inspection method only needs to test some Dies, which can significantly reduce the number of tests, shorten the test time, and improve the test efficiency. Especially on large-sized wafers with a large number of Dies, the efficiency advantage of the randomized sampling inspection method is particularly obvious.

[0137] Significant cost-effectiveness: Due to the reduction in the number of tests, the usage time and frequency of test equipment are significantly reduced, thereby reducing equipment depreciation, maintenance costs, and labor costs. At the same time, the substantial shortening of the test time also reduces the production time cost and improves the economic benefits of the enterprise.

[0138] 4. Relationship between Defect Distribution and Sampling Inspection In a mature chip production process, the defect distribution usually has certain regularity. The uniformity of the distribution of random defects provides a theoretical basis for randomized sampling inspection. Specifically: Random defects with uniform distribution: Since random defects are uniformly distributed, randomly selected test samples can effectively cover all regions on the wafer, thus ensuring the representativeness of test results. Even if there are a small number of random defects, the randomized sampling inspection method can infer the process status of the entire wafer through statistical analysis and reduce the missed inspection rate.

[0139] Identification of regional defects: Although random defects are uniformly distributed, in some cases, there may be regional defects on the wafer (such as edge effects or local high-defect regions caused by process fluctuations). By dynamically adjusting the sampling probability, the randomized sampling inspection method can effectively identify these regional defects and increase the test frequency in these regions, thereby further reducing the missed inspection rate.

[0140] In summary, in a mature chip production process, random defects usually have a small number, are uniformly distributed, and have little impact. Therefore, the randomized sampling inspection method can effectively control the missed inspection rate without significantly affecting the overall product quality. By randomly selecting test samples, statistically analyzing process reliability, and dynamically adjusting the sampling probability, the randomized sampling inspection method not only ensures test accuracy but also significantly improves test efficiency and reduces production costs. This technical principle makes the randomized sampling inspection method of the present invention have broad application prospects in mature semiconductor production processes.

[0141] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. The content not detailedly described in this specification belongs to the prior art well-known to those skilled in the art.

Claims

1. An in-situ test method for medium and small scale integrated circuit Dies on large-sized wafers, characterized in that It includes the following steps: S1: Set a controlled parametric randomization function, and sample and test Dies in-situ according to the aforementioned randomization function before wafer dicing; S2: According to the test results in S1, statistically analyze the process reliability of different regions on the wafer; S3: Adjust the parameters of the aforementioned randomization function according to the analysis results in S2, dynamically adjust the sampling probabilities of different regions, and / or dynamically adjust the division of regions; S4: After the test of each wafer is completed, return to step S1 to complete the in-situ test of the wafers in the entire production batch one by one; S5: Perform wafer dicing and package Dies according to the test results; Preferably, the number of Dies distributed on one wafer reaches more than one thousand; More preferably, the number of Dies distributed on one wafer reaches more than ten thousand.

2. The test method according to claim 1, wherein: In S5, mark the unqualified Dies according to the test results; then perform wafer dicing, and only package the qualified Dies, and discard the unqualified Dies.

3. The test method according to claim 1, characterized in that: Before S1, there is also step S0: S0: Regularly sample and test Dies in-situ before wafer dicing; or, Individually test all Dies in-situ before wafer dicing; According to the test results, statistically analyze the process reliability of different regions on the wafer, and initialize the parameters of the controlled parametric randomization function according to the statistical analysis results.

4. The test method according to claim 3, characterized in that: The regular sampling refers to sampling and testing Dies at fixed intervals in the horizontal and vertical directions; optionally, sample and test one every other one, or sample and test one every two, or sample and test one every three, and so on.

5. The test method according to claim 3, wherein: If the statistical results in step S0 show that there are significant differences in the chip defect densities of different regions, and the chip defect density of a certain region or certain regions is greater than a certain threshold, it indicates that there are intolerable defects in the production process, stop the subsequent tests, and return to the process flow to re-adjust the process parameters or repair the equipment; If the statistical results in step S0 show that the chip defect densities of all regions on the wafer are generally the same, but the overall Die qualification rate is lower than a preset threshold, it indicates that there are defects in the production process and it does not meet the expected process target, then stop the subsequent tests, and return to the process flow to re-adjust the process parameters or repair the equipment.

6. The test method according to claim 1, wherein: The Die test content includes electrical performance and logic function to ensure that the Dies meet the design requirements.

7. The test method according to claim 1, characterized in that: In step S2, the division of regions on the wafer adopts one of the following two methods: (1) Divide approximately evenly according to the regional area; (2) Divide regions according to the process reliability levels of different regions on the wafer obtained from the statistical analysis in step S0.

8. The testing method according to claim 7, characterized in that: Dividing approximately evenly according to the regional area is based on one of the following two methods: a. Taking the wafer center as the origin, equally divide the regions of the wafer at equal angles, that is, divide the regions at equal angles in polar coordinates; b. Taking the wafer center as the origin, equally divide each region at equal intervals in the abscissa and ordinate, that is, divide the regions at equal intervals in the plane rectangular coordinates.

9. The test method according to claim 7, wherein: Dividing regions according to the process reliability level of different regions on the wafer means dividing them into two regions, high and low, according to the Die qualification rate of different regions on the wafer; or dividing them into three regions, high, medium, and low; or dividing them into five regions, high, relatively high, medium, relatively low, and low.

10. The test method according to claim 1, wherein: In step S3, the sampling inspection strategy is dynamically adjusted by setting a reward and punishment function: Punishment: For regions with high reliability (high qualification rate), set a smaller density of the randomization function, that is, reduce the sampling inspection probability; Reward: For regions with low reliability (low qualification rate), set a larger density of the randomization function, that is, increase the sampling inspection probability.

11. The test method according to claim 10, characterized in that: Optionally, select that the density of the randomization function (sampling inspection probability) is in a negative linear proportional relationship with the Die qualification rate in a certain region, that is, the density of the randomization function (sampling inspection probability) is in a linear proportional relationship with the Die unqualified rate in a certain region; that is, set the reward and punishment function as follows: density of the randomization function (sampling inspection probability) = k·Die unqualified rate, where k is a preset constant coefficient; Optionally, the density of the randomization function (sampling probability) is selected to be non-linearly proportional to the defective rate of Dies within a certain area, such as a square relationship or an exponential relationship; optionally: density of the randomization function (sampling probability) = k' · defective rate of Dies 2 , where k' is a preset constant coefficient.

12. The test method according to claim 1, characterized in that: In step S3, the distribution status of defective Dies on the current wafer is statistically obtained again, combined with the test results of the previous wafer for statistical analysis, and the overall distribution status of defective Dies is obtained. Based on the overall distribution status of defective Dies, the region division is adjusted / not adjusted; After adjustment, continue to perform random sampling inspection on subsequent wafers. The distribution status of defective Dies on the subsequent wafers is statistically obtained again, combined with the overall test results of the previous wafers, and statistically analyzed again to obtain the new overall distribution status of defective Dies. Based on the new overall distribution status of defective Dies, the region is adjusted / not adjusted again; and so on continuously.

13. The test method according to claim 1, characterized in that: In step S3, the distribution status of defective Dies on the current wafer is statistically obtained again, and the sampling inspection probabilities of different regions are dynamically adjusted; Preferably, the region division is dynamically adjusted and the sampling inspection probabilities of different regions are dynamically adjusted at the same time; Preferably, when the statistical analysis result of the next wafer shows that the Die qualification rate in the adjacent area of a certain region has decreased, appropriately expand the scope of this region; otherwise, appropriately narrow the scope of this region.

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