Preparation method of metal interconnection structure and semiconductor device

Abstract

The invention provides a preparation method of a metal interconnection structure and a semiconductor device, and the preparation method comprises the following steps: providing a substrate which comprises a base, a semiconductor layer on the base, a plurality of contact holes formed in the semiconductor layer, and first conductive media in the contact holes; sequentially forming an etching stop layer, a sacrificial layer and an intermetallic dielectric layer on the surface of the substrate; the substrate is etched to form a plurality of grooves, the grooves extend to the surface of the substrate, and the projections of the grooves on the surface of the substrate cover the projections of the contact holes on the surface of the substrate; filling a second conducting medium in the groove; and planarizing the surface of the substrate and treating the substrate by adopting an annealing process, wherein the sacrificial layer is decomposed in the annealing process to form an air gap layer. According to the preparation method of the metal interconnection structure, the dielectric constant of the metal interconnection structure is reduced through the air gap layer, so that the capacitance coupling effect between the metal connecting wires is further reduced, the signal transmission resistance-capacitance delay is reduced, and the overall performance of a semiconductor chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices. Specifically, it relates to a method for manufacturing a metal interconnect structure and a semiconductor device. Background Art

[0002] In the continuous miniaturization process of semiconductor devices, the metal connection layer, as the core structure for signal transmission and device interconnection in integrated circuits, its design and manufacturing technology directly determine the performance and reliability of the devices. As the process node advances to the nanoscale, there are more and more metal wires per unit area, and the spacing between metal wires continues to shrink. When the metal wire spacing is reduced to the nanoscale (such as the 1nm node), the resistivity of copper-based interconnect materials increases significantly, leading to an exacerbation of the resistance-capacitance (RC) delay problem. In nodes below 10nm, the power consumption of the interconnect layer already accounts for one-third of the total chip power consumption, and the RC delay contribution is as high as 75%. At the same time, under high-density interconnection, the capacitive coupling effect between adjacent metal wires is enhanced, resulting in signal crosstalk and increased power consumption. The existing use of low-dielectric-constant materials to form the interlayer dielectric can effectively reduce the distributed capacitance between interconnect wires, thereby improving the overall performance of the chip. However, the mechanical strength of low-dielectric-constant (low-k) materials is insufficient, further exacerbating the structural stability problem and prone to generating crack or delamination defects during the manufacturing process. The purpose of the present invention is to develop a method for manufacturing a metal interconnect structure to reduce the coupling capacitance between metal wires in the metal interconnect structure, thereby improving the performance of the manufactured semiconductor device.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those skilled in the art. Summary of the Invention

[0004] Aiming at the problems in the prior art, the purpose of the present invention is to provide a method for manufacturing a metal interconnect structure and a semiconductor device. This manufacturing method reduces the dielectric constant of the metal interconnect structure through an air gap layer to further reduce the capacitive coupling effect, lower the signal transmission resistance-capacitance delay, and improve the overall performance of the semiconductor chip.

[0005] Specifically, the first aspect of the present invention provides a method for manufacturing a metal interconnect structure, and the manufacturing method includes the following steps:

[0006] Provide a substrate, where the substrate includes a base, a semiconductor layer on the base, a plurality of contact holes formed in the semiconductor layer, and a first conductive medium in the contact holes;

[0007] Form an etch stop layer, a sacrificial layer, and an intermetal dielectric layer on the surface of the substrate in sequence;

[0008] Etch the substrate to form a plurality of trenches, the trenches extending to the surface of the semiconductor layer, and the projection of the trenches on the surface of the substrate covering the projection of the contact holes on the surface of the substrate;

[0009] Fill a second conductive medium in the trenches;

[0010] Planarize the surface of the substrate and treat the substrate with an annealing process. During the annealing process, the sacrificial layer decomposes to form an air gap layer.

[0011] According to the first aspect of the present invention, the material of the etch stop layer is selected from at least one of nitrogen-doped silicon carbide, silicon carbide, and silicon nitride.

[0012] According to the first aspect of the present invention, the material of the sacrificial layer is a thermally decomposable polymer.

[0013] According to the first aspect of the present invention, the material of the sacrificial layer is selected from one or more of polylactic acid, poly(lactic-co-glycolic acid), polycarbonate, polystyrene, polymethyl methacrylate, and polyvinyl alcohol.

[0014] According to the first aspect of the present invention, the sacrificial layer is prepared by a spin coating process.

[0015] According to the first aspect of the present invention, the thickness of the sacrificial layer is between 100 Å and 200 Å.

[0016] According to the first aspect of the present invention, the deposited intermetal dielectric layer is one or a combination of multiple layers of a silicon dioxide layer, a fluorine-doped silicon dioxide layer, or a silicon nitride layer.

[0017] According to the first aspect of the present invention, the temperature in the annealing process is between 200 °C and 500 °C;

[0018] The time of the annealing process is 3 minutes to 60 minutes.

[0019] According to the first aspect of the present invention, filling the second conductive medium in the trenches includes the following steps:

[0020] Deposit a TaN / Ta layer on the sidewalls of the trenches;

[0021] Fill a metal layer in the trenches.

[0022] The second aspect of the present invention provides a semiconductor device, the semiconductor device including a metal interconnect structure electrically connected to a plurality of contact holes, and the metal interconnect structure is obtained by using the preparation method described in the first aspect.

[0023] Compared with the prior art, in the method for preparing the metal interconnect structure of the present invention, a polymer (thermal degradable polymer) that decomposes at a certain temperature is added as a sacrificial layer between the intermetal dielectric layer and the substrate. An air gap layer is formed at the sacrificial layer and removed by an annealing process in a subsequent step, thereby effectively reducing the dielectric constant of the metal interconnect structure, further reducing the capacitive coupling effect between metal wires in the metal interconnect structure, reducing the signal transmission resistance-capacitance (RC) delay, and improving the overall performance of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into and form a part of this specification, showing embodiments consistent with the present application, and are used in conjunction with the specification to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present invention will become more apparent. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0025] Figure 1 is a flowchart of the method for preparing the metal interconnect structure according to an embodiment of the present invention; and

[0026] Figures 2 to 5 is a schematic structural diagram of a substrate corresponding to each step in the preparation process of the metal interconnect structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The following specific examples illustrate the embodiments of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed herein. The present invention can also be implemented or applied through other different specific embodiments, and various details of the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0028] The following will describe the embodiments of the present invention in detail with reference to the drawings, so that those skilled in the art of the present invention can easily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0029] In the description of the present invention, the references to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics represented in connection with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials, or characteristics represented can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples represented in the present invention and the features of different embodiments or examples.

[0030] In order to clearly illustrate the present invention, devices irrelevant to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0031] Throughout the specification, when it is said that a device is "connected" to another device, this includes not only the case of "direct connection", but also the case of "indirect connection" with other elements interposed therebetween. In addition, when it is said that a certain device "includes" a certain constituent element, unless there is a particularly contrary record, it does not exclude other constituent elements, but means that other constituent elements can also be included.

[0032] When it is said that a device is "on" another device, this can be directly on the other device, but there can also be other devices therebetween. When it is said that a device is "directly" "on" another device by contrast, there are no other devices therebetween.

[0033] Although in some instances the terms first, second, etc. are used herein to denote various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first interface and a second interface, etc. are represented. Furthermore, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or meaning any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition only occurs when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0034] The technical terms used herein are only for referring to specific embodiments and are not intended to limit the present invention. The singular forms used herein also include the plural forms as long as the context does not clearly indicate the contrary meaning. The meaning of "including" used in the specification is to embody specific features, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other features, regions, integers, steps, operations, elements and / or components.

[0035] Although not defined differently, all terms, including the technical terms and scientific terms used herein, have the same meaning as generally understood by those skilled in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries are additionally interpreted to have meanings consistent with the relevant technical literature and the content presented currently. As long as they are not defined, they shall not be over-interpreted as ideal or overly formulaic meanings.

[0036] The following further elaborates the preparation method of the metal interconnect structure and the semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. It can be understood that each specific embodiment does not limit the protection scope of the present invention.

[0037] The present invention provides a method for preparing a metal interconnect structure. Figure 1 It is a flowchart of the method for preparing the metal interconnect structure according to an embodiment of the present invention. Specifically, the preparation method includes the following steps:

[0038] Step S100: Provide a substrate 10, where the substrate 10 includes a base, a semiconductor layer on the base, a plurality of contact holes 11 formed in the semiconductor layer, and a first conductive medium in the contact holes 11; the base can be an N-type doped or P-doped silicon wafer, and the doping concentration and thickness depend on the target performance of the semiconductor device. The semiconductor layer can be set according to the structure of the target semiconductor device. For example, the semiconductor layer of an Insulated Gate Bipolar Transistor (IGBT) includes a first-type conductive carrier storage layer, a second-type conductive well region layer, a first-type conductive emitter layer, and a gate trench structure therein, etc. The contact holes 11 are arranged between the gate trench structures, and the contact holes 11 extend in the thickness direction of the substrate 10 to the well region layer. After the contact holes 11 are filled with the first conductive medium, contact plugs electrically connected to the well region layer are formed. The first conductive medium can be an alloy of one or more combinations of tungsten (W), aluminum (Al), titanium (Ta), titanium nitride (TaN), cobalt (Co), nickel (Ni), nickel silicide SiNi, molybdenum (Mo), silver (Ag), or gold (Au).

[0039] Step S200: Sequentially form an etch stop layer 20, a sacrificial layer 30, and an intermetal dielectric layer 40 on the surface of the substrate 10, as shown in Figure 2As shown. The etch stop layer 20 can be formed by chemical vapor deposition. The material of the etch stop layer 20 is selected from at least one of silicon carbonitride SiCN doped with nitrogen, silicon carbide SiC, and silicon nitride Si3N4. That is, the etch stop layer 20 can be a single-layer structure or a multi-layer structure. For example, the etch stop layer 20 can be a single layer of silicon carbide SiC, or a stack including, for example, a silicon nitride Si3N4 layer and a silicon carbonitride SiCN layer doped with nitrogen, etc. The thickness of the etch stop layer 20 can be between 300 angstroms and 500 angstroms, such as a 300-angstrom SiCN etch stop layer.

[0040] The material of the sacrificial layer 30 in step S200 is a thermally decomposable polymer, that is, this type of polymer is a high-molecular material that undergoes chemical decomposition under specific temperatures or thermal conditions. Further, the material of the sacrificial layer 30 is selected from one or more of polylactic acid (PLA), poly(lactic-co-glycolic acid) (PLGA), polycarbonate (PC), polystyrene (PS), polymethyl methacrylate (PMMA), and polyvinyl alcohol (PVA). That is, the sacrificial layer 30 can be a single layer. For example, the sacrificial layer 30 is a polylactic acid layer with a thickness of 100 angstroms to 200 angstroms, or it can also be a stacked structure including multiple polymer layers. The decomposition conditions of different thermally decomposable polymers, such as decomposition temperature, time, etc., are different. For example, the thermal decomposition temperature of polylactic acid PLA is 200 - 300 °C, and it decomposes through random chain scission or depolymerization reactions at the decomposition temperature, and the final decomposition products are carbon dioxide and water; the thermal decomposition temperature of polyvinyl alcohol PVA is 200 - 250 °C, and it decomposes to produce water, acetic acid, carbon dioxide, etc. The sacrificial layer 30 can be prepared by a spin coating process. Specifically, the high-molecular polymer solution can be evenly dropped at the center position of the substrate through a pipette or a dropper, and the substrate is rotated to make the high-molecular polymer solution diffuse towards the edge of the substrate under the action of centrifugal force to form a preliminary liquid film; then the film is cured by processes such as heating or ultraviolet irradiation. The parameters of the spin coating process, such as the rotation speed or rotation time, etc., can be determined according to the material and thickness of the target sacrificial layer to be obtained. Of course, after the spin coating process, the cured film can also be planarized to obtain the sacrificial layer 30 with the target thickness.

[0041] The dielectric constant k of the intermetal dielectric layer used and the resistance of the interconnect metal jointly determine the RC delay performance of chip transmission. Using low dielectric constant materials is of great significance for reducing the RC delay of chips. Therefore, the intermetal dielectric layer 40 is a low dielectric constant (Low-K) dielectric layer. For example, the intermetal dielectric layer 40 can be one or a combination of multiple layers of a silicon dioxide layer, a fluorine-doped silicon dioxide layer, or a silicon nitride layer. The intermetal dielectric layer 40 can be prepared by plasma-enhanced chemical vapor deposition process. In actual operation, a target low dielectric constant (Low-K) intermetal dielectric layer and its mechanical strength can be adjusted by controlling the parameters of the plasma-enhanced chemical vapor deposition process, the percentage content of reaction gases, and the selection of precursors. Preferably, the thickness of the intermetal dielectric layer 40 can be ~1000 angstroms. Preferably, the thickness of the sacrificial layer 30 is about 20% of the thickness of the intermetal dielectric layer 40.

[0042] Step S300: Etch the substrate to form a plurality of trenches C. The trenches C extend to the surface of the semiconductor layer, that is, the trenches C penetrate through the intermetal dielectric layer 40, the sacrificial layer 30, and the etch stop layer 20, as shown in Figure 3 the figure. Step S300 can be specifically carried out by depositing a hard mask layer, then coating a photoresist layer on the surface of the hard mask layer, exposing and developing the photoresist layer to form a patterned photoresist layer, and then using the photoresist pattern as a mask layer to etch the hard mask layer, the intermetal dielectric layer 40, the sacrificial layer 30, and the etch stop layer 20 to form trenches C by a dry etching process, such as a reactive ion etching (ReacTave Ion Etch, RIE) process. The reaction gases that can be selected in the reactive ion etching process include mixed gases such as CF4 and CHF3. The energy of the plasma in the reactive ion etching process is relatively large and the gas density is relatively low. The etching of the film layer is promoted by the physical bombardment of the charged ions on the surface of the film layer to be etched. That is to say, the etching mainly occurs in the direction perpendicular to the surface of the film layer to be etched. In this way, the sidewalls of the etched trenches (vias) are close to vertical or have a slope of less than 90°. The width of the trenches C can be set according to the structure or performance of the semiconductor device to be fabricated.

[0043] Step S400: Fill the second conductive medium in the trenches C. Since the second conductive medium filled in the trenches C needs to form an electrical connection with the first conductive medium in the contact holes 11, the projection of the trenches C formed in step S300 on the surface of the substrate covers the projection of the contact holes 11 on the surface of the substrate. The width of the contact holes 11 can be ~90 nm. For example, the projection of the trenches C on the surface of the substrate completely covers the projection of the contact holes 11 on the surface of the substrate. Preferably, the width of the trenches C can be ~100 nm.

[0044] In order to improve the filling quality of the second conductive medium and the electrical performance after filling, in some embodiments, step S400 includes the following steps;

[0045] Step S410: Deposit a TaN / Ta layer 51 on the sidewalls of trench C;

[0046] Step S420: Fill trench C with a metal layer 50 on the sidewalls where the TaN / Ta layer is deposited, as shown, that is, the second conductive medium layer can be a coaxial multi-layer structure, and the material of the metal layer 50 can be copper Cu. Figure 4 Shown, that is, the second conductive medium layer can be a coaxial multi-layer structure, and the material of the metal layer 50 can be copper Cu.

[0047] After the conductive filling of trench C is formed, step S500 is performed: The substrate surface is planarized by processes such as Chemical Mechanical Polishing (CMP), and the substrate is treated by an annealing process. During the annealing process, the sacrificial layer 30 decomposes to form an air gap layer 60, as shown. The annealing process parameters of the sacrificial layer 30 made of different materials are different. In order to ensure that the annealing process does not affect the performance of the semiconductor device, preferably, the following conditions are met when the substrate is treated by the annealing process: Figure 5 Shown. The annealing process parameters of the sacrificial layer 30 made of different materials are different. In order to ensure that the annealing process does not affect the performance of the semiconductor device, preferably, the following conditions are met when the substrate is treated by the annealing process:

[0048] The temperature in the annealing process is between 200°C and 500°C;

[0049] The time of the annealing process is 3 minutes to 60 minutes.

[0050] For example, when the sacrificial layer 3 is a polylactic acid layer with a thickness of 150 angstroms, the temperature of the annealing process is 250°C, and the annealing time is 5 minutes. Among them, for the annealing chamber, gases such as Ar can be introduced to carry out the decomposition products of polylactic acid out of the reaction chamber.

[0051] After the sacrificial layer 30 of the substrate in step S500 decomposes to form the air gap layer 60, the etch stop layer 20 and the inter-metal dielectric layer 40 are connected through the filling of trench C, and a parallel plate capacitor structure is formed between the etch stop layer 20 and the inter-metal dielectric layer 40. According to the calculation formula of the capacitance C of the parallel plate capacitor C = εA / d, where ∈ is the dielectric constant, A is the plate area, and d is the distance between the plates, that is, the thickness of the air gap layer 60. When the medium between the plates is air, the dielectric constant ∈ of air is relatively small and approximately constant. When the plate area A is constant, the larger the thickness d of the air gap layer 60, the smaller the capacitance C; conversely, the smaller the thickness of the air gap layer 60, the larger the capacitance C. In actual use, the thickness of the air gap layer 60 (i.e., the sacrificial layer 30) can be designed according to the structure and performance of the target semiconductor device.

[0052] The preparation method of the metal interconnect structure of the present invention adds a polymer that decomposes at a certain temperature between the intermetal dielectric layer and the substrate as a sacrificial layer, and then removes it through an annealing process to form an air gap layer at the sacrificial layer, thereby effectively reducing the dielectric constant of the metal interconnect structure, further reducing the capacitive coupling effect between the metal wires in the metal interconnect structure, reducing the signal transmission resistance-capacitance delay, and improving the overall performance of the semiconductor chip.

[0053] The present invention also provides a semiconductor device, which includes a metal interconnect structure electrically connected to a plurality of contact holes, and the metal interconnect structure is obtained by using the above preparation method. The semiconductor device can be a metal-oxide-semiconductor field effect transistor (MOSFET), where the contact holes connect the source, drain, and the metal interconnect structure; it can be a bipolar junction transistor (BJT), where the contact holes connect the emitter, base, and collector to the metal interconnect structure; it can be a capacitor, where the contact holes connect the electrode to the metal interconnect structure; or it can be a power device, where the contact holes connect the gate, emitter, and collector to the metal interconnect structure. And so on, which will not be elaborated here. The distributed capacitance between the metal wires in the metal interconnect structure of the present invention is reduced, and the semiconductor device has better performance.

[0054] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0055] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for preparing a metal interconnect structure, characterized in that, The preparation method includes the following steps: Provide a substrate, which includes a base, a semiconductor layer on the base, a plurality of contact holes formed in the semiconductor layer, and a first conductive medium in the contact holes; Form an etch stop layer, a sacrificial layer, and an intermetallic dielectric layer on the surface of the substrate in sequence; Etch the substrate to form a plurality of trenches, the trenches extending to the surface of the semiconductor layer, and the projection of the trenches on the surface of the substrate covering the projection of the contact holes on the surface of the substrate; Fill a second conductive medium in the trenches; Planarize the surface of the substrate and subject the substrate to an annealing process. During the annealing process, the sacrificial layer decomposes to form an air gap layer.

2. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The material of the etch stop layer is selected from at least one of silicon carbide doped with nitrogen, silicon carbide, and silicon nitride.

3. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The material of the sacrificial layer is a thermally decomposable polymer.

4. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The material of the sacrificial layer is selected from one or more of polylactic acid, poly(lactic-co-glycolic acid), polycarbonate, polystyrene, polymethyl methacrylate, and polyvinyl alcohol.

5. The manufacturing method of the metal interconnect structure according to claim 1, wherein, The sacrificial layer is prepared by a spin coating process.

6. The manufacturing method of the metal interconnect structure according to claim 1, wherein The thickness of the sacrificial layer is between 100 Å and 200 Å.

7. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The deposited intermetallic dielectric layer is one or a combination of multiple layers of a silicon dioxide layer, a fluorine-doped silicon dioxide layer, or a silicon nitride layer.

8. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The temperature in the annealing process is between 200°C and 500°C; The time of the annealing process is 3 minutes to 60 minutes.

9. The manufacturing method of the metal interconnect structure according to claim 1, characterized in that, The step of filling a second conductive medium in the trenches includes the following steps: Deposit a TaN / Ta layer on the sidewalls of the trenches; Fill a metal layer in the trenches.

10. A semiconductor device, characterized in that, The semiconductor device includes a metal interconnect structure electrically connected to a plurality of contact holes, and the metal interconnect structure is obtained by using the preparation method according to any one of claims 1 to 9.

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