Structures including dipole-lined conductive wires and related systems and methods

Abstract

Methods and related structures and systems for suppressing electromigration in back-end-of-line metal lines in integrated circuits. An embodiment of the structure of the present disclosure includes a dipole liner including a dipole between an electrically conductive line and a low-k dielectric.

Description

Technical Field

[0001] The subject matter of the present disclosure relates to the field of integrated circuit manufacturing, particularly to the middle and back-end process handling in integrated circuit manufacturing. Background Art

[0002] Current back-end-of-line (BEOL) metal vias and lines suffer from electromigration over time, where electrons will escape through the low-k dielectric (LK) and cause dielectric breakdown on the device. A barrier metal can be employed between the LK and copper (Cu) in order to reduce / slow down the electromigration effect and improve the lifetime of the device.

[0003] Tantalum nitride (TaN) liners are used to improve Cu adhesion on LK and reduce electromigration and Cu migration effects. The main limitation of these is related to the thickness and thus the impact of the resistivity on the Cu lines. As the via size decreases, for the same liner size, the space for Cu will proportionally become less and less, since TaN must have a minimum thickness of 1 - 2 nm in order to maintain a sufficiently low resistivity and sufficiently good barrier properties.

[0004] Part of the solution to this problem is to use 2D materials as barriers, but they bring other challenges, such as adhesion (due to the inert behavior of 2D materials), the need for good quality growth of 2D materials across the entire wafer, and selective growth of the 2D layer within the via.

[0005] Therefore, there is still a need for improved barriers for metal lines and vias. Summary of the Invention

[0006] A structure including a conductive wire embedded in a low-k dielectric is described herein, where the conductive wire is surrounded by the low-k dielectric and separated from the low-k dielectric by means of a dipole liner including dipoles.

[0007] In some embodiments, the structure further includes a semiconductor wafer, where the conductive wire includes a planar portion and a lateral portion, the planar portion being substantially parallel to the semiconductor wafer, and the lateral portion being substantially perpendicular to the semiconductor wafer.

[0008] In some embodiments, the dipoles have a dipole moment pointing from the conductive wire towards the low-k dielectric.

[0009] In some embodiments, the dipole liner includes rare earth elements.

[0010] In some embodiments, the rare earth elements include at least one of lanthanum, scandium, and yttrium.

[0011] In some embodiments, the dipole liner includes rare earth element oxides.

[0012] In some embodiments, the rare earth element oxide is selected from La2O3, Sc2O3, and Y2O3.

[0013] In some embodiments, the dipole lining includes metal nitrides.

[0014] In some embodiments, the dipole lining includes post-transition metal nitrides.

[0015] In some embodiments, the post-transition metal nitride includes gallium nitride oxide.

[0016] In some embodiments, the dipole lining has a uniform thickness.

[0017] In some embodiments, the structure further includes a conductive lining, wherein the conductive lining is located between the conductive wire and the dipole lining.

[0018] In some embodiments, the conductive lining contains transition metal nitrides.

[0019] In some embodiments, the transition metal nitride includes tantalum nitride.

[0020] In some embodiments, the conductive lining includes a 2D material.

[0021] In some embodiments, the 2D material includes transition metal dichalcogenides.

[0022] Further described herein is a structure including a dipole lining that includes dipoles, the dipole lining separating a conductive wire from a low-k dielectric.

[0023] Further described herein is a method of forming a structure, the method including the step of providing a substrate to a reaction chamber, the substrate including a low-k dielectric, the method further including the step of forming a dipole lining including dipoles on the low-k dielectric.

[0024] In some embodiments, the dipole lining is formed by atomic layer deposition.

[0025] In some embodiments, the structure is the structure as described herein.

[0026] The present invention content is provided to introduce a selection of concepts in a simplified form. These concepts are further described in detail in the following detailed description of exemplary embodiments of the present disclosure. The present invention content is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 、 Figure 2 and Figure 3 illustrate embodiments of a structure according to embodiments of the present disclosure.

[0028] Figure 4 and Figure 5 illustrates an embodiment of a method according to the present disclosure.

[0029] Figure 6 illustrates an embodiment of a system according to the present disclosure.

[0030] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. Detailed Description

[0031] Although certain embodiments and examples are disclosed below, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments and / or uses of the invention and its obvious modifications and equivalents. Accordingly, it is intended that the scope of the disclosed invention not be limited by the specific disclosed embodiments described below.

[0032] As used herein, the term "substrate" may refer to any one or more underlying materials, including any one or more underlying materials that can be modified or on which devices, circuits, or films can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous; and combinations thereof. A substrate can be in any form, such as a powder, a plate, or a workpiece. A plate-like substrate can include wafers of various shapes and sizes. A substrate can be made of semiconductor materials, including, for example, silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide.

[0033] As an example, a substrate in powder form can have applications in pharmaceutical manufacturing. A porous substrate can include polymers. Examples of workpieces can include medical devices (such as stents and syringes), jewelry, tooling devices, components for battery manufacturing (such as anodes, cathodes, or separators), or components of photovoltaic cells, etc.

[0034] A continuous substrate can extend beyond the boundaries of a processing chamber in which a deposition process takes place. In some processes, a continuous substrate can move through the processing chamber such that the process continues until the end of the substrate is reached. A continuous substrate can be supplied from a continuous substrate feeding system to allow for the manufacture and output of the continuous substrate in any suitable form.

[0035] Non-limiting examples of continuous substrates can include sheets, non-woven membranes, rolls, foils, meshes, flexible materials, a bundle of continuous filaments or fibers (such as ceramic fibers or polymer fibers). A continuous substrate can also include a carrier or sheet on which a discontinuous substrate is mounted.

[0036] The term "cyclic deposition process" or "cyclic deposition process" can refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include an ALD component and a cyclic CVD component. In a preferred embodiment, the cyclic deposition method as disclosed herein refers to an atomic layer deposition method.

[0037] The term "atomic layer deposition" can refer to a vapor deposition process in which deposition cycles are carried out in a processing chamber, typically a plurality of consecutive deposition cycles. The term atomic layer deposition as used herein is also intended to include processes designated by related terms, such as chemical vapor atomic layer deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy when carried out using alternating pulses of precursor / reactant gas and purge gas (e.g., an inert carrier gas). In fact, the purge can separate subsequent pulses by intermittently exposing the substrate to the purge gas. In some embodiments, each pulse is followed by a purge with the purge gas. Suitable purge gases include inert or substantially inert gases. In some embodiments, the purge gas includes one or more of N2 and noble gases. Suitable noble gases include He, Ne, Ar, Kr, and Xe.

[0038] Typically, for an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbs onto the deposition surface (e.g., a substrate surface that may include previously deposited material from a previous ALD cycle or other material) and forms a material, such as a monolayer or sub-monolayer of material, or several monolayers of material, or multiple monolayers of material, which does not readily react with additional precursor (i.e., self-limiting reaction). Thereafter, in some cases, a reactant (e.g., another precursor or reaction gas) can subsequently be introduced into the processing chamber for converting the chemisorbed precursor into the desired material on the deposition surface. The reactant can be capable of further reacting with the precursor. During one or more cycles, e.g., during each step of each cycle, a purge step can be used to remove any excess precursor from the processing chamber and / or any excess reactant and / or reaction by-products from the reaction chamber. Note that as used herein, an ALD process can, but does not necessarily, include a series of self-limiting surface reactions.

[0039] Embodiments of a structure are described herein. The structure includes conductive lines embedded in a low-k dielectric. The conductive lines are surrounded by the low-k dielectric and are separated from the low-k dielectric by a dipole liner. The dipole liner includes dipoles.

[0040] The low-k dielectric can include silicon, oxygen, carbon, and hydrogen. The low-k dielectric can be porous. Optionally, the low-k dielectric can further include one or more other compounds, such as nitrogen and boron.

[0041] Additionally or alternatively, a structure according to an embodiment of the present disclosure may be described as including a dipole liner, which in turn includes dipoles. The dipole liner separates the conductive wire from the low-k dielectric.

[0042] In Figure 1 the embodiments of the structure are further explained. In particular, with reference to Figure 1 , a structure 100 according to an embodiment of the present disclosure is described. The structure 100 includes a conductive wire 130 embedded in a low-k dielectric 110. Exemplary conductive wires include conductive wires containing metals. Exemplary metals include copper, aluminum, silver, gold, ruthenium, molybdenum, and tungsten. The metal wire 130 is lined (i.e., surrounded) by a dipole liner 120 as described herein. In other words, the dipole liner 120 separates the conductive wire 130 from the low-k dielectric 110. The dipole liner 120 includes dipoles. Advantageously, such a dipole liner can inhibit electromigration in the conductive wire.

[0043] In some embodiments, the structure further includes a semiconductor wafer. In such embodiments, the conductive wire may include a planar portion and a lateral portion. The planar portion may be substantially parallel to the semiconductor wafer. The lateral portion may be substantially perpendicular to the semiconductor wafer. In Figure 2 the embodiments of the structure 200 are further explained. This embodiment of the structure 200 includes a first conductive wire 231 and a second conductive wire 232. The first conductive wire 231 and the second conductive wire 232 are electrically connected by a via 235. In some embodiments, the via 235, the first conductive wire 231, and the second conductive wire 232 may include the same material, such as the same metal. The via 235, the first conductive wire 231, and the second conductive wire 232 are lined (i.e., surrounded) by a dipole liner 220 including dipoles. Advantageously, such a dipole liner can inhibit electromigration in at least one of the first conductive wire 231, the second conductive wire 232, and the via 235.

[0044] Advantageously, the dipole may have a dipole moment 121 pointing from the conductive wire 130 to the low-k dielectric 110, as Figure 3 shown. Thus, the dipole may include a negative shared sheath surrounding the metal wire, which is surrounded by a positive charge sheath. Such a dipole can advantageously cause electron repulsion from the interface between the low-k dielectric and the conductive wire. When the electrical conduction in the conductive wire is mediated by electrons, as is the case with a metal wire, the electrons are repelled from the edge of the conductive wire. Thus, the chance of electrons colliding with defects at the edge of the conductive wire is smaller, and thus, electromigration can be advantageously reduced or even completely stopped.

[0045] In some embodiments, the conductive wire may include a metal, such as copper, aluminum, molybdenum, tungsten, or silver. In some embodiments, the conductive wire includes a transition metal. In some embodiments, the conductive wire includes a noble metal. In some embodiments, the conductive wire includes a post-transition metal. In some embodiments, the conductive wire includes an alkaline earth metal. In some embodiments, the conductive wire includes an alkali metal. In some embodiments, the conductive wire includes a rare earth metal.

[0046] In some embodiments, the dipole lining includes a rare earth element.

[0047] In some embodiments, the rare earth element includes at least one of lanthanum, scandium, and yttrium.

[0048] In some embodiments, the dipole lining includes a rare earth element oxide. In some embodiments, the dipole lining includes one or more of nitrides, carbides, sulfides, selenides, tellurides, borides, phosphides, and halides. In some embodiments, the dipole lining includes one or more of rare earth nitrides, carbides, sulfides, selenides, tellurides, borides, phosphides, and halides.

[0049] In some embodiments, the rare earth element oxide is selected from La2O3, Sc2O3, and Y2O3.

[0050] In some embodiments, the dipole includes a metal oxynitride. In some embodiments, the dipole includes an alkaline earth metal oxynitride. In some embodiments, the dipole includes an alkali metal oxynitride. In some embodiments, the dipole includes a transition metal oxynitride. In some embodiments, the dipole includes a rare earth metal oxynitride.

[0051] In some embodiments, the dipole includes a post-transition metal oxynitride. Such a dipole can provide good resistance to electromigration and good adhesion between a low-k dielectric.

[0052] In some embodiments, the post-transition metal oxynitride includes gallium oxynitride.

[0053] In some embodiments, the dipole lining has a uniform thickness. A cyclic deposition process such as atomic layer deposition (ALD) can advantageously obtain a uniform thickness. For example, the dipole lining can have a uniform thickness with a variation of at most 5 nm, or at most 4 nm, or at most 3 nm, or at most 2 nm, or at most 1 nm, or at most 0.5 nm, or at most 0.3 nm, or at most 0.1 nm.

[0054] In some embodiments, the structure further includes a conductive lining. The conductive lining can be located between the conductive wire and the dipole lining. The conductive lining can be made of a material different from that of the conductive wire.

[0055] In some embodiments, the conductive lining has a uniform thickness. A cyclic deposition process such as atomic layer deposition (ALD) can be advantageously used to obtain a uniform thickness. For example, the conductive lining can have a uniform thickness with a variation of at most 5 nm, or at most 4 nm, or at most 3 nm, or at most 2 nm, or at most 1 nm, or at most 0.5 nm, or at most 0.3 nm, or at most 0.1 nm.

[0056] In some embodiments, the conductive lining comprises a transition metal nitride. In some embodiments, the conductive lining comprises an alkali metal. In some embodiments, the conductive lining includes an alkaline earth metal. In some embodiments, the conductive lining includes a post-transition metal. In some embodiments, the conductive lining includes an oxide. In some embodiments, the conductive lining includes a sulfide. In some embodiments, the conductive lining includes a selenide. In some embodiments, the conductive lining includes a telluride. In some embodiments, the conductive lining includes a boride. In some embodiments, the conductive lining includes a phosphide.

[0057] In some embodiments, the transition metal nitride includes tantalum nitride.

[0058] In some embodiments, the conductive lining includes a 2D material. In some embodiments, the 2D material includes a transition metal dichalcogenide.

[0059] Embodiments of a method of forming a structure are further described herein. The method includes the step of providing a substrate to a reaction chamber. The substrate includes a low-k dielectric. The method further includes the step of forming a dipole lining on the low-k dielectric. The dipole lining includes dipoles. The dipole lining can be formed by means of a cyclic deposition process such as atomic layer deposition. In some embodiments, forming the structure as described herein includes performing the method as described herein.

[0060] In some embodiments, the method according to an embodiment of the present disclosure includes first forming a low-k dielectric. Refer to Figure 4 Embodiments are described. Figure 4 Embodiments particularly include forming a low-k dielectric 410. Then, a dipole lining 420 is formed on the low-k dielectric. Optionally, a conductive lining 430 is formed on the dipole lining. Then, a conductive line 440 is formed. The conductive line can be formed on the conductive lining (if present), or directly on the dipole lining in the absence of a conductive lining.

[0061] In some embodiments, the method according to an embodiment of the present disclosure includes first forming a conductive line. Refer to Figure 5 Embodiments are described. Figure 5Embodiments particularly include forming a conductive wire 510. Optionally, a conductive liner 520 is formed on the conductive wire. Then, a dipole liner 530 is formed. The dipole liner can be formed on the conductive liner (if present) or directly on the conductive wire in the absence of a conductive liner. Then, a low-k dielectric 540 is formed on the dipole liner.

[0062] A system 600 as described in Figure 6 can be used to form one or more of the low-k material, conductive wire, dipole liner, and conductive liner. Figure 6 A system 600 according to an exemplary embodiment of the present disclosure is shown. The system 600 can be used to perform the methods described herein and / or form the structures or device portions described herein.

[0063] In the illustrated example, the system 600 includes one or more reaction chambers 602, a first precursor gas source 604, a reactant gas source 606, a purge gas source 608, an exhaust device 610, and a controller 612.

[0064] The reaction chamber 602 can include any suitable reaction chamber, such as an ALD or CVD reaction chamber.

[0065] The first precursor gas source 604 can include a container and one or more precursors as described herein—either alone or mixed with one or more carrier gases (such as noble gases). The reactant gas source 606 can include a container and one or more reactants as described herein—either alone or mixed with one or more carrier gases. The purge gas source 608 can include one or more noble gases as described herein. Although shown as having four gas sources 604-608, the system 600 can include any suitable number of gas sources. The gas sources 604-608 can be coupled to the reaction chamber 602 via pipelines 614-618, and the pipelines 614-618 can each include a flow controller, a valve, a heater, etc.

[0066] The exhaust device 610 can include one or more vacuum pumps.

[0067] The controller 612 includes electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in system 600. Such circuitry and components operate to introduce precursors and purge gases from corresponding sources 604 - 608. The controller 612 can control the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to provide proper operation of system 600. The controller 612 can include control software to control valves electrically or pneumatically to control the flow of precursors, reactants, and purge gases into and out of reaction chamber 602. The controller 612 can include modules that perform certain tasks, such as software or hardware components, e.g., FPGA or ASIC. The modules can advantageously be configured to reside on an addressable storage medium of the control system and configured to execute one or more processes.

[0068] Other configurations of system 600 are possible, including different numbers and types of precursor and reactant sources and purge gas sources. Additionally, it should be understood that there are many arrangements of valves, conduits, precursor sources, and purge gas sources that can be used to achieve the goal of selectively feeding gases into reaction chamber 602. Additionally, as a schematic representation of the system, many components have been omitted for simplicity of illustration, and such components can include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0069] During operation of reactor system 600, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to reaction chamber 602. Once the substrate(s) is transferred to reaction chamber 602, one or more gases (such as precursors, reactants, carrier gas, and / or purge gas) from gas sources 604 - 608 are introduced into reaction chamber 602.

[0070] The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations for describing embodiments of the present disclosure.

[0071] The specific embodiments shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and embodiments in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Additionally, the connecting lines shown in the figures are intended to represent example functional relationships and / or physical couplings between various elements. Many alternative or additional functional relationships or physical connections may exist in the actual system and / or may not exist in some embodiments.

[0072] It should be understood that the configurations and / or methods described herein are exemplary in nature and these specific embodiments or examples should not be considered limiting as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Accordingly, the various acts shown may be performed in the order shown, in other orders, or in some cases, omitted.

[0073] The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems, and configurations, as well as other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A structure includes a conductive wire embedded in a low-k dielectric, wherein, The conductive wire is surrounded by a low-k dielectric and separated from the low-k dielectric by means of a dipole liner, and the dipole liner includes dipoles.

2. The structure according to claim 1 further includes a semiconductor wafer, wherein, The conductive wire includes a planar portion and a lateral portion, the planar portion being substantially parallel to the semiconductor wafer, and the lateral portion being substantially perpendicular to the semiconductor wafer.

3. The structure according to claim 1 or 2, wherein The dipole has a dipole moment pointing from the conductive wire to the low-k dielectric.

4. The structure according to any one of claims 1 to 3, wherein, The dipole liner includes rare earth elements.

5. The structure according to claim 4, wherein, The rare earth elements include at least one of lanthanum, scandium, and yttrium.

6. The structure according to claim 4, wherein The dipole liner includes rare earth element oxides.

7. The structure according to claim 6, wherein, The rare earth element oxides are selected from La2O3, Sc2O3, and Y2O3.

8. The structure according to claim 4, wherein, The dipole liner includes metal nitrides.

9. The structure according to claim 8, wherein, The dipole liner includes post-transition metal nitrides.

10. The structure according to claim 9, wherein, The post-transition metal nitrides include gallium oxynitride.

11. The structure according to any one of claims 1 to 10, wherein, The dipole liner has a uniform thickness.

12. The structure according to any one of claims 1 to 11 further includes a conductive liner, wherein the conductive liner is located between the conductive wire and the dipole liner.

13. The structure according to claim 12, wherein, The conductive liner includes transition metal nitrides.

14. The structure according to claim 13, wherein, The transition metal nitrides include tantalum nitride.

15. The structure according to claim 14, wherein, The conductive liner includes 2D materials.

16. The structure according to claim 15, wherein, The 2D materials include transition metal dichalcogenides.

17. A structure including a dipole liner, the dipole liner including dipoles, the dipole liner separating a conductive wire from a low-k dielectric.

18. A method of forming a structure, the method including the step of providing a substrate to a reaction chamber, the substrate including a low-k dielectric, the method further including the step of forming a dipole liner including dipoles on the low-k dielectric.

19. The method according to claim 18, wherein The dipole liner is formed by atomic layer deposition.

20. The method according to claim 18 or 19, wherein, The structure is the structure according to any one of claims 1 to 17.

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