High-precision anti-interference circuit structure

Abstract

The invention relates to the technical field of battery power supply, in particular to a high-precision anti-interference circuit structure. According to the invention, through the arrangement of the capacitor circuit, the first control circuit, the second control circuit and the follower circuit, the output control signal can be fixed to be a high-level signal after the input signal is at a rising edge and is greater than a first flip threshold voltage, and the output control signal can be fixed to be a low-level signal after the input signal is at a falling edge and is less than the first flip threshold voltage. And the output control signal is fixed as a low-level signal. Namely, the noise of the rising edge of the input signal is not identified as a plurality of rising edges, and the noise of the falling edge is not identified as a plurality of falling edges, so that the anti-interference capability, the control precision and the reliability of the circuit are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of battery power supply, and particularly to a circuit structure with high precision and anti-interference. Background Art

[0002] The existing battery charging circuit usually includes an integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip controls the power circuit to charge the battery load. When the battery load is being charged, the change of the battery load will generate high-frequency noise, which may be coupled to the chip pins through parasitic capacitance or PCB traces, thereby interfering with the control signal inside the chip, resulting in one rising edge or falling edge of the control signal being recognized as multiple rising edges or falling edges, causing the confusion of the control signal, reducing the accuracy of the battery charging circuit, and decreasing the reliability of the battery charging circuit. Summary of the Invention

[0003] In view of this, the present invention provides a circuit structure with high precision and anti-interference to solve the technical problem that the control signal in the battery charging circuit is easily interfered, resulting in the confusion of the control signal.

[0004] The technical solution provided by the present invention is as follows: The first aspect of the present invention provides a circuit structure with high precision and anti-interference, including: a follower circuit, whose first end receives an input signal, the second end is connected to the first end of a first control circuit and the first end of a capacitor circuit, the third end is connected to the first end of a second control circuit and the second end of the capacitor circuit, the fourth end is connected to the second end of the first control circuit, the fifth end is connected to the second end of the second control circuit, and the fourth end is used to output a control signal; a first control circuit, whose third end is connected to the third end of the capacitor circuit and the third end of the second control circuit; a capacitor circuit, whose fourth end is connected to an external power supply and whose fifth end is grounded; When the input signal is at a rising edge and greater than the first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a high-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time, the capacitor circuit enters a charging state; When the input signal is at a falling edge and less than the first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a low-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time, the capacitor circuit enters a charging state; Wherein, the first flip threshold voltage is the voltage when the components in the follower circuit undergo voltage flipping, and the second flip threshold voltage is the voltage when the components in the first control circuit and the second control circuit undergo voltage flipping.

[0005] In an alternative embodiment, when the input signal is at the rising edge and greater than the first flip threshold voltage, the follower circuit outputs a high-level control signal at the fourth terminal and a low-level signal at the fifth terminal according to the input signal and the low-level signal output by the second control circuit at the previous moment; the second terminal of the first control circuit receives the high-level control signal, and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitor circuit was charged at the previous moment and the state of the first control circuit at the previous moment; the second terminal of the second control circuit receives the low-level signal output by the fifth terminal of the follower circuit, and outputs a low-level signal at the first terminal according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal; When the input signal is at the falling edge and less than the first flip threshold voltage, the follower circuit outputs a low-level control signal at the fourth terminal and a high-level signal at the fifth terminal according to the input signal and the low-level signal output by the first control circuit at the previous moment; the second terminal of the second control circuit receives the high-level signal output by the fifth terminal of the follower circuit, and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitor circuit was charged at the previous moment and the state of the second control circuit at the previous moment, and under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

[0006] In an alternative embodiment, when the input signal is at the rising edge and greater than the first flip threshold voltage, the capacitor circuit enters the discharge state according to the high-level signal output by the first terminal of the first control circuit, and outputs a low-level signal when discharging to the second flip threshold voltage; the third terminal of the first control circuit receives the low-level signal generated after the capacitor circuit discharges, and outputs a low-level signal at the first terminal; the third terminal of the second control circuit receives the low-level signal generated after the capacitor circuit discharges, and outputs a low-level signal at the first terminal. Based on the low-level signal output by the first terminal of the first control circuit and the low-level signal output by the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. Meanwhile, the capacitor circuit enters the charging state; After the capacitor circuit is charged to a high level, the first terminal of the first control circuit and the first terminal of the second control circuit output low-level signals. Based on the low-level signals output by the first terminal of the first control circuit and the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. Meanwhile, the capacitor circuit maintains the charged high-level state.

[0007] In an alternative embodiment, when the input signal is at a falling edge and is less than the first flip threshold voltage, the capacitive circuit enters a discharging state according to the high-level signal output from the first terminal of the second control circuit. When discharging to the second flip threshold voltage, a low-level signal is output. The third terminal of the second control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal; the third terminal of the first control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal. Based on the low-level signals output from the first terminal of the first control circuit and the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit enters a charging state; After the capacitive circuit charges to a high level, the first terminal of the second control circuit and the first terminal of the first control circuit output low-level signals. Based on the low-level signals output from the first terminal of the first control circuit and the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit maintains the high-level state after charging.

[0008] In an alternative embodiment, when the circuit is just powered on and the input signal is a low-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first terminal according to the capacitive circuit in the initial state. The capacitive circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a low-level control signal at the fourth terminal according to the input signal and the low-level signal output by the first control circuit.

[0009] In an alternative embodiment, when the circuit is just powered on and the input signal is a high-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first terminal according to the capacitive circuit in the initial state. The capacitive circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a high-level control signal at the fourth terminal according to the input signal and the low-level signal output by the second control circuit.

[0010] In an alternative embodiment, the following circuit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate; the input terminal of the first inverter receives an input signal, the output terminal of the first inverter is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the output terminal of the third inverter, the input terminal of the third inverter is connected to the first terminal of the first control circuit and the first terminal of the capacitor circuit, the output terminal of the first NAND gate is connected to the first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the output terminal of the fourth inverter, the input terminal of the fourth inverter is connected to the first terminal of the second control circuit and the second terminal of the capacitor circuit, the output terminal of the second NAND gate is connected to the input terminal of the second inverter and the second terminal of the second control circuit, and the output terminal of the second inverter is connected to the second terminal of the first control circuit and outputs a control signal.

[0011] In an alternative embodiment, the first control circuit includes: a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; the first input terminal of the third NAND gate is connected to the output terminal of the eighth NAND gate and the third input terminal of the sixth NAND gate, the second input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate, the first input terminal of the fifth NAND gate, and the first input terminal of the sixth NAND gate, the output terminal of the third NAND gate is connected to the first input terminal of the fourth NAND gate, the second input terminal of the fourth NAND gate is connected to the second input terminal of the sixth NAND gate and the fourth terminal of the following circuit, the third input terminal of the fourth NAND gate is connected to the second input terminal of the eighth NAND gate, the third input terminal of the seventh NAND gate, the third terminal of the capacitor circuit, and the third terminal of the second control circuit, the second input terminal of the fifth NAND gate is connected to the output terminal of the seventh NAND gate, the output terminal of the fifth NAND gate is connected to the first input terminal of the seventh NAND gate, the second terminal of the following circuit, and the first terminal of the capacitor circuit, and the output terminal of the sixth NAND gate is connected to the second input terminal of the seventh NAND gate and the first input terminal of the eighth NAND gate.

[0012] In an alternative embodiment, the second control circuit includes: a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, and a fourteenth NAND gate; a first input terminal of the ninth NAND gate is connected to an output terminal of the fourteenth NAND gate and a third input terminal of the twelfth NAND gate, a second input terminal of the ninth NAND gate is connected to an output terminal of the tenth NAND gate, a first input terminal of the eleventh NAND gate, and a first input terminal of the twelfth NAND gate, an output terminal of the ninth NAND gate is connected to a first input terminal of the tenth NAND gate, a second input terminal of the tenth NAND gate is connected to a second input terminal of the twelfth NAND gate and a fifth terminal of the follower circuit, a third input terminal of the tenth NAND gate is connected to a second input terminal of the fourteenth NAND gate, a third input terminal of the thirteenth NAND gate, a third terminal of the capacitor circuit, and a third terminal of the first control circuit, a second input terminal of the eleventh NAND gate is connected to an output terminal of the thirteenth NAND gate, an output terminal of the eleventh NAND gate is connected to a first input terminal of the thirteenth NAND gate, a third terminal of the follower circuit, and a second terminal of the capacitor circuit, an output terminal of the twelfth NAND gate is connected to a second input terminal of the thirteenth NAND gate and a first input terminal of the fourteenth NAND gate.

[0013] In an alternative embodiment, the capacitor circuit includes: a first OR gate, a first capacitor, a first switching transistor, a second switching transistor, a third switching transistor, and a first current source; a first input terminal of the first OR gate is connected to a first terminal of the first control circuit and a second terminal of the follower circuit, a second input terminal of the first OR gate is connected to a first terminal of the second control circuit and a third terminal of the follower circuit, an output terminal of the first OR gate is connected to a first terminal of the first switching transistor, a second terminal of the first switching transistor is connected to one end of the first current source and an external power supply, a third terminal of the first switching transistor is connected to one end of the first capacitor, a first terminal of the second switching transistor, a third terminal of the first control circuit, and a third terminal of the second control circuit, the other end of the first capacitor is connected to a second terminal of the second switching transistor, a first terminal of the third switching transistor, and is grounded, a third terminal of the second switching transistor is connected to a second terminal, a third terminal of the third switching transistor, and the other end of the first current source.

[0014] In an alternative embodiment, the time T0 for the third terminal of the capacitor circuit to discharge to the second flip threshold voltage is expressed by the following formula: max[T1,T3]<T0<min[T1+T2,T3+T4] Wherein, T1 represents the time when the input signal rises from the first flip threshold voltage to the external power supply voltage at the rising edge, T2 represents the sum of the time when the input signal is at the high-level signal and the time when the input signal drops from the external power supply voltage to the first flip threshold voltage at the falling edge, T3 represents the time when the input signal drops from the first flip threshold voltage to the ground voltage at the falling edge; T4 represents the sum of the time when the input signal is at the low-level signal and the time when the input signal rises from the ground voltage to the first flip threshold voltage at the rising edge. The voltage of the high-level signal is equal to the external power supply voltage, and the voltage of the low-level signal is equal to the ground voltage.

[0015] The second aspect of the present invention provides a battery-powered circuit, including: an integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip includes the high-precision anti-interference circuit structure of the first aspect and any item of the first aspect of the present invention. The integrated circuit control chip controls the power circuit to supply power to the battery load according to the control signal output by the following circuit.

[0016] The technical solution of the present invention has the following advantages: In the present invention, through the settings of the capacitor circuit, the first control circuit, the second control circuit, and the following circuit, it can be ensured that after the input signal is at the rising edge and greater than the first flip threshold voltage, the output control signal is fixed as a high-level signal, and after the input signal is at the falling edge and less than the first flip threshold voltage, the output control signal is fixed as a low-level signal. That is, the noise at the rising edge of the input signal will not be recognized as multiple rising edges, and the noise at the falling edge will not be recognized as multiple falling edges, thereby improving the anti-interference ability, control accuracy, and reliability of the circuit.

[0017] In the present invention, a high-precision anti-interference circuit structure is set in the integrated circuit control chip, so that the control signal inside the integrated circuit control chip will not be interfered by the change of the battery load, improving the accuracy and reliability of the battery charging circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0019] Figure 1 It is the structural block diagram of the high-precision anti-interference circuit structure in the embodiment of the present invention; Figure 2 It is the structural schematic diagram of the high-precision anti-interference circuit structure in the embodiment of the present invention; Figure 3Schematic diagram of the input signal and output control signal waveforms of the high-precision anti-interference circuit structure in the embodiments of the present invention; Figure 4 Block diagram of the battery power supply circuit in the embodiments of the present invention. Specific embodiments

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0022] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the internal communication of two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0023] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] The embodiments of the present invention provide a high-precision anti-interference circuit structure, as Figure 1As shown, it includes: a follower circuit 10, whose first terminal receives an input signal IN, the second terminal is connected to the first terminal of a first control circuit 20 and the first terminal of a capacitance circuit 40, the third terminal is connected to the first terminal of a second control circuit 30 and the second terminal of the capacitance circuit 40, the fourth terminal is connected to the second terminal of the first control circuit 20, the fifth terminal is connected to the second terminal of the second control circuit 30, and the fourth terminal is used to output a control signal OUT; a first control circuit 20, whose third terminal is connected to the third terminal of the capacitance circuit 40 and the third terminal of the second control circuit 30; a capacitance circuit 40, whose fourth terminal is connected to an external power supply VCC and whose fifth terminal is grounded to GND.

[0025] When the input signal is at the rising edge and greater than the first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a high-level control signal. When the capacitance circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time, the capacitance circuit enters a charging state; When the input signal is at the falling edge and less than the first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a low-level control signal. When the capacitance circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time, the capacitance circuit enters a charging state; Wherein, the first flip threshold voltage is the voltage when the components in the follower circuit have a voltage flip, and the second flip threshold voltage is the voltage when the components in the first control circuit and the second control circuit have a voltage flip.

[0026] Wherein, when the circuit is just powered on, that is, when the external power supply connected to the capacitance circuit is just connected, the capacitance circuit has not been charged and is in an initial state. At this time, the terminal voltage of the third terminal of the capacitance circuit connected to the first control circuit and the second control circuit is a low-level signal. Then, the first control circuit and the second control circuit respectively output low-level signals at the first terminal according to the capacitance circuit in the initial state. The low-level signals output by the first control circuit and the second control circuit are then input to the capacitance circuit through the first terminal and the second terminal of the capacitance circuit, so that the capacitance circuit enters a charging state.

[0027] In an alternative embodiment, when the circuit is powered on and the input signal is at a low level, based on the low-level signal output by the first control circuit, after the low-level input signal is input to the follower circuit, the fourth terminal of the follower circuit outputs a low-level control signal, and the fifth terminal of the follower circuit outputs a high-level signal.

[0028] When the input signal switches from a low level to a high level (i.e., after the input signal is at the rising edge and greater than the first flip threshold voltage), the follower circuit outputs a high-level control signal at the fourth terminal and a low-level signal at the fifth terminal according to the input signal and the low-level signal output by the second control circuit at the previous moment (i.e., when the input signal is at a low level); the second terminal of the first control circuit receives the high-level control signal, and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitor circuit was charged at the previous moment and the state of the first control circuit at the previous moment (i.e., the state when the input signal was at a low level); the second terminal of the second control circuit receives the low-level signal output by the fifth terminal of the follower circuit, and outputs a low-level signal at the first terminal according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal.

[0029] After the input signal switches to a high level, the capacitor circuit enters a discharging state according to the high-level signal output by the first terminal of the first control circuit, and outputs a low-level signal when discharging to the second flip threshold voltage; the third terminal of the first control circuit receives the low-level signal generated after the capacitor circuit discharges, and outputs a low-level signal at the first terminal; the third terminal of the second control circuit receives the low-level signal generated after the capacitor circuit discharges, and outputs a low-level signal at the first terminal. Based on the low-level signal output by the first terminal of the first control circuit and the low-level signal output by the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitor circuit enters a charging state. After the capacitor circuit is charged to a high level, the first terminal of the first control circuit and the first terminal of the second control circuit output low-level signals. Based on the low-level signals output by the first terminal of the first control circuit and the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitor circuit maintains the high-level state after charging.

[0030] In an alternative embodiment, when the circuit is powered on and the input signal is at a high level, based on the low-level signal output by the second control circuit, after the high-level input signal is input to the follower circuit, the follower circuit outputs a high-level control signal at the fourth terminal and a low-level signal at the fifth terminal.

[0031] When the input signal switches from a high level to a low level (i.e., after the input signal is at the falling edge and is less than the first flip threshold voltage), the follower circuit outputs a low-level control signal at the fourth terminal and a high-level signal at the fifth terminal according to the input signal and the low-level signal output by the first control circuit at the previous moment (i.e., when the input signal is at a high level); the second terminal of the second control circuit receives the high-level signal output by the fifth terminal of the follower circuit, and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitor circuit was charged at the previous moment and the state of the second control circuit at the previous moment (i.e., the state when the input signal was at a high level). Under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

[0032] After the input signal switches to a low level, the capacitor circuit enters a discharging state according to the high-level signal output by the first terminal of the second control circuit. When the discharge reaches the second flip threshold voltage, a low-level signal is output. The third terminal of the second control circuit receives the low-level signal generated after the capacitor circuit discharges and outputs a low-level signal at the first terminal; the third terminal of the first control circuit receives the low-level signal generated after the capacitor circuit discharges and outputs a low-level signal at the first terminal. Based on the low-level signal output by the first terminal of the first control circuit and the low-level signal output by the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitor circuit enters a charging state. After the capacitor circuit is charged to a high level, the first terminal of the second control circuit and the first terminal of the first control circuit output low-level signals. Based on the low-level signals output by the first terminal of the first control circuit and the first terminal of the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitor circuit maintains the charged high-level state.

[0033] It should be noted that in the above signals, the low-level signal can be a ground signal, i.e., a zero-level signal, and the high-level signal can be an external power supply voltage signal. The control signal output by the fourth terminal of the follower circuit can be used as the output signal of this high-precision anti-interference circuit structure, that is, this circuit structure outputs a control signal to control other structures. Additionally, when this circuit structure is not set, in the related art, the input signal (as a control signal) may be directly used to control other structures. However, due to the existence of interference signals, this input signal may be affected. Therefore, the present invention provides this circuit structure, which can obtain an interference-free output signal by adjusting the input signal, and then the interference-free output signal can be used to control other structures.

[0034] Under normal circumstances, due to the large difference between the high-level signal and the low-level signal, when the input signal is at the low-level signal or the high-level signal, even if there is an interference signal in the external environment and this interference signal is input into the circuit structure, it will not cause the input signal to change from high level to low level or from low level to high level. Therefore, generally, it will not affect the output signal of the circuit structure. However, during the process of the input signal switching from the low-level signal to the high-level signal (i.e., the input signal is at the rising edge), or during the process of the input signal switching from the high-level signal to the low-level signal (i.e., the input signal is at the falling edge), this interference signal may affect the input signal. Therefore, through the settings of the above-mentioned capacitor circuit, first control circuit, second control circuit, and follower circuit, it can be ensured that after the input signal is at the rising edge and greater than the first flip threshold voltage, the output control signal is fixed at the high-level signal, and after the input signal is at the falling edge and less than the first flip threshold voltage, the output control signal is fixed at the low-level signal. Thus, the output control signal is not affected by the interference signal.

[0035] In the present invention, through the settings of the capacitor circuit, first control circuit, second control circuit, and follower circuit, it can be ensured that after the input signal is at the rising edge and greater than the first flip threshold voltage, the output control signal is fixed at the high-level signal, and after the input signal is at the falling edge and less than the first flip threshold voltage, the output control signal is fixed at the low-level signal. That is, the noise at the rising edge of the input signal will not be recognized as multiple rising edges, and the noise at the falling edge will not be recognized as multiple falling edges, thereby improving the anti-interference ability, control accuracy, and reliability of the circuit.

[0036] In an optional implementation manner, as Figure 2 shown, the follower circuit includes: a first inverter N1, a second inverter N2, a third inverter N3, a fourth inverter N4, a first NAND gate A1, and a second NAND gate A2; the input end of the first inverter N1 receives the input signal, the output end of the first inverter N1 is connected to the first input end of the first NAND gate A1, the second input end of the first NAND gate A1 is connected to the output end of the third inverter N3, the input end of the third inverter N3 is connected to the first end of the first control circuit and the first end of the capacitor circuit, the output end of the first NAND gate A1 is connected to the first input end of the second NAND gate A2, the second input end of the second NAND gate A2 is connected to the output end of the fourth inverter N4, the input end of the fourth inverter N4 is connected to the first end of the second control circuit and the second end of the capacitor circuit, the output end of the second NAND gate A2 is connected to the input end of the second inverter N2 and the second end of the second control circuit, and the output end of the second inverter N2 is connected to the second end of the first control circuit and outputs the control signal.

[0037] The first control circuit includes: the third NAND gate A3, the fourth NAND gate A4, the fifth NAND gate A5, the sixth NAND gate A6, the seventh NAND gate A7, and the eighth NAND gate A8; the first input terminal of the third NAND gate A3 is connected to the output terminal of the eighth NAND gate A8 and the third input terminal of the sixth NAND gate A6, the second input terminal of the third NAND gate A3 is connected to the output terminal of the fourth NAND gate A4, the first input terminal of the fifth NAND gate A5, and the first input terminal of the sixth NAND gate A6, the output terminal of the third NAND gate A3 is connected to the first input terminal of the fourth NAND gate A4, the second input terminal of the fourth NAND gate A4 is connected to the second input terminal of the sixth NAND gate A6 and the fourth terminal of the follower circuit, the third input terminal of the fourth NAND gate A4 is connected to the second input terminal of the eighth NAND gate A8, the third input terminal of the seventh NAND gate A7, the third terminal of the capacitor circuit, and the third terminal of the second control circuit, the second input terminal of the fifth NAND gate A5 is connected to the output terminal of the seventh NAND gate A7, the output terminal of the fifth NAND gate A5 is connected to the first input terminal of the seventh NAND gate A7, the second terminal of the follower circuit, and the first terminal of the capacitor circuit, the output terminal of the sixth NAND gate A6 is connected to the second input terminal of the seventh NAND gate A7 and the first input terminal of the eighth NAND gate A8.

[0038] The second control circuit includes: the ninth NAND gate A9, the tenth NAND gate A10, the eleventh NAND gate A11, the twelfth NAND gate A12, the thirteenth NAND gate A13, and the fourteenth NAND gate A14; the first input terminal of the ninth NAND gate A9 is connected to the output terminal of the fourteenth NAND gate A14 and the third input terminal of the twelfth NAND gate A12, the second input terminal of the ninth NAND gate A9 is connected to the output terminal of the tenth NAND gate A10, the first input terminal of the eleventh NAND gate A11, and the first input terminal of the twelfth NAND gate A12, the output terminal of the ninth NAND gate A9 is connected to the first input terminal of the tenth NAND gate A10, the second input terminal of the tenth NAND gate A10 is connected to the second input terminal of the twelfth NAND gate A12 and the fifth terminal of the follower circuit, the third input terminal of the tenth NAND gate A10 is connected to the second input terminal of the fourteenth NAND gate A14, the third input terminal of the thirteenth NAND gate A13, the third terminal of the capacitor circuit, and the third terminal of the first control circuit, the second input terminal of the eleventh NAND gate A11 is connected to the output terminal of the thirteenth NAND gate A13, the output terminal of the eleventh NAND gate A11 is connected to the first input terminal of the thirteenth NAND gate A13, the third terminal of the follower circuit, and the second terminal of the capacitor circuit, the output terminal of the twelfth NAND gate A12 is connected to the second input terminal of the thirteenth NAND gate A13 and the first input terminal of the fourteenth NAND gate A14.

[0039] The capacitive circuit includes: a first OR gate F1, a first capacitor C1, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a first current source B1; the first input terminal of the first OR gate F1 is connected to the first terminal of the first control circuit and the second terminal of the follower circuit, the second input terminal of the first OR gate F1 is connected to the first terminal of the second control circuit and the third terminal of the follower circuit, the output terminal of the first OR gate F1 is connected to the first terminal of the first switching transistor M1, the second terminal of the first switching transistor M1 is connected to one end of the first current source B1 and an external power supply, the third terminal of the first switching transistor M1 is connected to one end of the first capacitor C1, the first terminal of the second switching transistor M2, the third terminal of the first control circuit, and the third terminal of the second control circuit, the other end of the first capacitor C1 is connected to the second terminal of the second switching transistor M2, the first terminal of the third switching transistor M3, and is grounded, and the third terminal of the second switching transistor M2 is connected to the second terminal, the third terminal of the third switching transistor M3, and the other end of the first current source B1.

[0040] Based on the specific structures of the above-mentioned follower circuit, first control circuit, second control circuit, and capacitive circuit, the working principle of this high-precision anti-interference circuit structure is as follows: When the circuit is just powered on, the terminal voltage of the first capacitor C1 is 0, that is, at this time, one input terminal of the fourth NAND gate A4, the seventh NAND gate A7, and the eighth NAND gate A8 is at a low level. Therefore, both the fourth NAND gate A4 and the seventh NAND gate A7 output a high level to the fifth NAND gate A5, and the fifth NAND gate A5 outputs a low level to the first OR gate F1; at the same time, one input terminal of the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 is at a low level. Therefore, both the tenth NAND gate A10 and the thirteenth NAND gate A13 output a high level to the eleventh NAND gate A11, and the eleventh NAND gate A11 outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switching transistor M1, and the first switching transistor M1 conducts, pulling the terminal voltage of the first capacitor C1 to a high level.

[0041] Therefore, after the circuit is powered on, the third inverter N3 outputs a high level to the first NAND gate A1, the fourth inverter N4 outputs a high level to the second NAND gate A2, and the first capacitor C1 outputs a high level to the third input terminal of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the third input terminal of the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14.

[0042] At the same time, the first current source B1 raises the control terminal voltages of the second switching transistor M2 and the third switching transistor M3, and the second switching transistor M2 and the third switching transistor M3 conduct. At this time, the aspect ratio of the second switching transistor M2 and the third switching transistor M3 is designed as M:1, and the current generated in the first current source B1 is denoted as I1. Therefore, it can be obtained that the current flowing through the second switching transistor M2 is .

[0043] (1) When the input signal IN is at a low level, the first inverter N1 outputs a high level, the first NAND gate A1 outputs a low level, the second NAND gate A2 outputs a high level, and the second inverter N2 outputs a low level. That is, at this time, the control signal OUT is also at a low level. This low-level signal is input into the fourth NAND gate A4 and the sixth NAND gate A6. The fourth NAND gate A4 and the sixth NAND gate A6 output high levels. At this time, both input terminals of the eighth NAND gate A8 are input with high levels. Therefore, the eighth NAND gate A8 outputs a low level to the third NAND gate A3, and the third NAND gate A3 outputs a high level to the first input terminal of the fourth NAND gate A4. At the same time, the high-level signal output by the second NAND gate A2 is input into the second control circuit. And when just powered on, both the fourteenth NAND gate A14 and the tenth NAND gate A10 output high-level signals to the ninth NAND gate A9. The ninth NAND gate A9 outputs a low-level signal to the tenth NAND gate A10, and the tenth NAND gate 10 outputs a high-level signal to the eleventh NAND gate A11. And the fourteenth NAND gate A14 outputs a high-level signal to the twelfth NAND gate A12. Thus, all three input terminals of the twelfth NAND gate A12 are input with high-level signals. Therefore, the twelfth NAND gate A12 outputs a low-level signal, the thirteenth NAND gate A13 outputs a high level, and the eleventh NAND gate A11 outputs a low-level signal based on two high-level signals. That is, when the input signal is at a low level, the first terminal of the second control circuit keeps outputting a low-level signal.

[0044] When the input signal IN switches from a low level to a high level, that is, when the rising-edge voltage of the input signal IN rises to the first flip threshold voltage V1 of the first inverter N1, the first inverter N1 outputs a low level, and the first NAND gate A1 outputs a high level. That is, both input terminals of the second NAND gate A2 are at high levels. Therefore, the second NAND gate A2 outputs a low level, and the output terminal of the second inverter N2 switches from a low level to a high level. So at this time, the control signal OUT switches from a low level to a high level. That is, at this time, the second input terminals of the fourth NAND gate A4 and the sixth NAND gate A6 are input with high levels. Therefore, all three input terminals of the fourth NAND gate A4 are input with high levels. So the fourth NAND gate A4 outputs a low level. This low-level signal is input into the sixth NAND gate A6 and the fifth NAND gate A5. The sixth NAND gate A6 and the fifth NAND gate A5 both output high levels. So at this time, the first OR gate F1 outputs a high level, and the third inverter N3 outputs a low level. At the same time, the low level output by the second NAND gate A2 is input into the tenth NAND gate A10 and the twelfth NAND gate A12. The tenth NAND gate A10 and the twelfth NAND gate A12 output high levels. And because the output terminal of the eleventh NAND gate A11 was in a low-level state before, at this time, the thirteenth NAND gate A13 outputs a high level, the eleventh NAND gate A11 still outputs a low level, and the fourth inverter N4 still outputs a high level.

[0045] As can be seen from the above analysis, when the input signal IN switches from low level to high level, the third inverter N3 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the first NAND gate A1 always outputs a high level to the second NAND gate A2. Also, since the fourth inverter N4 outputs a high level to the second NAND gate A2, therefore, the second NAND gate A2 always outputs a low level, and the second inverter N2 always outputs a high level, that is, the control signal OUT is always at a high level. That is, at this time, the change of the input signal IN does not affect the control signal OUT. At the same time, since the first OR gate F1 outputs a high level, the first switch tube M1 is turned off, and the first capacitor C1 discharges through the second switch tube M2, and the discharge current is equal to , when the terminal voltage of the first capacitor C1 discharges to be lower than the second flip threshold voltage V2 of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14, both the fourth NAND gate A4 and the seventh NAND gate A7 output high levels to the fifth NAND gate A5. The fifth NAND gate A5 outputs a low level to the first OR gate F1 and the third inverter N3. The output terminal of the third inverter N3 switches from low level to high level. The output signal of the first NAND gate A1 is determined by the input signal IN. That is, at this time, the control signal OUT follows the change of the input signal IN. And, since the input voltage of the eighth NAND gate A8 is lower than the second flip threshold voltage V2, the eighth NAND gate A8 outputs a high level. Therefore, at this time, both input terminals of the third NAND gate A3 are at high levels, and the third NAND gate A3 outputs a low level. At the same time, all three input terminals of the sixth NAND gate A6 are at high levels, so the sixth NAND gate A6 outputs a low level. At the same time, both the tenth NAND gate A10 and the thirteenth NAND gate A13 output high levels to the eleventh NAND gate A11. And since the output terminal of the eleventh NAND gate A11 was in a low level state before, the thirteenth NAND gate A13 outputs a high level, and the eleventh NAND gate A11 still outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switch tube M1, and the first switch tube M1 conducts, and the terminal voltage of the first capacitor C1 is instantaneously pulled to a high level. That is, at this time, the input terminals of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 switch back to the high level state again.

[0046] At this time, according to the above analysis, the output of the eleventh NAND gate A11 is still low level, which will not be elaborated here; at the same time, since the output terminal of the third NAND gate A3 was in a low level state before, when the third input terminal of the fourth NAND gate A4 switches back to the high level state, the fourth NAND gate A4 still outputs a high level, and since the output terminal of the sixth NAND gate A6 was in a low level state before, the eighth NAND gate A8 still outputs a high level to the sixth NAND gate A6, that is, at this time, all three input terminals of the sixth NAND gate A6 are at high level, so the sixth NAND gate A6 outputs a low level to the seventh NAND gate A7, and the seventh NAND gate A7 outputs a high level to the fifth NAND gate A5. Therefore, both input terminals of the fifth NAND gate A5 are at high level, and the fifth NAND gate A5 still outputs a low level to the first OR gate F1 and the third inverter N3. Therefore, the output terminal of the third inverter N3 remains at high level, and the control signal OUT changes following the input signal IN. At the same time, the first OR gate F1 outputs a low level, and the first switching transistor M1 is always in the conducting state, and the terminal voltage of the first capacitor C1 is always in the high level state; (2) When the input signal IN is at high level, the first inverter N1 outputs a low level, and the first NAND gate A1 outputs a high level. From the above analysis, the fourth inverter N4 outputs a high level to the second NAND gate A2. Therefore, the second NAND gate A2 outputs a low level, and this low level signal is input into the tenth NAND gate A10 and the twelfth NAND gate A12. The tenth NAND gate A10 and the twelfth NAND gate A12 output high levels. At this time, both input terminals of the fourteenth NAND gate A14 input high levels. Therefore, the fourteenth NAND gate A14 outputs a low level to the ninth NAND gate A9, and the ninth NAND gate A9 outputs a high level to the first input terminal of the tenth NAND gate A10. At the same time, the control signal OUT is a high level signal and is input into the first control circuit. When just powered on, both the eighth NAND gate A8 and the fourth NAND gate A4 output high level signals to the third NAND gate A3. The third NAND gate A3 outputs a low level signal to the fourth NAND gate A4, and the fourth NAND gate A4 outputs a high level signal to the fifth NAND gate A5. And the eighth NAND gate A8 outputs a high level signal to the sixth NAND gate A6. Thus, all three input terminals of the sixth NAND gate A6 input high level signals. Therefore, the sixth NAND gate A6 outputs a low level signal, the seventh NAND gate A7 outputs a high level signal, and the fifth NAND gate A5 outputs a low level signal based on two high level signals. That is, when the input signal of the first end of the first control circuit is a high level signal, it keeps outputting a low level signal.

[0047] When the input signal IN switches from a high level to a low level, that is, when the falling-edge voltage of the input signal IN drops to the first flip threshold voltage V1 of the first inverter N1, the first inverter N1 outputs a high level. From the above analysis, it can be seen that the third inverter N3 outputs a high level to the first NAND gate A1. Therefore, the first NAND gate A1 outputs a low level to the second NAND gate A2, and the second NAND gate A2 outputs a high level. The output terminal of the second inverter N2 switches from a high level to a low level. Thus, at this time, the control signal OUT switches from a high level to a low level. This low level is input into the fourth NAND gate A4 and the sixth NAND gate A6. The fourth NAND gate A4 and the sixth NAND gate A6 output high levels. And because the output terminal of the fifth NAND gate A5 was in a low-level state before, at this time, the seventh NAND gate A7 outputs a high level, the fifth NAND gate A5 still outputs a low level, and the third inverter N3 still outputs a high level. At the same time, the second input terminals of the tenth NAND gate A10 and the twelfth NAND gate A12 input high levels. Therefore, all three input terminals of the tenth NAND gate A10 input high levels, so the tenth NAND gate A10 outputs a low level. This low-level signal is input into the eleventh NAND gate A11 and the twelfth NAND gate A12, and both the eleventh NAND gate A11 and the twelfth NAND gate A12 output high levels. Thus, at this time, the first OR gate F1 outputs a high level, and the fourth inverter N4 outputs a low level.

[0048] From the above analysis, it can be seen that when the input signal IN switches from a high level to a low level, the fourth inverter N4 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 outputs a high level to the second inverter N2, and the second inverter N2 always outputs a low level, that is, the control signal OUT is always at a low level. That is, at this time, the change of the input signal IN does not affect the control signal OUT. At the same time, because the first OR gate F1 outputs a high level, the first switching transistor M1 is turned off, and the first capacitor C1 discharges through the second switching transistor M2, and the discharge current is equal to , when the first capacitor C1 discharges until its terminal voltage is lower than the second flip threshold voltage V2 of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14, both the tenth NAND gate A10 and the thirteenth NAND gate A13 output high levels to the eleventh NAND gate A11. The eleventh NAND gate A11 outputs a low level to the first OR gate F1 and the fourth inverter N4. The output terminal of the fourth inverter N4 switches from a low level to a high level. The output signal of the second NAND gate A2 is determined by the input signal IN. That is, at this time, the control signal OUT changes following the input signal IN. And because the input voltage of the fourteenth NAND gate A14 is lower than the second flip threshold voltage V2, the fourteenth NAND gate A14 outputs a high level. Therefore, at this time, both input terminals of the ninth NAND gate A9 are at high levels, and the ninth NAND gate A9 outputs a low level. At the same time, all three input terminals of the twelfth NAND gate A12 are at high levels. Therefore, the twelfth NAND gate A12 outputs a low level. At the same time, both the fourth NAND gate A4 and the seventh NAND gate A7 output high levels to the fifth NAND gate A5. And because the output terminal of the fifth NAND gate A5 was in a low level state before, the seventh NAND gate A7 outputs a high level, and the fifth NAND gate A5 still outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switching transistor M1, and the first switching transistor M1 conducts. The terminal voltage of the first capacitor C1 is instantaneously pulled to a high level. That is, at this time, the input terminals of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 switch back to the high level state.

[0049] At this time, according to the above analysis, it can be known that the fifth NAND gate A5 still outputs a low level, which will not be elaborated here. At the same time, because the output terminal of the ninth NAND gate A9 was in a low level state before, when the third input terminal of the tenth NAND gate A10 switches back to the high level state, the tenth NAND gate A10 still outputs a high level. And because the output terminal of the twelfth NAND gate A12 was in a low level state before, the fourteenth NAND gate A14 still outputs a high level to the twelfth NAND gate A12. That is, at this time, all three input terminals of the twelfth NAND gate A12 are at high levels. Therefore, the twelfth NAND gate A12 outputs a low level to the thirteenth NAND gate A13, and the thirteenth NAND gate A13 outputs a high level to the eleventh NAND gate A11. Therefore, both input terminals of the eleventh NAND gate A11 are at high levels, and the eleventh NAND gate A11 still outputs a low level to the first OR gate F1 and the fourth inverter N4. Therefore, the output terminal of the fourth inverter N4 remains at a high level, the control signal OUT changes following the input signal IN. At the same time, the first OR gate F1 outputs a low level, the first switching transistor M1 is always in the conducting state, and the terminal voltage of the first capacitor C1 is always in the high level state.

[0050] According to the above analysis of the circuit principle, it can be obtained thatFigure 3 Waveform diagram of the input signal IN and the control signal OUT shown; as Figure 3 shown, when the rising edge voltage of the input signal IN rises to the first flip threshold voltage V1, the control signal OUT switches from low level to high level, and when the falling edge voltage of the input signal IN drops to the first flip threshold voltage V1, the control signal OUT switches from high level to low level, ensuring that the noise on the rising edge of the input signal IN will not be recognized as multiple rising edges, and the noise on the falling edge will not be recognized as multiple falling edges, thereby improving the anti-interference ability, control accuracy and reliability of the circuit.

[0051] In an alternative embodiment, the time T0 for the voltage at the third terminal of the capacitor circuit to discharge from the external power supply voltage to the voltage (i.e., the second flip threshold voltage V2) at which the components in the first control circuit and the second control circuit undergo voltage inversion is expressed by the following formula: max[T1,T3]<T0<min[T1+T2,T3+T4] In the formula, T1 represents the time for the input signal to rise from the first flip threshold voltage to the external power supply voltage on the rising edge, T2 represents the sum of the time when the input signal is at the high-level signal and the time for the input signal to drop from the external power supply voltage to the first flip threshold voltage on the falling edge, T3 represents the time for the input signal to drop from the first flip threshold voltage to the ground voltage on the falling edge; T4 represents the sum of the time when the input signal is at the low-level signal and the time for the input signal to rise from the ground voltage to the first flip threshold voltage on the rising edge.

[0052] Specifically, when the input signal IN switches from low level to high level, the third inverter N3 outputs low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 always outputs low level, and the second inverter N2 always outputs high level, that is, the control signal OUT is always high level. That is, at this time, the change of the input signal IN does not affect the control signal OUT until the first capacitor C1 discharges to a terminal voltage lower than the second flip threshold voltage V2, the output terminal of the third inverter N3 switches from low level to high level, and the output signal of the first NAND gate A1 is determined by the input signal IN. That is, at this time, the control signal OUT changes following the input signal IN; therefore, within the time T0 for the first capacitor C1 to discharge from the external power supply voltage VCC to a terminal voltage lower than the second flip threshold voltage V2, the change of the input signal IN does not affect the control signal OUT. At this time, the time T0 is designed to be greater than the time T1 for the voltage of the input signal IN to rise from V1 to VCC on the rising edge, and less than the time T1 for the voltage of the input signal IN to rise from V1 to VCC on the rising edge plus the time T2 for the external power supply voltage VCC at which the voltage of the input signal IN is at the high level to drop from VCC to V1 on the falling edge.

[0053] Similarly, when the input signal IN switches from high level to low level, the fourth inverter N4 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 outputs a high level to the second inverter N2, and the second inverter N2 always outputs a low level, that is, the control signal OUT is always at a low level. That is, at this time, the change of the input signal IN does not affect the control signal OUT until the first capacitor C1 discharges to a terminal voltage lower than the second flip threshold voltage V2, and the output terminal of the fourth inverter N4 switches from low level to high level. The output signal of the second NAND gate A2 is determined by the input signal IN. That is, at this time, the control signal OUT changes following the input signal IN. Therefore, within the time T0 when the first capacitor C1 discharges from the external power supply voltage VCC to a terminal voltage lower than the second flip threshold voltage V2, the change of the input signal IN does not affect the control signal OUT. At this time, the time T0 is designed to be greater than the time T3 when the voltage of the input signal IN drops from V1 to 0 at the falling edge, and less than the time T3 when the voltage of the input signal IN drops from V1 to 0 at the falling edge plus the time T4 when the voltage of the input signal IN at the low level of the ground voltage GND rises from 0 to V1 at the rising edge.

[0054] Therefore, based on the above two paragraphs of analysis, the time T0 when the first capacitor C1 discharges from the external power supply voltage VCC to a terminal voltage lower than the second flip threshold voltage V2 is designed to be greater than max[T1, T3] and less than min[T1 + T2, T3 + T4]. At this time, by selecting appropriate capacitance value of the first capacitor C1, magnitude of the current I1, and magnitude of the coefficient M, T0 is made to be within the designed range.

[0055] In the present invention, when the rising edge voltage of the input signal IN rises to the first flip threshold voltage V1, the control signal OUT switches from low level to high level. When the falling edge voltage of the input signal IN drops to the first flip threshold voltage V1, the control signal OUT switches from high level to low level, ensuring that the noise at the rising edge of the input signal IN is not recognized as multiple rising edges, and the noise at the falling edge is not recognized as multiple falling edges, thereby improving the anti-interference ability, control accuracy, and reliability of the circuit. At the same time, by selecting appropriate capacitance value of the first capacitor C1, magnitude of the current I1, and magnitude of the coefficient M, it is applicable to control circuits with any cycle time and duty ratio, and the application range of the high-precision anti-interference circuit structure is improved.

[0056] The present invention also provides a battery-powered circuit, as Figure 4 shown, including: an integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip includes the high-precision anti-interference circuit structure of the above embodiment, and the integrated circuit control chip controls the power circuit to supply power to the battery load according to the control signal output by the following circuit.

[0057] In the present invention, by providing the above-mentioned high-precision anti-interference circuit structure in the integrated circuit control chip, the control signal inside the integrated circuit control chip is not interfered by the change of the battery load, thereby improving the accuracy and reliability of the battery charging circuit.

[0058] Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims. Such modifications and variations fall within the scope defined by the appended claims. For other examples, those of ordinary skill in the art should easily understand that the order of the process steps can be changed while maintaining the scope of protection of the present invention.

[0059] In addition, the application scope of the present invention is not limited to the processes, mechanisms, manufacturing, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of the present invention, as those of ordinary skill in the art will readily understand, for the processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps that currently exist or will be developed in the future, and which perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described in the present invention, they can be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacturing, compositions of matter, means, methods, or steps within their scope of protection.

Claims

1. A circuit structure with high precision and anti-interference, characterized in that, Including: A follower circuit, whose first terminal receives an input signal, the second terminal is connected to the first terminal of a first control circuit and the first terminal of a capacitance circuit, the third terminal is connected to the first terminal of a second control circuit and the second terminal of the capacitance circuit, the fourth terminal is connected to the second terminal of the first control circuit, the fifth terminal is connected to the second terminal of the second control circuit, and the fourth terminal is used to output a control signal; A first control circuit, whose third terminal is connected to the third terminal of the capacitance circuit and the third terminal of the second control circuit; A capacitance circuit, whose fourth terminal is connected to an external power supply and whose fifth terminal is grounded; When the input signal is at a rising edge and greater than a first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a high-level control signal. When the capacitance circuit discharges to a second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time the capacitance circuit enters a charging state; When the input signal is at a falling edge and less than the first flip threshold voltage, the control signal output by the follower circuit does not change following the input signal and always outputs a low-level control signal. When the capacitance circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit changes following the input signal, and at the same time the capacitance circuit enters a charging state; Wherein, the first flip threshold voltage is the voltage when the components in the follower circuit have a voltage flip, and the second flip threshold voltage is the voltage when the components in the first control circuit and the second control circuit have a voltage flip.

2. The high-precision anti-interference circuit structure according to claim 1, characterized in that When the input signal is at a rising edge and greater than the first flip threshold voltage, the follower circuit outputs a high-level control signal at the fourth terminal and a low-level signal at the fifth terminal according to the input signal and the low-level signal output by the second control circuit at the previous moment; the second terminal of the first control circuit receives the high-level control signal and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitance circuit was charged at the previous moment and the state of the first control circuit at the previous moment; the second terminal of the second control circuit receives the low-level signal output by the fifth terminal of the follower circuit and outputs a low-level signal at the first terminal according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal; When the input signal is at a falling edge and less than the first flip threshold voltage, the follower circuit outputs a low-level control signal at the fourth terminal and a high-level signal at the fifth terminal according to the input signal and the low-level signal output by the first control circuit at the previous moment; the second terminal of the second control circuit receives the high-level signal output by the fifth terminal of the follower circuit and outputs a high-level signal at the first terminal according to the high-level signal generated after the capacitance circuit was charged at the previous moment and the state of the second control circuit at the previous moment. Under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

3. The high-precision anti-interference circuit structure according to claim 1, wherein: When the input signal is at the rising edge and greater than the first flip threshold voltage, the capacitive circuit enters the discharge state according to the high-level signal output from the first terminal of the first control circuit. When the discharge reaches the second flip threshold voltage, a low-level signal is output. The third terminal of the first control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal. The third terminal of the second control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal. Based on the low-level signals output from the first terminals of the first control circuit and the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit enters the charging state; After the capacitive circuit is charged to the high level, the first terminals of the first control circuit and the second control circuit output low-level signals. Based on the low-level signals output from the first terminals of the first control circuit and the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit maintains the high-level state after charging.

4. The high-precision anti-interference circuit structure according to claim 1, wherein: When the input signal is at the falling edge and less than the first flip threshold voltage, the capacitive circuit enters the discharge state according to the high-level signal output from the first terminal of the second control circuit. When the discharge reaches the second flip threshold voltage, a low-level signal is output. The third terminal of the second control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal. The third terminal of the first control circuit receives the low-level signal generated after the capacitive circuit discharges and outputs a low-level signal at the first terminal. Based on the low-level signals output from the first terminals of the first control circuit and the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit enters the charging state; After the capacitive circuit is charged to the high level, the first terminals of the second control circuit and the first control circuit output low-level signals. Based on the low-level signals output from the first terminals of the first control circuit and the second control circuit, the control signal output by the follower circuit changes following the input signal. At the same time, the capacitive circuit maintains the high-level state after charging.

5. The high-precision anti-interference circuit structure according to claim 1, wherein: When the circuit is just powered on and the input signal is a low-level signal, the first control circuit and the second control circuit output low-level signals at the first terminals respectively according to the capacitive circuit in the initial state. The capacitive circuit enters the charging state according to the low-level signals output by the first control circuit and the second control circuit. The follower circuit outputs a low-level control signal at the fourth terminal according to the input signal and the low-level signal output by the first control circuit.

6. The high-precision anti-interference circuit structure according to claim 1, wherein, When the circuit is just powered on and the input signal is a high-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first end according to the capacitive circuit in the initial state, and the capacitive circuit enters the charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a high-level control signal at the fourth end according to the input signal and the low-level signal output by the second control circuit.

7. The high-precision anti-interference circuit structure according to claim 1, characterized in that, The follower circuit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate; The input end of the first inverter receives the input signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the third inverter, the input end of the third inverter is connected to the first end of the first control circuit and the first end of the capacitive circuit, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the first end of the second control circuit and the second end of the capacitive circuit, the output end of the second NAND gate is connected to the input end of the second inverter and the second end of the second control circuit, and the output end of the second inverter is connected to the second end of the first control circuit and outputs a control signal.

8. The high-precision anti-interference circuit structure according to claim 1, wherein The first control circuit includes: a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; The first input end of the third NAND gate is connected to the output end of the eighth NAND gate and the third input end of the sixth NAND gate, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the first input end of the fifth NAND gate, and the first input end of the sixth NAND gate, the output end of the third NAND gate is connected to the first input end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the second input end of the sixth NAND gate and the fourth end of the follower circuit, the third input end of the fourth NAND gate is connected to the second input end of the eighth NAND gate, the third input end of the seventh NAND gate, the third end of the capacitive circuit, and the third end of the second control circuit, the second input end of the fifth NAND gate is connected to the output end of the seventh NAND gate, the output end of the fifth NAND gate is connected to the first input end of the seventh NAND gate, the second end of the follower circuit, and the first end of the capacitive circuit, and the output end of the sixth NAND gate is connected to the second input end of the seventh NAND gate and the first input end of the eighth NAND gate.

9. The high-precision anti-interference circuit structure according to claim 1, characterized in that The second control circuit includes: a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, and a fourteenth NAND gate; The first input terminal of the ninth NAND gate is connected to the output terminal of the fourteenth NAND gate and the third input terminal of the twelfth NAND gate. The second input terminal of the ninth NAND gate is connected to the output terminal of the tenth NAND gate, the first input terminal of the eleventh NAND gate, and the first input terminal of the twelfth NAND gate. The output terminal of the ninth NAND gate is connected to the first input terminal of the tenth NAND gate. The second input terminal of the tenth NAND gate is connected to the second input terminal of the twelfth NAND gate and the fifth terminal of the following circuit. The third input terminal of the tenth NAND gate is connected to the second input terminal of the fourteenth NAND gate, the third input terminal of the thirteenth NAND gate, the third terminal of the capacitor circuit, and the third terminal of the first control circuit. The second input terminal of the eleventh NAND gate is connected to the output terminal of the thirteenth NAND gate. The output terminal of the eleventh NAND gate is connected to the first input terminal of the thirteenth NAND gate, the third terminal of the following circuit, and the second terminal of the capacitor circuit. The output terminal of the twelfth NAND gate is connected to the second input terminal of the thirteenth NAND gate and the first input terminal of the fourteenth NAND gate.

10. The high-precision anti-interference circuit structure according to claim 1, characterized in that The capacitor circuit includes: a first OR gate, a first capacitor, a first switching transistor, a second switching transistor, a third switching transistor, and a first current source; The first input terminal of the first OR gate is connected to the first terminal of the first control circuit and the second terminal of the following circuit. The second input terminal of the first OR gate is connected to the first terminal of the second control circuit and the third terminal of the following circuit. The output terminal of the first OR gate is connected to the first terminal of the first switching transistor. The second terminal of the first switching transistor is connected to one end of the first current source and an external power supply. The third terminal of the first switching transistor is connected to one end of the first capacitor, the first terminal of the second switching transistor, the third terminal of the first control circuit, and the third terminal of the second control circuit. The other end of the first capacitor is connected to the second terminal of the second switching transistor, the first terminal of the third switching transistor, and is grounded. The third terminal of the second switching transistor is connected to the second terminal, the third terminal of the third switching transistor, and the other end of the first current source.

11. The circuit structure with high precision and anti-interference according to claim 1, characterized in that, The time T0 for the capacitor circuit to discharge to the second flip threshold voltage is expressed by the following formula: max[T1,T3]<T0<min[T1+T2,T3+T4] Wherein, T1 represents the time for the input signal to rise from the first flip threshold voltage to the external power supply voltage at the rising edge. T2 represents the sum of the time when the input signal is at the high-level signal and the time for the input signal to drop from the external power supply voltage to the first flip threshold voltage at the falling edge. T3 represents the time for the input signal to drop from the first flip threshold voltage to the ground voltage at the falling edge. T4 represents the sum of the time when the input signal is at the low-level signal and the time for the input signal to rise from the ground voltage to the first flip threshold voltage at the rising edge. The voltage of the high-level signal is equal to the external power supply voltage, and the voltage of the low-level signal is equal to the ground voltage.

12. A battery-powered circuit, characterized in that, Including: An integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip includes the high-precision anti-interference circuit structure according to any one of claims 1-11. The integrated circuit control chip controls the power circuit to supply power to the battery load according to the control signal output by the following circuit.

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