Buck converter and electronic device including same

Abstract

The invention provides a buck converter and an electronic device. The buck converter generates an output voltage from an input voltage in response to a switching signal, compares the output voltage to a reference voltage during an activation time interval of the switching signal, and compares a sum of the output voltage and a voltage reflecting a current flowing through the inductor to the reference voltage during a deactivation time interval of the switching signal. Even if the load current is changed, the accurate output voltage can be generated, and the fast transient response characteristic can be obtained.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0001453, filed with the Korean Intellectual Property Office (KIPO) on January 4, 2024, and Korean Patent Application No.

[0003] 10 - 2024 - 0034865, filed with the Korean Intellectual Property Office (KIPO) on March 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0004] Some example embodiments generally relate to voltage converters, and more particularly, to a buck converter configured to generate an accurate and stable output voltage, and an electronic device including the buck converter. Background art

[0005] An electronic device may include various semiconductor devices, and each of the semiconductor devices may require an appropriate direct current (DC) voltage. The electronic device may also include a semiconductor device referred to as a power management integrated circuit (PMIC) for generating the DC voltage required for each semiconductor device. The PMIC may include at least one DC - DC converter that generates an output DC voltage desired by at least one semiconductor device based on an input DC voltage. A buck converter, which is a type of DC - DC converter (e.g., a switching regulator), may generate an output voltage having a voltage level lower than the input voltage. Research has been conducted to improve the accuracy of the output voltage regardless of the load current and to improve the transient response characteristics when the load current changes. Summary of the invention

[0006] Some example embodiments of the present disclosure provide a buck converter that can improve the accuracy of the output voltage regardless of the load current and can generate a stable output voltage in a relatively short time even when the load current changes rapidly.

[0007] Some example embodiments of the present disclosure provide an electronic device including a buck converter.

[0008] Some example embodiments provide a buck converter that includes a power switch circuit, a low-pass filter, a first resistor, a capacitor, a switch, a comparator, and an SR latch. The power switch circuit alternately transfers an input voltage and a ground voltage to an output terminal based on a switch signal. The low-pass filter includes an inductor having a first end connected to the output terminal and a second end connected to a load capacitor, and the inductor generates an output voltage at the second end. The first resistor and the capacitor are connected in series between the output terminal and the second end of the inductor. The switch is located between a common node and the second end of the inductor. The common node is connected to the first resistor and the capacitor. The comparator generates a comparison signal by comparing a sensed voltage at the common node with a reference voltage. The SR latch receives the comparison signal as a set signal, receives a delay signal as a reset signal, and generates the switch signal based on the comparison signal and the delay signal. The delay signal is activated after the comparison signal is activated. During an activation time interval of the switch signal, the switch electrically connects the common node and the second end of the inductor.

[0009] Some example embodiments also provide a buck converter that includes a power switch circuit, a low-pass filter, a first resistor, a first capacitor, a switch, a first comparator, a delay circuit, and a first SR latch. The power switch circuit alternately transfers an input voltage and a ground voltage to an output terminal based on a switch signal. The low-pass filter includes an inductor having a first end connected to the output terminal and a second end connected to a load capacitor, and the inductor generates an output voltage at the second end. The first resistor and the first capacitor are connected in series between the output terminal and the second end of the inductor. The switch is located between a common node and the second end of the inductor. The common node is connected to the first resistor and the first capacitor. The first comparator generates a first comparison signal by comparing a sensed voltage at the common node with a first reference voltage. The delay circuit generates a delay signal by delaying the first comparison signal. The first SR latch receives the first comparison signal as a set signal, receives the delay signal as a reset signal, and generates the switch signal based on the first comparison signal and the delay signal. The first SR latch activates the switch signal when the first comparison signal is activated and deactivates the switch signal when the delay signal is activated. The switch electrically connects the common node and the second end of the inductor during an activation time interval of the switch signal and electrically disconnects the common node from the second end of the inductor during a deactivation time interval of the switch signal.

[0010] Some example embodiments also provide an electronic device, which includes a first semiconductor chip, an inductor, a load capacitor, and a second semiconductor chip. The first semiconductor chip includes a power switch circuit, a sense voltage generator, and a switch signal generator. The power switch circuit alternately transfers an input voltage and a ground voltage to an output terminal based on a switch signal having an active time interval and a deactive time interval. The sense voltage generator generates a sense voltage. The switch signal generator generates a switch signal based on the sense voltage. The inductor and the load capacitor generate an output voltage by low-pass filtering a voltage at the output terminal. The second semiconductor chip receives the output voltage as a power supply voltage. During the active time interval of the switch signal, the sense voltage generator generates a sense voltage equal to the output voltage. During the deactive time interval of the switch signal, the sense voltage generator generates a sense voltage equal to the sum of the output voltage and a voltage reflecting a current flowing through the output terminal.

[0011] In a buck converter according to some example embodiments, an accurate and stable output voltage can be generated regardless of a load current, and even when the load current rapidly changes, a stable output voltage can be generated within a relatively short time. Accordingly, the overall performance of the buck converter can be improved or enhanced.

[0012] In an electronic device including a buck converter according to some example embodiments, an accurate and stable output voltage can be provided from the buck converter to a load device. Accordingly, the performance of the electronic device can be always ensured regardless of the load current. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Exemplary, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the drawings.

[0014] Figure 1 is a block diagram showing a DC-DC converter according to some example embodiments.

[0015] Figure 2 is a circuit diagram showing a buck converter according to some example embodiments.

[0016] Figure 3 is a diagram showing Figure 2 the operation of the buck converter in a steady state with a constant load current in a timing diagram.

[0017] Figure 4 is a diagram showing Figure 2 the operation of the buck converter in a state of transitioning from a small load current to a large load current in a timing diagram.

[0018] Figure 5 is a diagram showing Figure 2Timing diagram of the operation of the buck converter in the state of transitioning from a large load current to a small load current.

[0019] Figure 6A is a circuit diagram showing Figure 2 an example of the delay circuit in

[0020] Figure 6B is a diagram for describing Figure 2 the operation of the delay circuit in

[0021] Figure 7A is a circuit diagram showing Figure 2 an example of the delay circuit in

[0022] Figure 7B is a diagram for describing Figure 2 the operation of the delay circuit in

[0023] Figure 8 is a circuit diagram showing a buck converter according to some example embodiments.

[0024] Figure 9 is a block diagram showing an electronic device including a buck converter according to some example embodiments. Detailed Description

[0025] Some example embodiments will be described more fully with reference to the accompanying drawings. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals refer to like elements.

[0026] When the terms "about" or "substantially" are used in combination with a numerical value in this specification, it is intended that the associated numerical value includes manufacturing or operating tolerances near the stated value (e.g., ±10%). Further, when the words "about" and "substantially" are used in combination with a geometry, it is intended that the precision of the geometry is not required, but rather the latitude of the shape is within the scope of the present disclosure. Additionally, whether the numerical value or shape is modified by "about" or "substantially", it is understood that these values and shapes should be interpreted as including manufacturing or operating tolerances near the stated numerical value or shape (e.g., ±10%). When a range is specified, the range includes all values therebetween such as increments of 0.1%.

[0027] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "selected from at least one of the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0028] Figure 1is a block diagram showing a DC-DC converter according to some example embodiments.

[0029] Referring Figure 1 , the DC-DC converter may include a semiconductor chip 101 and a low-pass filter (or LC filter) 20. For example, the semiconductor chip 101 and the low-pass filter 20 may be mounted on a printed circuit board (PCB) (not shown). For example, the DC-DC converter 100 may be electrically connected to a load device (not shown) that consumes a load current I LOAD and may supply the load current I LOAD to the load device. For example, the DC-DC converter 100 may be a buck converter that reduces an input voltage Vin by using the semiconductor chip 101 and the low-pass filter 20 to generate an output voltage Vout, and the voltage level of the output voltage Vout may be lower than the voltage level of the input voltage Vin. The detailed configuration of the buck converter will be described with reference to Figure 2 the following.

[0030] The semiconductor chip 101 may include input terminals T1 and T2, an output terminal T3, a feedback terminal T4, a power switch circuit 10, a sense voltage generator 30, and a switch signal generator 40.

[0031] The input terminals T1 and T2 may supply the input voltage Vin and the ground voltage Vss to the semiconductor chip 101, respectively. The power switch circuit 10 may alternately transfer (or send) the input voltage Vin and the ground voltage Vss to the output terminal T3 in response to a switch signal PS. For example, the switch signal PS may be a pulse signal including repeatedly arranged active time intervals and deactive time intervals.

[0032] The sense voltage generator 30 may include a capacitor C1 and may generate a sense voltage (or detection voltage) V C1 based on the switch signal PS, the voltage V A across the capacitor C1, and the output voltage Vout. The voltage V C1 across the capacitor C1 may be obtained by reflecting the current flowing through the output terminal T3 and may be referred to as the capacitor voltage. The output voltage Vout may be received through the feedback terminal T4. For example, the current flowing through the output terminal T3 may be substantially equal to the inductor current (e.g., Figure 2 the inductor current I L ) in Figure 2 or substantially the same as the inductor current (e.g., L ) in the inductor L included in the low-pass filter 20. For example, the current flowing through the output terminal T3 may include the load current I LOADThe DC component and the AC component of the coupled current generated on the switching signal PS.

[0033] The switching signal generator 40 can generate the switching signal PS by comparing the sensed voltage V A with the first reference voltage Vref1. The switching signal PS generated by the switching signal generator 40 can be activated when the sensed voltage V A is equal to or lower than the first reference voltage Vref1, can remain activated for a desired (and / or alternatively, predetermined) time interval, and can then be deactivated. For example, the desired (and / or alternatively, predetermined) time interval during which the switching signal PS remains activated can be determined by Figure 2 the delay circuit D1 in.

[0034] Hereinafter, signal activation can represent a signal transition from a logic low level to a logic high level, and signal deactivation can represent a signal transition from a logic high level to a logic low level. However, some example embodiments are not limited thereto. In some example embodiments, signal activation can represent a signal transition from a logic high level to a logic low level, and signal deactivation can represent a signal transition from a logic low level to a logic high level.

[0035] The sensed voltage generator 30 can output the output voltage Vout as the sensed voltage V during the activation time interval of the switching signal PS (or when the switching signal PS is activated) A and can output the sum of the output voltage Vout and the voltage V across the capacitor C1 as the sensed voltage V during the deactivation time interval of the switching signal PS (or when the switching signal PS is deactivated) C1 The power switch circuit 10 can transfer the input voltage Vin to the output terminal T3 during the activation time interval of the switching signal PS and can transfer the ground voltage Vss to the output terminal T3 during the deactivation time interval of the switching signal PS. A The low-pass filter 20 can include an inductor L and a load capacitor C

[0036] and can generate the output voltage Vout by smoothing the voltage transferred to the output terminal T3 and can transfer the output voltage Vout to the load device. L In the DC-DC converter 100 according to some example embodiments, during the activation time interval of the switching signal PS, the voltage V across the capacitor C1 can be reset, and the DC component of the inductor current I

[0037] can be limited and / or prevented or suppressed from causing the voltage V across the capacitor C1 C1 to change, and the DC component of the voltage V across the capacitor C1 can be limited and / or prevented or suppressed from being caused by the DC component of the inductor current I L across the capacitor C1. C1changes. Therefore, based on the voltage V across the capacitor C1 C1 the generated sensed voltage V A can accurately reflect the state of the output voltage Vout, and can improve or enhance the accuracy of the output voltage Vout according to the load current I LOAD Even if the load current I LOAD changes rapidly, the output voltage Vout can be stabilized within a relatively fast response time.

[0038] Figure 2 is a circuit diagram showing a buck converter according to some example embodiments.

[0039] Referring to Figure 2 , the buck converter 100_1 may include a power switch circuit 10, a low-pass filter 20, a sensed voltage generator 30, and a switching signal generator 40.

[0040] The buck converter 100_1 may be Figure 1 an example of the DC-DC converter 100. For example, the DC-DC converter according to some example embodiments may be a buck converter. Compared with Figure 1 , the same reference numerals refer to the same elements. For the sake of brevity, the descriptions repeated or duplicated with Figure 1 will be omitted.

[0041] The power switch circuit 10 may include a drive circuit 10_1, a first power switch PS0, and a second power switch PS1.

[0042] The drive circuit 10_1 may generate a signal S1 and a signal S2 in response to the switching signal PS. The signal S1 may be used to turn on the first power switch PS0 during the active time interval of the switching signal PS, and the signal S2 may be used to turn on the second power switch PS1 during the deactivation time interval of the switching signal PS.

[0043] The first power switch PS0 may be turned on during the active time interval of the switching signal PS in response to the signal S1, and may transfer the input voltage Vin to the output terminal T3. The second power switch PS1 may be turned on during the deactivation time interval of the switching signal PS in response to the signal S2, and may transfer the ground voltage Vss to the output terminal T3. In Figure 2 and the subsequent drawings, three parallel straight lines with different lengths connected to the second power switch PS1 may represent the ground voltage Vss.

[0044] Although Figure 2It is shown that the first power switch PS0 and the second power switch PS1 are n-type metal oxide semiconductor (NMOS) transistors, but some example embodiments are not limited thereto. For example, the first power switch PS0 can be replaced with a p-type metal oxide semiconductor (PMOS) transistor.

[0045] The low-pass filter 20 may include an inductor L and a load capacitor C L . For example, the inductor L can be modeled as including a first resistor R1 connected in series with the inductor L, and the load capacitor C L can be modeled as including a second resistor R2 connected in series with the load capacitor C L .

[0046] The first resistor R1 can be a modeling element of the direct current resistor (DCR) of the coil constituting the inductor (L). The second resistor R2 can be a modeling element of the equivalent series resistor (ESR) inside the dielectric of the load capacitor C L . The first resistor R1 and the second resistor R2 may not be included in the actual product (for example, the first resistor R1 and the second resistor R2 may be parasitic components). Since the resistance of the first resistor R1 is used to determine the voltage V across the capacitor C1 in the sense voltage generator 30 C1 , the first resistor R1 can be shown in Figure 2 .

[0047] Hereinafter, when describing the physical connection of the inductor L in the buck converter 100_1, the first resistor R1 will be described as non-existent. For example, the first end (or one end) of the inductor L can be connected to the output terminal T3, and the second end (or the other end) of the inductor L can be connected to one end of the load capacitor C L to provide the output voltage Vout to the load device.

[0048] The sense voltage generator 30 may include a third resistor R3, a capacitor C1, and a switch TG.

[0049] The third resistor R3 and the capacitor C1 can be connected in series between the output terminal T3 and the second end of the inductor L, and can form an RC filter. The voltage V C1 reflecting the current flowing through the inductor L can be stored in the capacitor C1. For example, the series-connected third resistor R3 and capacitor C1 can be connected in parallel with the inductor L. For example, the voltage V across the capacitor C1 can be obtained based on Equation 1 C1 .

[0050] [Equation 1]

[0051]

[0052] In Equation 1, V C1 represents the voltage across capacitor C1, I L represents the inductor current flowing through inductor L, R1 represents the resistance of the first resistor R1 (e.g., an equivalent series resistor, a modeling resistor, or a parasitic resistor connected in series with inductor L), s represents the Laplace variable, L represents the inductance of inductor L, R3 represents the resistance of the third resistor R3, and C1 represents the capacitance of capacitor C1. If the value of L / R1 and the value of R3C1 are selected to be the same value, the voltage V across capacitor C1 C1 can be proportional to the inductor current I L proportional.

[0053] Switch TG can be set at or located between the second end of inductor L and the common node CN, and the common node CN is commonly connected to the third resistor R3 and capacitor C1. Switch TG can electrically connect or disconnect the common node CN from the second end of inductor L in response to the switch signal PS. For example, switch TG can include a transmission gate.

[0054] The switch signal generator 40 can include a comparator CP1, a delay circuit D1, and a first SR latch L1.

[0055] Comparator CP1 can generate or output a comparison signal CS1 by comparing the sensed voltage V at the common node CN A and the first reference voltage Vref1. For example, the comparison signal CS1 can be activated when the sensed voltage V A is equal to or less than the first reference voltage Vref1, and can be deactivated when the sensed voltage V A is higher than the first reference voltage Vref1.

[0056] The delay circuit D1 can generate a delay signal DCS1, which is activated after the comparison signal CS1 is activated.

[0057] The first SR latch L1 can receive the comparison signal CS1 as a set signal, can receive the delay signal DCS1 as a reset signal, and can generate the switch signal PS based on the comparison signal CS1 and the delay signal DCS1. The switch signal PS can be activated in response to the activation of the comparison signal CS1, and can then be deactivated in response to the activation of the delay signal DCS1.

[0058] In some example embodiments, the activation time interval of the switching signal PS can be determined according to the delay time of the delay circuit D1. For example, the delay time of the delay circuit D1 can vary or change according to the voltage level of the input voltage Vin and / or the voltage level of the output voltage Vout during the operation of the buck converter 100_1. For example, the delay time of the delay circuit D1 can be fixed regardless of the voltage level of the input voltage Vin. Reference will be made to Figure 6A , Figure 6B , Figure 7A and Figure 7B to describe the detailed configuration and operation of the delay circuit D1.

[0059] The switching signal PS generated by the switching signal generator 40 can be transmitted to the power switching circuit 10 and the switch TG.

[0060] During the activation time interval of the switching signal PS, the first power switch PS0 in the power switching circuit 10 can transmit the input voltage Vin to the output terminal T3 to increase the inductor current I L . During the deactivation time interval of the switching signal PS, the second power switch PS1 in the power switching circuit 10 can transmit the ground voltage Vss to the output terminal T3 to decrease the inductor current I L .

[0061] During the activation time interval of the switching signal PS, the switch TG can electrically connect the common node CN to the second end of the inductor L, and can reset the voltage V L across the capacitor C1 through the inductor current I C1 , and can maintain the voltage V C1 across the capacitor C1 at approximately 0V. Therefore, during the activation time interval of the switching signal PS, the sensed voltage V A can be substantially equal to the output voltage Vout (e.g., V A = Vout). During the deactivation time interval of the switching signal PS, the switch TG can electrically disconnect the common node CN from the second end of the inductor L. Therefore, during the deactivation time interval of the switching signal PS, the sensed voltage V A can be obtained as the sum of the voltage V C1 across the capacitor C1 and the output voltage Vout (e.g., V A = Vout + V C1 ).

[0062] The buck converter 100_1 can remove the inductor current I C1 by resetting the voltage V L across the capacitor C1 during the activation time interval of the switching signal PS.The DC component, and thus the accuracy of the output voltage Vout can be increased by accurately reflecting the state of the output voltage Vout in the sense voltage V A For example, the accuracy of the output voltage Vout can be increased in continuous current mode (CCM) and / or discontinuous current mode (DCM). In continuous current mode, a relatively large load current is consumed in the load device, and in discontinuous current mode, a relatively small load current is consumed in the load device.

[0063] The buck converter 100_1 can, during the deactivation time interval of the switch signal PS, sense the output voltage Vout and the inductor current I L to obtain the sense voltage V A and compare it with the first reference voltage Vref1. Thus, even if the load current I LOAD changes rapidly, the output voltage Vout can be stably generated in a relatively short time.

[0064] Hereinafter, the operation of the buck converter 100_1 will be described with reference to Figure 3 、 Figure 4 and Figure 5 in various operating states. Figure 2 FIG.

[0065] Figure 3 is a timing diagram showing the operation of the buck converter 100_1 in a steady state with a constant load current. Figure 2 FIG.

[0066] Referring to Figure 3 shows an example of the load current I Figure 2 in LOAD 、the inductor current I L 、the first reference voltage Vref1, the sense voltage V A 、the output voltage Vout, the voltage V C1 across the capacitor C1, and the switch signal PS. The operation of the buck converter according to some example embodiments will be described with reference to Figure 2 and Figure 3 FIG.

[0067] The comparator CP1 can compare the first reference voltage Vref1 with the sense voltage V A and, when the sense voltage V AWhen it becomes equal to the first reference voltage Vref1, the comparison signal CS1 can be activated at time point t1. The first SR latch L1 can activate the switch signal PS in response to the activated comparison signal CS1, can maintain the activated state of the switch signal PS during the delay time tD, and can deactivate the switch signal PS in response to the delay signal DCS1 after the delay time tD has elapsed since time point t1.

[0068] The switch TG can electrically connect the common node CN and the second end of the inductor L in response to the activated switch signal PS, can reset the voltage V across the capacitor C1 to approximately 0V, and can hold the voltage V across the capacitor C1 at approximately 0V during the delay time tD, which is the time interval during which the switch signal PS is activated. For example, during the activation time interval of the switch signal PS (e.g., from time point t1 to time point t2), the sensed voltage V C1 can have a voltage level that is substantially the same as the voltage level of the output voltage Vout (e.g., V C1 = Vout). A can have a voltage level that is substantially the same as the voltage level of the output voltage Vout (e.g., V A = Vout).

[0069] During the deactivation time interval of the switch signal PS (e.g., from time point t2 to time point t3), the switch TG can electrically disconnect the common node CN from the second end of the inductor L in response to the deactivated switch signal PS, and as the inductor current I L decreases, the voltage V across the capacitor C1 C1 can be lower than approximately 0V, and can be expressed as Equation 1. For example, during the deactivation time interval of the switch signal PS, the voltage level of the sensed voltage V A can be substantially equal to the sum of the voltage V across the capacitor C1 C1 and the output voltage Vout (e.g., V A = Vout + V C1 ).

[0070] As the voltage V across the capacitor C1 C1 decreases, the sensed voltage V A can decrease. At the time point t3 when the sensed voltage V A is equal to the first reference voltage Vref1, the comparator CP1 can activate the switch signal PS again.

[0071] During the activation time interval of the switch signal PS (e.g., from time point t1 to time point t2), the power switch circuit 10 can turn on the first power switch PS0 to apply the input voltage Vin to the output terminal T3, and can increase the inductor current I flowing through the inductor L Lto increase the output voltage Vout. During the deactivation time interval of the switching signal PS (e.g., from time point t2 to time point t3), the power switch circuit 10 may turn on the second power switch PS1 to apply the ground voltage Vss to the output terminal T3, and may decrease the inductor current I flowing through the inductor L L to decrease the output voltage Vout.

[0072] Figure 4 is a timing diagram showing Figure 2 the operation of the buck converter 100_1 in a state of transitioning from a small load current to a large load current.

[0073] Referring to Figure 4 shows Figure 2 the load current I in LOAD the inductor current I L the first reference voltage Vref1, the sense voltage V A the output voltage Vout, the voltage V across the capacitor C1 C1 and an example of the switching signal PS. The operation of the buck converter according to some example embodiments will be described with reference to Figure 2 Figure 3 and Figure 4 When the load current I

[0074] changes from a relatively small load current to a relatively large load current, the output voltage Vout may decrease due to the relatively large load current. When the sense voltage V LOAD becomes equal to the first reference voltage Vref1, the comparator CP1 may activate the comparison signal CS1 at the time point t4, and the first SR latch L1 may generate a switching signal PS in the form of a pulse with an activation time interval equal to the delay time tD. During the time interval from the time point t4 to the time point t5, the switching signal PS may be activated more frequently than the switching signal PS in the A steady state, thereby increasing the inductor current I Figure 3 more. L Thus, the undershoot of the output voltage Vout can be limited and / or prevented, and the output voltage Vout can be stabilized in a relatively short time.

[0075] Figure 5 is a timing diagram showing Figure 2 the operation of the buck converter 100_1 in a state of transitioning from a large load current to a small load current.

[0076] Referring to Figure 5 shows Figure 2 the load current I in LOAD the inductor current I L ​, the first reference voltage Vref1, the sense voltage V A , the output voltage Vout, the voltage V across the capacitor C1 C1 and an example of the switch signal PS. Reference will be made to Figure 2 , Figure 3 and Figure 5 to describe the operation of the buck converter according to some example embodiments.

[0077] Starting from the time point t6 when the load current I LOAD changes or transitions from a relatively large load current to a relatively small load current, the output voltage Vout can start to increase. At the time point t7 when the sense voltage V A becomes equal to the first reference voltage Vref1, the comparator CP1 can activate the comparison signal CS1, where the sense voltage V A is the sum of the output voltage Vout and the voltage V across the capacitor C1 during the deactivation time interval of the switch signal PS, and the first SR latch L1 can generate the switch signal PS with an activation time interval equal to the delay time tD in the form of a pulse. During the time interval from the time point t6 to the time point t7, the deactivation time interval of the switch signal PS can be longer than C1 the deactivation time interval of the switch signal PS in the steady state of Figure 3 thereby reducing the inductor current I L . Therefore, the overshoot of the output voltage Vout can be limited and / or prevented, and the output voltage Vout can be stabilized within a relatively short time.

[0078] Figure 6A is a circuit diagram showing an example of the delay circuit D1 in Figure 2 . Figure 6B is a diagram for describing Figure 2 the operation of the delay circuit D1 in

[0079] Referring to Figure 6A and Figure 6B , the delay circuit 601 can include a flip-flop FF, a current source 61, a capacitor C2, a comparator CP2, an SR latch L2, and a delay unit D2.

[0080] The flip-flop FF can generate a signal S3 based on the comparison signal CS1 and the delay signal DCS1. For example, the signal S3 can be activated when the comparison signal CS1 is activated and the switch signal PS is deactivated, and can be deactivated when the delay signal DCS1 is activated.

[0081] The current source 61 can generate a current of A*Vin / R that is proportional to the input voltage Vin. The capacitor C2 can generate a ramp voltage Vramp by accumulating the current from the current source 61 during the activation time interval of the signal S3. The switches SW1 and SW2 can be arranged between the current source 61 and the capacitor C2. For example, the connection and / or disconnection of the current source 61 and the capacitor C2 can be controlled by the switches SW1 and SW2, such that the current from the current source 61 is accumulated in the capacitor C2 during the activation time interval of the signal S3, and the capacitor C2 is discharged during the deactivation time interval of the signal S3.

[0082] The comparator CP2 can generate a comparison signal CS2 by comparing the ramp voltage Vramp with a second reference voltage Vref2. For example, the second reference voltage Vref2 can be A*Vt that is proportional to the target output voltage (Vt) of the buck converter. For example, the proportionality coefficient (e.g., A) of the current source 61 to the input voltage Vin and the proportionality coefficient (e.g., A) of the second reference voltage Vref2 to the target output voltage Vt can be equal to each other.

[0083] The SR latch L2 can receive the comparison signal CS2 as a set signal, and can generate a delayed signal DCS1 based on the comparison signal CS2. For example, the delayed signal DCS1 can be activated when the comparison signal CS2 is activated. Figure 2 The SR latch L1 in can deactivate the switch signal PS in response to the activation of the delayed signal DCS1.

[0084] The delay unit D2 can generate a signal DS3 based on the signal S3. To delay the deactivation transmission of the signal S3, the delay unit D2 can include inverters, each of which includes a capacitor Cd, a resistor Rd, and transistors TR1 and TR2. For example, the signal DS3 can have a phase that is generally opposite to the phase of the signal S3. Compared with the length of the activation time interval of the signal S3, the length of the deactivation time interval of the signal DS3 can increase the time interval Ta, and the time interval Ta can be determined by the delay components of the capacitor Cd and the resistor Rd included in the delay unit D2. The signal DS3 can be input to the SR latch L2 as a reset signal, and the SR latch L2 can generate a delayed signal DCS1 based on the signal DS3. For example, when the signal DS3 is activated, the SR latch L2 can deactivate the delayed signal DCS1. The delay components of the capacitor Cd and the resistor Rd included in the delay unit D2 can ensure a minimum activation time interval Ta of the delayed signal DCS1. For example, the minimum activation time interval Ta of the delayed signal DCS1 can be used to ensure a minimum deactivation time interval of the switch signal PS and a minimum conduction time interval of the second power switch PS1 included in the Figure 2 power switch circuit 10.

[0085] The delay time (e.g., the activation time interval Ton of the switching signal PS) determined by Figure 6A the delay circuit 601 can be obtained based on Equation 2.

[0086] [Equation 2]

[0087]

[0088] In Equation 2, Ton represents the activation time interval of the switching signal PS, Vout represents the output voltage of the buck converter, Vin represents the input voltage, R represents the resistance of the current source 61, and C2 represents the capacitance of the capacitor C2. The activation time interval Ton of the switching signal PS can be changed according to the input voltage Vin, the output voltage Vout, the resistance of the current source 61, and the capacitance of the capacitor C2.

[0089] As described with reference to Figure 6A the delay circuit 601, a control scheme for controlling, adjusting, and / or changing the activation time interval of the switching signal PS at least according to the voltage level of the input voltage Vin can be referred to as an Adaptive On-Time (AOT) scheme.

[0090] Figure 7A is a circuit diagram showing Figure 2 an example of the delay circuit D1 in Figure 7B is a diagram for describing Figure 2 the operation of the delay circuit D1 in

[0091] Referring to Figure 7A and Figure 7B , the delay circuit 701 can include a flip-flop FF, a current source 71, a capacitor C2, a comparator CP2, an SR latch L2, and a delay unit D2.

[0092] Except for changing the configuration of the current source 71, Figure 7A the delay circuit 701 in Figure 7B and the related operations shown in Figure 6A the delay circuit 601 in Figure 6B and the related operations shown in Figure 6A and Figure 6B are substantially the same. For the sake of brevity, the descriptions that are repetitive or overlapping with

[0093] Unlike the current source 61 in Figure 6A , the current source 71 in Figure 7A can generate a constant current I BIAS , regardless of the input voltage Vin. For example, by Figure 7AThe delay time determined by the delay circuit 701 (e.g., the activation time interval Ton of the switching signal PS) can be fixed regardless of the change in the input voltage Vin.

[0094] As described with reference to Figure 7A the delay circuit 701, the control scheme with a fixed activation time interval of the switching signal PS can be referred to as a constant on-time (COT) scheme.

[0095] Figure 8 is a circuit diagram showing a buck converter according to some example embodiments.

[0096] Referring to Figure 8 , the buck converter 100_2 can include a power switch circuit 10, a low-pass filter 20, a sense voltage generator 30, and a switching signal generator 40, and can also include resistors R5, R6, R7, and R8.

[0097] In addition to Figure 8 the buck converter 100_2 further includes resistors R5, R6, R7, and R8, Figure 8 the buck converter 100_2 can be substantially the same as Figure 2 the buck converter 100_1. For the sake of brevity, the descriptions that are repeated or overlapped with Figure 2 will be omitted.

[0098] Resistors R5 and R6 can be connected in series between the output terminal T3 and the ground voltage Vss, and resistors R7 and R8 can be connected in series between the second end of the inductor L and the ground voltage Vss. The first end of the third resistor R3 can be connected to the common node CN2, which is commonly connected to resistors R5 and R6, and the first end of the capacitor C1 can be connected to the common node CN3, which is commonly connected to resistors R7 and R8. For example, the resistances of resistors R5, R6, R7, and R8 can be substantially equal to each other.

[0099] The sense voltage generator 30 included in the buck converter 100_2 may not be directly connected between the output terminal T3 and the second end of the inductor L (e.g., the feedback terminal T4), and may be connected at an intermediate node (e.g., the common nodes CN2 and CN3) of the resistor divider (e.g., resistors R5, R6, R7, and R8). The resistor divider can be used to improve the withstand voltage characteristics of the switch TG connected in parallel with the resistor R3.

[0100] Figure 9 is a block diagram showing an electronic device including a buck converter according to some example embodiments.

[0101] Referring to Figure 9, the electronic device 1000 may include a first semiconductor chip 101, a second semiconductor chip 300, and a low-pass filter 20, and may further include a printed circuit board (PCB) 500 on which the first semiconductor chip 101, the second semiconductor chip 300, and the low-pass filter 20 are mounted.

[0102] The first semiconductor chip 101 and the low-pass filter 20 may form Figure 2 the buck converter 100_1 and / or Figure 8 the buck converter 100_2. For example, the first semiconductor chip 101 may include a power switch circuit 10, a sense voltage generator 30, and a switch signal generator 40. The power switch circuit 10 may receive an input voltage Vin from a battery (not shown), and may alternately transfer the input voltage Vin and the ground voltage Vss to the output terminal T3 in response to a switch signal PS having an active time interval and a de-active time interval. The sense voltage generator 30 may generate a sense voltage V A . The switch signal generator 40 may generate the switch signal PS based on the sense voltage V A . The low-pass filter 20 may generate an output voltage Vout by low-pass filtering the voltage at the output terminal T3. The second semiconductor chip 300 may receive the output voltage Vout as a power supply voltage, and may consume a load current I LOAD . For example, the second semiconductor chip 300 may be or may include one of a memory or a central processing unit (CPU) having computing capabilities.

[0103] In some example embodiments, the first semiconductor chip 101 included in the electronic device 1000 may further include a linear regulator (e.g., a low dropout (LDO) regulator) and one of a DC-DC converter having a different type from the buck converter. The electronic device 1000 may further include a controller 400 that sets the buck converter to operate in an AOT scheme or a COT scheme according to an operation mode of the second semiconductor chip 300 as a load device (e.g., according to the load current I LOAD ).

[0104] In the electronic device 1000 including a buck converter according to some example embodiments, even if the load current changes rapidly, a desired output voltage may be accurately generated within a relatively fast response time. Therefore, deterioration of the overall performance of the electronic device 1000 may be limited and / or prevented.

[0105] Some example embodiments can be applied to various electronic devices and systems including a buck converter. For example, some example embodiments can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0106] One or more of the elements disclosed above can include the following or can be implemented in the following: processing circuitry such as hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0107] The foregoing is illustrative of some example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made without substantially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined by the claims. Therefore, it should be understood that the foregoing is illustrative of various example embodiments and should not be construed as specifically limited to the disclosed example embodiments, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A step-down converter, comprising: A power switch circuit configured to alternately transfer an input voltage and a ground voltage to an output terminal based on a switching signal; A low-pass filter including an inductor having a first end connected to the output terminal and a second end connected to a load capacitor, the inductor being configured to generate an output voltage at the second end; A first resistor and a capacitor, the first resistor and the capacitor being connected in series between the output terminal and the second end of the inductor; A switch located between a common node and the second end of the inductor, the common node being connected to the first resistor and the capacitor; A comparator configured to generate a comparison signal by comparing a sensed voltage at the common node with a reference voltage; And An SR latch configured to receive the comparison signal as a set signal, receive a delay signal as a reset signal, and generate the switching signal based on the comparison signal and the delay signal, the delay signal being activated after the comparison signal is activated, Wherein, the switch is configured to electrically connect the common node and the second end of the inductor during an activation time interval of the switching signal.

2. The buck converter according to claim 1, wherein, The SR latch is configured to activate the switching signal in response to the activation of the comparison signal and then deactivate the switching signal in response to the activation of the delay signal.

3. The step-down converter according to claim 2, wherein, The switch is configured to electrically disconnect the common node from the second end of the inductor during a deactivation time interval of the switching signal.

4. The buck converter according to claim 3, wherein, The switch includes a transmission gate.

5. The buck converter according to claim 3, wherein, During the activation time interval of the switching signal, a first voltage across the capacitor is 0V, and the sensed voltage at the common node is equal to the output voltage.

6. The buck converter according to claim 3, wherein, During the deactivation time interval of the switching signal, the first voltage across the capacitor is based on Equation 1 below: [Equation 1] where I L represents the inductor current flowing through the inductor, R1 represents the resistance of the equivalent series resistor of the inductor, L represents the inductance of the inductor, R3 represents the resistance of the first resistor, and C1 represents the capacitance of the capacitor, and s represents the Laplace variable.

7. The buck converter according to claim 6, wherein, During the deactivation time interval of the switching signal, the sensed voltage is equal to the sum of the output voltage and the first voltage.

8. The step-down converter according to claim 7, wherein, During the deactivation time interval of the switching signal, the first voltage changes to a voltage lower than 0V.

9. The step-down converter according to claim 3, wherein, The comparator is configured to activate the comparison signal when the sensed voltage is equal to or lower than the reference voltage, and Wherein, the activation time interval of the switching signal is based on a delay time from when the comparison signal is activated to when the delay signal is activated.

10. The step-down converter according to claim 9, wherein, The delay time is at least variable according to the voltage level of the input voltage.

11. The step-down converter according to claim 9, wherein, The delay time is fixed regardless of the change in the input voltage.

12. The buck converter according to claim 3, wherein, The power switch circuit includes: A first power switch configured to transfer the input voltage to the output terminal during an activation time interval of the switching signal; and A second power switch configured to transfer the ground voltage to the output terminal during a deactivation time interval of the switching signal.

13. The buck converter according to claim 1, wherein, The power switch circuit, the switch, the comparator, and the SR latch are included in a semiconductor chip, and Wherein, the inductor and the load capacitor are located outside the semiconductor chip.

14. The step-down converter according to claim 1, further comprising: A second resistor and a third resistor, the second resistor and the third resistor being connected in series between the output terminal and the ground voltage; And A fourth resistor and a fifth resistor, the fourth resistor and the fifth resistor being connected in series between the second end of the inductor and the ground voltage, Wherein, the first end of the first resistor is connected to a second common node, the second common node is connected to the second resistor and the third resistor, and Wherein, the first end of the capacitor is connected to a third common node, and the third common node is connected to the fourth resistor and the fifth resistor.

15. The buck converter according to claim 14, wherein, The resistances of the second resistor, the third resistor, the fourth resistor and the fifth resistor are equal to each other.

16. A step-down converter, comprising: A power switch circuit configured to alternately transfer an input voltage and a ground voltage to an output terminal based on a switching signal; A low-pass filter including an inductor having a first end connected to the output terminal and a second end connected to a load capacitor, the inductor being configured to generate an output voltage at the second end; A first resistor and a first capacitor, the first resistor and the first capacitor being connected in series between the output terminal and the second end of the inductor; A switch located between a common node and the second end of the inductor, the common node being connected to the first resistor and the first capacitor; A first comparator configured to generate a first comparison signal by comparing a sensed voltage at the common node with a first reference voltage; A delay circuit configured to generate a delay signal by delaying the first comparison signal; And A first SR latch configured to receive the first comparison signal as a set signal, receive the delay signal as a reset signal, and generate the switching signal based on the first comparison signal and the delay signal, the first SR latch being configured to activate the switching signal when the first comparison signal is activated and deactivate the switching signal when the delay signal is activated, and Wherein, the switch is configured to electrically connect the common node and the second end of the inductor during an activation time interval of the switching signal, and electrically disconnect the common node from the second end of the inductor during a deactivation time interval of the switching signal.

17. The step-down converter according to claim 16, wherein, The delay circuit includes: A current source configured to generate a first current proportional to the input voltage; A second capacitor configured to generate a ramp voltage based on the first current starting from when the switching signal is activated; A second comparator configured to generate a second comparison signal by comparing the ramp voltage with a second reference voltage; and A second SR latch configured to receive the second comparison signal as a second set signal, and activate the delay signal based on the second comparison signal.

18. The buck converter according to claim 17, wherein, The delay circuit further includes: A trigger configured to activate a first signal, wherein the delay circuit is configured to transmit the first current to the second capacitor in response to the first signal, starting from when the switch signal is activated until the delay signal is activated, and wherein the second SR latch is configured to deactivate the delay signal based on a second signal that is activated at a time interval after the first signal is deactivated.

19. The step-down converter according to claim 18, wherein, The delay circuit further includes: At least one additional resistor or additional capacitor configured to determine when to deactivate the first signal and when to activate the second signal.

20. An electronic device, comprising: A first semiconductor chip including: A power switch circuit configured to alternately transmit an input voltage and a ground voltage to an output terminal based on a switch signal having an activation time interval and a deactivation time interval, A sense voltage generator configured to generate a sense voltage, and A switch signal generator configured to generate the switch signal based on the sense voltage; An inductor and a load capacitor configured to generate an output voltage by low-pass filtering the voltage at the output terminal; and A second semiconductor chip configured to receive the output voltage as a power supply voltage, wherein during the activation time interval of the switch signal, the sense voltage generator is configured to generate the sense voltage equal to the output voltage, and wherein during the deactivation time interval of the switch signal, the sense voltage generator is configured to generate the sense voltage equal to the sum of the output voltage and a voltage reflecting the current flowing through the output terminal.

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