Frequency conversion processing method for synchronous amplitude modulation and dual-thread parallel control system

Abstract

The invention provides a frequency conversion processing method for synchronous amplitude modulation and a dual-thread parallel control system, which are applied to the dual-thread parallel control system, and the method comprises the following steps: a field editable logic gate module receives multiple groups of first frequency words and amplitude words input in a first transmission format through a parallel interface, and stores each amplitude word in a storage module; the field editable logic gate module receives a second frequency word input in a second transmission format through the parallel interface, sends the second frequency word to the direct digital synthesis module, reads a target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion module; the direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word; the frequency mixing module receives the frequency signal and the analog voltage at the same time and outputs a target frequency signal according to the analog voltage and the frequency signal, and high-speed and synchronous frequency conversion and amplitude modulation are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of variable frequency drive, and in particular, to a variable frequency processing method with synchronous amplitude modulation and a dual-thread parallel control system. Background Art

[0002] Variable frequency drive can achieve the output of variable frequency signals within a wide frequency band and adjust the amplitude of the output frequency signal.

[0003] In the prior art, there are two methods for adjusting the variable frequency amplitude. The first is amplitude modulation based on a direct digital synthesis chip (Direct Digital Synthesis, DDS), and the second is external analog modulation based on a mixer. Among them, the first adjustment based on the DDS chip is limited by the serial transmission of multiple amplitude words, resulting in a slow amplitude modulation speed and the inability to achieve the synchronization of variable frequency and amplitude modulation. The second external analog modulation based on mixing is limited by the timing problem of external analog signals and internal variable frequency time, and synchronization is relatively complex and difficult.

[0004] Therefore, there is an urgent need for a variable frequency processing method capable of synchronous amplitude modulation. Summary of the Invention

[0005] The purpose of the present application is to provide a variable frequency processing method with synchronous amplitude modulation and a dual-thread parallel control system for the deficiencies in the above prior art, so as to achieve high-speed and synchronous variable frequency and amplitude modulation.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a variable frequency processing method with synchronous amplitude modulation, which is applied to a dual-thread parallel control system. The dual-thread parallel control system includes: a field programmable gate array module, a storage module, a direct digital synthesis module, a digital-to-analog conversion module, and a mixing module. The method includes:

[0008] The field programmable gate array module receives multiple groups of first frequency words and amplitude words input in a first transmission format through a parallel interface, and stores each of the amplitude words in the storage module;

[0009] The field programmable gate array module receives a second frequency word input in a second transmission format through a parallel interface, sends the second frequency word to the direct digital synthesis module, reads a target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion module. The target amplitude word is the amplitude word stored in the storage address indicated by the second frequency word;

[0010] The direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word;

[0011] The mixing module simultaneously receives the frequency signal and the analog voltage, and outputs a target frequency signal according to the analog voltage and the frequency signal.

[0012] Optionally, the first transmission format is parallel transmission of an M-bit first frequency word and an N-bit amplitude word, where both M and N are integers greater than 0, and M is greater than N.

[0013] Optionally, the storing each of the amplitude words into the storage module includes:

[0014] Taking the M-bit first frequency word in a group of M-bit first frequency words and N-bit amplitude words as a storage address, and storing the N-bit amplitude word in the group of M-bit first frequency words and N-bit amplitude words as the stored data in the storage address into the storage module.

[0015] Optionally, the M-bit first frequency word in a group of M-bit first frequency words and N-bit amplitude words corresponds to a frequency range, the amplitude words corresponding to the frequencies within the frequency range are all the N-bit amplitude words, the starting frequency of the frequency range is the frequency corresponding to the first frequency word, and the ending frequency of the frequency range is the frequency corresponding to the first frequency word plus 1 KHZ.

[0016] Optionally, the second transmission format is parallel transmission of a P-bit second frequency word, P is an integer greater than 0, and P is greater than M.

[0017] Optionally, the reading the target amplitude word from the storage module according to the second frequency word includes:

[0018] Taking the high M-bit frequency word in the P-bit second frequency word as the reading address;

[0019] Searching in the storage module for a target storage address matching the reading address, and reading the target stored data stored in the target storage address, and taking the target stored data as the target amplitude word.

[0020] Optionally, the searching in the storage module for a target storage address matching the reading address includes:

[0021] Traversing the storage addresses in the storage module, and for the currently traversed storage address, determining whether the current storage address is the same as the reading address, and if so, taking the current storage address as the target storage address.

[0022] Optionally, the direct digital synthesis module generating a frequency signal according to the second frequency includes:

[0023] The on-site programmable logic gate module controls the direct digital synthesis module to generate a frequency signal according to the second frequency after a preset delay.

[0024] Optionally, the outputting the target frequency signal according to the analog voltage and the frequency signal includes:

[0025] Performing synchronous power compensation on the frequency signal by using the analog voltage to obtain a compensated frequency signal, and using the compensated frequency signal as the target frequency signal.

[0026] In a second aspect, an embodiment of the present application further provides a dual-thread parallel control system, which includes: an on-site programmable logic gate module, a storage module, a direct digital synthesis module, a digital-to-analog conversion module, and a mixing module;

[0027] The dual-thread parallel control system is used to execute the method steps described in the first aspect to perform signal processing.

[0028] The beneficial effects of the present application are:

[0029] A frequency conversion processing method and a dual-thread parallel control system for synchronous amplitude modulation provided by the present application. The on-site programmable logic gate module receives multiple groups of first frequency words and amplitude words input in a first transmission format through a parallel interface, and stores each amplitude word in the storage module; by adopting a method of internally supporting high-speed reading and writing of amplitude words, multiple amplitude words are stored in the storage module for preservation. Compared with the external analog modulation of a mixer in the prior art, it is not restricted by the timing problems of external analog signals and internal frequency conversion time, so as to facilitate subsequent synchronous frequency conversion and amplitude modulation. When the on-site programmable logic gate module receives a second frequency word input in a second transmission format through the parallel interface, it sends the second frequency word to the direct digital synthesis module, reads a target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion module; the direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word; the mixing module simultaneously receives the frequency signal and the analog voltage, and outputs a target frequency signal according to the analog voltage and the frequency signal. By adopting a dual-thread parallel control method, digital-to-analog conversion is performed while performing frequency conversion, and parallel modulation is performed through a high-speed digital-to-analog conversion module and a mixing module, so as to achieve high-speed amplitude adjustment. Description of the Drawings

[0030] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0031] Figure 1 A dual-thread parallel control system provided for the embodiments of the present application;

[0032] Figure 2 A schematic flowchart of a method for synchronous amplitude modulation and frequency conversion processing provided for the embodiments of the present application;

[0033] Figure 3 Another schematic flowchart of a method for synchronous amplitude modulation and frequency conversion processing provided for the embodiments of the present application;

[0034] Figure 4 A complete schematic flowchart of a method for synchronous amplitude modulation and frequency conversion processing provided for the embodiments of the present application. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. It should be understood that the accompanying drawings in the present application only serve the purposes of illustration and description, and are not used to limit the protection scope of the present application. In addition, it should be understood that the schematic accompanying drawings are not drawn according to the actual scale. The flowcharts used in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations in the flowchart may not be implemented in sequence, and the steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of the present application.

[0036] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0037] It should be noted that the term "including" will be used in the embodiments of the present application to indicate the existence of the features stated thereafter, but does not exclude the addition of other features.

[0038] The process of adjusting the DDS amplitude word is to first send the frequency word to the variable-frequency drive through the serial port. After receiving the frequency word, the variable-frequency drive starts frequency conversion and outputs a corresponding frequency signal. Then, the amplitude word is sent to the variable-frequency drive through the serial port. After receiving the amplitude word, the variable-frequency drive starts amplitude modulation to control the amplitude of the output frequency signal. This method requires sending binary values bit by bit, resulting in a slow amplitude modulation speed and inability to synchronize with frequency conversion.

[0039] External analog adjustment based on mixing is adjusted based on the fact that the conduction state of the nonlinear element inside the mixer is affected by the bias voltage. This method can respond quickly and synchronously adjust the frequency and amplitude. However, because it is non-linear modulation, the accuracy is not high, and it is very difficult to ensure the timing of the external voltage and the frequency conversion operation.

[0040] Next, the specific implementation process of the variable-frequency processing with synchronous amplitude modulation provided in the embodiments of the present application will be specifically explained.

[0041] Figure 1 A dual-thread parallel control system provided in an embodiment of the present application may include: a Field-Programmable Gate Array (FPGA) module, a storage module (FLASH), a Direct Digital Synthesis (DDS) module, a Digital-to-Analog Conversion (DAC) module, and a mixing module (Mixer module). As Figure 1 shown, the FPGA module is respectively connected to the storage module, the direct digital synthesis module, and the digital-to-analog conversion module. The digital-to-analog conversion module and the direct digital synthesis module are respectively connected to the mixing module, and the mixing module outputs a target frequency signal.

[0042] Among them, the FPGA module can receive data, the FPGA module can transmit data to the storage module, the storage module can also transmit data to the FPGA module, the FPGA module can unidirectionally transmit data to the direct digital synthesis module, the FPGA module can also unidirectionally transmit data to the digital-to-analog conversion module, and both the digital-to-analog conversion module and the direct digital synthesis module can unidirectionally transmit data to the mixing module.

[0043] Among them, the dual-thread parallel control system can be applied to a variable-frequency drive.

[0044] Based on Figure 1 each module in the dual-thread parallel control system can achieve synchronous frequency conversion and amplitude modulation by using the variable-frequency processing method with synchronous amplitude modulation provided in the embodiments of the present application.

[0045] Figure 2 A schematic flow chart of a method for variable-frequency processing with synchronous amplitude modulation provided in an embodiment of the present application. This method is applied to the dual-thread parallel control system described above, asFigure 2 As shown, the method may include:

[0046] S101. The field programmable gate array (FPGA) module receives multiple groups of first frequency words and amplitude words input in a first transmission format through a parallel interface, and stores each amplitude word in a storage module.

[0047] Optionally, the frequency word refers to a frequency tuning word (FTW), which represents the frequency in binary form. The amplitude word (DAC value) refers to the amplitude word corresponding to the frequency word in binary form. One amplitude word corresponds to an analog voltage, and the corresponding amplitude adjustment can be generated by acting on the mixing module.

[0048] Wherein, one first frequency word and one amplitude word form a group of first frequency words and amplitude words. The first frequency word in a group of first frequency words and amplitude words is used to represent the input first frequency, and the amplitude word in the group of first frequency words and amplitude words is used to represent the amplitude corresponding to the first frequency in the group.

[0049] Optionally, each group of first frequency words and amplitude words is input by the user according to actual needs, and different amplitude words can be configured for different first frequency words. Each group of first frequency words and amplitude words can be input into the FPGA module in the first transmission format through the parallel interface. When the FPGA module receives a group of first frequency words and amplitude words, it can transmit the amplitude word of the group to the storage module, so that the storage module saves the received amplitude word of the group. Each amplitude word corresponds to a storage address when stored. After the FPGA module receives multiple groups of first frequency words and amplitude words, multiple amplitude words can be pre-stored in the storage module, and each amplitude word corresponds to a first frequency word.

[0050] Exemplarily, if the FPGA module receives the first group of first frequency word 1 and amplitude word 1, it stores the amplitude word 1 in storage address 1 of the storage module; after receiving the second group of first frequency word 2 and amplitude word 2, it stores the amplitude word 2 in storage address 2 of the storage module; after receiving the third group of first frequency word 3 and amplitude word 3, it stores the amplitude word 3 in storage address 3 of the storage module; and so on, storing each amplitude word in the storage module.

[0051] S102. The FPGA module receives a second frequency word input in a second transmission format through the parallel interface, sends the second frequency word to the direct digital synthesis (DDS) module, reads a target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion (DAC) module.

[0052] Among them, the target amplitude word is the amplitude word stored at the storage address indicated by the second frequency word. The second frequency word is also a frequency represented in binary form, and the number of bits of the second frequency word is different from that of the first frequency word.

[0053] Optionally, when the field-programmable logic gate module receives the second frequency word input in the second transmission format through the parallel interface, it performs dual-thread parallel synchronous processing on the second frequency word, that is, two threads can be executed simultaneously. One thread is to directly send the second frequency word to the direct digital synthesis module, and the other thread is to read the target amplitude word from the storage module according to the second frequency word and send the target amplitude word to the digital-to-analog conversion module.

[0054] Optionally, since the storage module stores multiple groups of amplitude words in step S101, and each amplitude word corresponds to a storage address, the field-programmable logic gate module can use a preset method to determine the storage address indicated by the second frequency word according to the second frequency word, and then can use the amplitude word at the storage address indicated by the second frequency word as the target amplitude word of the second frequency word.

[0055] Exemplarily, if the field-programmable logic gate module receives the second frequency word 1, it directly sends the second frequency word 1 to the direct digital synthesis module, and at the same time reads the target amplitude word corresponding to the second frequency word from the storage module according to the second frequency word 1. If the target amplitude word is the amplitude word 2 stored in the storage module as described above, that is, the field-programmable logic gate module sends the amplitude word 2 to the digital-to-analog conversion module.

[0056] S103. The direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word.

[0057] Optionally, when the direct digital synthesis module receives the second frequency word, it can perform format conversion on the second frequency word to generate a frequency signal corresponding to the second frequency word, and send the generated frequency signal to the mixing module. When the digital-to-analog conversion module receives the target amplitude word corresponding to the second frequency word, it converts the target amplitude word into an analog voltage and sends the generated analog voltage to the mixing module.

[0058] Exemplarily, when the direct digital synthesis module receives the second frequency word 1, it converts the second frequency word 1 in binary form into a frequency; at the same time, the digital-to-analog conversion module converts the received amplitude word 2 into an analog voltage.

[0059] S104. The mixing module simultaneously receives the frequency signal and the analog voltage, and outputs a target frequency signal according to the analog voltage and the frequency signal.

[0060] Optionally, the mixing module can receive the frequency signal sent by the direct digital synthesis module and the analog voltage sent by the digital-to-analog conversion module simultaneously. Then, the mixing module can output a target frequency signal according to the received frequency signal and analog voltage. The target frequency signal is a frequency signal after amplitude adjustment.

[0061] In this embodiment, the field programmable gate module receives multiple groups of first frequency words and amplitude words input in the first transmission format through a parallel interface, and saves each amplitude word into the storage module; by adopting the method of internally supporting high-speed reading and writing of amplitude words, multiple amplitude words are stored in the storage module for saving. Compared with the external analog modulation of the mixer in the prior art, it is not limited by the timing problems of external analog signals and internal frequency conversion time, so as to facilitate subsequent synchronous frequency conversion and amplitude modulation. When the field programmable gate module receives the second frequency word input in the second transmission format through the parallel interface, it sends the second frequency word to the direct digital synthesis module, reads the target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion module; the direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word; the mixing module receives the frequency signal and the analog voltage simultaneously, and outputs a target frequency signal according to the analog voltage and the frequency signal. By adopting the dual-thread parallel control method, digital-to-analog conversion is performed while frequency conversion, and parallel modulation is performed through the high-speed digital-to-analog conversion module and the mixing module, so that high-speed amplitude adjustment can be realized.

[0062] Optionally, the above first transmission format is an M-bit first frequency word and an N-bit amplitude word, where both M and N are integers greater than 0 and M is greater than N.

[0063] Exemplarily, M can be 20 bits and N can be 12 bits. The parallel interface can be a 32-bit data transmission interface. Through this 32-bit data transmission interface, data can be transmitted in the form of a 20-bit first frequency word + 12-bit amplitude word. The high 20 bits of data in this 32-bit data transmission interface are the first frequency word, and the low 12 bits of data are used as the amplitude word.

[0064] Optionally, saving each amplitude word into the storage module in S101 above may include:

[0065] Specifically, the M-bit first frequency word in a group of M-bit first frequency words and N-bit amplitude words is used as a storage address, and the N-bit amplitude word in a group of M-bit first frequency words and N-bit amplitude words is used as the stored data in the storage address and stored in the storage module. Among them, the storage module can be a parallel non-volatile memory (fast large area scanhardware, FLASH), which can support the fast reading and writing function at the ns level and support power-off preservation at the same time.

[0066] Exemplarily, the high 20-bit first frequency word in the 32-bit data transmitted through the parallel interface is used as the storage address of the low 12-bit amplitude word, and the low 12-bit amplitude word is stored at the storage address of the high 20-bit first frequency word.

[0067] In this embodiment, by means of the method of the amplitude word with built-in high-speed reading and writing, the amplitude words corresponding to each first frequency word can be written into and stored in the storage module at high speed, and the field programmable gate array module can also read the amplitude words at high speed during subsequent reading, realizing high-speed amplitude adjustment. And the 12-bit amplitude word is customized in size and saved during power-off, which can realize subsequent amplitude compensation for any frequency signal, that is, different frequency words match different amplitude words.

[0068] Optionally, the M-bit first frequency words in a group of M-bit first frequency words and N-bit amplitude words correspond to a frequency range, and the amplitude words corresponding to each frequency within the frequency range are all N-bit amplitude words, that is, the amplitude words corresponding to each frequency within the frequency range corresponding to the M-bit first frequency word are shared. The starting frequency of the frequency range is the frequency corresponding to the first frequency word, and the ending frequency of the frequency range is the frequency corresponding to the first frequency word plus 1 KHZ.

[0069] Since the low 12 bits are discarded in the parallel 32-bit data, that is, the high 20 bits in the 32-bit data are used as the first frequency word, when the 20-bit first frequency word is incremented by 1, the frequency corresponding to the 20-bit first frequency word is incremented by 1 KHZ. Within the frequency range of 1 kHz, the change in the amplitude caused by frequency conversion is extremely small and can be ignored, so the sharing method can be adopted.

[0070] Exemplarily, if the 32-bit frequency word corresponding to 50 MHz is: 00001100 110011001100110011001101. 00001100110011001100 is the high 20-bit frequency word. After adding 1 to 00001100110011001100, we get 00001100 11001100 11011100 11001101. The calculated frequency value is 50.000953 MHz, that is, the frequency increases by 953 Hz, approximately 1 kHz. If it is a full 32-bit addition, that is, 00001100 11001100 1100110011001110, the frequency increases by 0.23 Hz. Therefore, the high bits of the frequency word have a greater weight and affect a larger increment of the frequency value. When discarding the low 12 bits and using the high 20 bits as the storage address, as long as the high 20 bits of the second frequency word are the same as those of the first frequency word, then the stored data at that storage address is read correspondingly. That is, 00001100 11001100 1100110011001101 = 50 MHz and 0000110011001100 11001111 11111111 = 50.00019 MHz, and the amplitude word stored in 0000110011001100 1100 is used in both cases.

[0071] Exemplarily, when the frequency corresponding to the 20-bit first frequency word is 50.000 MHz and the storage address is the stored data of the 20-bit first frequency word with an amplitude of 1, the frequency range corresponding to the 20-bit first frequency word is 50.000 MHz to 50.000999 MHz. The first frequency words corresponding to each frequency within the range of 50.000 MHz to 50.000999 MHz are the same. Therefore, the amplitude words read between 50.000 MHz and 50.000999 MHz are the same, which is the amplitude of 1.

[0072] Optionally, the second transmission format is parallel transmission of a P-bit second frequency word, where P is an integer greater than 0 and P is greater than M. For example, P is 32 bits, that is, all 32 bits of data in the parallel interface are input as frequency words into the field programmable logic gate module.

[0073] Figure 3 It is a schematic flowchart of another method for synchronous amplitude modulation frequency conversion processing provided by an embodiment of the present application, as Figure 3 shown. In the above S102, reading the target amplitude word from the storage module according to the second frequency word may include:

[0074] S201. Use the high M-bit frequency word in the P-bit second frequency word as the reading address.

[0075] Optionally, since the storage address of the amplitude word in the storage module is an M-bit first frequency word and the received second frequency word is P-bit, when the field programmable logic gate module receives the transmitted P-bit second frequency word through the parallel interface, the high M-bit data is extracted from the P-bit second frequency word as the read address.

[0076] Exemplarily, if the field programmable logic gate module receives the transmitted 32-bit second frequency word 1 through the parallel interface, the high 20-bit data is extracted from the 32-bit second frequency word 1 as the read address.

[0077] S202. Search for a target storage address in the storage module that matches the read address, and read the target storage data stored in the target storage address, and use the target storage data as the target amplitude word.

[0078] Exemplarily, if the high 20-bit data extracted from the 32-bit second frequency word is 0001 0001 1110 1011 1000, search for a target storage address in the storage module that matches 0001 0001 1110 1011 1000, that is, search for a 20-bit first frequency word that matches 0001 0001 1110 1011 1000. If the 20-bit first frequency word that matches 0001 0001 1110 1011 1000 is 0001 0001 1110 1011 1000, use the target storage data stored in 0001 0001 1110 1011 1000 as the target amplitude word. This target amplitude word is the amplitude word for amplitude adjustment of this 32-bit second frequency word.

[0079] Optionally, after the field programmable logic gate module reads the target amplitude word, it sends the target amplitude word to the digital-to-analog conversion module. After receiving the target amplitude word, the digital-to-analog conversion module converts the target amplitude word into an analog voltage, and controls the DC bias of the mixing module through this analog voltage, so that the mixing module generates a corresponding amplitude size adjustment.

[0080] In this embodiment, when receiving a 32-bit second frequency word, the target amplitude word corresponding to the high 20-bit data can be quickly read from the storage module directly according to the high 20-bit data in the 32-bit second frequency word, and the read target amplitude word is sent to the digital-to-analog conversion module for conversion to obtain the analog voltage corresponding to the target amplitude word, so as to send this analog voltage to the mixing module. At the same time, the mixing module can also receive the frequency signal sent by the direct digital synthesis module, and then the mixing module can perform synchronous frequency conversion and amplitude modulation, high-speed and synchronous frequency conversion and amplitude modulation.

[0081] Optionally, the above S202, searching for a target storage address in the storage module that matches the read address, may include:

[0082] Specifically, traverse the storage addresses in the storage module. For the currently traversed storage address, determine whether the current storage address is the same as the read address. If they are the same, use the current storage address as the target storage address.

[0083] Exemplarily, if the high 20-bit data extracted from the 32-bit second frequency word is 20-bit data A, traverse the storage addresses in the storage module. If the currently traversed storage address is the 20-bit first frequency word 2 and the 20-bit first frequency word 2 is the same as the extracted 20-bit data, use the 20-bit first frequency word as the target storage address.

[0084] Optionally, in the above S103, the direct digital synthesis module generates a frequency signal according to the second frequency word, which may include:

[0085] Optionally, the field programmable gate module can control the direct digital synthesis module to generate a frequency signal according to the second frequency after a preset delay. Since the frequency conversion processing time of the direct digital synthesis module and the amplitude modulation processing time of the digital-to-analog conversion module are different, the field programmable gate module can control the update delay time of the frequency signal generated by the direct digital synthesis module, thereby realizing frequency conversion and amplitude modulation at the ns level.

[0086] Optionally, in the above S104, outputting the target frequency signal according to the analog voltage and the frequency signal may include:

[0087] Optionally, the mixing module can perform synchronous power compensation on the frequency signal using the analog voltage, obtain the compensated frequency signal, and use the compensated frequency signal as the target frequency signal.

[0088] The following uses a complete example to illustrate the process of the dual-thread parallel synchronization processing of the present application. Figure 4 It is a complete flow schematic diagram of a frequency conversion processing method for synchronous amplitude modulation provided by an embodiment of the present application, as Figure 4 shown:

[0089] S301. The field programmable gate module receives multiple groups of 20-bit first frequency words + 12-bit amplitude words through the parallel interface.

[0090] S302. Use the 20-bit first frequency word as the storage address and the 12-bit amplitude word as the storage data to store in the storage module.

[0091] S303. Determine whether the reception of multiple groups of 20-bit first frequency words + 12-bit amplitude words is completed.

[0092] Optionally, if the reception is completed, execute the following step S304; if the reception is not completed, return to execute step S301.

[0093] S304. The field programmable logic gate module receives a 32-bit second frequency word.

[0094] Optionally, when the field programmable logic gate module receives a 32-bit second frequency word, the following steps S305 and S309 are processed in parallel and synchronously using two threads.

[0095] S305. The field programmable logic gate module extracts the upper 20 bits of data as the read address.

[0096] Specifically, the field programmable logic gate module uses the upper 20 bits of data in the 32-bit second frequency word as the read address.

[0097] S306. Read the target amplitude word from the storage module.

[0098] Specifically, the target amplitude word corresponding to the upper 20 bits of data is quickly read from the storage module. If the target amplitude word is the amplitude word 2 stored in the 20-bit first frequency word 2.

[0099] S307. Send the target amplitude word to the digital-to-analog conversion module.

[0100] Exemplarily, the field programmable logic gate module sends the amplitude word 2 to the digital-to-analog conversion module.

[0101] S308. The digital-to-analog conversion module converts the target amplitude word into an analog voltage and sends the analog voltage to the mixing module.

[0102] Exemplarily, the digital-to-analog conversion module converts the received amplitude word 2 into an analog voltage.

[0103] S309. The field programmable logic gate module directly sends the received 32-bit second frequency word to the direct digital synthesis module.

[0104] S310. The direct digital synthesis module converts the received 32-bit second frequency word into a frequency signal corresponding to the second frequency word and sends the generated frequency signal to the mixing module.

[0105] S311. The mixing module can receive the frequency signal sent by the direct digital synthesis module and the analog voltage sent by the digital-to-analog conversion module at the same time, and output the target frequency signal.

[0106] Specifically, the mixing module can perform synchronous power compensation on the frequency signal using the analog voltage, thereby outputting the target frequency signal.

[0107] S312. Determine whether the frequency conversion is completed.

[0108] Optionally, if the frequency conversion is completed, end; if the frequency conversion is not completed, return to step S304 for execution.

[0109] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the method embodiments, and will not be elaborated herein. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some communication interfaces, and the indirect couplings or communication connections of the devices or modules can be in electrical, mechanical or other forms.

[0110] In addition, in each embodiment of this application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks or optical discs that can store program codes.

[0111] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application.

Claims

1. A frequency conversion processing method for synchronous amplitude modulation, characterized in that Applied to a dual-thread parallel control system, the dual-thread parallel control system includes: a field programmable gate array module, a storage module, a direct digital synthesis module, a digital-to-analog conversion module, and a mixing module. The method includes: The field programmable gate array module receives multiple groups of first frequency words and amplitude words input in a first transmission format through a parallel interface, and saves each of the amplitude words to the storage module; The field programmable gate array module receives a second frequency word input in a second transmission format through a parallel interface, sends the second frequency word to the direct digital synthesis module, reads a target amplitude word from the storage module according to the second frequency word, and sends the target amplitude word to the digital-to-analog conversion module. The target amplitude word is the amplitude word stored in the storage address indicated by the second frequency word; The direct digital synthesis module generates a frequency signal according to the second frequency word, and the digital-to-analog conversion module generates an analog voltage according to the target amplitude word; The mixing module simultaneously receives the frequency signal and the analog voltage, and outputs a target frequency signal according to the analog voltage and the frequency signal.

2. The frequency conversion processing method with synchronous amplitude modulation according to claim 1, characterized in that The first transmission format is parallel transmission of an M-bit first frequency word and an N-bit amplitude word, where both M and N are integers greater than 0, and M is greater than N.

3. The frequency conversion processing method for synchronous amplitude modulation according to claim 2, characterized in that The saving each of the amplitude words to the storage module includes: Taking the M-bit first frequency word in a group of M-bit first frequency words and N-bit amplitude words as a storage address, and taking the N-bit amplitude word in a group of M-bit first frequency words and N-bit amplitude words as the stored data in the storage address and storing it in the storage module.

4. The frequency conversion processing method with synchronous amplitude modulation according to claim 3, characterized in that, The M-bit first frequency word in a group of M-bit first frequency words and N-bit amplitude words corresponds to a frequency range. The amplitude words corresponding to each frequency within the frequency range are all the N-bit amplitude words. The starting frequency of the frequency range is the frequency corresponding to the first frequency word, and the ending frequency of the frequency range is the frequency corresponding to the first frequency word plus 1 KHZ.

5. The frequency conversion processing method of synchronous amplitude modulation according to claim 1, characterized in that The second transmission format is parallel transmission of a P-bit second frequency word, where P is an integer greater than 0 and P is greater than M.

6. The frequency conversion processing method with synchronous amplitude modulation according to claim 5, characterized in that The reading the target amplitude word from the storage module according to the second frequency word includes: Taking the high M-bit frequency word in the P-bit second frequency word as the reading address; Searching in the storage module for a target storage address matching the reading address, and reading the target stored data stored in the target storage address, and taking the target stored data as the target amplitude word.

7. The frequency conversion processing method with synchronous amplitude modulation according to claim 6, characterized in that, The searching in the storage module for a target storage address matching the reading address includes: Traversing the storage addresses in the storage module. For the currently traversed storage address, determining whether the current storage address is the same as the reading address. If the same, taking the current storage address as the target storage address.

8. The frequency conversion processing method with synchronous amplitude modulation according to claim 1, characterized in that, The direct digital synthesis module generating a frequency signal according to the second frequency includes: The field programmable gate array module controls the direct digital synthesis module to generate a frequency signal according to the second frequency after a preset delay.

9. The frequency conversion processing method with synchronous amplitude modulation according to claim 1, characterized in that Outputting a target frequency signal according to the analog voltage and the frequency signal includes: Performing synchronous power compensation on the frequency signal by using the analog voltage to obtain a compensated frequency signal, and using the compensated frequency signal as the target frequency signal.

10. A dual-thread parallel control system, characterized in that, The dual-thread parallel control system includes: a field programmable gate array module, a storage module, a direct digital synthesis module, a digital-to-analog conversion module, and a mixing module; The dual-thread parallel control system is configured to execute the steps of the frequency conversion processing method for synchronous amplitude modulation according to any one of claims 1-9 to perform signal processing.

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