Clock duty ratio adjusting method and system

Abstract

The invention relates to a clock duty ratio adjusting method and system in the technical field of clock adjustment. The clock duty ratio adjusting method comprises the following steps of configuring numerical values of a first current source, a first capacitor, a second current source and a second capacitor based on a target clock duty ratio; performing two-phase non-overlapping processing on the original input clock signal to obtain a first phase clock signal and a second phase clock signal, and performing phase inversion processing on the original input clock signal to obtain an inverted input clock signal; enabling the first current source to charge the first capacitor, and enabling the second current source to charge the second capacitor; acquiring a first voltage and a second voltage, and performing stability detection based on the first voltage and the second voltage; if a stable state is reached, directly outputting an original input clock signal; and if the stable state is not reached, channel impedance adjustment is performed according to the detection result until the stable state is reached, so that the problems that the existing fixed clock duty ratio setting flexibility is relatively low and the application scene compatibility is relatively low are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of clock adjustment, and specifically relates to a method and system for adjusting the clock duty cycle. Background Art

[0002] With the continuous development of communication technology, the system has higher and higher requirements for the clock. In the prior art, the clock duty cycle is usually accurately adjusted to a fixed value. However, in the application of some devices, too high a clock duty cycle will affect the power consumption of the system. For example, in the dynamic comparator of an analog-to-digital converter (ADC), when the comparator makes a comparison during the high level period, two parts of current will be generated, namely dynamic current and static current. Since the dynamic current drops to 0 after the comparison action is completed, the dynamic current is not affected by the duty cycle, but the static current will continue throughout the high level period of the clock, and the larger the clock duty cycle, the longer the high level time, and the longer the duration of the static current, and the corresponding power consumption of the analog-to-digital converter is also larger.

[0003] On the other hand, too low a clock duty cycle has problems of not being able to meet the timing constraints or compensating for the asymmetry of the signal path in some application scenarios. For example, in a digital-to-time converter (DTC), when performing dynamic delay control on the input clock, the clock falling edge is usually used for sampling the time delay control word to ensure that there is enough time to complete the control of the internal switches of the time-to-digital converter. However, when the clock duty cycle is too small, as the frequency of the input clock increases, the time interval between the clock falling edge and the rising edge of the subsequent clock is insufficient, resulting in the time-to-digital converter being unable to complete the sampling of the time delay control word.

[0004] Therefore, the existing fixed clock duty cycle setting has low flexibility, cannot achieve flexible allocation in multiple application scenarios, and cannot meet the requirements of the clock duty cycle in different application scenarios. Summary of the Invention

[0005] Aiming at the deficiencies in the prior art, the present invention provides a method and system for adjusting the clock duty cycle, which solves the problems of low flexibility of the existing fixed clock duty cycle setting and low compatibility of application scenarios.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] A method for adjusting the clock duty cycle includes the following steps:

[0008] Based on the target clock duty cycle, configure the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit, so that the duty cycle-voltage conversion circuit is in a stable state after receiving a clock signal with the target clock duty cycle;

[0009] The original input clock signal is processed to obtain a non-overlapping two-phase clock signal, resulting in a first-phase clock signal and a second-phase clock signal. At the same time, the original input clock signal is inverted to obtain an inverted input clock signal;

[0010] Based on the first-phase clock signal, the second-phase clock signal, the inverted input clock signal, and the original input clock signal, the first current source charges the first capacitor, and the second current source charges the second capacitor, and the first capacitor and the second capacitor are alternately charged;

[0011] Obtain the first voltage when the first capacitor is charged each time and the second voltage when the second capacitor is charged each time, and perform stability detection on the first voltage and the second voltage obtained each time;

[0012] If the detection result of the stability detection reaches a stable state, the original input clock signal is directly output; if the detection result does not reach a stable state, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state.

[0013] Optionally, the first current source charging the first capacitor includes the following steps:

[0014] When the first-phase clock signal is at a low level, the second-phase clock signal is at a high level, and the inverted input clock signal is at a high level, the first current source charges the first capacitor.

[0015] Optionally, the second current source charging the second capacitor includes the following steps:

[0016] When the first-phase clock signal is at a low level, the second-phase clock signal is at a high level, and the inverted input clock signal is at a low level, the second current charges the second capacitor.

[0017] Optionally, performing stability detection on the first voltage and the second voltage obtained each time includes the following steps:

[0018] Amplify the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and store all the amplified voltages;

[0019] Compare all the stored amplified voltages with a reference voltage, and generate an identification signal regarding the magnitude relationship between the first voltage and the second voltage after comparison;

[0020] Judge whether the high-level average value and the low-level average value of the identification signal are equal. If not, the detection result of the stability detection does not reach a stable state; if so, the detection result of the stability detection reaches a stable state.

[0021] Optionally, if the detection result is not in a stable state, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal, including the following steps:

[0022] The identification signal is filtered to generate a primary voltage control signal. When the average high-level value of the identification signal is greater than the average low-level value, the channel impedance is adjusted according to the primary voltage control signal to increase the falling-edge slope and decrease the rising-edge slope of the original input clock signal;

[0023] When the average high-level value of the identification signal is less than the average low-level value, the channel impedance is adjusted according to the primary voltage control signal to decrease the falling-edge slope and increase the rising-edge slope of the original input clock signal.

[0024] Optionally, the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches a stable state, including the following steps:

[0025] Obtain the input clock adjustment signal obtained after channel impedance adjustment, perform two-phase non-overlapping processing on the input clock adjustment signal to obtain a first-phase clock adjustment signal and a second-phase clock adjustment signal, and at the same time perform an inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal;

[0026] Based on the first-phase clock adjustment signal, the second-phase clock adjustment signal, the inverted input clock adjustment signal, and the input clock adjustment signal, the first current source charges the first capacitor, and the second current source charges the second capacitor, and the first capacitor and the second capacitor are alternately charged;

[0027] Obtain the first voltage when the first capacitor is charged each time and the second voltage when the second capacitor is charged each time, and re-perform stability detection on the obtained first voltage and second voltage each time;

[0028] If the detection result of the re-performed stability detection reaches a stable state, directly output the input clock adjustment signal; if the detection result is not in a stable state, generate a secondary voltage control signal according to the detection result, and adjust the channel impedance of the input clock adjustment signal based on the secondary voltage control signal until the detection result reaches a stable state.

[0029] Optionally, after the cross-charging of the first capacitor and the second capacitor is completed, the following steps are further included:

[0030] Perform a reset process on the first capacitor and the second capacitor.

[0031] Optionally, the reset process for the first capacitor and the second capacitor includes the following steps:

[0032] When the first-phase clock signal is at a high level and the second-phase clock signal is at a low level, the first capacitor and the second capacitor enter the discharge process, and when the first capacitor and the second capacitor complete the discharge, the reset is completed.

[0033] Optionally, the configuration formulas for the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit based on the target clock duty cycle are as follows:

[0034] , where D represents the target clock duty cycle, CH represents the capacitance value of the second capacitor, IL represents the current value of the first current source, CL represents the capacitance value of the first capacitor, and IH represents the current value of the second current source.

[0035] A clock duty cycle adjustment system, which is used to execute the clock duty cycle adjustment method described in any one of the above, includes a clock buffer circuit, a clock generation circuit, a duty cycle-voltage conversion circuit, a comparison circuit, and a filtering circuit;

[0036] The clock generation circuit is used to perform two-phase non-overlapping processing on the original input clock signal to obtain a first-phase clock signal and a second-phase clock signal, and at the same time perform an inversion process on the original input clock signal to obtain an inverted input clock signal;

[0037] The duty cycle-voltage conversion circuit is used to charge the first capacitor by the first current source to obtain a first voltage and charge the second capacitor by the second current source to obtain a second voltage based on the first-phase clock signal, the second-phase clock signal, the inverted input clock signal, and the original input clock signal, and the first capacitor and the second capacitor are alternately charged;

[0038] The comparison circuit is used to obtain the first voltage when the first capacitor is charged each time and the second voltage when the second capacitor is charged each time, and perform stability detection on the first voltage and the second voltage obtained each time;

[0039] The filtering circuit is used to filter the identification signal;

[0040] The clock buffer circuit is used to directly output the original input clock signal when the detection result of the stability detection reaches the stable state; when the detection result does not reach the stable state, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches the stable state.

[0041] Adopting the technical solution provided by the present invention, compared with the prior art, it has the following beneficial effects:

[0042] By configuring the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit, the duty cycle-voltage conversion circuit is made to be in a stable state after receiving a clock signal with a target clock duty cycle, serving as the basis for adjusting the clock duty cycle. At the same time, the adjustment scheme is simple. Only by adjusting the values of the first current source, the first capacitor, the second current source, and the second capacitor, any clock duty cycle adjustment can be achieved, enabling users to flexibly change the clock duty cycle according to different application scenario requirements, preventing the problem of increased power consumption caused by a too high clock duty cycle or the inability to meet timing constraints or compensate for signal path asymmetry due to a too low clock duty cycle when using a unified clock duty cycle in different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for description in the embodiments or the prior art. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1 It is a flowchart of a method for adjusting clock duty cycle proposed in Embodiment 1;

[0045] Figure 2 It is a circuit diagram for implementing the method for adjusting clock duty cycle proposed in Embodiment 1 and Embodiment 2;

[0046] Figure 3 It is a circuit diagram of a clock buffer circuit proposed in Embodiment 2;

[0047] Figure 4 It is a circuit diagram of a clock generation circuit proposed in Embodiment 2;

[0048] Figure 5 It is a circuit diagram of a duty cycle-voltage conversion circuit proposed in Embodiment 2;

[0049] Figure 6 It is a circuit diagram of a comparison circuit proposed in Embodiment 2;

[0050] Figure 7 It is a circuit diagram of a low-pass filter circuit proposed in Embodiment 2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] The present invention will be further described in detail below in conjunction with embodiments. The following embodiments are explanations of the present invention, and the present invention is not limited to the following embodiments.

[0052] Embodiment 1

[0053] As Figure 1 shown, a method for adjusting the clock duty cycle includes the following steps: Step 1: Configure the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit based on the target clock duty cycle, so that the duty cycle-voltage conversion circuit is in a stable state after receiving a clock signal with the target clock duty cycle.

[0054] As Figure 2 shown, before modulating the clock duty cycle, first configure the duty cycle-voltage conversion circuit. In the duty cycle-voltage conversion circuit, set the values of the first current source IL, the first capacitor CL, the second current source IH, and the second capacitor CH. The first capacitor CL and the second capacitor CH are alternately charged. When a clock signal is input, the charging time ratio of the first current source IL to the first capacitor CL and the charging time of the second current source IH to the second capacitor CH is equal to the duration ratio of the high and low levels in the clock signal, thereby realizing the modulation of the clock duty cycle.

[0055] Specifically, if the charging times of the first capacitor CL and the second capacitor CH are to be equal to the duration of the high and low levels in the clock signal, it is necessary to satisfy that the first voltage VL when the first capacitor CL is charged and the second voltage VH when the second capacitor CH is charged in the duty cycle-voltage conversion circuit are equal, that is: VH = VL. According to the duty cycle-voltage conversion circuit, ; , so, it can be obtained that , and since the clock duty cycle , where T is the entire clock period; TH is the charging time of the second capacitor, corresponding to the time of the high level of the input clock; TL is the charging time of the first capacitor, corresponding to the time of the low level of the input clock; therefore, substituting into the calculation formula of the clock duty cycle D, it can be obtained that .

[0056] Therefore, when it is necessary to modulate the clock duty cycle of the clock signal, first, it is necessary to configure the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit based on the target clock duty cycle D.

[0057] After the configuration is completed, since the duty cycle of the input original clock signal cannot be confirmed whether it is the duty cycle required by the current system, it is necessary to verify the clock duty cycle. First, execute Step 2: perform non-overlapping two-phase processing on the original input clock signal to obtain a first-phase clock signal and a second-phase clock signal. At the same time, invert the original input clock signal to obtain an inverted input clock signal.

[0058] Specifically, the original input clock signal is processed in three directions. The first direction is to divide the original input clock signal by two through a frequency divider, and then perform non-overlapping two-phase processing through a non-overlapping two-phase clock circuit, so as to obtain a first-phase clock signal CLKIN2_N and a second-phase clock signal CLKIN2_P with non-overlapping high levels and opposite phases; the second processing direction is to invert the original input clock signal through an inverter to obtain an inverted input clock signal CK_L with a phase opposite to that of the original input clock signal; the last processing direction is to retain the original input clock signal and mark this signal as CK_H.

[0059] Finally, based on the obtained first-phase clock signal CLKIN2_N, second-phase clock signal CLKIN2_P, inverted input clock signal CK_L, and the retained original input clock signal CK_H, a charging trigger basis for controlling the charging of the first capacitor and the second capacitor in the duty cycle-voltage conversion circuit is provided, that is: Step 3: Based on the first-phase clock signal, second-phase clock signal, inverted input clock signal, and the original input clock signal, make the first current source charge the first capacitor and the second current source charge the second capacitor, and the first capacitor and the second capacitor are alternately charged.

[0060] Among them, the first current source charging the first capacitor includes the following steps: when the first-phase clock signal CLKIN2_N is at a low level, the second-phase clock signal CLKIN2_P is at a high level, and the inverted input clock signal CK_L is at a high level, the first current IL source charges the first capacitor CL; the second current source charging the second capacitor includes the following steps: when the first-phase clock signal CLKIN2_N is at a low level, the second-phase clock signal CLKIN2_P is at a high level, and the inverted input clock signal CK_L is at a low level, the second current IH charges the second capacitor CH.

[0061] Thus, according to the high and low level conditions of the first-phase clock signal, second-phase clock signal, inverted input clock signal, and the original input clock signal, the alternate charging of the first capacitor and the second capacitor is triggered.

[0062] Then, perform step 4: obtain the first voltage VL during each charging of the first capacitor and the second voltage VH during each charging of the second capacitor, and perform stability detection on the first voltage VL and the second voltage VH obtained each time. Specifically, performing stability detection on the first voltage VL and the second voltage VH obtained each time includes the following steps: amplify the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and store all the amplified voltages; compare all the stored amplified voltages with a reference voltage, and generate an identification signal regarding the magnitude relationship between the first voltage and the second voltage after comparison; determine whether the high-level average value and the low-level average value of the identification signal are equal. If not, the detection result of the stability detection is that the stable state is not reached; if so, the detection result of the stability detection is that the stable state is reached.

[0063] More specifically, after the first capacitor CL is fully charged, obtain the first voltage VL during the charging of the first capacitor CL. After the second capacitor CH is fully charged, obtain the second voltage VH during the charging of the second capacitor CH. Then, input the first voltage VL to the negative terminal of the operational amplifier, and input the second voltage VH to the positive terminal of the operational amplifier, so as to output an amplified voltage EAO, and store the amplified voltage EAO in the holding capacitor C_HOLD.

[0064] It should be noted that since the clock signal alternates between high and low levels, the first voltage VL and the second voltage VH will be generated multiple times, and multiple amplified voltages will be generated through the operational amplifier and stored in the holding capacitor C_HOLD. Furthermore, the multiple generated amplified voltages will be compared with the reference voltage in sequence. Finally, all the comparison results generate an identification signal, where the amplified voltage EAO = (the second voltage VH - the first voltage VL) * the gain of the operational amplifier.

[0065] When the first-phase clock signal is at a high level and the second-phase clock signal is at a low level, the amplified voltage EAO stored in the holding capacitor C_HOLD is used as the positive input of the comparator and compared with the reference voltage VREF at the negative input of the comparator. If the second voltage VH is greater than the first voltage VL, it indicates that the clock duty cycle is too large. At this time, the output of the operational amplifier is at a high level, and the holding capacitor C_HOLD connected to the positive input of the comparator maintains a high level, which is greater than the reference voltage VREF. The identification signal CMPO output by the comparator is at a high level, and the system has not reached a stable state. If the second voltage VH is less than the first voltage VL, it indicates that the clock duty cycle is too small. At this time, the output of the operational amplifier is at a low level, and the holding capacitor C_HOLD connected to the positive input of the comparator maintains a low level, which is less than the reference voltage VREF. The identification signal CMPO output by the comparator is at a low level, and the system has not reached a stable state. If the second voltage VH is equal to the first voltage VL, it indicates that the clock duty cycle has reached the duty cycle to be modulated, and there is no need to adjust the channel impedance. The original input clock signal can be directly output as CLKOUT.

[0066] On the other hand, when the first-phase clock signal is at a high level and the second-phase clock signal is at a low level, the first capacitor and the second capacitor enter the discharge process, that is, the first capacitor and the second capacitor are reset. And when the first capacitor and the second capacitor complete the discharge, the reset is completed, so that the next stability detection is not affected by the previous detection result.

[0067] Further, when the detection result of the stability detection does not reach the stable state, a primary voltage control signal needs to be generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches the stable state.

[0068] Specifically, the identification signal is filtered to generate a primary voltage control signal VC. When the high-level average value of the identification signal CMPO is greater than the low-level average value, the channel impedance is adjusted according to the primary voltage control signal VC to increase the slope of the falling edge of the original input clock signal and decrease the slope of the rising edge. When the high-level average value of the identification signal CMPO is less than the low-level average value, the channel impedance is adjusted according to the primary voltage control signal VC to decrease the slope of the falling edge of the original input clock signal and increase the slope of the rising edge.

[0069] In this embodiment, a PMOS device and an NMOS device are used to adjust the channel impedance. The pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device are controlled by a primary voltage control signal VC, so as to adjust the clock edge slope of the original input clock signal. When the voltage of the primary voltage control signal VC increases (i.e., the high-level average value of the identification signal CMPO is greater than the low-level average value), the pull-up channel impedance of the corresponding PMOS device becomes larger, and the pull-down channel impedance of the NMOS device becomes smaller. Therefore, the rising edge of the original input clock signal becomes slower, the falling edge becomes steeper, and the clock duty cycle decreases; conversely, when the voltage of the primary voltage control signal VC decreases (i.e., the high-level average value of the identification signal CMPO is less than the low-level average value), the pull-up channel impedance of the corresponding PMOS device becomes smaller, and the pull-down channel impedance of the NMOS device becomes larger. Therefore, the rising edge of the original input clock signal becomes steeper, the falling edge becomes slower, and the clock duty cycle increases.

[0070] After the channel impedance adjustment is completed, in order to ensure that the clock signal reaches the final required target clock duty cycle, it is also necessary to perform a stability detection on the input clock adjustment signal after the channel impedance adjustment is completed until the detection result reaches a stable state.

[0071] Specifically, it includes the following steps: obtaining the input clock adjustment signal obtained after the channel impedance adjustment, performing two-phase non-overlapping processing on the input clock adjustment signal to obtain a first-phase clock adjustment signal and a second-phase clock adjustment signal, and at the same time performing an inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal; based on the first-phase clock adjustment signal, the second-phase clock adjustment signal, the inverted input clock adjustment signal, and the input clock adjustment signal, enabling a first current source to charge a first capacitor, and enabling a second current source to charge a second capacitor, and the first capacitor and the second capacitor are alternately charged; obtaining a first voltage when the first capacitor is charged each time and a second voltage when the second capacitor is charged each time, and re-performing a stability detection on the first voltage and the second voltage obtained each time; if the detection result of the re-performed stability detection reaches a stable state, directly output the input clock adjustment signal; if the detection result does not reach a stable state, generate a secondary voltage control signal according to the detection result, and perform channel impedance adjustment on the input clock adjustment signal based on the secondary voltage control signal until the detection result reaches a stable state.

[0072] The processing method of the input clock adjustment signal CLK is the same as that of the original input clock signal. First, the clock adjustment signal is processed in three directions. The first direction is to divide the input clock adjustment signal CLK by a frequency divider and then perform two-phase non-overlapping processing through a two-phase non-overlapping clock circuit, so as to obtain a first-phase clock adjustment signal CLKIN2_N' and a second-phase clock adjustment signal CLKIN2_P' with non-overlapping high levels and opposite phases. The second processing direction is to invert the input clock adjustment signal CLK through an inverter to obtain an inverted input clock adjustment signal CK_L with a phase opposite to that of the input clock adjustment signal CLK. The last processing direction is to retain the input clock adjustment signal CLK and mark this signal as CK_H.

[0073] Then, based on the obtained first-phase clock adjustment signal CLKIN2_N', second-phase clock adjustment signal CLKIN2_P', inverted input clock adjustment signal CK_L, and the retained input clock adjustment signal CK_H, a charging trigger basis for controlling the charging of the first capacitor and the second capacitor in the duty cycle-voltage conversion circuit is provided, enabling the first current source to charge the first capacitor and the second current source to charge the second capacitor, and the first capacitor and the second capacitor are alternately charged.

[0074] Among them, the first current source charging the first capacitor includes the following steps: when the first-phase clock adjustment signal CLKIN2_N' is at a low level, the second-phase clock adjustment signal CLKIN2_P' is at a high level, and the inverted input clock adjustment signal CK_L is at a high level, the first current IL source charges the first capacitor CL; the second current source charging the second capacitor includes the following steps: when the first-phase clock adjustment signal CLKIN2_N' is at a low level, the second-phase clock adjustment signal CLKIN2_P' is at a high level, and the inverted input clock adjustment signal CK_L is at a low level, the second current IH charges the second capacitor CH.

[0075] It should be noted that since the first capacitor and the second capacitor have been discharged and reset before this charging, when the first capacitor and the second capacitor are charged this time, the charging time of both can accurately reflect the duration of the high and low levels respectively, that is, it can accurately correspond to the duty cycle of the clock signal.

[0076] Thus, the alternate charging of the first capacitor and the second capacitor is triggered according to the high and low level conditions of the first-phase clock adjustment signal, second-phase clock adjustment signal, inverted input clock adjustment signal, and input clock adjustment signal.

[0077] Next, the difference between the first voltage and the second voltage obtained each time is amplified to obtain an amplified voltage, and all the amplified voltages are stored; all the stored amplified voltages are compared with a reference voltage, and an identification signal regarding the magnitude relationship between the first voltage and the second voltage is generated after the comparison; it is determined whether the high-level average value and the low-level average value of the identification signal are equal. If not, the detection result of the stability detection is that the stable state is not reached; if so, the detection result of the stability detection is that the stable state is reached.

[0078] More specifically, after the first capacitor CL is fully charged, the first voltage VL during the charging of the first capacitor CL is obtained. After the second capacitor CH is fully charged, the second voltage VH during the charging of the second capacitor CH is obtained. Then, the first voltage VL is input to the negative terminal of the operational amplifier, and the second voltage VH is input to the positive terminal of the operational amplifier, thereby outputting an amplified voltage EAO, and the amplified voltage EAO is stored in the holding capacitor C_HOLD.

[0079] When the first-phase clock adjustment signal is at a high level and the second-phase clock adjustment signal is at a low level, the amplified voltage EAO stored in the holding capacitor C_HOLD is used as the positive input of the comparator and compared with the reference voltage VREF input to the negative terminal of the comparator. If the second voltage VH is greater than the first voltage VL, it means that the clock duty cycle is too large. At this time, the output of the operational amplifier is at a high level, and the holding capacitor C_HOLD connected to the positive terminal of the comparator maintains a high level, which is greater than the reference voltage VREF. The identification signal CMPO output by the comparator is at a high level, and the system has not reached a stable state; if the second voltage VH is less than the first voltage VL, it means that the clock duty cycle is too small. At this time, the output of the operational amplifier is at a low level, and the holding capacitor C_HOLD connected to the positive terminal of the comparator maintains a low level, which is less than the reference voltage VREF. The identification signal CMPO output by the comparator is at a low level, and the system has not reached a stable state; if the second voltage VH is equal to the first voltage VL, it means that the clock duty cycle has reached the required modulation duty cycle, and there is no need to adjust the channel impedance. The original input clock signal can be directly output as CLKOUT.

[0080] On the other hand, when the first-phase clock adjustment signal is at a high level and the second-phase clock adjustment signal is at a low level, the first capacitor and the second capacitor enter the discharging process, that is: the first capacitor and the second capacitor are reset, and when the first capacitor and the second capacitor are fully discharged, the reset is completed, so that the next stability detection is not affected by the previous detection result.

[0081] Furthermore, when the detection result of the stability detection does not reach the stable state, a secondary voltage control signal needs to be generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the secondary voltage control signal until the detection result reaches the stable state.

[0082] Specifically, the identification signal is filtered to generate a secondary voltage control signal VC. When the high-level average value of the identification signal CMPO is greater than the low-level average value, the channel impedance is adjusted according to the secondary voltage control signal VC to increase the falling-edge slope and decrease the rising-edge slope of the input clock adjustment signal. When the high-level average value of the identification signal CMPO is less than the low-level average value, the channel impedance is adjusted according to the secondary voltage control signal VC to decrease the falling-edge slope and increase the rising-edge slope of the input clock adjustment signal.

[0083] In this embodiment, a PMOS device and an NMOS device are borrowed to implement the adjustment of the channel impedance. The secondary voltage control signal VC is used to control the pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device, thereby adjusting the clock edge slope of the input clock adjustment signal. When the voltage of the secondary voltage control signal VC increases (i.e., the high-level average value of the identification signal CMPO is greater than the low-level average value), the pull-up channel impedance of the corresponding PMOS device becomes larger, and the pull-down channel impedance of the NMOS device becomes smaller. Therefore, the rising edge of the input clock adjustment signal becomes slower, the falling edge becomes steeper, and the clock duty cycle decreases. On the contrary, when the voltage of the secondary voltage control signal VC decreases (i.e., the high-level average value of the identification signal CMPO is less than the low-level average value), the pull-up channel impedance of the corresponding PMOS device becomes smaller, and the pull-down channel impedance of the NMOS device becomes larger. Therefore, the rising edge of the input clock adjustment signal becomes steeper, the falling edge becomes slower, and the clock duty cycle increases.

[0084] After the channel impedance adjustment is completed, to ensure that the clock signal reaches the final required target clock duty cycle, similarly, the input clock adjustment signal after the channel impedance adjustment needs to be subjected to a stability test again. If the stable state is not reached, the voltage control signal is repeatedly generated to adjust the channel impedance until the test result reaches the stable state.

[0085] The present invention configures the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit so that the duty cycle-voltage conversion circuit is in a stable state after receiving a clock signal with a target clock duty cycle, as the adjustment basis of the clock duty cycle. At the same time, the adjustment scheme is simple. By only adjusting the values of the first current source, the first capacitor, the second current source, and the second capacitor, any clock duty cycle can be adjusted, enabling users to flexibly change the clock duty cycle according to different application scenario requirements, preventing the problems of increased power consumption caused by a too high clock duty cycle or inability to meet the timing constraints or compensate for the signal path asymmetry caused by a too low clock duty cycle when using a unified clock duty cycle in different application scenarios.

[0086] On the other hand, the present invention provides a control basis for alternately charging the first capacitor and the second capacitor through two-phase non-overlapping processing and inverting processing of the original input clock signal, maps the charging time of the first capacitor and the second capacitor to the high and low level durations of the original input clock signal, verifies whether the clock duty cycle accurately reaches the target value according to stability detection, and when the detection result does not reach the stable state, adjusts it by means of channel impedance regulation to achieve precise modulation of the clock duty cycle.

[0087] Embodiment 2

[0088] As Figure 2 shown, a clock duty cycle adjustment system includes a clock buffer circuit, a clock generation circuit, a duty cycle-voltage conversion circuit, a comparison circuit, and a filtering circuit; the output end of the clock generation circuit is connected to the input end of the duty cycle-voltage conversion circuit, the output end of the duty cycle-voltage conversion circuit is connected to the input end of the comparison circuit, the input end of the comparison circuit is also connected to the output end of the clock generation circuit, the input end of the filtering circuit is respectively connected to the output end of the clock generator and the output end of the comparison circuit, the output end of the filtering circuit is connected to the input end of the clock buffer circuit, and the output end of the clock buffer circuit is connected to the input end of the clock generation circuit.

[0089] Among them, as Figure 3 shown, the clock buffer circuit includes a plurality of series-connected PMOS devices and a plurality of series-connected NMOS devices, and the plurality of series-connected PMOS devices and the plurality of series-connected NMOS are connected. The input end of the clock buffer circuit inputs the original clock signal CLKIN and the voltage control signal VC.

[0090] The main function of the clock buffer circuit is to receive the input clock and adjust the slope of its output clock edge by controlling the pull-up channel impedance of the PMOS device and the pull-down channel impedance of the NMOS device through the voltage control signal VC. When the voltage of the voltage control signal VC increases, the pull-up channel impedance of the corresponding PMOS device becomes larger, and the pull-down channel impedance of the NMOS device becomes smaller. Therefore, the rising edge of the output clock becomes slower, the falling edge becomes steeper, and the duty cycle decreases; conversely, when the voltage of the voltage control signal VC decreases, the pull-up channel impedance of the corresponding PMOS device becomes smaller, and the pull-down channel impedance of the NMOS device becomes larger. Therefore, the rising edge of the output clock becomes steeper, the falling edge becomes slower, and the duty cycle increases.

[0091] As Figure 4As shown in the figure, the clock generation circuit includes a frequency divider by two, a two-phase non-overlapping clock generation circuit, an inverter, an AND logic 1, and an AND logic 2. The input end of the frequency divider by two receives the signal CLK. The output end of the frequency divider by two is connected to the output end of the two-phase non-overlapping clock generation circuit, and the output end of the two-phase non-overlapping clock generation circuit outputs the signal CLKIN2_N and the signal CLKIN2_P. The signal CLK also inputs to the input end of the inverter, and the output end of the inverter outputs the signal CK_L. The input ends of the AND logic 1 respectively receive the signal CLKIN2_P and the signal CK_L, and output the SL signal. The input ends of the AND logic 2 respectively receive the signal CLKIN2_P and the signal CLK (i.e., the signal CK_H), and output the SH signal.

[0092] The main function of the clock generator is to generate non-overlapping clock signals to control the opening and closing of the subsequent switches. Its principle is to use a frequency division circuit by two and logic gate circuits for logical combination. The high-level time of SL and SH corresponds to the low-level time and high-level time of its input clock. The frequency division circuit by two divides its input clock by two. During the high-level period after frequency division, it is used to convert the duty cycle of the input clock into voltage. During the low-level period, the comparison signal is filtered and fed back to the clock buffer, and at the same time, the CL and CH capacitors are reset.

[0093] As Figure 5 shown in the figure, the duty cycle-voltage conversion circuit includes a first current source IL, a second current source IH, a first switch S1, a second switch S2, a fourth switch S4, a fifth switch S5, a first capacitor CL, and a second capacitor CH. Its main function is to convert the clock duty cycle information into a voltage signal. Its principle is to control the constant current source to charge the capacitor through SL and SH, and finally generate a voltage signal on the capacitor.

[0094] Among them, the process of converting the clock duty cycle information into a voltage signal is as follows:

[0095] When CLKIN2_P is at a high level and CLKIN2_N is at a low level: First, the AND logic 1 and the AND logic 2 normally transmit CK_L and CK_H to SL and SH. At the same time, the reset circuit controlled by CLKIN2_N disconnects the upper plate of the capacitor from the ground (i.e., the fourth switch S4 and the fifth switch S5 are disconnected); then when CK_L is at a high level, SL becomes a high level. At this time, the first switch S1 controlled by SL is closed, and the first current source IL charges the first capacitor CL with a constant current. If the high-level duration of SL is TL, then the first voltage VL at the node is equal to IL×TL÷CL; similarly, when CK_H is at a high level, SH becomes a high level. At this time, the second switch controlled by SH is closed, and the second current source IH charges the second capacitor CH with a constant current. If the high-level duration of SH is TH, then the second voltage VH at the node is equal to IH×TH÷CH.

[0096] When CLKIN2_P is at a low level and CLKIN2_N is at a high level: First, the AND logic 1 and AND logic 2 output a low level. SL and SH are not controlled by CK_L and CK_H and are always at a low level, and their corresponding first switch S1 and second switch S2 are always in an open state. Second, the reset circuit conducts (i.e., the fourth switch S4 and the fifth switch S5 are closed), and the first capacitor CL and the second capacitor CH are discharged to the ground through the reset switches (the fourth switch S4 and the fifth switch S5). After the discharge is completed, the voltages VH = VL = 0 on the capacitors.

[0097] As Figure 6 shown, the comparison circuit includes an operational amplifier, a holding capacitor, and a comparator. The positive input of the operational amplifier receives the second voltage VH and the first voltage VL. The output of the operational amplifier is connected to the third switch S3, and the on / off of the third switch is controlled by the signal CLKIN2_P. The other end of the third switch is connected to the holding capacitor and the positive input terminal of the comparator. The negative input terminal of the comparator receives the reference voltage VREF, and the output terminal of the comparator outputs the identification signal CMPO.

[0098] The main function of the comparison circuit is to compare the magnitudes of VH and VL. The comparison result is the relationship between the actual duty cycle and the ideal duty cycle. When the output is at a high level, it indicates that the duty cycle is larger than the expected value. Conversely, the actual duty cycle is less than the expected duty cycle. Its principle is to amplify the difference between VH and VL through the operational amplifier, and compare the amplified EAO with the reference voltage (VREF) input to the comparator, and generate an identification signal of the magnitude relationship between VH and VL.

[0099] As Figure 7 shown, the main function of the low-pass filter circuit is to filter the square wave signal output by the comparator and output a DC voltage signal. It includes a sixth switch S6 and a low-pass filter. The on / off of the sixth switch S6 is controlled by the signal CLKIN2_N. When the sixth switch S6 conducts, the input terminal of the low-pass filter receives the identification signal CMPO, and the output terminal of the low-pass filter outputs the voltage control signal VC.

[0100] Furthermore, the operating principles of the duty cycle-voltage conversion circuit, the comparison circuit, and the low-pass filter circuit are as follows:

[0101] When the CLKIN2_P clock is at a high level, at this time, the control signal SL of the first switch S1 is the same as CK_L, and the control signal SH of the second switch S2 is the same as CK_H. The third switch S3 conducts, and the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all in an off state. At this time, the system is in the sampling stage, and the duty cycle information of the clock output by the clock buffer circuit is sampled and processed through the duty cycle-voltage converter and the comparison circuit.

[0102] When the CLKIN2_N clock is at a high level, the first switch S1, the second switch S2, and the third switch S3 are all turned off, and the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned on. At this time, the system is in the feedback stage. The output voltage control signal VC of the low-pass filter is used to control the pull-up impedance and pull-down impedance of the clock buffer, so as to adjust the clock edge slope and finally adjust the duty cycle of the output clock.

[0103] The specific process is as follows:

[0104] First, when CLKIN2_P is at a high level and CLKIN2_N is at a low level:

[0105] If CLK is at a high level, at this time CK_H is at a high level, SH is at a high level, and the second switch S2 is turned on. The second current source IH charges the second capacitor CH. If the high-level duration of SH is TH, then there is ;

[0106] If CLK is at a low level, at this time CK_L is at a high level, SL is at a high level, and the first switch S1 is turned on. The first current source IL charges the first capacitor CL. If the high-level duration of SL is TL, then there is ;

[0107] If the second voltage VH is greater than the first voltage VL, it means that the duty cycle is too large. At this time, the output voltage EAO of the operational amplifier is at a high level, and the hold capacitor C_HOLD connected to the positive terminal of the comparator maintains a high level. This high level is greater than the VREF voltage, and the comparator output CMPO is at a high level;

[0108] If the first voltage VL is greater than the second voltage VH, it means that the duty cycle is too small. At this time, the output voltage EAO of the operational amplifier is at a low level, and the hold capacitor C_HOLD connected to the positive terminal of the comparator maintains a low level. This high level is less than the VREF voltage, and the comparator output CMPO is at a low level.

[0109] Second, when CLKIN2_P is at a low level and CLKIN2_N is at a high level:

[0110] If the comparator output CMPO is at a high level, the output voltage of the low-pass filter increases, that is, the VC voltage increases. The pull-down impedance of the clock buffer circuit decreases, and the pull-up impedance increases. At this time, the falling edge slope increases, the rising edge slope decreases, and the duty cycle decreases;

[0111] If the comparator output CMPO is at a low level, the output voltage of the low-pass filter decreases, that is, the VC voltage decreases. The pull-down impedance of the clock buffer circuit increases, and the pull-up impedance decreases. At this time, the falling edge slope decreases, the rising edge slope increases, and the duty cycle increases;

[0112] When the system is stable, VH and VL are equal, and the average level of the comparator output CMPO is the average of its output high level and low level.

[0113] Finally, since the clock duty cycle adjustment system of this embodiment is used to execute the clock duty cycle adjustment method as shown in Embodiment 1, therefore, the clock generation circuit is used to perform two-phase non-overlapping processing on the original input clock signal to obtain a first-phase clock signal and a second-phase clock signal, and at the same time perform an inversion process on the original input clock signal to obtain an inverted input clock signal; the duty cycle-voltage conversion circuit is used to charge a first capacitor by a first current source to obtain a first voltage and charge a second capacitor by a second current source to obtain a second voltage based on the first-phase clock signal, the second-phase clock signal, the inverted input clock signal, and the original input clock signal, and the first capacitor and the second capacitor are alternately charged; the comparison circuit is used to obtain the first voltage when the first capacitor is charged each time and the second voltage when the second capacitor is charged each time, and perform stability detection on the first voltage and the second voltage obtained each time; the filtering circuit is used to filter the identification signal; the clock buffer circuit is used to directly output the original input clock signal when the detection result of the stability detection reaches the stable state; when the detection result does not reach the stable state, a primary voltage control signal is generated according to the detection result, and the channel impedance of the original input clock signal is adjusted based on the primary voltage control signal until the detection result reaches the stable state.

[0114] The above is only the preferred embodiment of the present invention, and it is not a limitation to any form and essence of the present invention. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the method of the present invention, several improvements and supplements can still be made, and these improvements and supplements should also be regarded as the protection scope of the present invention. Those skilled in the art, without departing from the spirit and scope of the present invention, when making some equivalent changes, modifications and evolutions using the technical content disclosed above, are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for adjusting the clock duty cycle, characterized in that, Including the following steps: Configuring the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty cycle-voltage conversion circuit based on the target clock duty cycle, so that the duty cycle-voltage conversion circuit is in a stable state after inputting a clock signal with the target clock duty cycle; Performing two-phase non-overlapping processing on the original input clock signal to obtain a first-phase clock signal and a second-phase clock signal, and simultaneously performing inversion processing on the original input clock signal to obtain an inverted input clock signal; Based on the first-phase clock signal, the second-phase clock signal, the inverted input clock signal, and the original input clock signal, causing the first current source to charge the first capacitor, the second current source to charge the second capacitor, and the first capacitor and the second capacitor to be alternately charged; Obtaining a first voltage when the first capacitor is charged each time and a second voltage when the second capacitor is charged each time, and performing stability detection on the first voltage and the second voltage obtained each time; If the detection result of the stability detection reaches a stable state, directly outputting the original input clock signal; if the detection result does not reach a stable state, generating a primary voltage control signal according to the detection result, and adjusting the channel impedance of the original input clock signal based on the primary voltage control signal until the detection result reaches a stable state.

2. The clock duty cycle adjustment method according to claim 1, wherein The first current source charging the first capacitor includes the following steps: When the first-phase clock signal is at a low level, the second-phase clock signal is at a high level, and the inverted input clock signal is at a high level, the first current source charges the first capacitor.

3. A method for adjusting the clock duty cycle according to claim 1, characterized in that, The second current source charging the second capacitor includes the following steps: When the first-phase clock signal is at a low level, the second-phase clock signal is at a high level, and the inverted input clock signal is at a low level, the second current charges the second capacitor.

4. A method for adjusting the clock duty cycle according to any one of claims 1-3, characterized in that, Performing stability detection on the first voltage and the second voltage obtained each time includes the following steps: Amplifying the difference between the first voltage and the second voltage obtained each time to obtain an amplified voltage, and storing all the amplified voltages; Comparing all the stored amplified voltages with a reference voltage, and generating an identification signal regarding the magnitude relationship between the first voltage and the second voltage after comparison; Judging whether the high-level average value and the low-level average value of the identification signal are equal. If not, the detection result of the stability detection does not reach a stable state; if so, the detection result of the stability detection reaches a stable state.

5. A clock duty cycle adjustment method according to claim 4, characterized in that If the detection result does not reach a stable state, generating a primary voltage control signal according to the detection result, and adjusting the channel impedance of the original input clock signal based on the primary voltage control signal includes the following steps: Filtering the identification signal to generate a primary voltage control signal. When the high-level average value of the identification signal is greater than the low-level average value, adjusting the channel impedance according to the primary voltage control signal to increase the falling-edge slope and decrease the rising-edge slope of the original input clock signal. When the high - voltage average value of the identification signal is less than the low - voltage average value, adjust the channel impedance according to the primary voltage control signal to reduce the falling - edge slope and increase the rising - edge slope of the original input clock signal.

6. A method for adjusting the clock duty cycle according to claim 1, characterized in that, Based on the primary voltage control signal, perform channel impedance adjustment on the original input clock signal until the detection result reaches a stable state, including the following steps: Obtain the input clock adjustment signal obtained after channel impedance adjustment, perform two - phase non - overlapping processing on the input clock adjustment signal to obtain a first - phase clock adjustment signal and a second - phase clock adjustment signal, and at the same time, perform inversion processing on the input clock adjustment signal to obtain an inverted input clock adjustment signal; Based on the first - phase clock adjustment signal, the second - phase clock adjustment signal, the inverted input clock adjustment signal, and the input clock adjustment signal, make the first current source charge the first capacitor, and the second current source charge the second capacitor, and the first capacitor and the second capacitor are alternately charged; Obtain the first voltage when the first capacitor is charged each time and the second voltage when the second capacitor is charged each time, and re - perform stability detection on the first voltage and the second voltage obtained each time; If the detection result of the re - performed stability detection reaches a stable state, directly output the input clock adjustment signal; if the detection result does not reach a stable state, generate a secondary voltage control signal according to the detection result, and based on the secondary voltage control signal, perform channel impedance adjustment on the input clock adjustment signal until the detection result reaches a stable state.

7. A method for adjusting the clock duty cycle according to claim 1, characterized in that, After each cross - charging of the first capacitor and the second capacitor is completed, the following steps are further included: Perform a reset process on the first capacitor and the second capacitor.

8. A method for adjusting the clock duty cycle according to claim 7, characterized in that, Performing a reset process on the first capacitor and the second capacitor includes the following steps: When the first - phase clock signal is at a high level and the second - phase clock signal is at a low level, the first capacitor and the second capacitor enter a discharging process, and when the first capacitor and the second capacitor complete discharging, the reset is completed.

9. A method for adjusting the clock duty cycle according to claim 1, characterized in that The configuration formula for configuring the values of the first current source, the first capacitor, the second current source, and the second capacitor in the duty - cycle - to - voltage conversion circuit based on the target clock duty cycle is as follows: , where D represents the target clock duty cycle, CH represents the capacitance value of the second capacitor, IL represents the current value of the first current source, CL represents the capacitance value of the first capacitor, and IH represents the current value of the second current source.

10. A clock duty cycle adjustment system, characterized in that The clock duty - cycle adjustment system is used to execute the clock duty - cycle adjustment method according to any one of claims 1 - 9, and includes a clock buffer circuit, a clock generation circuit, a duty - cycle - to - voltage conversion circuit, a comparison circuit, and a filtering circuit; The clock generation circuit is used to perform two - phase non - overlapping processing on the original input clock signal to obtain a first - phase clock signal and a second - phase clock signal, and at the same time, perform inversion processing on the original input clock signal to obtain an inverted input clock signal; The duty - cycle - to - voltage conversion circuit is used to, based on the first - phase clock signal, the second - phase clock signal, the inverted input clock signal, and the original input clock signal, make the first current source charge the first capacitor to obtain a first voltage, and the second current source charge the second capacitor to obtain a second voltage, and the first capacitor and the second capacitor are alternately charged; The comparison circuit is configured to obtain a first voltage during each charging of the first capacitor and a second voltage during each charging of the second capacitor, and perform stability detection on the obtained first voltage and second voltage each time; The filtering circuit is configured to filter the identification signal; The clock buffer circuit is configured to directly output the original input clock signal when the detection result of the stability detection reaches the stable state; when the detection result does not reach the stable state, generate a primary voltage control signal according to the detection result, and adjust the channel impedance of the original input clock signal based on the primary voltage control signal until the detection result reaches the stable state.

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