Module for controlling three wires through two wires and control method

Abstract

The invention aims to provide the module for controlling three wires by using two wires and the control method, an IO expansion chip is not needed, an additional third signal is generated from the existing clock signal, three control signals are obtained from two IO ports, and the purpose of saving cost is achieved. A clock signal is connected to the positive input end of a first voltage comparator through an input resistor, the negative input end of the first voltage comparator is connected with the negative input end of a second voltage comparator, the negative input end of the first voltage comparator is connected with a node of a first divider resistor and a node of a second divider resistor, and the output end of the first voltage comparator is divided into two paths, one path is connected to the positive input end of the second voltage comparator through a charging resistor, the other path is connected to the positive input end of the second voltage comparator through a discharging resistor and a discharging diode, the positive input end of the second voltage comparator is connected with the system ground through a capacitor, and the output end of the second voltage comparator serves as a port of a third signal. The method is applied to the technical field of IO expansion.

Description

Technical Field

[0001] The present invention is applied to the technical field of IO expansion, and particularly relates to a module and a control method for controlling three lines with two lines. Background Art

[0002] The original design only reserved 2 IO ports for controlling the actions of external devices. Since the design has been finalized and cannot be modified, the IO of the master controller cannot meet the requirements. If more IO ports are obtained through an expansion chip, the cost will increase. For example, the Chinese patent with the publication number CN201477572U discloses a DVI-I interface expansion device, which redefines the 4th and 5th pins of the DVI-I interface. Existing DVI monitors all use a single-channel bus to transmit data. Therefore, the 4th and 5th pins of the existing DVI-I interface are reserved and unused. The 4th pin of the existing DVI-I interface is defined as DATA4- (data 4 negative), and it redefines the 4th pin of the DVI-I interface as VGA_SCL (VGA display data channel clock). The 5th pin of the existing DVI-I interface is defined as DATA4+ (data 4 positive), and it redefines the 5th pin of the DVI-I interface as VGA_SDA (VGA display data channel data). Although more IO ports are obtained, the cost is relatively high. Therefore, it is necessary to provide a module and a control method for controlling three lines with two lines, without using an IO expansion chip, generating an additional third signal from the existing clock signal, and realizing obtaining three control signals from two IO ports, so as to achieve the purpose of cost savings. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, and provide a module and a control method for controlling three lines with two lines, without using an IO expansion chip, generating an additional third signal from the existing clock signal, and realizing obtaining three control signals from two IO ports, so as to achieve the purpose of cost savings.

[0004] The technical solution adopted by the present invention is as follows: The present invention includes an input resistor, a first voltage comparator, a second voltage comparator, a first voltage-dividing resistor, a second voltage-dividing resistor, a charging resistor, a discharging resistor, a discharging diode, and a capacitor. The clock signal is connected to the positive input terminal of the first voltage comparator through the input resistor. The negative input terminal of the first voltage comparator is connected to the negative input terminal of the second voltage comparator. The negative input terminal of the first voltage comparator is connected to the node of the first voltage-dividing resistor and the second voltage-dividing resistor. The second voltage-dividing resistor is connected to the system ground. The output terminal of the first voltage comparator is divided into two paths. One path is connected to the positive input terminal of the second voltage comparator through the charging resistor, and the other path is connected to the positive input terminal of the second voltage comparator through the discharging resistor and the discharging diode. The positive input terminal of the second voltage comparator is connected to the system ground through the capacitor. The output terminal of the second voltage comparator serves as the port of the third signal.

[0005] As can be seen from the above solution, this application is applicable to a circuit module that requires only two IO control signals, namely the clock signal CLK and the data signal SDA, but needs the third signal STB to work together. The third signal STB required by the module is valid at a low level and needs to remain at a low level during data transmission. The data latch time of the module is generated at the rising edge of the clock signal CLK. This application can generate an additional third signal from the existing clock signal without using an IO expansion chip, thereby achieving the purpose of cost savings.

[0006] A preferred solution is that the module for controlling three lines with two lines further includes a first feedback resistor and a second feedback resistor. The positive input terminal of the first voltage comparator is connected to the output terminal of the first voltage comparator through the first feedback resistor. The positive input terminal of the second voltage comparator is connected to the output terminal of the second voltage comparator through the second feedback resistor.

[0007] A preferred solution is that the module for controlling three lines with two lines further includes a first voltage source and a second voltage source. The first voltage source is connected to the first voltage comparator, and the first voltage source provides power supply for the first voltage comparator. The other end of the first voltage-dividing resistor is connected to the first voltage source. The second voltage source is connected to the second voltage comparator, and the second voltage source provides power supply for the second voltage comparator.

[0008] A preferred solution is that the resistance values of the first voltage-dividing resistor and the second voltage-dividing resistor are equal, and the voltage at the connection point of the first voltage-dividing resistor and the second voltage-dividing resistor is half of the first voltage source.

[0009] A preferred solution is that the control method includes the following steps: Step 1: When the clock signal changes from low level to high level and delays for a period of time, the third signal changes from low level to high level. The clock signal is the input terminal of this module. Step 2: Since the resistance values of the first voltage-dividing resistor and the second voltage-dividing resistor are equal, the voltage at the negative input terminal of the first voltage comparator is half of the first voltage source. Step 3: When the clock signal is idle, the level is high. Step 4: Since the voltage at the negative input terminal of the first voltage comparator is half of the first voltage source, and the voltage at the positive input terminal of the first voltage comparator is higher than the voltage at the negative input terminal of the first voltage comparator, the output of the first voltage comparator is high level. Step 5: The high-level output of the first voltage comparator charges the positive electrode of the capacitor through the charging resistor. Step 6: The voltage of the positive electrode of the capacitor becomes higher and higher. Since the positive electrode of the capacitor is connected to the positive input terminal of the second voltage comparator, therefore, the voltage at the positive input terminal of the second voltage comparator also becomes higher and higher. Step 7: Until the voltage at the positive input terminal of the second voltage comparator is higher than the voltage at the negative input terminal of the second voltage comparator, the output of the second voltage comparator is high level. Step 8: At this time, the clock signal is high level, and the third signal is also high level. Step 9: When the clock signal changes from high level to low level, the voltage at the positive input terminal of the first voltage comparator is the voltage obtained by dividing the output voltage of the first voltage comparator by the input resistor and the first feedback resistor. Step 10: Since the resistance value of the input resistor is much smaller than the resistance value of the first feedback resistor, the voltage at the positive input terminal of the first voltage comparator is lower than the voltage at the negative input terminal of the first voltage comparator, and the output terminal of the first voltage comparator is low level. Step 11: The voltage of the positive electrode of the capacitor discharges to the output terminal of the first voltage comparator through the discharge diode and the discharge resistor. Step 12: Since the resistance value of the discharge resistor is small, the voltage of the positive electrode of the capacitor drops rapidly. Step 13: Since the positive input terminal of the voltage comparator U2 is connected to the positive electrode of the capacitor, the voltage at the positive input terminal of the second voltage comparator is equal to the voltage of the positive electrode of the capacitor. When the voltage of the positive electrode of the capacitor drops to be lower than half of the first voltage source, the voltage at the positive input terminal of the second voltage comparator is lower than the voltage at the negative input terminal of the second voltage comparator, and the output of the second voltage comparator becomes low level. Step 14: Since the voltage of the capacitor drops rapidly, after the clock signal changes from high level to low level, the third signal also rapidly changes from high level to low level; Step 15: When the clock signal changes from low level to high level, since the resistance value of the input resistor is much smaller than that of the first feedback resistor, the voltage at the positive input terminal of the first voltage comparator is higher than the voltage at the negative input terminal of the first voltage comparator, and the output terminal of the first voltage comparator is at high level; Step 16: The positive electrode of the capacitor is charged through the charging resistor. Since the resistance value of the charging resistor is large, the capacitor is charged slowly; before the positive electrode voltage of the capacitor reaches half of the first voltage source, the output of the second voltage comparator remains at low level; due to the arrival of a new clock cycle, the clock signal changes from high level back to low level; Step 17: Repeat this way. When the clock signal continuously changes between high and low levels, the output of the second voltage comparator remains at low level; Step 18: When the data transmission ends, after the clock signal remains at high level for a period of time, when the positive electrode voltage of the capacitor rises to be higher than half of the first voltage source, the output of the second voltage comparator becomes high level; Step 19: Since the resistance value of the charging resistor is much larger than that of the discharging resistor, the charging time of the capacitor is much longer than its discharging time, so that when the clock signal changes from high level to low level, the third signal can rapidly change from high level to low level, and after the clock signal changes from low level to high level and lasts for a period of time, the third signal can change from low level to high level. This time is jointly determined by the charging resistor and the capacitor. Description of the Drawings

[0010] Figure 1 is the circuit schematic diagram of the present invention; Figure 2 is the circuit simulation of the present invention. Detailed Embodiment

[0011] Such as Figure 1 And Figure 2As shown, in this embodiment, the present invention includes an input resistor R1, a first voltage comparator U1, a second voltage comparator U2, a first voltage-dividing resistor R2, a second voltage-dividing resistor R3, a charging resistor R5, a discharging resistor R9, a discharging diode D1, and a capacitor C1. The clock signal CLK is connected to the positive input terminal of the first voltage comparator U1 through the input resistor R1. The negative input terminal of the first voltage comparator U1 is connected to the negative input terminal of the second voltage comparator U2. The negative input terminal of the first voltage comparator U1 is connected to the node of the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3. The second voltage-dividing resistor R3 is connected to the system ground. The output terminal of the first voltage comparator U1 is branched into two paths. One path is connected to the positive input terminal of the second voltage comparator U2 through the charging resistor R5, and the other path is connected to the positive input terminal of the second voltage comparator U2 through the discharging resistor R9 and the discharging diode D1. The positive input terminal of the second voltage comparator U2 is connected to the system ground through the capacitor C1. The output terminal of the second voltage comparator U2 serves as the port of the third signal STB.

[0012] As Figure 1 and Figure 2 shown, in this embodiment, the module for controlling three lines with two lines further includes a first feedback resistor R4 and a second feedback resistor R8. The positive input terminal of the first voltage comparator U1 is connected to the output terminal of the first voltage comparator U1 through the first feedback resistor R4. The positive input terminal of the second voltage comparator U2 is connected to the output terminal of the second voltage comparator U2 through the second feedback resistor R8.

[0013] As Figure 1 and Figure 2 shown, in this embodiment, the module for controlling three lines with two lines further includes a first voltage source V1 and a second voltage source V2. The first voltage source V1 is connected to the first voltage comparator U1. The first voltage source V1 provides power supply for the first voltage comparator U1. The other end of the first voltage-dividing resistor R2 is connected to the first voltage source V1. The second voltage source V2 is connected to the second voltage comparator U2. The second voltage source V2 provides power supply for the second voltage comparator U2.

[0014] As Figure 1 and Figure 2 shown, in this embodiment, the resistance value of the first voltage-dividing resistor R2 is equal to the resistance value of the second voltage-dividing resistor R3. The voltage at the connection point of the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 is half of the first voltage source V1.

[0015] As Figure 1 and Figure 2 shown, in this embodiment, the control method includes the following steps: Step 1: When the clock signal CLK changes from low level to high level and delays for a period of time, the third signal STB changes from low level to high level. The clock signal CLK is the input terminal of this module. Step 2: Since the resistance values of the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 are equal, the voltage at the negative input terminal of the first voltage comparator U1 is half of the first voltage source V1. Step 3: When the clock signal CLK is idle, its level is high. Step 4: Since the voltage at the negative input terminal of the first voltage comparator U1 is half of the first voltage source V1, and the voltage at the positive input terminal of the first voltage comparator U1 is higher than the voltage at the negative input terminal of the first voltage comparator U1, the output of the first voltage comparator U1 is high level. Step 5: The high-level output of the first voltage comparator U1 charges the positive electrode of the capacitor C1 through the charging resistor R5. Step 6: The voltage of the positive electrode of the capacitor C1 becomes higher and higher. Since the positive electrode of the capacitor C1 is connected to the positive input terminal of the second voltage comparator U2, therefore, the voltage at the positive input terminal of the second voltage comparator U2 also becomes higher and higher. Step 7: Until the voltage at the positive input terminal of the second voltage comparator U2 is higher than the voltage at the negative input terminal of the second voltage comparator U2, the output of the second voltage comparator U2 is high level. Step 8: At this time, the clock signal CLK is at high level, and the third signal STB is also at high level. Step 9: When the clock signal CLK changes from high level to low level, the voltage at the positive input terminal of the first voltage comparator U1 is the voltage obtained by dividing the output voltage of the first voltage comparator U1 by the input resistor R1 and the first feedback resistor R4. Step 10: Since the resistance value of the input resistor R1 is much smaller than the resistance value of the first feedback resistor R4, the voltage at the positive input terminal of the first voltage comparator U1 is lower than the voltage at the negative input terminal of the first voltage comparator U1, and the output terminal of the first voltage comparator U1 is at low level. Step 11: The voltage of the positive electrode of the capacitor C1 discharges to the output terminal of the first voltage comparator U1 through the discharge diode D1 and the discharge resistor R9. Step 12: Since the resistance value of the discharge resistor R9 is small, the voltage of the positive electrode of the capacitor C1 drops rapidly. Step 13: Since the positive input terminal of the voltage comparator U2 is connected to the positive electrode of the capacitor C1, the voltage at the positive input terminal of the second voltage comparator U2 is equal to the voltage at the positive electrode of the capacitor C1. When the voltage at the positive electrode of the capacitor C1 drops below half of the first voltage source V1, the voltage at the positive input terminal of the second voltage comparator U2 is lower than the voltage at the negative input terminal of the second voltage comparator U2, and the output of the second voltage comparator U2 becomes low level. Step 14: Since the voltage of the capacitor C1 drops rapidly, after the clock signal CLK changes from high level to low level, the third signal STB also rapidly changes from high level to low level. Step 15: When the clock signal CLK changes from low level to high level, since the resistance value of the input resistor R1 is much smaller than the resistance value of the first feedback resistor R4, the voltage at the positive input terminal of the first voltage comparator U1 is higher than the voltage at the negative input terminal of the first voltage comparator U1, and the output terminal of the first voltage comparator U1 is at high level. Step 16: The positive electrode of the capacitor C1 is charged through the charging resistor R5. Since the resistance value of the charging resistor R5 is large, the capacitor C1 is charged slowly; before the voltage at the positive electrode of the capacitor C1 reaches half of the first voltage source V1, the output of the second voltage comparator U2 remains low level; due to the arrival of a new clock cycle, the clock signal CLK changes from high level to low level. Step 17: Repeating this way, when the clock signal CLK continuously changes between high and low levels, the output of the second voltage comparator U2 remains low level. Step 18: When the data transmission ends, after the clock signal CLK remains at high level for a period of time, when the voltage at the positive electrode of the capacitor C1 rises above half of the first voltage source V1, the output of the second voltage comparator U2 becomes high level. Step 19: Since the resistance value of the charging resistor R5 is much larger than the resistance value of the discharging resistor R9, the charging time of the capacitor C1 is much longer than its discharging time, so that when the clock signal CLK changes from high level to low level, the third signal STB can rapidly change from high level to low level, and after the clock signal CLK changes from low level to high level and lasts for a period of time, the third signal STB can change from low level to high level. This time is jointly determined by the charging resistor R5 and the capacitor C1.

[0016] Although the embodiments of the present invention are described with actual schemes, they do not constitute a limitation to the meaning of the present invention. For those skilled in the art, modifications to its implementation schemes according to this specification and combinations with other schemes are obvious.

Claims

1. A module for controlling three lines with two lines, characterized in that: It includes an input resistor (R1), a first voltage comparator (U1), a second voltage comparator (U2), a first voltage-dividing resistor (R2), a second voltage-dividing resistor (R3), a charging resistor (R5), a discharging resistor (R9), a discharging diode (D1), and a capacitor (C1). The clock signal (CLK) is connected to the positive input terminal of the first voltage comparator (U1) through the input resistor (R1). The negative input terminal of the first voltage comparator (U1) is connected to the negative input terminal of the second voltage comparator (U2). The negative input terminal of the first voltage comparator (U1) is connected to the node of the first voltage-dividing resistor (R2) and the second voltage-dividing resistor (R3). The second voltage-dividing resistor (R3) is connected to the system ground. The output terminal of the first voltage comparator (U1) is divided into two paths. One path is connected to the positive input terminal of the second voltage comparator (U2) through the charging resistor (R5), and the other path is connected to the positive input terminal of the second voltage comparator (U2) through the discharging resistor (R9) and the discharging diode (D1). The positive input terminal of the second voltage comparator (U2) is connected to the system ground through the capacitor (C1). The output terminal of the second voltage comparator (U2) serves as the port of the third signal (STB).

2. The module for controlling three lines with two lines according to claim 1, characterized in that, The module for controlling three lines with two lines further includes a first feedback resistor (R4) and a second feedback resistor (R8). The positive input terminal of the first voltage comparator (U1) is connected to the output terminal of the first voltage comparator (U1) through the first feedback resistor (R4). The positive input terminal of the second voltage comparator (U2) is connected to the output terminal of the second voltage comparator (U2) through the second feedback resistor (R8).

3. The module for controlling three lines with two lines according to claim 2, characterized in that, The module for controlling three lines with two lines further includes a first voltage source (V1) and a second voltage source (V2). The first voltage source (V1) is connected to the first voltage comparator (U1), and the first voltage source (V1) provides power supply for the first voltage comparator (U1). The other end of the first voltage-dividing resistor (R2) is connected to the first voltage source (V1). The second voltage source (V2) is connected to the second voltage comparator (U2), and the second voltage source (V2) provides power supply for the second voltage comparator (U2).

4. The module for controlling three lines with two lines according to claim 3, characterized in that, The resistance value of the first voltage-dividing resistor (R2) is equal to that of the second voltage-dividing resistor (R3), and the voltage at the connection point of the first voltage-dividing resistor (R2) and the second voltage-dividing resistor (R3) is half of the first voltage source (V1).

5. A control method for a module that controls three lines with two lines as described in claim 4, characterized in that, The control method includes the following steps: Step 1: When the clock signal (CLK) changes from low level to high level and delays for a period of time, the third signal (STB) changes from low level to high level. The clock signal (CLK) is the input terminal of this module; Step 2: Since the resistance values of the first voltage-dividing resistor (R2) and the second voltage-dividing resistor (R3) are equal, the voltage at the negative input terminal of the first voltage comparator (U1) is half of the first voltage source (V1); Step 3: When the clock signal (CLK) is idle, its level is high. Step 4: Since the voltage at the negative input terminal of the first voltage comparator (U1) is half of the first voltage source (V1), and the voltage at the positive input terminal of the first voltage comparator (U1) is higher than that at the negative input terminal of the first voltage comparator (U1), the output of the first voltage comparator (U1) is high. Step 5: The high-level output of the first voltage comparator (U1) charges the positive electrode of the capacitor (C1) through the charging resistor (R5). Step 6: The voltage of the positive electrode of the capacitor (C1) increases. Since the positive electrode of the capacitor (C1) is connected to the positive input terminal of the second voltage comparator (U2), the voltage at the positive input terminal of the second voltage comparator (U2) also increases. Step 7: Until the voltage at the positive input terminal of the second voltage comparator (U2) is higher than that at the negative input terminal of the second voltage comparator (U2), the output of the second voltage comparator (U2) is high. Step 8: At this time, the clock signal (CLK) is high and the third signal (STB) is also high. Step 9: When the clock signal (CLK) changes from high level to low level, the voltage at the positive input terminal of the first voltage comparator (U1) is the voltage obtained by dividing the output voltage of the first voltage comparator (U1) by the input resistor (R1) and the first feedback resistor (R4). Step 10: Since the resistance value of the input resistor (R1) is much smaller than that of the first feedback resistor (R4), the voltage at the positive input terminal of the first voltage comparator (U1) is lower than that at the negative input terminal of the first voltage comparator (U1), and the output terminal of the first voltage comparator (U1) is low. Step 11: The voltage of the positive electrode of the capacitor (C1) discharges to the output terminal of the first voltage comparator (U1) through the discharge diode (D1) and the discharge resistor (R9). Step 12: Since the resistance value of the discharge resistor (R9) is small, the voltage of the positive electrode of the capacitor (C1) drops rapidly. Step 13: Since the positive input terminal of the voltage comparator U2 is connected to the positive electrode of the capacitor (C1), the voltage at the positive input terminal of the second voltage comparator (U2) is equal to the voltage of the positive electrode of the capacitor (C1). When the voltage of the positive electrode of the capacitor (C1) drops below half of the first voltage source (V1), the voltage at the positive input terminal of the second voltage comparator (U2) is lower than that at the negative input terminal of the second voltage comparator (U2), and the output of the second voltage comparator (U2) becomes low. Step 14: Since the voltage of the capacitor (C1) drops rapidly, when the clock signal (CLK) changes from high level to low level, the third signal (STB) also rapidly changes from high level to low level. Step 15: When the clock signal (CLK) changes from low level to high level, since the resistance value of the input resistor (R1) is much smaller than that of the first feedback resistor (R4), the voltage at the positive input terminal of the first voltage comparator (U1) is higher than the voltage at the negative input terminal of the first voltage comparator (U1), and the output terminal of the first voltage comparator (U1) is at high level; Step 16: The positive electrode of the capacitor (C1) is charged through the charging resistor (R5). Since the resistance value of the charging resistor (R5) is large, the capacitor (C1) is charged slowly; before the positive electrode voltage of the capacitor (C1) reaches half of the first voltage source (V1), the output of the second voltage comparator (U2) remains at low level; due to the arrival of a new clock cycle, the clock signal (CLK) returns from high level to low level; Step 17: Repeat this way. When the clock signal (CLK) continuously changes between high and low levels, the output of the second voltage comparator (U2) remains at low level; Step 18: When the data transmission ends and the clock signal (CLK) remains at high level for a period of time, when the positive electrode voltage of the capacitor (C1) rises to be higher than half of the first voltage source (V1), the output of the second voltage comparator (U2) becomes high level; Step 19: Since the resistance value of the charging resistor (R5) is much larger than that of the discharging resistor (R9), the charging time of the capacitor (C1) is much longer than its discharging time, so that when the clock signal (CLK) changes from high level to low level, the third signal (STB) can quickly change from high level to low level, and after the clock signal (CLK) changes from low level to high level and lasts for a period of time, the third signal (STB) can change from low level to high level. This time is jointly determined by the charging resistor (R5) and the capacitor (C1).

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