Signal acquisition circuits and electronic equipment

Abstract

This application discloses a signal acquisition circuit and electronic device. The signal acquisition circuit includes: an acquisition interface for electrically connecting a sensor and a signal processing circuit to receive signals acquired and output by the sensor; a differential-mode interference protection circuit electrically connected to both the acquisition interface and the signal processing circuit for filtering differential-mode interference signals from the signals output by the acquisition interface; a common-mode interference protection circuit electrically connected to both the acquisition interface and the signal processing circuit for filtering common-mode interference signals from the signals output by the acquisition interface; and a signal processing circuit that processes the signal after filtering out differential-mode and common-mode interference signals. The embodiments of this application can effectively improve the interference protection level and avoid affecting the devices within the signal processing device.

Description

Technical Field

[0001] This application relates to the field of signal acquisition and processing technology, and in particular to a signal acquisition circuit and electronic device. Background Technology

[0002] Signal acquisition is a crucial step in determining and adjusting the operating status of electronic devices such as switches and servers. Strict limitations must be imposed on signal acquisition to obtain accurate signals, thereby accurately determining the operating status of the electronic devices or adjusting their operation.

[0003] During the signal acquisition process, some interference signals may enter the signal processing devices, affecting their operation or even damaging them, thus preventing them from acquiring accurate signals. Summary of the Invention

[0004] The main objective of this application is to provide a signal acquisition circuit and electronic device. This application can effectively filter out interference signals and prevent them from affecting the device.

[0005] In a first aspect, embodiments of this application provide a signal acquisition circuit, which includes: an acquisition interface, a differential-mode interference protection circuit, a common-mode interference protection circuit, and a signal processing circuit;

[0006] The acquisition interface is used to electrically connect the sensor and the signal processing circuit to receive the signal acquired and output by the sensor.

[0007] The differential mode interference protection circuit is electrically connected to the acquisition interface and the signal processing circuit respectively, and is used to filter out differential mode interference signals in the signal output by the acquisition interface;

[0008] A common-mode interference protection circuit, electrically connected to both the acquisition interface and the signal processing circuit, is used to filter out common-mode interference signals from the signal output by the acquisition interface; and

[0009] The signal processing circuit is used to process the signal after filtering out differential-mode interference signals and common-mode interference signals.

[0010] In this embodiment, a differential-mode interference protection circuit and a common-mode interference protection circuit are electrically connected to the acquisition interface. The differential-mode interference protection circuit filters out differential-mode interference signals in the signal, and the common-mode interference protection circuit filters out common-mode interference signals in the signal output from the acquisition interface. This can effectively filter out all interference signals, prevent interference signals present in the acquisition interface from affecting signal processing-related devices, and improve the interference protection level.

[0011] In some implementations of the first aspect, the differential mode interference protection circuit includes: a first clamping circuit;

[0012] The first connection terminal of the first clamping circuit is connected to the first output terminal of the acquisition interface, and the second connection terminal of the first clamping circuit is connected to the second output terminal of the acquisition interface and the signal processing circuit.

[0013] The first clamping circuit is used to clamp the voltage when the first voltage between the first output terminal and the second output terminal of the acquisition interface is greater than the first preset voltage.

[0014] In this embodiment, the first voltage between the first output terminal and the second output terminal of the acquisition interface can be clamped within a set range by setting the first clamping circuit. Under the condition of ensuring no differential mode interference, the signal between the first output terminal and the second output terminal of the acquisition interface is output to the signal processing circuit.

[0015] In some implementations of the first aspect, the first clamping circuit includes a first clamping diode; the input terminal of the first clamping diode is electrically connected to a first power supply and a first output terminal of the acquisition interface, and the output terminal of the first clamping diode is electrically connected to a second output terminal of the acquisition interface and a signal processing circuit.

[0016] In some implementations of the first aspect, the common-mode interference protection circuit includes: a second clamping circuit and a common-mode discharge circuit; the first connection terminal of the second clamping circuit is electrically connected to the first output terminal and the second output terminal of the acquisition interface, and the second connection terminal of the second clamping circuit is electrically connected to the third output terminal of the acquisition interface and the common-mode discharge circuit; the second clamping circuit is used to perform voltage clamping when the second voltage between the first output terminal and the third output terminal of the acquisition interface is greater than a second preset voltage and / or the third voltage between the second output terminal and the third output terminal of the acquisition interface is greater than a third preset voltage; the common-mode discharge circuit is used to discharge the clamped second voltage and / or the clamped third voltage.

[0017] By setting up the second clamping circuit and the common-mode discharge circuit, the second voltage between the first and third output terminals of the acquisition interface can be clamped within a set range, and the third voltage between the second and third output terminals of the acquisition interface can be clamped within a set range. Furthermore, excess voltage in the clamped second and third voltages can be discharged. This allows the signals between the first and third output terminals and between the second and third output terminals of the acquisition interface to be output to the signal processing circuit while ensuring no common-mode interference.

[0018] In some implementations of the first aspect, the second clamping circuit includes: a second clamping diode and a third clamping diode;

[0019] The input terminal of the second clamping diode is electrically connected to the first output terminal of the acquisition interface, the input terminal of the third clamping diode is electrically connected to the second output terminal of the acquisition interface, and the output terminals of both the second and third clamping diodes are electrically connected to the third output terminal of the acquisition interface and the common-mode discharge circuit.

[0020] In some implementations of the first aspect, the signal acquisition circuit further includes: a first capacitor; the first end of the first capacitor is electrically connected to the second end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit, respectively; the second end of the first capacitor is electrically connected to the third end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit, respectively.

[0021] In some implementations of the first aspect, the signal acquisition circuit further includes: a first capacitor; the first capacitor is connected in parallel across the third clamping diode.

[0022] In this embodiment, by setting the first capacitor, the voltage applied instantaneously across the third clamping diode D3 can be effectively prevented from being too high, thereby avoiding any impact on the third clamping diode D3.

[0023] In some implementations of the first aspect, the common-mode discharge circuit includes: a gas discharge tube; a first end of the gas discharge tube is electrically connected to a second connection terminal of the second clamping circuit, and a second end of the gas discharge tube is electrically connected to a protective ground terminal.

[0024] In some implementations of the first aspect, the common-mode discharge circuit includes: a second capacitor; a first terminal of the second capacitor is electrically connected to a second connection terminal of the second clamping circuit, and a second terminal of the second capacitor is electrically connected to a protective ground terminal.

[0025] This embodiment of the application uses a second clamping diode to clamp the second voltage between the first and third output terminals of the acquisition interface, and uses a gas discharge tube and a second capacitor to discharge the clamped second voltage. Similarly, a third clamping diode is used to clamp the third voltage between the second and third output terminals of the acquisition interface, and a second capacitor and a gas discharge tube are used to discharge the clamped third voltage. This prevents common-mode interference signals transmitted by the acquisition interface from being transmitted to the signal processing circuit and affecting the working state of the signal processing circuit.

[0026] In some implementations of the first aspect, the signal processing circuit includes: a voltage follower circuit and a processing chip; the voltage follower circuit is electrically connected to the second output terminal of the acquisition interface, the differential mode interference protection circuit, the common mode interference protection circuit, and the processing chip respectively; the voltage follower circuit is used to perform voltage following on the signal.

[0027] In some implementations of the first aspect, the voltage follower circuit includes: a first resistor, a second resistor, a third resistor, a third capacitor, and an inverting follower;

[0028] The first end of the first resistor is electrically connected to the first end of the second resistor and the output end of the acquisition interface; the second end of the first resistor is electrically connected to the positive input end of the inverting follower; and the second end of the second resistor is grounded.

[0029] The inverting input terminal of the inverting follower is electrically connected to the output terminal of the inverting follower, the first terminal of the third resistor, and the first terminal of the third capacitor, respectively.

[0030] The second terminal of the third resistor is electrically connected to the processing chip, and the second terminal of the third capacitor is grounded.

[0031] In this embodiment, a voltage follower circuit can perform voltage following on the signal according to the transmission timing set by the processing chip, so as to accurately transmit the signal to the processing chip; the processing chip can analyze the received signal to obtain the data information that needs to be acquired.

[0032] In some implementations of the first aspect, there is a power supply circuit and a reverse-current protection circuit; the power supply circuit is electrically connected to the processing chip and the voltage follower circuit through the reverse-current protection circuit; the power supply circuit is used to provide a power supply voltage to the processing chip through the reverse-current protection circuit.

[0033] In this embodiment, the power supply circuit can generate the power supply voltage required by the processing chip, and then output the power supply voltage to the power supply terminal of the processing chip through the anti-reverse current circuit to power the processing chip.

[0034] In some implementations of the first aspect, the power supply circuit includes: a voltage conversion circuit;

[0035] The voltage conversion circuit is electrically connected to the processing chip and the voltage follower circuit through the anti-reverse current circuit; the voltage conversion circuit is also electrically connected to the second power supply.

[0036] A voltage conversion circuit is used to convert the power supply voltage output from the second power supply into the power supply voltage required by the processing chip.

[0037] The power supply circuit of this application embodiment is provided with a voltage conversion circuit, which can convert the power supply voltage output by the second power supply into the power supply voltage used by the processing chip, so as to avoid the power supply voltage output by the second power supply being mismatched with the power supply voltage required by the processing chip.

[0038] In some implementations of the first aspect, the power supply circuit further includes: a filter circuit;

[0039] The filter circuit is electrically connected to the voltage conversion circuit and the second power supply; the filter circuit is used to filter the power supply voltage output by the second power supply.

[0040] The power supply circuit in this embodiment is also equipped with a filter circuit, which can filter out interference signals in the second power supply and avoid interference from the power supply voltage.

[0041] In some implementations of the first aspect, the filter circuit includes: a fourth capacitor and a fifth capacitor;

[0042] The first terminal of the fourth capacitor is electrically connected to the positive output terminal of the second power supply and the input terminal of the voltage conversion circuit, respectively, and the second terminal of the fourth capacitor is electrically connected to the protective ground terminal.

[0043] The first terminal of the fifth capacitor is electrically connected to the negative output terminal of the second power supply, and the second terminal of the fifth capacitor is electrically connected to the protective ground terminal.

[0044] In some implementations of the first aspect, the anti-reverse current circuit includes a first diode and a second diode;

[0045] The cathode of the first diode is electrically connected to the output terminal of the power supply circuit, the anode of the first diode is electrically connected to the cathode of the second diode and the processing chip, and the cathode of the second diode is electrically connected to the negative output terminal of the second power supply.

[0046] Secondly, embodiments of this application provide an electronic device, which includes a sensor and a signal acquisition circuit;

[0047] The signal acquisition circuit is electrically connected to the acquisition interface of the sensor and the acquisition circuit.

[0048] The technical effects achieved by the second aspect are similar to those achieved by the corresponding technical means in the first aspect, and will not be repeated here. Attached Figure Description

[0049] Figure 1 This is a first structural schematic diagram of the first embodiment of the signal acquisition circuit in this application;

[0050] Figure 2 This is a schematic diagram of the second embodiment of the signal acquisition circuit in this application;

[0051] Figure 3 This is a circuit schematic diagram of the differential mode interference protection circuit of the signal acquisition circuit in this application;

[0052] Figure 4 This is a schematic diagram of the structure of the third embodiment of the signal acquisition circuit in this application;

[0053] Figure 5 This is a circuit schematic of the common-mode interference protection circuit of the signal acquisition circuit in this application;

[0054] Figure 6This is a schematic diagram of the first structure of the fourth embodiment of the signal acquisition circuit in this application;

[0055] Figure 7 This is a circuit diagram of the voltage follower circuit of the signal acquisition circuit in this application;

[0056] Figure 8 This is a schematic diagram of the second structure of the fourth embodiment of the signal acquisition circuit in this application;

[0057] Figure 9 This is a schematic diagram of the third structure of the fourth embodiment of the signal acquisition circuit in this application;

[0058] Figure 10 This is a schematic diagram of the fourth structure of the signal acquisition circuit in the fourth embodiment of this application;

[0059] Figure 11 This is a circuit diagram of the signal acquisition circuit in this application.

[0060] Explanation of reference numerals in the attached figures:

[0061] 10. Acquisition Interface; 20. Differential Mode Interference Protection Circuit; 201. First Clamping Circuit; 30. Common Mode Interference Protection Circuit; 301. Second Clamping Circuit; 302. Common Mode Discharge Circuit; 40. Signal Processing Circuit; 401. Voltage Follower Circuit; 402. Processing Chip; 50. Power Supply Circuit; 501. Voltage Conversion Circuit; 502. Filtering Circuit; 60. Anti-Reverse Current Circuit;

[0062] VCC1, First power supply; VCC2, Second power supply; D1, First clamping diode; D2, Second clamping diode; D3, Third clamping diode; D4, First diode; D5, Second diode; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; C4, Fourth capacitor; C5, Fifth capacitor; R1, First resistor; R2, Second resistor; R3, Third resistor; A, Reverse follower; PE, Protective ground; AGND, Analog ground; DGND, Digital ground. Detailed Implementation

[0063] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" do not necessarily imply that they are different.

[0064] It should be noted that in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0065] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0066] This application provides an electronic device, which includes a sensor and a signal acquisition circuit; the signal acquisition circuit is connected to the sensor. The sensor establishes a connection with the signal acquisition circuit through an acquisition interface. The signal acquisition circuit is used to acquire information such as temperature and humidity in the environment in which the electronic device is located. The signal acquisition circuit may include the sensor or may be connected to the sensor.

[0067] Specifically, electronic devices typically operate continuously without interruption. When prolonged operation is required, it's necessary to monitor the device's status to understand its current operating environment and adjust its operating state accordingly. For example, in the case of a server, a signal acquisition circuit can determine the server's current operating state by collecting signals. If this state differs from the server's standard operating state, a controller can adjust the server's status to prevent prolonged operation in a non-standard state. This controller can be one of the following components within the server: a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), or a Baseboard Management Controller (BMC). The signal acquisition circuit can output a filtered signal to the controller. Upon receiving the signal, the controller compares its value with the values ​​observed during normal server operation to determine the server's current operating state and whether adjustments are necessary.

[0068] Of course, the processing chip in the signal acquisition circuit and the controller in the server can be the same device, which can simultaneously perform signal processing and server operation status control functions. Naturally, the electronic device in this application is not limited to the aforementioned server; it can also be a switch or other devices. For interference protection in signal acquisition from other devices, please refer to the description in the server section.

[0069] It should be understood that during signal acquisition, some interference signals may enter the signal processing device, such as electrical fast transient (EFT), electrostatic discharge (ESD), surge interference, and conducted interference. When this interference enters the signal processing device, it can affect its operation, such as causing some components to burn out or malfunctioning. During testing, there is ESD interference according to standard IEC 61000-4-2, transient pulse interference according to IEC 61000-4-4, or surge interference according to IEC 61000-4-5, requiring effective protection against these standards. In practical use, interference protection is also necessary to prevent device malfunction when any of these types of interference are present. The signal processing device can be an FPGA, DSP, or similar device equipped with a processing chip and peripheral circuitry.

[0070] This application presents a first embodiment of a signal acquisition circuit; please refer to [link / reference]. Figure 1 , Figure 1 This is a first structural schematic diagram of a first embodiment of the signal acquisition circuit of this application.

[0071] In the first embodiment, the signal acquisition circuit includes: an acquisition interface 10, a differential mode interference protection circuit 20, a common mode interference protection circuit 30, and a signal processing circuit 40;

[0072] The acquisition interface 10 is used to electrically connect the sensor and the signal processing circuit 40 to receive the signal acquired and output by the sensor.

[0073] The differential mode interference protection circuit 20 is electrically connected to the acquisition interface 10 and the signal processing circuit 40 respectively, and is used to filter out the differential mode interference signal in the signal output by the acquisition interface 10.

[0074] Common-mode interference protection circuit 30 is electrically connected to acquisition interface 10 and signal processing circuit 40 respectively, and is used to filter out common-mode interference signals in the signal output from acquisition interface 10; and

[0075] The signal processing circuit 40 is used to process the signal after filtering out differential-mode interference signals and common-mode interference signals.

[0076] It should be noted that the acquisition interface 10 is used to establish a connection with the sensor. When electrically connected to the sensor, the acquisition interface 10 can receive the signal output by the sensor. In addition, the acquisition interface 10 may also receive interference signals that could affect other components in the signal sampling circuit. These interference signals manifest as common-mode interference signals and differential-mode interference signals along the transmission path of the acquisition interface 10. The sensor connected to the acquisition interface 10 can acquire signals related to the operating status and environment of the electronic device. For example, when temperature signals need to be acquired, the sensor connected to the acquisition interface 10 is a temperature sensor. This temperature sensor can acquire the current temperature signal of the electronic device. By acquiring the ambient temperature signal, it can be determined whether the operating status of the electronic device needs to be adjusted. Similarly, when humidity signals need to be acquired, the sensor connected to the acquisition interface 10 is a humidity sensor.

[0077] It is understandable that when interference such as electrostatic discharge, transient pulse interference, and surge interference occurs, it manifests as differential-mode interference signals or common-mode interference signals along the transmission path. The interference protection circuit is used to filter out interference signals for the protection of the signal processing circuit. Specifically, it can include differential-mode interference protection circuit 20 and common-mode interference protection circuit 30. Differential-mode interference protection circuit 20 is used to filter out differential-mode interference signals in the signal output from acquisition interface 10. This circuit can filter out differential-mode interference signals in the signal output from acquisition interface 10, thereby preventing differential-mode interference signals, which are interference signals, from entering the signal processing circuit 40. Similarly, common-mode interference protection circuit 30 is used to filter out common-mode interference signals in the signal output from acquisition interface 10, thereby preventing common-mode interference signals, which are interference signals, from entering the signal processing circuit 40. During the filtering of interference signals, the interference signal can be identified by the parameter difference between the interference signals and the signal. For example, if the interference signal is an electrostatic signal, the peak value of the electrostatic signal is significantly greater than the amplitude of the signal in a short period of time, and the amplitude of the signal is relatively stable. If the signal with the larger peak value is identified, the signal with the larger peak value can be filtered out.

[0078] The signal processing circuit 40 processes the signal after filtering out differential-mode interference and common-mode interference. Typically, the sensor input signal is a voltage or current signal. The signal processing circuit 40 can determine the actual information acquired by the sensor based on this voltage or current signal. For example, if a temperature sensor inputs a voltage signal reflecting temperature changes, the signal processing circuit 40 can analyze the specific waveform of this voltage signal to deduce the temperature information acquired by the temperature sensor.

[0079] In specific implementation, the acquisition interface 10 can receive signals input from the connected sensors. During signal transmission, the differential-mode interference protection circuit 20 connected to the acquisition interface 10 can filter out differential-mode interference signals in the signals output by the acquisition interface 10, and the common-mode interference protection circuit 30 connected to the differential-mode interference protection circuit 20 can filter out common-mode interference signals in the signals. At this time, there are no differential-mode interference signals or common-mode interference signals in the signals output by the acquisition interface 10. The signal processing circuit 40 can directly process the signals after filtering out differential-mode interference signals and common-mode interference signals. The signal processing circuit 40 can determine the working state of the electronic device through the signal processing process. For example, if the acquired signal is a temperature signal, the temperature signal can be analyzed and processed to determine the temperature information of the environment in which the electronic device is located, and then determine whether the working state of the electronic device needs to be adjusted.

[0080] The signal reflects the current environmental state of the electronic device. This signal is related to the sensors actually connected to the signal acquisition circuit. For example, the acquired information may include temperature, humidity, voltage, and current.

[0081] In the first embodiment, since the differential-mode signal and common-mode signal have different transmission paths, the differential-mode interference signal is transmitted through the differential-mode path between the first and second output terminals of the acquisition interface 10, while the common-mode interference signal is transmitted through the path between the first and third output terminals and between the second and third output terminals of the acquisition interface 10. A differential-mode interference protection circuit and a common-mode interference protection circuit electrically connected to the acquisition interface are provided. The differential-mode interference protection circuit filters out the differential-mode interference signal in the signal, and the common-mode interference protection circuit filters out the common-mode interference signal in the signal output from the acquisition interface. This effectively filters out all interference signals, preventing interference signals present in the acquisition interface from affecting signal processing-related devices and improving the interference protection level.

[0082] Based on the first embodiment of the signal acquisition circuit of this application, a second embodiment of the signal acquisition circuit of this application is proposed. (Refer to...) Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the signal acquisition circuit in this application.

[0083] In the second embodiment of the signal acquisition circuit of this application, the contents that are the same as or similar to those in the first embodiment described above can be referred to the above description and will not be repeated hereafter.

[0084] Based on this, in the embodiments of this application, the differential mode interference protection circuit 20 includes: a first clamping circuit 201;

[0085] The first connection terminal of the first clamping circuit 201 is electrically connected to the first output terminal of the acquisition interface 10, and the second connection terminal of the first clamping circuit 201 is electrically connected to the second output terminal of the acquisition interface 10 and the signal processing circuit 40.

[0086] It should be understood that there are many ways to filter interference signals. In the embodiments of this application, voltage clamping can be used to filter out differential mode interference signals in the transmission path.

[0087] It should be noted that a clamping circuit is used to clamp the voltage between the devices or wires connected at both ends of the clamping circuit. By clamping, the voltage between the devices or wires connected at both ends of the clamping circuit can be maintained below a certain value, preventing the voltage between the devices or wires connected at both ends of the clamping circuit from becoming too high. The specific voltage value that the clamping circuit needs to clamp is related to the signal processing circuit 40 at the back end that receives the signal.

[0088] The first clamping circuit 201 is used to clamp the signal voltage between the first output terminal and the second output terminal of the acquisition interface 10, so as to prevent the voltage value input to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10 from being too high.

[0089] In a specific implementation, the first clamping circuit 201 can clamp the voltage when the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 is greater than a first preset voltage. For example, if the first voltage output through the first output terminal and the second output terminal of the acquisition interface 10 is 10V, and the voltage to be output to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10 needs to be 3V, that is, the devices in the signal processing circuit 40 can withstand a maximum voltage of 3V; at this time, the first clamping circuit 201 can clamp the voltage value of the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 to 3V, thereby ensuring that the voltage value input to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10 is maintained at 3V.

[0090] The first preset voltage is a pre-set voltage used to determine whether a differential-mode interference signal exists between the first and second output terminals of the acquisition interface 10. When the first voltage between the first and second output terminals of the acquisition interface 10 is greater than the first preset voltage, it indicates that a differential-mode interference signal exists between them; when the first voltage between the first and second output terminals of the acquisition interface 10 is not greater than the first preset voltage, it indicates that no differential-mode interference signal exists between them. The specific value of the first preset voltage can be determined based on the signal voltage value, and can be selected from a voltage value within a certain range greater than the signal voltage value; for example, if the signal voltage value is 3V, the first preset voltage can be set to 4V.

[0091] In the second embodiment, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped within a set range by setting the first clamping circuit 201, so that the signal between the first output terminal and the second output terminal of the acquisition interface 10 can be output to the signal processing circuit 40 while ensuring no differential mode interference.

[0092] Reference Figure 3 In the second embodiment, the first clamping circuit 201 includes: a first clamping diode D1;

[0093] The input terminal of the first clamping diode D1 is connected to the first power supply (Volt Current Condenser1, VCC1) and the first output terminal of the acquisition interface 10, and the output terminal of the first clamping diode D1 is connected to the second output terminal of the acquisition interface 10 and the signal processing circuit 40.

[0094] It should be understood that the first clamping diode D1 clamps the voltage between the devices or wires connected to its input and output terminals. The specific clamping voltage of the first clamping diode D1 is related to the first voltage that needs to be input to the signal processing circuit 40 between the first and second output terminals of the acquisition interface 10. The first clamping diode D1 can be selected based on the voltage value required to be input to the signal processing circuit 40. The first power supply VCC1 can be a 15V power supply, which can form a high voltage at the first connection terminal of the first clamping diode D1. The first connection terminal of the first clamping diode D1 can be an input terminal, and the second connection terminal can be an output terminal.

[0095] exist Figure 3In the first clamping circuit 201, a first clamping diode D1 is included. In specific implementation, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped by the first clamping diode D1, thereby effectively avoiding differential mode interference signals output to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10.

[0096] Based on the first or second embodiment of the signal acquisition circuit of this application, a third embodiment of the signal acquisition circuit of this application is proposed. (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the third embodiment of the signal acquisition circuit in this application.

[0097] In the third embodiment of the signal acquisition circuit of this application, the contents that are the same as or similar to those in the first or second embodiment described above can be referred to the above description and will not be repeated hereafter.

[0098] Based on this, in the third embodiment, the common-mode interference protection circuit 30 includes: a second clamping circuit 301 and a common-mode discharge circuit 302;

[0099] The first connection terminal of the second clamping circuit 301 is electrically connected to the first and second output terminals of the acquisition interface 10, and the second connection terminal of the second clamping circuit 301 is electrically connected to the third output terminal of the acquisition interface 10 and the common mode discharge circuit 302.

[0100] In the third embodiment, voltage clamping and discharging are also used to filter out common-mode interference signals in the transmission path. The second clamping circuit 301 clamps the signal voltage between the first and third output terminals of the acquisition interface 10, and also clamps the signal voltage between the second and third output terminals of the acquisition interface 10; this prevents excessively high voltage values ​​input to the signal processing circuit 40 between the first and third output terminals or between the second and third output terminals of the acquisition interface 10. The common-mode discharging circuit 302 discharges the clamped voltage between the first and third output terminals and between the second and third output terminals of the acquisition interface 10.

[0101] In specific implementation, the second clamping circuit 301 can clamp the voltage when the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 is greater than the second preset voltage; the common-mode discharge circuit 302 can discharge the clamped second voltage; and the second clamping circuit 301 can clamp the voltage when the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 is greater than the third preset voltage; the common-mode discharge circuit 302 can also discharge the clamped third voltage.

[0102] The second preset voltage is a pre-set voltage used to determine whether a common-mode interference signal exists between the first and third output terminals of the acquisition interface 10. When the second voltage between the first and third output terminals of the acquisition interface 10 is greater than the second preset voltage, it indicates that a common-mode interference signal exists between the first and third output terminals of the acquisition interface 10; when the second voltage between the first and third output terminals of the acquisition interface 10 is not greater than the second preset voltage, it indicates that no common-mode interference signal exists between the first and third output terminals of the acquisition interface 10. Similarly, the third preset voltage is a pre-set voltage used to determine whether a common-mode interference signal exists between the second and third output terminals of the acquisition interface 10. When the third voltage between the second and third output terminals of the acquisition interface 10 is greater than the third preset voltage, it indicates that a common-mode interference signal exists between the second and third output terminals of the acquisition interface 10; when the third voltage between the second and third output terminals of the acquisition interface 10 is not greater than the third preset voltage, it indicates that no common-mode interference signal exists between the second and third output terminals of the acquisition interface 10. The specific voltage values ​​of the second and third preset voltages can also be determined based on the signal voltage value, and a voltage value within a certain range greater than the signal voltage value can be selected.

[0103] It should be emphasized that if there is a voltage value greater than the corresponding preset voltage among the second voltage between the first output terminal and the third output terminal and the third voltage between the second output terminal and the third output terminal of the acquisition interface 10, the second clamping circuit 301 can directly clamp the second voltage or the third voltage that contains common-mode interference signal, and the common-mode discharge circuit 302 can discharge the excess voltage and common-mode interference signal in the second voltage or the third voltage.

[0104] In the third embodiment, the second clamping circuit 301 and the common-mode discharge circuit 302 can clamp the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 within a set range and clamp the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 within a set range. The excess voltage in the clamped second voltage and the third voltage can be discharged. The signals between the first output terminal and the third output terminal and between the second output terminal and the third output terminal of the acquisition interface 10 can be output to the signal processing circuit 40 without common-mode interference.

[0105] Reference Figure 5 In the third embodiment, the second clamping circuit 301 includes: a second clamping diode D2 and a third clamping diode D3;

[0106] The input terminal of the second clamping diode D2 is connected to the first output terminal of the acquisition interface 10, the input terminal of the third clamping diode D3 is connected to the second output terminal of the acquisition interface 10, and the output terminals of the second clamping diode D2 and the third clamping diode D3 are both connected to the third output terminal of the acquisition interface 10 and the common mode discharge circuit 302.

[0107] It should be noted that the second clamping diode D2 clamps the voltage between the devices or wires connected to its input and output terminals. The specific clamping voltage of the second clamping diode D2 is related to the second voltage that needs to be input to the signal processing circuit 40 between the first and third output terminals of the acquisition interface 10. Similarly, the third clamping diode D3 clamps the voltage between the devices or wires connected to its input and output terminals. The specific clamping voltage of the third clamping diode D3 is related to the third voltage that needs to be input to the signal processing circuit 40 between the second and third output terminals of the acquisition interface 10.

[0108] Furthermore, the second clamping diode D2 can be selected based on the voltage values ​​that need to be input to the signal processing circuit 40 from the first and third output terminals of the acquisition interface 10; similarly, the third clamping diode D3 can be selected based on the voltage values ​​that need to be input to the signal processing circuit 40 from the second and third output terminals of the acquisition interface 10. The first connection terminal of the second clamping diode D2 and the third clamping diode D3 can be an input terminal, and the second connection terminal can be an output terminal.

[0109] Furthermore, in the third embodiment, the signal acquisition circuit further includes: a first capacitor C1; the first end of the first capacitor C1 is electrically connected to the second end of the acquisition interface 10, the common-mode interference protection circuit 30 and the signal processing circuit 40 respectively, and the second end of the first capacitor C1 is electrically connected to the third end of the acquisition interface 10, the common-mode interference protection circuit 30 and the signal processing circuit 40 respectively.

[0110] It is understandable that during the clamping process of the common-mode interference protection circuit 30 on the voltage between the second and third output terminals and the voltage between the first and second output terminals of the acquisition interface 10, there may be excessive interference signals or instantaneous current spikes in the event of interference signals, resulting in excessively high instantaneous voltages input to the devices in the common-mode interference protection circuit 30, which will affect the operation of these devices. The devices in the common-mode interference protection circuit 30 that may be affected are those that control the input voltage, such as clamping diodes.

[0111] In the third embodiment, a first capacitor C1 is also provided. The first capacitor C1 is connected to the input and output terminals of the common-mode interference protection circuit 30. It can control the voltage input to the common-mode interference protection circuit 30 to rise slowly, so as to avoid affecting the devices inside the common-mode interference protection circuit 30.

[0112] In some examples, the first capacitor C1 is connected in parallel across the third clamping diode D3.

[0113] It is understandable that during the clamping process of the third clamping diode D3 between the second and third output terminals of the acquisition interface 10, there may be excessive interference signals or instantaneous current spikes in the event of interference signals, resulting in excessively high instantaneous voltage input to the third clamping diode D3, which affects the operation of the third clamping diode D3.

[0114] In the third embodiment, by setting the first capacitor C1, the capacitance of the first capacitor C1 allows the voltage across the third clamping diode D3 to rise slowly until it reaches the clamping voltage corresponding to the second clamping diode D3. Therefore, even in the event of a large voltage surge, the voltage across the third clamping diode D3 can be controlled to rise slowly to the clamping voltage corresponding to the third clamping diode D3, thereby effectively preventing the voltage applied to the third clamping diode D3 from being too high instantaneously and affecting the third clamping diode D3.

[0115] In the third embodiment, the common-mode discharge circuit 302 includes a gas discharge tube (GDT).

[0116] The first end of the gas discharge tube GDT is connected to the second connection terminal of the second clamping circuit 301, and the second end of the gas discharge tube GDT is connected to the protective ground terminal PE.

[0117] It should be understood that a gas discharge tube (GDT) is a power transistor that is sealed in a ceramic cavity filled with inert gas to stabilize the discharge voltage of the tube. Under conditions of significant voltage surges, the current flowing through the GDT is substantial. Excessive voltage can momentarily activate the GDT, thus providing a low-impedance discharge path. The GDT can be used to discharge common-mode interference signals between the second and third output terminals of the acquisition interface 10, as well as between the first and second output terminals.

[0118] The common-mode discharge circuit includes: a second capacitor C2; the first end of the second capacitor C2 is connected to the second connection terminal of the second clamping circuit 301, and the second end of the second capacitor C2 is connected to the protective ground terminal PE.

[0119] It is understandable that the second capacitor C2 is a low-impedance capacitor relative to the common-mode interference signal. The common-mode interference signal between the first output terminal and the third output terminal of the acquisition interface 10 can be transmitted through the second capacitor C2, thereby dissipating the common-mode interference signal. Of course, the common-mode interference signal between the second output terminal and the third output terminal of the acquisition interface 10 can also be transmitted through the second capacitor C2, thereby dissipating the common-mode interference signal.

[0120] Considering that both the second capacitor C2 and the gas discharge tube GDT can discharge power supply interference signals, in this embodiment of the application, a second capacitor C2 or a gas discharge tube GDT can be provided between the second terminal of the second clamping circuit 301 and the protective ground terminal; of course, both the second capacitor C2 and the gas discharge tube GDT can be provided between the second terminal of the second clamping circuit 301 and the protective ground terminal, wherein the second capacitor C2 and the gas discharge tube GDT are connected in parallel.

[0121] Furthermore, the gas discharge tube GDT can be electrically connected to the second terminal of the second clamping diode D2 in the second clamping circuit 301, and the second capacitor C2 can be connected to the second terminal of the third clamping diode D3 in the second clamping circuit 301; of course, the gas discharge tube GDT can be electrically connected to the second terminal of the third clamping diode D3 in the second clamping circuit 301, and the second capacitor C2 can be connected to the second terminal of the second clamping diode D2 in the second clamping circuit 301; or the gas discharge tube GDT and the second capacitor C2 can both be electrically connected to the second terminal of the second clamping diode D2 and the second terminal of the third clamping diode D3.

[0122] In the third embodiment, when the second clamping circuit 301 selects the second clamping diode D2 and the third clamping diode D3, the common-mode discharge circuit 302 can also select other devices to discharge the clamped second voltage and the third voltage; similarly, when the common-mode discharge circuit 302 selects the second capacitor C2 and the gas discharge tube GDT, the second clamping circuit 301 can also select other devices to clamp the second voltage and the third voltage transmitted by the acquisition interface 10, without specific limitations here.

[0123] Furthermore, in the case where the third embodiment references the second embodiment, the first voltage between the first output terminal and the second output terminal of the acquisition interface 10 can be clamped by the first clamping diode D1, thereby effectively avoiding differential-mode interference signals output to the signal processing circuit 40 between the first output terminal and the second output terminal of the acquisition interface 10; at the same time, the second voltage between the first output terminal and the third output terminal of the acquisition interface 10 can be clamped by the second clamping diode D2, and the clamped second voltage can be discharged by the gas discharge tube GDT and the second capacitor C2; and the third voltage between the second output terminal and the third output terminal of the acquisition interface 10 can be clamped by the third clamping diode D3, and the clamped third voltage can be discharged by the second capacitor C2 and the gas discharge tube GDT, thereby preventing any interference signal, either differential-mode interference signal or common-mode interference signal transmitted by the acquisition interface 10, from being transmitted to the signal processing circuit 40 and affecting the working state of the signal processing circuit 40.

[0124] Based on any one of the first to third embodiments of the signal acquisition circuit of this application, a fourth embodiment of the signal acquisition circuit of this application is proposed. (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the first structure of the fourth embodiment of the signal acquisition circuit in this application.

[0125] In the fourth embodiment of the signal acquisition circuit of this application, the contents that are the same as or similar to those in the first to third embodiments described above can be referred to the above description and will not be repeated hereafter.

[0126] In this embodiment of the application, the signal processing circuit 40 includes: a voltage follower circuit 401 and a processing chip 402;

[0127] The voltage follower circuit 401 is electrically connected to the acquisition interface 10 and the processing chip 402 respectively.

[0128] It should be understood that during signal transmission, there may be timing requirements. For example, if the actual transmission timing differs from the set timing, the processing chip 402 may fail to recognize the currently received signal as a signal, or the received signal may have missing waveforms. The voltage follower circuit 401 is used to adjust the signal transmission timing. The timing of the voltage follower circuit 401 is related to the specific timing settings of the processing chip 402.

[0129] It should be noted that the processing chip 402 is used to analyze the signal to obtain the acquired information. The processing chip 402 can be configured according to the specific information to be acquired. For example, when it is necessary to acquire a temperature signal, since the signal output by the temperature sensor is an analog signal waveform, the processing chip 402 can be a digital signal processing (DSP) chip with analog-to-digital conversion.

[0130] In a specific implementation, the voltage follower circuit 401 can perform voltage following on the signal according to the transmission timing set by the processing chip 402, so as to accurately transmit the signal to the processing chip 402; the processing chip 402 can analyze the received signal to obtain the data information that needs to be acquired.

[0131] In scenarios where the electronic device is a server, considering that servers typically contain controllers such as BMC, CPU, FPGA, or DSP, these controllers are primarily used to control the server's operating state. In this embodiment, the controller within the server can also replace the processing chip 402 for signal parsing and processing. Of course, this controller can also implement other control functions within the server, such as adjusting the server's operating parameters. Furthermore, if the controller within the server does not have signal processing capabilities, a separate processing chip 402 can be configured, electrically connected to the controller within the server, and then the processed signal can be transmitted to the controller via signal transmission to adjust the server's operating state.

[0132] Reference Figure 7 In the fourth embodiment, the voltage follower circuit 401 includes: a first resistor R1, a second resistor R2, a third resistor R3, a third capacitor C3, and an inverting follower A;

[0133] The first end of the first resistor R1 is electrically connected to the first end of the second resistor R2 and the output end of the acquisition interface 10. The second end of the first resistor R1 is electrically connected to the positive input end of the inverting follower A. The second end of the second resistor R2 is grounded to GND.

[0134] The inverting input terminal of the inverting follower A is electrically connected to the output terminal of the inverting follower A, the first terminal of the third resistor R3, and the first terminal of the third capacitor C3, respectively.

[0135] The second terminal of the third resistor R3 is electrically connected to the processing chip 402, and the second terminal of the third capacitor C3 is grounded to GND.

[0136] It should be noted that the first resistor R1 and the second resistor R2 are voltage divider resistors used to adjust the voltage value input to the positive input terminal of the inverting follower A. The third resistor R3 is a voltage divider resistor, and the third capacitor C3 is a voltage regulator capacitor. The inverting follower A is used to follow the input signal, thereby adjusting the timing of the signal.

[0137] In a specific implementation, the acquisition interface 10 can output the signal to the positive input terminal of the inverting follower A after voltage division by the first resistor R1 and the second resistor R2. Then, timing adjustment is performed in the inverting follower A, and the timing-followed signal is output at the output terminal of the inverting follower A. The signal is then input to the processing chip through the third capacitor C3 and the third resistor R3.

[0138] Reference Figure 8 , Figure 8 This is a schematic diagram of the second structure of the fourth embodiment of the signal acquisition circuit in this application.

[0139] In the fourth embodiment, the signal acquisition circuit further includes: a power supply circuit 50 and an anti-reverse current circuit 60;

[0140] The power supply circuit 50 is electrically connected to the processing chip 402 and the voltage follower circuit 401 through the anti-backflow circuit 60.

[0141] It should be understood that the processing chip 402 needs a power supply voltage to wake it up before it can work normally. When the processing chip 402 is in the woke-up state, it can receive signals and analyze them.

[0142] It should be noted that the power supply circuit 50 is used to output power supply voltage to the processing chip 402 so that the control chip 402 can work normally. When the power supply circuit 50 is connected to the voltage follower circuit 401, the power supply voltage output by the power supply circuit 50 may be directly input in reverse to the output terminal of the voltage follower circuit 401, thus causing the sampling signal output by the voltage follower circuit 401 to fail to be output to the processing chip 402 normally. In the fourth embodiment, an anti-reverse current circuit 60 is also provided. The anti-reverse current circuit 60 is used to prevent the power supply voltage output by the power supply circuit 50 from flowing back into the voltage follower circuit 401 when the power supply circuit 50 and the voltage follower circuit 401 are connected, thus preventing the power supply voltage from flowing back into the voltage follower circuit 401.

[0143] In a specific implementation, the power supply circuit 50 can generate the power supply voltage required by the processing chip 402, and then output the power supply voltage to the power supply terminal of the processing chip 402 through the anti-reverse current circuit 60 to power the processing chip 402.

[0144] Reference Figure 9 , Figure 9This is a schematic diagram of the third structure of the fourth embodiment of the signal acquisition circuit in this application. The power supply circuit includes: a voltage conversion circuit 501;

[0145] The voltage conversion circuit 501 is connected to the processing chip 402 and the voltage follower circuit 401 through the anti-reverse current circuit 60; the voltage conversion circuit 501 is also connected to the second power supply (Volt Current Condenser2, VCC2).

[0146] It should be understood that the second power supply VCC2 can be a power supply that outputs DC voltage. The voltage output by this second power supply VCC2 may not match the supply voltage required by the processing chip 402. Typically, the power supply output voltage does not change with the voltage required by the load, such as a fixed 12V or 5V power supply voltage. To avoid this mismatch between the power supply voltage output by the second power supply VCC2 and the supply voltage required by the processing chip 402, the power supply circuit 50 includes a voltage conversion circuit 501. This voltage conversion circuit 501 converts the power supply voltage output by the second power supply VCC2 into the supply voltage used by the processing chip 402. For example, if the power supply voltage output by the second power supply VCC2 is 5V, while the supply voltage required by the processing chip 402 is 3.3V, the voltage conversion circuit 501 can convert the 5V voltage to 3.3V to supply power to the processing chip 402.

[0147] It should be noted that the voltage conversion circuit 501 can be a transformer and related peripheral structures, or a Buck-Boost circuit; no specific limitation is made here.

[0148] In a specific implementation, the voltage conversion circuit 501 can convert the power supply voltage to the power supply voltage required by the processing chip 402 according to the power supply voltage required by the processing chip 402 when it receives the power supply voltage output by the second power supply VCC2, and then supply power to the processing chip 402 through the anti-reverse power supply circuit 60.

[0149] In addition, refer to Figure 10 In the fourth embodiment, the power supply circuit 50 further includes a filter circuit 502;

[0150] The filter circuit 502 is connected to the voltage conversion circuit 501 and the second power supply VCC2.

[0151] It should be noted that when the second power supply VCC2 outputs power supply voltage, there may be interference signals that affect the voltage value of the power supply. For example, electronic noise may cause the voltage value of the power supply to be unstable, which in turn may cause abnormal power supply voltage to the processing chip 402, thus affecting the working state of the processing chip 402.

[0152] In the fourth embodiment, to avoid interference from the power supply voltage, a filter circuit 502 is also provided in the power supply circuit 50. This filter circuit 502 can filter out interference signals in the second power supply VCC2. The filter circuit 502 can be composed of a high-frequency filter or other components with filtering functions.

[0153] In a specific implementation, the filter circuit 502 can filter the power supply voltage output by the second power supply to obtain a stable power supply voltage, and then output the stable power supply voltage to the voltage conversion circuit 501. After being converted into a power supply voltage by the voltage conversion circuit 501, it supplies power to the processing chip 402.

[0154] Reference Figure 11 In the fourth embodiment, the filter circuit 502 includes: a fourth capacitor C4 and a fifth capacitor C5;

[0155] The first end of the fourth capacitor C4 is connected to the positive output terminal of the second power supply VCC2 and the input terminal of the voltage conversion circuit 501, respectively. The second end of the fourth capacitor C4 is connected to the protective ground terminal PE.

[0156] The first terminal of the fifth capacitor C5 is connected to the negative output terminal of the second power supply VCC2, and the second terminal of the fifth capacitor C5 is connected to the protective ground terminal PE.

[0157] It should be understood that the second power supply VCC2 is a DC power supply with a stable output voltage. Noise and interference signals are usually high-frequency signals. By setting a capacitor, the high-frequency interference signals in the power supply voltage output by the second power supply VCC2 can be filtered out.

[0158] Therefore, in the fourth embodiment, by setting two capacitors, the fourth capacitor C4 and the fifth capacitor C5, respectively, to filter the voltage values ​​output from the positive and negative output terminals of the second power supply VCC2, high-frequency interference signals in the power supply voltage output by the second power supply VCC2 can be effectively filtered out, thereby avoiding the interference signals in the power supply voltage from affecting the working state of the processing chip 402.

[0159] In addition, refer to Figure 11 In the fourth embodiment, the anti-reverse current circuit 60 includes a first diode D4 and a second diode D5;

[0160] The cathode of the first diode D4 is connected to the output terminal of the power supply circuit 50, the anode of the first diode D4 is connected to the cathode of the second diode D5 and the processing chip 402, and the cathode of the second diode D5 is connected to the negative output terminal of the second power supply VCC2.

[0161] It should be understood that a diode has a unidirectional conduction characteristic, and the current flow within the branch containing the diode can be effectively controlled. In the fourth embodiment, two diodes can be used: one to prevent the power supply voltage output from the positive terminal of the second power supply VCC2 from flowing back into the voltage follower circuit 401, and the other to prevent the signal output from the voltage follower circuit 401 from flowing back into the negative input terminal of the second power supply VCC2.

[0162] In specific implementation, the first diode D4 can prevent the supply voltage from being input to the voltage follower circuit 401 during the supply voltage output process; the second diode D5 can prevent the signal output by the voltage follower circuit 401 from being fed back to the negative input terminal of the second power supply VCC2, thereby ensuring that there is no abnormality caused by voltage backflow between the voltage follower circuit 401 and the second power supply VCC2.

[0163] In addition, refer to Figure 11 ,exist Figure 11 In the signal acquisition interface 10, when transmitting common-mode interference signals, since the analog ground terminal AGND and the digital ground terminal DGND are directly connected, there are two discharge paths for the common-mode interference signals: one is through the second clamping diode D2, the third clamping diode D3, the gas discharge tube GDT, and the second capacitor C2; the other is through the voltage follower circuit 401, the voltage conversion circuit 501, and the filter circuit 502, i.e., through the analog ground terminal AGND, the digital ground terminal DGND, and the filter circuit 502. Because the first and second discharge paths are connected in parallel, when some common-mode interference signals are discharged through the second discharge path, they will be input to the processing chip 402, affecting the working state of the processing chip 402. During the operation of the signal sampling circuit, when electrostatic discharge occurs, some static electricity may be input to the processing chip 402 through the voltage follower circuit 401, or through the analog ground terminal AGND and the digital ground terminal DGND.

[0164] Furthermore, in this embodiment, by reducing the impedance in the first discharge path or increasing the impedance in the second discharge path, most of the common-mode interference signals can be discharged through the first discharge path, and the small portion of common-mode interference signals will not affect the operating state of the processing chip 402. Reducing the impedance in the first discharge path can be achieved by optimizing the layout and routing to shorten the distance between the common-mode discharge circuit 302 and the protective ground terminal PE, and by increasing the diameter of the connecting wire between the common-mode discharge circuit 302 and the protective ground terminal PE. Increasing the impedance in the second discharge path can be achieved by connecting an additional resistor in series, adjusting the resistance value of the first resistor R1 or the third resistor R3, and adjusting the capacitance values ​​of the fourth capacitor C4 and the fifth capacitor C5. For example, adjusting the resistance value of the first resistor R1 from 10 ohms to 4.7 kΩ can effectively increase the impedance in the second discharge path. By reducing the impedance in the first discharge path or increasing the impedance in the second discharge path, the fifth capacitor C5 and the fourth capacitor C4 can be retained. This not only avoids interference signals from affecting the working state of the processing chip 402, but also ensures the stability of the power supply voltage input to the processing chip 402.

[0165] Furthermore, when the power supply voltage output by the second power supply VCC2 is stable, the fourth capacitor C4 and the fifth capacitor C5 can be removed to block the second discharge path and prevent common-mode interference signals from entering the processing chip 402 and affecting its operation.

[0166] exist Figure 11 In the process, the power supply voltage output by the second power supply VCC2 can be filtered by the fourth capacitor C4 and the fifth capacitor C5 and then input to the voltage conversion circuit 501. The voltage conversion circuit 501 can convert the power supply voltage into the power supply voltage required by the processing chip 402, thereby powering the processing chip 402. When the processing chip 402 receives the power supply voltage and operates normally, the sensor can collect the required information and output a signal to the acquisition interface 10. The acquisition interface 10 can transmit the signal through the transmission path between the voltage follower circuit 401 and the voltage follower circuit 401. After the differential mode interference signal in the transmission path is filtered out by the first clamping diode D1 and the first capacitor C1, and the common mode interference signal in the transmission path is filtered out by the second clamping diode D2, the third clamping diode D3, the gas discharge tube GDT and the second capacitor C2, the signal in the transmission path is input to the positive input terminal of the inverting follower A through the voltage divider of the first resistor R1 and the second resistor R2. After the output of the inverting follower A, it is transmitted to the processing chip 402 through the third capacitor C3 and the third resistor R3. The processing chip 402 parses the corresponding collected information according to the signal.

[0167] Furthermore, it should be emphasized that the signal output from the acquisition interface 10 may not contain any interference signals, i.e., neither differential-mode interference nor common-mode interference signals. In this case, the signal output from the acquisition interface 10 will also be free of interference and will not affect the operation of the signal processing circuit 40. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 do not need to filter out interference signals; the signal can be directly output to the signal processing circuit 40. However, if either differential-mode interference or common-mode interference exists, the corresponding differential-mode interference protection circuit 20 or common-mode interference protection circuit 30 needs to filter out either the existing differential-mode interference or common-mode interference signal. For example, if differential-mode interference exists in the signal, Figure 10 In the structure, when the acquisition interface 10 outputs a signal, the differential-mode interference protection circuit 20 can filter out the differential-mode interference signal in the signal, while the common-mode interference protection circuit 30 does not need to filter out non-existent common-mode interference signals. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 can directly output the signal after filtering out the differential-mode interference signal to the signal processing circuit 40. Of course, when there is a common-mode interference signal in the signal, when the acquisition interface 10 outputs a signal, the common-mode interference protection circuit 30 can filter out the common-mode interference signal, while the differential-mode interference protection circuit 20 does not need to filter out non-existent differential-mode interference signals. The differential-mode interference protection circuit 20 and the common-mode interference protection circuit 30 can directly output the signal after filtering out the common-mode interference signal to the signal processing circuit 40. Thus, it is possible to filter out either the differential-mode interference signal or the common-mode interference signal in the signal when either the differential-mode interference signal or the common-mode interference signal is present.

[0168] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A signal acquisition circuit, characterized in that, The signal acquisition circuit includes an acquisition interface, a differential mode interference protection circuit, a common mode interference protection circuit, and a signal processing circuit. The acquisition interface is used to electrically connect the sensor and the signal processing circuit to receive the signal acquired and output by the sensor. The differential mode interference protection circuit is electrically connected to the acquisition interface and the signal processing circuit respectively, and is used to filter out differential mode interference signals in the signal output by the acquisition interface; The common-mode interference protection circuit is electrically connected to both the acquisition interface and the signal processing circuit, and is used to filter out common-mode interference signals in the signal output from the acquisition interface; and The signal processing circuit is used to process the signal after filtering out the differential-mode interference signal and the common-mode interference signal. The differential mode interference protection circuit includes: a first clamping circuit; The first connection terminal of the first clamping circuit is electrically connected to the first output terminal of the acquisition interface, and the second connection terminal of the first clamping circuit is electrically connected to the second output terminal of the acquisition interface and the signal processing circuit. The first clamping circuit is used to clamp the voltage when the first voltage between the first output terminal and the second output terminal of the acquisition interface is greater than a first preset voltage; and The common-mode interference protection circuit includes: a second clamping circuit and a common-mode discharge circuit; The first connection terminal of the second clamping circuit is electrically connected to the first and second output terminals of the acquisition interface, and the second connection terminal of the second clamping circuit is electrically connected to the third output terminal of the acquisition interface and the common-mode discharge circuit. The second clamping circuit is used to perform voltage clamping when the second voltage between the first output terminal and the third output terminal of the acquisition interface is greater than the second preset voltage and / or the third voltage between the second output terminal and the third output terminal of the acquisition interface is greater than the third preset voltage; The common-mode discharge circuit is used to discharge the clamped second voltage and / or the clamped third voltage.

2. The signal acquisition circuit as described in claim 1, characterized in that, The first clamping circuit includes: a first clamping diode; The input terminal of the first clamping diode is electrically connected to the first power supply and the first output terminal of the acquisition interface, and the output terminal of the first clamping diode is electrically connected to the second output terminal of the acquisition interface and the signal processing circuit.

3. The signal acquisition circuit as described in claim 1, characterized in that, The second clamping circuit includes: a second clamping diode and a third clamping diode; The input terminal of the second clamping diode is electrically connected to the first output terminal of the acquisition interface, the input terminal of the third clamping diode is electrically connected to the second output terminal of the acquisition interface, and the output terminals of the second clamping diode and the third clamping diode are both electrically connected to the third output terminal of the acquisition interface and the common-mode discharge circuit.

4. The signal acquisition circuit as described in claim 1, characterized in that, The signal acquisition circuit further includes: a first capacitor; The first end of the first capacitor is electrically connected to the second end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit, respectively. The second end of the first capacitor is electrically connected to the third end of the acquisition interface, the common-mode interference protection circuit, and the signal processing circuit, respectively.

5. The signal acquisition circuit as described in claim 1, characterized in that, The common-mode discharge circuit includes: a gas discharge tube; The first end of the gas discharge tube is electrically connected to the second connection terminal of the second clamping circuit, and the second end of the gas discharge tube is electrically connected to the protective ground terminal; and / or The common-mode discharge circuit includes: a second capacitor; The first terminal of the second capacitor is electrically connected to the second connection terminal of the second clamping circuit, and the second terminal of the second capacitor is electrically connected to the protective ground terminal.

6. The signal acquisition circuit as described in any one of claims 1 to 5, characterized in that, The signal processing circuit includes: a voltage follower circuit and a processing chip; The voltage follower circuit is electrically connected to the second output terminal of the acquisition interface, the differential mode interference protection circuit, the common mode interference protection circuit, and the processing chip, respectively. The voltage follower circuit is used to perform voltage following on the signal.

7. The signal acquisition circuit as described in claim 6, characterized in that, The signal acquisition circuit also includes: a power supply circuit and a backflow prevention circuit; The power supply circuit is electrically connected to the processing chip and the voltage follower circuit through the anti-backflow circuit; The power supply circuit is used to provide power supply voltage to the processing chip through the anti-backflow circuit.

8. An electronic device, characterized in that, The electronic device includes a sensor and the signal acquisition circuit according to any one of claims 1 to 7; The sensor is electrically connected to the acquisition interface of the acquisition circuit.

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