High-speed analog-to-digital converter phase generation circuit and method
Through the negative feedback mechanism of the delay chain and closed-loop calibration control and suppression module, the high power consumption and clock phase instability of the high-speed multiphase clock generation circuit are solved, and low power consumption and stable internal multiphase clock generation are achieved.
Patent Information
- Application Number
- CN202510331245.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-04
AI Technical Summary
The existing high-speed multi-phase clock generation circuit is generated through external clock synchronization, with high power consumption and area requirements, and the delay chain is sensitive to process voltage temperature fluctuations, resulting in unstable clock phase.
The delay chain and closed-loop calibration control and suppression module are adopted to suppress the process voltage temperature fluctuations of the delay chain through a negative feedback mechanism, generate multiple internal timings, and form a negative feedback closed loop through the pulse width generation circuit, time voltage converter, dynamic voltage comparator and counter, and adjust the supply voltage of the delay chain to stabilize the clock phase.
It realizes internal multiphase clock generation at 5ps level, saves power consumption, simplifies clock driving circuit design, and maintains clock phase stability under PVT changes.
Smart Images
Figure CN120263189A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of digital - analog mixed - signal technology, and particularly relates to a phase generation circuit and method for a high - speed analog - to - digital converter. Background Art
[0002] A high - speed ADC (Analog - to - Digital Converter) requires a high - speed clock as an input, which is the source of internal timing control. Especially for a pipeline ADC, the internal timing is complex and usually includes a sample phase, a convert phase, an amplify phase, a capacitor reset phase, etc. Each phase has a specific sequence and different pulse widths, which places high requirements on the multi - phase clock generation circuit. However, the existing high - speed multi - phase clock generation circuit generates the above - mentioned 4 phases through an external clock synchronization method, and the pulse width requires a very high frequency, resulting in high power consumption requirements.
[0003] Based on this, a new technical solution is needed. Summary of the Invention
[0004] In view of this, the present application provides a phase generation circuit and method for a high - speed analog - to - digital converter.
[0005] The present application provides the following technical solutions:
[0006] A phase generation circuit for a high - speed analog - to - digital converter according to the present application includes a delay chain and a closed - loop calibration control suppression module connected to the delay chain. The delay chain delays the external clock of the high - speed analog - to - digital converter to generate multiple internal timings, and the closed - loop calibration control suppression module introduces negative feedback to suppress the process - voltage - temperature fluctuations of the delay chain.
[0007] Preferably, the external clock is internally divided by two, and the external clock extracts a first delay tap and a second delay tap through the delay chain, and is configured such that the divided - by - two, the first delay tap, and the second delay tap are used to construct multiple phase pulses;
[0008] The closed - loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses, compares the pulse widths of the first calibration pulse and the second calibration pulse, and feeds back to the supply - end voltage of the delay chain to form a negative - feedback closed - loop.
[0009] Preferably, the closed - loop calibration control suppression module includes a pulse - width generation circuit, a time - to - voltage converter, a dynamic voltage comparator, a counter, and a tuning array module;
[0010] The pulse - width generation circuit generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses;
[0011] The time-voltage converter converts the first calibration pulse into a first output voltage and the second calibration pulse into a second output voltage;
[0012] The dynamic voltage comparator enables the clock to enable the comparison of the first output voltage and the second output voltage, and outputs a voltage comparison result, which is used to negatively regulate the power supply voltage result of the delay chain;
[0013] The counter generates an adjustment codeword according to the voltage comparison result;
[0014] The tuning array module generates a power supply voltage for the delay chain according to the adjustment codeword to control the delay size, forming a negative feedback closed loop.
[0015] Preferably, the tuning array module includes a current source array and a current mirror circuit; the current source array generates a drive current according to the adjustment codeword; the current mirror circuit drives and adjusts the delay chain according to the drive current to control the delay size.
[0016] Preferably, the delay chain includes a plurality of delay units, and the delay units are cascaded, and the current mirror circuit is connected to each delay unit.
[0017] Preferably, the phase generation circuit further includes a logic gate module, and the delay chain extracts a preset node and generates a multi-phase clock required for the high-speed analog-to-digital converter through the logic gate module.
[0018] Preferably, the phase pulse includes an amplification phase, a reset phase, a sampling phase, and a conversion phase;
[0019] The first calibration pulse is the sum of the pulse widths of the amplification phase and the reset phase, and the second calibration pulse is the pulse width of the sampling phase.
[0020] According to the present application, a method for generating a phase of a high-speed analog-to-digital converter is further provided, including: delaying an external clock of the high-speed analog-to-digital converter through a delay chain to generate a plurality of internal timings, and introducing negative feedback through a closed-loop calibration control suppression module to suppress process voltage temperature fluctuations of the delay chain.
[0021] Preferably, in this phase generation method, the external clock is internally divided by two, and the external clock extracts a first delay tap and a second delay tap through the delay chain, and constructs a plurality of phase pulses through the division by two, the first delay tap, and the second delay tap;
[0022] The closed-loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed plurality of phase pulses, compares the pulse widths of the first calibration pulse and the second calibration pulse, and feeds back to the power supply terminal voltage of the delay chain to form a negative feedback closed loop;
[0023] The preset nodes extracted from the delay chain with adjusted delay and pulse width generate the multi-phase clock required for the high-speed analog-to-digital converter through the logic gate module.
[0024] Preferably, in the negative feedback of the closed-loop control suppression module, the pulse width generation circuit generates the first calibration pulse and the second calibration pulse according to the constructed multiple phase pulses;
[0025] The first calibration pulse is converted into a first output voltage through the time-voltage converter, and the second calibration pulse is converted into a second output voltage;
[0026] The dynamic voltage comparator enables the clock to compare the first output voltage and the second output voltage, and outputs the voltage comparison result, which is used to negatively regulate the power supply voltage result of the delay chain;
[0027] The counter generates an adjustment codeword according to the voltage comparison result;
[0028] The tuning array module generates a power supply voltage for the delay chain according to the adjustment codeword to control the delay size, forming a negative feedback closed loop.
[0029] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in this application at least include:
[0030] This application can delay the external clock of the high-speed ADC through the delay chain to generate multiple internal timings. The PVT fluctuations of the delay chain are suppressed by closed-loop calibration control. Thus, an internal multi-phase clock at the 5 ps level can be achieved with an ADC external clock that is synchronous with the sampling clock, saving power consumption, area, and simplifying the design of the clock drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions of the embodiments of this application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0032] Figure 1 It is a schematic diagram of the typical structure of the ADC lock delay loop DLL;
[0033] Figure 2 It is a timing diagram of the calibration combining the Pipeline ADC of the present invention;
[0034] Figure 3 It is a system block diagram of the present invention.
[0035] Reference numerals: 1, delay chain; 2, pulse width generation circuit; 3, time-voltage converter; 4, dynamic voltage comparator; 5, counter; 6, current source array; 7, current mirror circuit. Detailed implementation manners
[0036] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0037] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the scope of protection of the present application.
[0038] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or practice this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.
[0039] It should also be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.
[0040] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.
[0041] In view of this, through in-depth research and improvement exploration of the phase generation circuit, the applicant has found that there are many implementation schemes for high-speed multi-phase clock generation circuits, and common ones include high-frequency synchronous clocks, open-loop delay chains (Delay-Line), delay-locked loops (DLL), etc. As Figure 1 shown, for the external clock to generate the above 4 phases in a synchronous manner, the pulse width requires a very high frequency, which is not conducive to power consumption, area, and the design of the driving circuit. The traditional DLL scheme requires a charge pump (Charge Pump) + loop filter (LoopFilter), and the area is relatively large.
[0042] Based on this, the following will describe the technical solutions provided by the embodiments of the present application in conjunction with the accompanying drawings.
[0043] An embodiment of this specification proposes a phase generation circuit for a high-speed analog-to-digital converter. As Figure 2 and Figure 3 shown, it includes a delay chain 1 and a closed-loop calibration control suppression module connected to the delay chain 1. The delay chain 1 delays the external clock of the high-speed analog-to-digital converter to generate multiple internal timings, and the closed-loop calibration control suppression module introduces negative feedback to suppress the process voltage temperature fluctuations of the delay chain 1. The delay chain 1 is a delay chain formed by cascading delay units.
[0044] In one embodiment, the external clock is internally divided by two, and the external clock extracts a first delay tap and a second delay tap through the delay chain 1, and is configured such that the divided-by-two, the first delay tap, and the second delay tap are used to construct multiple phase pulses. The closed-loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses, compares the pulse width sizes of the first calibration pulse and the second calibration pulse, and feeds back to the supply voltage of the delay chain 1 to form a negative feedback closed loop.
[0045] This application is different from the closed-loop control scheme of the DLL in Figure 1 . The DLL extracts N taps to generate N-phase clocks. This application borrows the DLL concept. For example, when N = 3, that is, 3 delay units, 3 taps are extracted to construct a 2-phase clock. clk_div2 is the first clock, clk_d0 is the second clock, and clk_d1 is the third clock. The first clock and the second clock construct a first calibration pulse through a logic gate, and the second clock and the third clock construct a second calibration pulse through a logic gate. Figure 3 In
[0046] In one embodiment, the closed-loop calibration control suppression module includes a pulse width generation circuit 2, a time-to-voltage converter 3, a dynamic voltage comparator 4, a counter 5, and a tuning array module. The pulse width generation circuit 2 generates a first calibration pulse and a second calibration pulse according to a plurality of constructed phase pulses. The time-to-voltage converter 3 converts the first calibration pulse into a first output voltage and the second calibration pulse into a second output voltage. The dynamic voltage comparator 4 enables the clock to compare the first output voltage and the second output voltage, and outputs a voltage comparison result, which is used to negatively adjust the power supply voltage result of the delay chain 1. The counter 5 generates an adjustment code word according to the voltage comparison result. The tuning array module generates a power supply voltage for the delay chain 1 according to the adjustment code word to control the delay size, forming a negative feedback closed loop. The pulse width generation circuit 2 is composed of 2 pulse width generation circuits 2 constructed with delay taps as inputs. The time-to-voltage converter is used to convert the pulse width into voltage. The counter 5 accumulates the code word according to the output result of the comparator.
[0047] Figure 2 In the figure, a timing waveform of a Pipeline ADC, CKEXT: external clock; ck_div2: divided by two; ck_d0: second delay tap; ck_d1: first delay tap; ck: phase pulse, clock phase; A: amplification (amplification phase); R: capacitor reset (reset phase); S: sampling (sampling phase); C: conversion quantization (conversion phase); Widthadjust: pulse width generation circuit 2; t2v: time-to-voltage converter 3; cmp_clk: enable clock; cmp_res: voltage output result; code: adjustment code word; TVC: time-to-voltage converter 3; Comparator: comparator; Counter: counter 5. Four clock phases: S represents sampling, C represents conversion quantization, A represents amplification, and R represents sampling capacitor reset.
[0048] In one embodiment, the tuning array module includes a current source array 6 and a current mirror circuit 7. The current source array 6 generates a drive current according to the adjustment code word. The current mirror circuit 7 drives and adjusts the delay chain 1 according to the drive current to control the delay size. The current source array 6 is controlled by the code word of the counter 5, and the current mirror circuit 7 is used to supply power to the delay chain 1.
[0049] In one embodiment, the delay chain 1 includes a plurality of delay units, and the delay units are cascaded, and the current mirror circuit 7 is connected to each delay unit.
[0050] In one embodiment, the phase generation circuit further includes a logic gate module. The delay chain 1 extracts a preset node and generates a multi-phase clock required for the high-speed analog-to-digital converter through the logic gate module.
[0051] In one embodiment, the phase pulses include an amplification phase, a reset phase, a sampling phase, and a conversion phase; the first calibration pulse is the sum of the pulse widths of the amplification phase and the reset phase, and the second calibration pulse is the pulse width of the sampling phase.
[0052] As Figure 2 and Figure 3 shown, the pulse width generation circuit 2 corresponds to Figure 2 the "Width Adjust" operation; the time-to-voltage converter 3 corresponds to Figure 2 the "T2V" operation; the voltage comparator is controlled by cmp_clk, and the output result is cmp_res; the Up / Dn counter 5 is used to convert the cmp_res result into a calibration codeword; the current source array 6 is used to convert the calibration codeword into a drive current; the mirror current is used to drive and adjust the delay chain 1; after adjusting the delay and pulse width, a specified node is extracted from the delay chain 1 and passed through a logic gate to generate the multi-phase clock required by the ADC.
[0053] The external clock CKEXT is divided by two to obtain the clock ck_div2. Two taps ck_d0 and ck_d1 are extracted through the delay chain 1, and the above-mentioned 4 phase pulses can be constructed. Since the rising edge of the amplification phase A and the falling edge of the sampling phase S are both determined by the global clock CKEXT and do not fluctuate with PVT, two calibration pulses can be constructed. One is the sum of the pulse widths of the A+R two phases, and the other is the pulse width of S. In this way, the delay only affects the relative width difference between the two pulses, and their width sum remains unchanged.
[0054] The external clock CKEXT, the internal divided-by-two ck_div2 and the ck_d0 / d1 obtained after it passes through the delay chain 1 can construct the multi-phase clock S / C / A / R (merged and shown in the Figure 2 ck waveform).
[0055] The two pulses A+R and S are used for calibration. t2v (Time-To-Voltage) converts the two pulse widths into two output voltages to represent the pulse width size. Then, the comparator is enabled by the enable clock cmp_clk to compare the voltages to obtain cmp_res. cmp_res is used to negatively adjust the supply voltage result of the delay chain 1. cmp_res generates an adjustment codeword code through the counter 5. The adjustment codeword finally passes through a tuning array to generate a supply voltage for the delay chain 1 to control the delay size, forming a negative feedback closed loop as a whole. Ensure the stability of the PVT phase relationship.
[0056] This embodiment of the specification also discloses a method for generating the phase of a high-speed analog-to-digital converter, including: delaying the external clock of the high-speed analog-to-digital converter through the delay chain 1 to generate multiple internal timings, and introducing negative feedback through the closed-loop calibration control suppression module to suppress the process voltage temperature fluctuations of the delay chain 1.
[0057] In one embodiment, in this phase generation method, the external clock is divided by two internally, and the first delay tap and the second delay tap are extracted from the external clock through Delay Chain 1. Multiple phase pulses are constructed through the division by two, the first delay tap, and the second delay tap. The closed-loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses, compares the pulse widths of the first calibration pulse and the second calibration pulse, and feeds back to the supply voltage at the power supply end of Delay Chain 1 to form a negative feedback closed loop. The Delay Chain 1 with adjusted delay and pulse width extracts a preset node and generates the multi-phase clock required by the high-speed analog-to-digital converter through the logic gate module.
[0058] In one embodiment, during the negative feedback in the closed-loop control suppression module, the pulse width generation circuit 2 generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses; the time-to-voltage converter 3 converts the first calibration pulse into a first output voltage and the second calibration pulse into a second output voltage; the dynamic voltage comparator 4 enables the clock to enable the comparison of the first output voltage and the second output voltage, and outputs the voltage comparison result, and the voltage comparison result is used to negatively adjust the supply voltage result of Delay Chain 1; the counter 5 generates an adjustment code word according to the voltage comparison result; the tuning array module generates a supply voltage for Delay Chain 1 according to the adjustment code word to control the delay size, forming a negative feedback closed loop.
[0059] This application uses Delay Chain 1 to provide clock edges, and through logical operations, a low-speed external clock can also generate a stable multi-phase internal clock. However, the biggest problem with Delay Chain 1 is that the delay fluctuates greatly with PVT (Process-Voltage-Temperature), which is very likely to cause the multi-phase clock to be out of phase. To solve this problem, this application extracts 3 taps from Delay Chain 1, constructs 2 pulses, compares and adjusts their pulse widths, and feeds one back to the supply voltage at the power supply end of Delay Chain 1 to form a negative feedback closed loop, thereby ensuring stable delay under PVT.
[0060] This application uses a digital solution of time-to-voltage converter 3 (TVC) + comparator + counter 5 to achieve a function similar to that of a DLL. This application relates to an analog-to-digital converter clock generation circuit, which is a high-speed analog-to-digital converter phase generation circuit. This application provides a closed-loop multi-phase clock generation circuit for providing a multi-phase (Multi-Phase) clock for a high-speed ADC, which can effectively reduce the external clock frequency and make its phase stable under PVT (Process-Voltage-Temperature).
[0061] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and for the relevant parts, reference can be made to the corresponding parts of the foregoing embodiments.
[0062] As described above, the foregoing is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A phase generation circuit for a high-speed analog-to-digital converter, characterized in that, It includes a delay chain and a closed-loop calibration control suppression module for connecting the delay chain. The delay chain delays the external clock of the high-speed analog-to-digital converter to generate multiple internal timings, and the closed-loop calibration control suppression module introduces negative feedback to suppress the process voltage temperature fluctuations of the delay chain.
2. The phase generation circuit of the high-speed analog-to-digital converter according to claim 1, characterized in that The external clock is internally divided by two, and the external clock extracts a first delay tap and a second delay tap through the delay chain, and is configured such that the divided-by-two, the first delay tap, and the second delay tap are used to construct multiple phase pulses; The closed-loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses, compares the pulse widths of the first calibration pulse and the second calibration pulse, and feeds back to the supply voltage terminal of the delay chain to form a negative feedback closed loop.
3. The phase generation circuit of the high-speed analog-to-digital converter according to claim 2, wherein The closed-loop calibration control suppression module includes a pulse width generation circuit, a time-voltage converter, a dynamic voltage comparator, a counter, and a tuning array module; The pulse width generation circuit generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses; The time-voltage converter converts the first calibration pulse into a first output voltage and converts the second calibration pulse into a second output voltage; The dynamic voltage comparator enables the clock to enable the comparison of the first output voltage and the second output voltage, and outputs a voltage comparison result, and the voltage comparison result is used to negatively adjust the supply voltage result of the delay chain; The counter generates an adjustment code word according to the voltage comparison result; The tuning array module generates a supply voltage according to the adjustment code word to supply power to the delay chain to control the delay size, forming a negative feedback closed loop.
4. The phase generation circuit of the high-speed analog-to-digital converter according to claim 3, wherein The tuning array module includes a current source array and a current mirror circuit; the current source array generates a drive current according to the adjustment code word; the current mirror circuit drives and adjusts the delay chain according to the drive current to control the delay size.
5. The phase generation circuit of the high-speed analog-to-digital converter according to claim 3, characterized in that, The delay chain includes multiple delay units, and the delay units are cascaded, and the current mirror circuit is connected to each delay unit.
6. The phase generation circuit of the high-speed analog-to-digital converter according to claim 1, wherein The phase generation circuit further includes a logic gate module, and the delay chain extracts a preset node and generates a multi-phase clock required by the high-speed analog-to-digital converter through the logic gate module.
7. The phase generation circuit of the high-speed analog-to-digital converter according to claim 2, characterized in that The phase pulses include an amplification phase, a reset phase, a sampling phase, and a conversion phase; The first calibration pulse is the sum of the pulse widths of the amplification phase and the reset phase, and the second calibration pulse is the pulse width of the sampling phase.
8. A method for generating a phase of a high-speed analog-to-digital converter, characterized in that, It includes: The external clock of the high-speed analog-to-digital converter is delayed by the delay chain to generate multiple internal timings, and negative feedback is introduced through the closed-loop calibration control suppression module to suppress the process voltage temperature fluctuations of the delay chain.
9. The method for generating a phase of a high-speed analog-to-digital converter according to claim 8, wherein In this phase generation method, the external clock is internally divided by two, and the external clock extracts a first delay tap and a second delay tap through the delay chain, and multiple phase pulses are constructed through the divided-by-two, the first delay tap, and the second delay tap; The closed-loop control suppression module generates a first calibration pulse and a second calibration pulse according to the constructed multiple phase pulses, compares the pulse widths of the first calibration pulse and the second calibration pulse, and feeds back to the supply voltage terminal of the delay chain to form a negative feedback closed loop; The delay chain with adjusted delay and pulse width extracts a preset node and generates a multi-phase clock required by the high-speed analog-to-digital converter through the logic gate module.
10. The method for generating a phase of a high-speed analog-to-digital converter according to claim 9, wherein In the negative feedback of the closed-loop control suppression module, a first calibration pulse and a second calibration pulse are generated by a pulse width generation circuit according to a plurality of constructed phase pulses; The first calibration pulse is converted into a first output voltage, and the second calibration pulse is converted into a second output voltage by a time-voltage converter; The first output voltage and the second output voltage are enabled to be compared by a dynamic voltage comparator through an enable clock, and a voltage comparison result is output. The voltage comparison result is used to negatively adjust the power supply voltage result of the delay chain; An adjustment codeword is generated by a counter according to the voltage comparison result; A power supply voltage is generated by a tuning array module according to the adjustment codeword to supply power to the delay chain to control the delay size, forming a negative feedback closed loop.