Bias current circuit with calibration function applied to sigma delta ADC

Abstract

The invention discloses a bias current circuit with a calibration function. The bias current circuit mainly comprises a bias circuit, a current calibration circuit, a source negative feedback resistance circuit, a current output gear logic control circuit and a bias current output circuit. The bias circuit provides four bias voltages for the current mirror circuit so as to provide quiescent working point voltage for the circuit; the current calibration circuit is composed of a five-bit register TRIMlt; 4: 0gt; the magnitude of the calibration current is controlled; the source negative feedback resistance circuit is composed of 15 resistors R1-R15, the output impedance of the circuit is increased, and the noise of a circuit module is reduced; four transmission gates are adopted in the current output gear logic control circuit, and the current is controlled to be output at different positions by turning off and turning on the four transmission gates; the bias current output circuit copies current through a PMOS cascode current mirror, bias current output is controlled by current output gears, and bias current IBAIS1 and IBAIS2 are output respectively. The circuit has the advantage that the precision of the output bias current IBAIS1 and IBAIS2 is improved by using the current calibration circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and particularly relates to a bias current circuit with a calibration function applied to a Sigma Delta ADC. Background Art

[0002] The IBAIS (Current Digital to Analog Converter) circuit refers to an internal current output digital to analog converter. This circuit is mainly used to adjust the feedback voltage at the input end of the ADC, thereby realizing the control of the internal reference voltage and gain of the ADC.

[0003] In terms of the technical background, the application of the IBAIS circuit in the ADC is to provide flexible reference voltage and gain adjustment functions to meet the requirements for signal acquisition accuracy and range in different application scenarios. By controlling the current value output by the IBAIS, the feedback voltage at the input end of the ADC can be adjusted, thereby realizing the adjustment of the reference voltage and gain of the ADC. In this way, under different measurement ranges and accuracy requirements, appropriate reference voltage and gain values can be flexibly selected to improve the performance and applicability of the ADC.

[0004] In a high-precision and low-power ADC chip such as the Sigma Delta ADC, the IBAIS circuit is well-designed and can provide a stable and reliable current output to realize the control of the feedback voltage at the input end of the ADC. Through the adjustment of the IDAC circuit, the ADC can be flexibly switched under different working modes to meet the requirements for signal acquisition accuracy and range in different application scenarios.

[0005] Generally speaking, the application of the IBAIS circuit in the ADC chip is to provide flexible adjustment functions for the reference voltage and gain to meet the requirements for signal acquisition accuracy and range under different application needs. With the technical support of the IBAIS circuit, the ADC chip can realize more accurate, stable and reliable signal acquisition and conversion functions.

[0006] The disadvantages of the traditional IBAIS circuit are as follows:

[0007] 1. Limited accuracy: The accuracy and stability of the current source are limited, which will affect the accuracy of the entire converter. Because the output current of the current source is unstable or affected by factors such as temperature change, the accuracy of the IBAIS output current will decrease.

[0008] 2. Noise influence: In the traditional IBAIS circuit, the current source itself may generate noise, which affects the quality of the output signal. The noise will cause the stability and accuracy of the output signal to decrease, affecting the performance of the entire system.

[0009] 3. Temperature Drift Effect: In the traditional IBAIS circuit, the output current of the current source may be affected by temperature changes, resulting in the drift of the output current, which affects the accuracy and stability of the system.

[0010] In summary, the traditional IBAIS circuit has disadvantages such as limited precision, noise influence, and temperature drift effect. To overcome these disadvantages, the IBAIS circuit adopts more advanced technologies and methods, such as using high-precision current sources, noise suppression technologies, current calibration, etc., to improve the performance and stability of the IBAIS circuit.

[0011] After retrieval, the application publication number is CN101067753A. The power supply bias circuit with negative feedback includes a bias generation circuit, a mirror branch, a feedback branch, and a current output branch. The bias generation circuit consists of current sources I1, I2, NMOS transistors n1, n2, and is used to generate a bias current independent of the power supply. The mirror branch consists of PMOS transistor p1 and NMOS transistor n3, and is used to mirror the current in the bias generation circuit and mirror the current to the current output branch. The feedback branch consists of current source I3 and equivalent switch SW, and is used to generate a current feedback amount to adjust the magnitude of the bias current in the bias generation circuit. The current output branch consists of PMOS transistor p5 and is used to output a stable bias current. The present invention stabilizes the bias independent of the power supply at a fixed value, can better stabilize the output bias current than the existing power supply bias circuit, and reduces the sensitivity to the power supply voltage. The present invention introduces the concept of negative feedback, and adjusts the current in the bias generation circuit to keep the current at a certain value, so that the output bias current has higher precision.

[0012] Differences and deficiencies: The patent introduces the concept of negative feedback, and adjusts the current in the bias generation circuit to keep it at a certain value, so that the output bias current has higher precision. However, this circuit does not have the function of calibrating the output current, cannot perform corresponding trimming on the current, and the noise of the circuit is relatively large.

[0013] Overcoming method: The circuit in this patent has a current calibration circuit for calibrating the output current. The size of the calibration current is controlled by a five-bit register TRIM<4:0> (i.e., 16 gears), and the output current can be correspondingly trimmed (trimmed larger or smaller) by controlling the logical value of the register, so that the bias current value can be accurately output; and a source negative feedback resistor is also used to reduce the noise influence of the circuit, making the stability and accuracy of the output current higher. Summary of the Invention

[0014] The present invention aims to solve the above problems of the prior art. A bias current circuit with a calibration function applied to a sigma delta ADC is proposed. The technical solution of the present invention is as follows:

[0015] A bias current circuit with calibration function applied to a sigma delta ADC, which comprises: a bias circuit, a current calibration circuit, a source negative feedback resistor circuit, a current output gear logic control circuit, and a bias current output circuit. The bias circuit is connected to the current calibration circuit to provide a bias voltage for the static operation of the current calibration circuit; the current output gear logic control circuit is connected to the current calibration circuit to logically control the output of currents at different gears of the current calibration circuit; the source negative feedback resistor circuit is connected to the power supply or ground wire to reduce the influence of noise on the circuit. The bias circuit externally inputs a reference current source and precisely replicates the externally input reference current by adopting the structure of a cascode current mirror; the current calibration circuit is controlled by a five-bit register TRIM<4:0> to control the magnitude of the calibration current, wherein the upper four bits are used to calibrate the output current value, and the lowest bit is used as a flag bit. When TRIM<0> = 0, the output current is calibrated in the increasing direction, and when TRIM<0> = 1, the output current is calibrated in the decreasing direction; the source negative feedback resistor circuit is composed of 15 resistors R1 - R15 and is used to increase the output impedance of the circuit and reduce the noise of the circuit module; the current output gear logic control circuit adopts four transmission gates TG1, TG2, TG3, and TG4, and uses the turn-off and closure of the four transmission gates to control the output of currents at different gears; the bias current output circuit replicates the current through a PMOS cascode current mirror, and the output of the bias current is controlled by the current output gear to respectively output bias currents IBAIS1 and IBAIS2.

[0016] Further, the bias circuit includes NMOS transistors (MN1, MN2, MN3, MN4) and PMOS transistors (MP1, MP2). The NMOS transistors MN1, MN3 and MN2, MN4 of the bias circuit are diode-connected to provide the static operating point voltages VBN2 and VBN1 for the NMOS transistors MN5, MN7 and MN6, MN8. The PMOS transistors MP1 and MP3 of the bias circuit are diode-connected to provide the static operating point voltage VBP1 for the PMOS transistors MP7, MP10 and MP13. The PMOS transistors MP17 and MP18 are series PMOS transistors with diode connection plus drain and source connected. MP17 provides the required gate-source voltage difference VGS, and MP18 generates the required overdrive voltage Vsat to provide the static operating point voltage VBP2 for the PMOS transistors MP2, MP5, MP9, MP12, MP15, MP20, MP22, MP24, MP26, MP28, MP30, MP32 and MP34. The PMOS transistors MP19 and MP21 are diode-connected to provide the static operating point voltage VBP1ˊ for the PMOS transistor MP23. The PMOS transistor MP25 is diode-connected to provide the static operating point voltage VBP1ˊˊ for the PMOS transistors MP27, MP29, MP31 and MP33.

[0017] Further, the current calibration circuit includes six inverters INV1, INV2, INV3, INV4, INV5, INV6 and four current calibration branches IMP3, IMP7, IMP10, IMP13. The IMP3 current calibration branch is composed of PMOS transistors MP3, MP4 and MP5; the IMP7 current calibration branch is composed of PMOS transistors MP7, MP8 and MP9; the IMP10 current calibration branch is composed of PMOS transistors MP10, MP11 and MP12; the IMP13 current calibration branch is composed of PMOS transistors MP13, MP14 and MP15. The current calibration circuit is controlled by a five-bit register TRIM<4:0> to control the magnitude of the calibration current. Among them, the upper four bits TRIM<4:1> are used to calibrate the output current value, and the lowest bit TRIM<0> is used as a flag bit. When TRIM<4:0> = 0, that is, TRIM1 = TRIM2 = TRIM3 = TRIM4 = 1, all four current calibration branches IMP3, IMP7, IMP10, IMP13 are turned off. At this time, the bias current calibration circuit does not work, that is, it does not have the calibration function. When TRIM<0> = 0, that is, the PMOS transistor MP6 is in the conducting state and the PMOS transistor MP16 is in the off state. Therefore, the current of the IMP6 current branch flows into the IMP24 current branch at this time, making the current of the IMP24 current branch increase, that is, the current of the IMN11 current branch increases, making the current of the IMN14 current branch mirror and copy the current of the IMN11 branch also increase. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches mirror and copy the current of the IMP25 branch also increase, so as to calibrate the output current in the larger direction. When TRIM<0> = 1, that is, the PMOS transistor MP6 is in the off state and the PMOS transistor MP16 is in the conducting state. Therefore, the current of the IMP16 current branch flows into the IMP20 current branch at this time. Also, because the current of the IMN7 current branch mirrors and copies the externally input reference current source I_IN, the current of the IMN7 current branch remains unchanged. Therefore, the current of the IMP19 current branch will decrease, so that the gate voltages of the PMOS transistors MP19, MP21 and MP23 increase. Therefore, the current of the IMP23 current branch decreases, that is, the current of the IMN11 current branch decreases, making the current of the IMN14 current branch mirror and copy the current of the IMN11 branch also decrease. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches mirror and copy the current of the IMP25 branch also decrease, so as to calibrate the output current in the smaller direction.

[0018] Further, the source negative feedback resistor circuit includes 15 resistors R1 - R15. Among them, resistors R1 - R7 are respectively connected to the sources of NMOS transistors MN2, MN4, MN6, MN8, MN10, MN13, and MN15; resistors R8 - R15 are respectively connected to the sources of PMOS transistors MP19, MP21, MP23, MP25, MP27, MP29, MP31, and MP33. Adding source negative feedback resistors to the bias circuit and the bias current output circuit can reduce the noise gain in the circuit, thereby effectively reducing the noise level of the entire circuit. Specifically, the source negative feedback resistor in the bias circuit can help stabilize the static operating point of the MOS transistor, making the operating state of the circuit more stable; the stable static operating point is used to reduce the drift of the bias voltage in the circuit, reduce the sensitivity of the circuit to temperature and power supply voltage changes, and thus reduce the generation of noise; the source negative feedback resistor can reduce the non - linear distortion of the MOS transistor and improve the linearity of the circuit; in circuits such as signal amplifiers, the source negative feedback resistor reduces the difference between the output signal and the input signal, thereby improving the linearity and stability of the circuit. In addition, the addition of the source negative feedback resistor reduces the amplification factor of the circuit and the amplitude of the output signal, so it also reduces the amplification factor of the noise signal; by controlling the gain, the amplitude of the noise signal transmitted to the output end is reduced, thereby reducing the noise level of the entire circuit.

[0019] Further, the current output gear logic control circuit uses four transmission gates TG1, TG2, TG3, and TG4. The conduction and closing of the four transmission gates are controlled by logic P1 and P2, where P1N and P2N are the inversions of logic P1 and P2; the on - off and closing of the four transmission gates are used to control the output of different current positions. When P1 = P2 = 0, that is, P1N = P2N = 1, the four transmission gates TG1, TG2, TG3, and TG4 are all closed, and at this time, the output bias currents IBAIS1 and IBAIS2 are both 0; when P1 or P2 = 1, that is, P1N or P2N = 0, one of the four transmission gates TG1, TG2, TG3, and TG4 is conducting, and at this time, the output bias current IBAIS1 or IBAIS2 = 50uA; when P1 and P2 = 1, that is, P1N and P2N = 0, all four transmission gates TG1, TG2, TG3, and TG4 are conducting, and at this time, the output bias current IBAIS1 = IBAIS2 = 100uA.

[0020] Furthermore, the bias current output circuit consists of four current branches IMP27, IMP29, IMP31, and IMP33, which accurately replicate the current of the IMP25 current branch through a PMOS cascode current mirror. The output of the bias current is controlled by the current output gear, and the bias currents IBAIS1 and IBAIS2 are output respectively. A current calibration circuit is used to improve the accuracy of the output bias currents IBAIS1 and IBAIS2.

[0021] The advantages and beneficial effects of the present invention are as follows:

[0022] The IBAIS (current digital-to-analog converter) with current calibration and noise suppression functions of the present invention has the following advantages compared with the traditional IBAIS:

[0023] 1. Improve accuracy and stability: Through the current calibration function, the current output by the IBAIS can be calibrated and adjusted to improve the output accuracy and stability. Current calibration can eliminate the errors of the current source and reduce the drift of the output current, thereby improving the accuracy of the entire converter.

[0024] 2. Reduce the noise level: The IBAIS with noise suppression function can effectively reduce the noise in the input signal and improve the quality of the output signal. The noise suppression technology can effectively filter out the noise generated in the circuit, improve the signal-to-noise ratio, and thus improve the signal-to-noise ratio of the system.

[0025] 3. Improve dynamic performance: The IBAIS with current calibration and noise suppression functions usually has high dynamic performance, fast response speed, and is suitable for the requirements of high-speed data conversion. At the same time, through current calibration, the dynamic range of the system can be improved, enabling the system to maintain accurate output within a wide input range.

[0026] 4. Reduce power consumption: The optimized IBAIS circuit usually adopts current sources and noise suppression circuits with low power consumption while performing current calibration and noise suppression, thereby reducing the power consumption of the entire circuit.

[0027] In summary, the IBAIS with current calibration and noise suppression functions has the advantages of improving accuracy and stability, reducing the noise level, and improving dynamic performance compared with the traditional IBAIS. These advantages enable this type of IBAIS to improve the performance and reliability of the system.

[0028] The main difference in this patent is that the circuit has a current calibration function. The calibration current size is controlled by a five-bit register TRIM<4:0> (i.e., 16 gears), and the output current can be adjusted accordingly (increased or decreased) by controlling the logical value of the register, so that the bias current value can be accurately output. In addition, a source negative feedback resistor is used to reduce the noise influence of the circuit, making the stability and accuracy of the output current higher. Brief Description of the Drawings

[0029] Figure 1 It is the overall bias current circuit of the preferred embodiment provided by the present invention;

[0030] Figure 2 Transient simulation diagrams of different gears of IBAIS1 of the present invention;

[0031] Figure 3 Transient simulation diagrams of different gears of IBAIS1 of the present invention;

[0032] Figure 4 Transient simulation diagrams of process corners of IBAIS1 and IBAIS2 of the present invention;

[0033] Figure 5 1MC simulation diagrams of gears of IBAIS1 and IBAIS2 of the present invention;

[0034] Figure 6 2MC simulation diagrams of gears of IBAIS1 and IBAIS2 of the present invention;

[0035] Figure 7 PPM MC simulation diagrams of IBAIS1 and IBAIS2 of the present invention;

[0036] Figure 8 PPM_MATCH MC simulation diagrams of IBAIS1 and IBAIS2 of the present invention. Detailed Description of the Invention

[0037] Next, the technical solutions in the embodiments of the present invention will be clearly and detailedly described in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention.

[0038] The technical solution for the present invention to solve the above technical problems is:

[0039] As Figure 1 shown, a bias current circuit with a calibration function mainly includes a bias circuit, a current calibration circuit, a source negative feedback resistor circuit, a current output gear logic control circuit, and a bias current output circuit.

[0040] The function of the bias circuit is to provide a bias voltage for static operation to the current calibration circuit, the current output gear logic control circuit, and the bias current output circuit. The bias circuit externally inputs a reference current source and precisely replicates the externally input reference current using the structure of a cascode current mirror. The NMOS transistors MN1, MN3 and MN2, MN4 of the bias circuit are diode-connected to provide the static operating point voltages VBN2 and VBN1 for the NMOS transistors MN5, MN7 and MN6, MN8. The PMOS transistors MP1 and MP3 of the bias circuit are diode-connected to provide the static operating point voltage VBP1 for the PMOS transistors MP7, MP10 and MP13. The PMOS transistors MP17 and MP18 are a series of PMOS transistors with diode connection plus drain and source connected. MP17 provides the required voltage difference VGS between the gate and the source, and MP18 generates the required overdrive voltage Vsat to provide the static operating point voltage VBP2 for the PMOS transistors MP2, MP5, MP9, MP12, MP15, MP20, MP22, MP24, MP26, MP28, MP30, MP32 and MP34. The PMOS transistors MP19 and MP21 are diode-connected to provide the static operating point voltage VBP1ˊ for the PMOS transistor MP23. The PMOS transistor MP25 is diode-connected to provide the static operating point voltage VBP1ˊˊ for the PMOS transistors MP27, MP29, MP31 and MP33. Thereby ensuring that each MOS transistor can operate normally and enabling the circuit module to function properly.

[0041] The current calibration circuit consists of six inverters INV1, INV2, INV3, INV4, INV5, INV6 and four current calibration branches IMP3, IMP7, IMP10, IMP13. Among them, the IMP3 current calibration branch consists of PMOS transistors MP3, MP4 and MP5; the IMP7 current calibration branch consists of PMOS transistors MP7, MP8 and MP9; the IMP10 current calibration branch consists of PMOS transistors MP10, MP11 and MP12; the IMP13 current calibration branch consists of PMOS transistors MP13, MP14 and MP15. The current calibration circuit is controlled by a five-bit register TRIM<4:0> to control the magnitude of the calibration current. Among them, the upper four bits TRIM<4:1> are used to calibrate the output current value, and the lowest bit TRIM<0> is used as a flag bit. When TRIM<4:0> = 0, that is, TRIM1 = TRIM2 = TRIM3 = TRIM4 = 1, all four current calibration branches IMP3, IMP7, IMP10, IMP13 are turned off, and at this time the bias current calibration circuit does not work, that is, it does not have the calibration function. When TRIM<0> = 0, that is, the PMOS transistor MP6 is in the conducting state and the PMOS transistor MP16 is in the off state. Therefore, the current of the IMP6 current branch flows into the IMP24 current branch at this time, making the current of the IMP24 current branch increase, that is, the current of the IMN11 current branch increases, making the current of the IMN14 current branch that mirrors the current of the IMN11 branch also increase. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches that mirror the current of the IMP25 branch also increase, so as to calibrate the output current in the larger direction; when TRIM<0> = 1, that is, the PMOS transistor MP6 is in the off state and the PMOS transistor MP16 is in the conducting state. Therefore, the current of the IMP16 current branch flows into the IMP20 current branch at this time. Also, because the current of the IMN7 current branch mirrors the externally input reference current source I_IN, the current of the IMN7 current branch remains unchanged. Therefore, the current of the IMP19 current branch will decrease, so that the gate voltages of the PMOS transistors MP19, MP21 and MP23 increase. Therefore, the current of the IMP23 current branch decreases, that is, the current of the IMN11 current branch decreases, making the current of the IMN14 current branch that mirrors the current of the IMN11 branch also decrease. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches that mirror the current of the IMP25 branch also decrease, so as to calibrate the output current in the smaller direction.

[0042] The source negative feedback resistor circuit is composed of 15 resistors R1 - R15. Adding a source negative feedback resistor to the bias circuit and the bias current output circuit can reduce the noise of the circuit. This is because the function of the source negative feedback resistor can reduce the noise gain in the circuit, thereby effectively reducing the noise level of the entire circuit. Specifically, the source negative feedback resistor in the bias circuit can help stabilize the static operating point of the MOS transistor, making the operating state of the circuit more stable. A stable static operating point can reduce the drift of the bias voltage in the circuit, reduce the sensitivity of the circuit to temperature and power supply voltage changes, and thus reduce the generation of noise; the source negative feedback resistor can reduce the non-linear distortion of the MOS transistor and improve the linearity of the circuit. In circuits such as signal amplifiers, the source negative feedback resistor can reduce the difference between the output signal and the input signal, thereby improving the linearity and stability of the circuit. In addition, the addition of the source negative feedback resistor can reduce the amplification factor of the circuit, reduce the amplitude of the output signal, and thus also reduce the amplification factor of the noise signal. By controlling the gain, the amplitude of the noise signal transmitted to the output end can be reduced, thereby reducing the noise level of the entire circuit. Generally speaking, adding a source negative feedback resistor can reduce the noise of the bias circuit and improve the signal-to-noise ratio of the entire circuit. It can effectively reduce the noise level and improve the overall performance of the circuit.

[0043] For the current output gear logic control circuit and the bias current output circuit, the current output gear logic control circuit uses four transmission gates TG1, TG2, TG3, and TG4. The conduction and closing of the four transmission gates are controlled by logic P1 and P2, where P1N and P2N are the inverses of logic P1 and P2. The on / off of the four transmission gates is used to control the output of different current levels; when P1 = P2 = 0, that is, P1N = P2N = 1, the four transmission gates TG1, TG2, TG3, and TG4 are all closed, and at this time, the output bias currents IBAIS1 and IBAIS2 are both 0; when P1 or P2 = 1, that is, P1N or P2N = 0, one of the four transmission gates TG1, TG2, TG3, and TG4 is conducting, and at this time, the output bias current IBAIS1 or IBAIS2 = 50uA; when P1 and P2 = 1, that is, P1N and P2N = 0, all four transmission gates TG1, TG2, TG3, and TG4 are conducting, and at this time, the output bias currents IBAIS1 = IBAIS2 = 100uA. The bias current output circuit is composed of four current branches IMP27, IMP29, IMP31, and IMP33, and accurately replicates the current of the IMP25 current branch through a PMOS cascode current mirror. The output of the bias current is controlled by the current output gear, and the bias currents IBAIS1 and IBAIS2 are output respectively. A current calibration circuit is used to improve the accuracy of the output bias currents IBAIS1 and IBAIS2.

[0044] Simulation results

[0045] Figure 2 Shows the transient simulation diagrams of the output current values at two different levels of the bias current IBAIS1, 50 μA and 100 μA. The current outputs are 50.383 μA and 100.762 μA respectively, and the accuracies of the output current values at the two different levels of 50 μA and 100 μA are 0.766% and 0.762% respectively.

[0046] Figure 3 Shows the transient simulation diagrams of the output current values at two different levels of the bias current IBAIS2, 50 μA and 100 μA. The current outputs are 50.383 μA and 100.762 μA respectively, and the accuracies of the output current values at the two different levels of 50 μA and 100 μA are 0.766% and 0.762% respectively.

[0047] Figure 4 Shows the transient simulation diagrams of the output current values at two different levels of 50 μA and 100 μA of IBAIS1 and IBAIS2 at 135 process corners. It can be seen from the figure that the maximum and minimum current values output at the 50 μA current level are 49.9679 μA and 50.5837 μA respectively. Then the current accuracy output at the 50 μA current level at the process corner is between 0.0642% and 1.1674%. The maximum and minimum current values output at the 100 μA current level are 99.923 μA and 101.162 μA respectively. Then the current accuracy output at the 100 μA current level at the process corner is between 0.0769% and 1.162%.

[0048] Figure 5 Shows the Monte Carlo simulation diagrams of IBAIS1 and IBAIS2 at the 50 μA level with 200 random numbers. The simulation results show that the average output current magnitude is 50.3756 μA.

[0049] Figure 6 Shows the Monte Carlo simulation diagrams of IBAIS1 and IBAIS2 at the 100 μA level with 200 random numbers. The simulation results show that the average output current magnitude is 100.748 μA.

[0050] Figure 7 Shows the Monte Carlo simulation diagrams of the temperature drift coefficient of the output current of IBAIS1 and IBAIS2 with 200 random numbers. It can be seen from the figure that the temperature drift coefficient is 33.7998 ppm / °C.

[0051] Figure 8 Shows the Monte Carlo simulation diagrams of the temperature drift coefficient mismatch of the output current of IBAIS1 and IBAIS2 at the same current level with 200 random numbers. It can be seen from the figure that the temperature drift coefficient mismatch value is 2.70378 ppm / °C.

[0052] As can be seen from the above results, a bias current circuit with a calibration function according to the present invention reduces the noise of the circuit and improves the accuracy and stability of the output current.

[0053] The systems, devices, modules or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions.

[0054] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, commodity or device comprising the element.

[0055] The above embodiments should be understood as being only for the purpose of illustrating the present invention and not for limiting the scope of protection of the present invention. After reading the content recorded in the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A bias current circuit with a calibration function applied to a sigma delta ADC, characterized in that, Including: A bias circuit, a current calibration circuit, a source negative feedback resistance circuit, a current output gear logic control circuit, and a bias current output circuit. The bias circuit is connected to the current calibration circuit to provide a bias voltage for the static operation of the current calibration circuit. The current output gear logic control circuit is connected to the current calibration circuit to logically control the output of currents at different gears of the current calibration circuit. The source negative feedback resistance circuit is connected to the power supply or the ground wire. Among them, the bias current output circuit provides a bias voltage for static operation. The bias circuit inputs a reference current source externally and uses the structure of a cascode current mirror to accurately copy the externally input reference current. The current calibration circuit is controlled by a five-bit register TRIM<4:0> to control the magnitude of the calibration current. Among them, the upper four bits are used to calibrate the output current value, and the lowest bit is used as a flag bit. When TRIM<0> = 0, the output current is calibrated in the larger direction. When TRIM<0> = 1, the output current is calibrated in the smaller direction. The source negative feedback resistance circuit consists of 15 resistors R1 - R15 and is used to increase the output impedance of the circuit and reduce the noise of the circuit module. The current output gear logic control circuit uses four transmission gates TG1, TG2, TG3, and TG4 to control the output of different bits of current by the turn-off and closure of the four transmission gates. The bias current output circuit copies the current through a PMOS cascode current mirror, and the bias current output is controlled by the current output gear and outputs bias currents IBAIS1 and IBAIS2 respectively.

2. The bias current circuit with a calibration function applied to a sigma delta ADC according to claim 1, characterized in that, The bias circuit includes NMOS transistors MN1, MN2, MN3, MN4 and PMOS transistors MP1, MP2. The NMOS transistors MN1, MN3 and MN2, MN4 of the bias circuit are connected by diodes to provide the static operating point voltages VBN2 and VBN1 for the NMOS transistors MN5, MN7 and MN6, MN8. The PMOS transistor MP1 of the bias circuit is connected by a diode to provide the static operating point voltage VBP1 for the PMOS transistors MP7, MP10 and MP13. The PMOS transistors MP17 and MP18 are a series of PMOS transistors with a diode connection plus the drain and source connected. MP17 provides the required gate-source voltage difference VGS, and MP18 generates the required overdrive voltage Vsat to provide the static operating point voltage VBP2 for the PMOS transistors MP2, MP5, MP9, MP12, MP15, MP20, MP22, MP24, MP26, MP28, MP30, MP32 and MP34. The PMOS transistors MP19 and MP21 are connected by a diode connection to provide the static operating point voltage VBP1ˋ for the PMOS transistor MP23. The PMOS transistor MP25 is connected by a diode connection to provide the static operating point voltage VBP1ˋˋ for the PMOS transistors MP27, MP29, MP31 and MP33.

3. The bias current circuit with a calibration function applied to a sigma delta ADC according to claim 2, wherein The current calibration circuit includes six inverters INV1, INV2, INV3, INV4, INV5, INV6 and four current calibration branches IMP3, IMP7, IMP10, IMP13. Among them, the IMP3 current calibration branch consists of PMOS transistors MP3, MP4 and MP5; the IMP7 current calibration branch consists of PMOS transistors MP7, MP8 and MP9; the IMP10 current calibration branch consists of PMOS transistors MP10, MP11 and MP12; the IMP13 current calibration branch consists of PMOS transistors MP13, MP14 and MP15. The current calibration circuit is controlled by a five-bit register TRIM<4:0> to control the magnitude of the calibration current. Among them, the upper four bits TRIM<4:1> are used to calibrate the output current value, and the lowest bit TRIM<0> is used as a flag bit. When TRIM<4:0> = 0, that is, TRIM1 = TRIM2 = TRIM3 = TRIM4 = 1, the four current calibration branches IMP3, IMP7, IMP10, IMP13 are all turned off. At this time, the bias current calibration circuit does not work, that is, it does not have the calibration function. When TRIM<0> = 0, that is, the PMOS transistor MP6 is in the conducting state and the PMOS transistor MP16 is in the off state. Therefore, the current of the IMP6 current branch flows into the IMP24 current branch at this time, making the current of the IMP24 current branch increase, that is, the current of the IMN11 current branch increases, making the current of the IMN14 current branch mirror and copy the current of the IMN11 branch also increase. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches mirror and copy the current of the IMP25 branch also increase, so that the output current is calibrated in the larger direction. When TRIM<0> = 1, that is, the PMOS transistor MP6 is in the off state and the PMOS transistor MP16 is in the conducting state. Therefore, the current of the IMP16 current branch flows into the IMP20 current branch at this time. Also, because the current of the IMN7 current branch mirrors and copies the externally input reference current source I_IN, the current of the IMN7 current branch remains unchanged. Therefore, the current of the IMP19 current branch will decrease, so that the gate voltages of the PMOS transistors MP19, MP21 and MP23 increase. Therefore, the current of the IMP23 current branch decreases, that is, the current of the IMN11 current branch decreases, making the current of the IMN14 current branch mirror and copy the current of the IMN11 branch also decrease. Similarly, the currents of the IMP27, IMP29, IMP31 and IMP33 current branches mirror and copy the current of the IMP25 branch also decrease, so that the output current is calibrated in the smaller direction.

4. A bias current circuit with a calibration function applied to a sigma delta ADC according to claim 3, characterized in that, The source negative feedback resistor circuit includes 15 resistors R1 - R15. Among them, resistors R1 - R7 are respectively connected to the sources of NMOS transistors MN2, MN4, MN6, MN8, MN10, MN13, and MN15; resistors R8 - R15 are respectively connected to the sources of PMOS transistors MP19, MP21, MP23, MP25, MP27, MP29, MP31, and MP33. Adding source negative feedback resistors in the bias circuit and the bias current output circuit can reduce the noise gain in the circuit, thereby effectively reducing the noise level of the entire circuit. Specifically, the source negative feedback resistor in the bias circuit can help stabilize the static operating point of the MOS transistor, making the operating state of the circuit more stable; the stable static operating point is used to reduce the drift of the bias voltage in the circuit, reduce the sensitivity of the circuit to temperature and power supply voltage changes, and further reduce the generation of noise; the source negative feedback resistor can reduce the non - linear distortion of the MOS transistor and improve the linearity of the circuit; in circuits such as signal amplifiers, the source negative feedback resistor reduces the difference between the output signal and the input signal, thereby improving the linearity and stability of the circuit. In addition, the addition of the source negative feedback resistor reduces the amplification factor of the circuit and the amplitude of the output signal, so it also reduces the amplification factor of the noise signal; by controlling the gain, the amplitude of the noise signal transmitted to the output end is reduced, thereby reducing the noise level of the entire circuit.

5. A bias current circuit with a calibration function applied to a sigma delta ADC according to claim 4, characterized in that, The current output gear logic control circuit uses four transmission gates TG1, TG2, TG3, and TG4. The conduction and closing of the four transmission gates are controlled by logic P1 and P2, where P1N and P2N are the inverses of logic P1 and P2; the off - state and on - state of the four transmission gates are used to control the output of different current levels; when P1 = P2 = 0, that is, P1N = P2N = 1, the four transmission gates TG1, TG2, TG3, and TG4 are all closed, and at this time, the output bias currents IBAIS1 and IBAIS2 are both 0; when P1 or P2 = 1, that is, P1N or P2N = 0, one of the four transmission gates TG1, TG2, TG3, and TG4 is conducting, and at this time, the output bias current IBAIS1 or IBAIS2 = 50uA; when P1 and P2 = 1, that is, P1N and P2N = 0, all four transmission gates TG1, TG2, TG3, and TG4 are conducting, and at this time, the output bias currents IBAIS1 = IBAIS2 = 100uA.

6. A bias current circuit with a calibration function applied to a sigma delta ADC according to claim 5, characterized in that The bias current output circuit consists of four current branches IMP27, IMP29, IMP31, and IMP33. The current of the IMP25 current branch is accurately replicated through a PMOS cascode current mirror. The output of the bias current is controlled by the current output gear and outputs bias currents IBAIS1 and IBAIS2 respectively. A current calibration circuit is used to improve the accuracy of the output bias currents IBAIS1 and IBAIS2.

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