RS and 64B / 66B coding combined circuit and parallelism degree configuration method

Abstract

The invention provides an RS and 64B / 66B coding combined circuit and a parallelism degree configuration method, and relates to the technical field of parallelism degree configuration of coding combined circuits, and the circuit comprises a 64B / 66B coding module which is used for coding input 64-bit data to generate 66-bit data, and outputting the 66-bit data to a bit width conversion module; the bit width conversion module is used for performing bit width adjustment on 66-bit data to obtain w-bit data and outputting the w-bit data to the configurable RS parallel coding module, and w is the bit width of an RS code symbol; the RS coding parallel generator polynomial coefficient calculation module is used for outputting a parallel coefficient to the configurable RS parallel coding module according to configuration information, and the configurable RS parallel coding module is used for completing configuration and coding based on w-bit data and the parallel coefficient and outputting a coding result to the output cache module; and the output cache module realizes the output of the data and the verification data. The joint coding circuit has the advantages of being high in resource efficiency and excellent in performance.

Description

Technical Field

[0001] The present invention relates to the technical field of parallelism configuration of coding combined circuits, and more specifically, to an RS and 64B / 66B coding combined circuit and a parallelism configuration method. Background Art

[0002] With the rapid development of digital information transmission technology, high-speed data transmission has occupied a crucial position in modern communication systems. In order to ensure the integrity and reliability of data during high-speed transmission, coding technologies have been widely applied. Among them, Reed-Solomon (RS) coding and 64B / 66B coding are two widely used coding methods.

[0003] When 64B / 66B coding is used alone, its error correction ability is weak, and bit deflection may occur during transmission, resulting in decoding errors and making it difficult to meet the reliability requirements of complex communication environments. In order to balance efficient data transmission and high reliability, combining RS coding with 64B / 66B coding has become an optimized solution. 64B / 66B coding provides efficient data frame synchronization, and RS coding corrects error codes. The combination of the two forms a coding solution that takes into account both transmission efficiency and data integrity. However, this combination usually has a high occupancy rate, high power consumption, and it is difficult to ensure real-time performance.

[0004] Therefore, designing a combined coding circuit with high resource efficiency and excellent performance has become a difficult problem in current research. Summary of the Invention

[0005] The purpose of the present invention is to provide an RS and 64B / 66B coding combined circuit and a parallelism configuration method, which can achieve a combined coding circuit with high resource efficiency and excellent performance.

[0006] The present invention is realized through the following technical solutions:

[0007] An RS and 64B / 66B coding combined circuit includes a 64B / 66B coding module, an RS coding parallel generation polynomial coefficient calculation module, a bit width conversion module, a configurable RS parallel coding module, a control module, and an output buffer module;

[0008] The 64B / 66B coding module is used to encode the input 64-bit data to generate 66-bit data and output the 66-bit data to the bit width conversion module;

[0009] The bit width conversion module is used to adjust the bit width of the 66-bit data to obtain w-bit data and output the w-bit data to the configurable RS parallel coding module, where w is the bit width of the RS code symbol;

[0010] The RS coding parallel generating polynomial coefficient calculation module is used to output parallel coefficients to the configurable RS parallel coding module according to configuration information;

[0011] The configurable RS parallel coding module is used to complete configuration and coding based on the w-bit data and the parallel coefficients, and output the coding result to the output buffer module;

[0012] The output buffer module realizes the output of data and check data

[0013] The control module is used to control and adjust the operation of each module.

[0014] Preferably, the 64B / 66B coding module includes a first counter module, a coding module, and a splicing module;

[0015] The method for encoding the input data to generate 66-bit data is as follows:

[0016] For each 64-bit data input encoded by the 64B / 66B coding module, the first counter performs counting. According to different counting states, the coding module encodes two different synchronization headers for the input 64-bit data;

[0017] The synchronization header and the input 64-bit data are spliced through the splicing module;

[0018] When the count reaches , the control module generates a control signal to control the 64B / 66B coding module to encode the synchronization header 11 for the next 64-bit data and end the current coding, where k is the number of information symbols of the RS code.

[0019] Preferably, the method for performing bit width adjustment to obtain w-bit data is as follows:

[0020] Fill bit 0 in the output module, then receive the 66-bit data output by the 64B / 66B coding module and convert it into w-bit data;

[0021] The output order is: first output the filled bits, and then output the w-bit data, where [.] means rounding, and k is the number of information symbols of the RS code;

[0022] The counter inside the bit width conversion module counts the converted w-bit data. After counting reaches p, p w-bit data to be encoded and m - p invalid data are output in parallel to the configurable RS parallel coding module, and a valid signal for this coding is sent, and then the counter is cleared, where p is the variable parallelism and m is the maximum parallelism.

[0023] Preferably, the configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iteration module, and a parity generation module;

[0024] The data transposition module is configured to receive the m w-bit data to be encoded and the control information output by the control module, perform a transposition operation on the m w-bit data, and output m groups of data, where m is the maximum parallelism;

[0025] The parallel encoding module is configured to perform a parallel encoding operation on the input data from the data transposition module to obtain first encoded data of (n - k)×w bits, and input it to the parity generation module, where n is the RS code length and k is the number of RS code information symbols;

[0026] The parity generation module is configured to directly store the first encoded data in the register module according to the control information of the control module, or perform a finite field addition with the second encoded data output by the iteration module and then input it into the register module;

[0027] The iteration module is configured to receive the (n - k)×w-bit data in the register module and the control information of the control module, generate second encoded data of (n - k)×w bits, and input it to the parity generation module.

[0028] Preferably, the iteration module includes a data shift module and m groups of calculation modules, and the calculation module includes (n - k) first finite field multipliers and one first finite field adder;

[0029] The data shift module performs a shift operation on the (n - k) w-bit data input by the parallel encoding module according to the variable parallelism p, the last group flag bit last_vld input by the control module, and the number a of valid w-bit data in the last group, and outputs a total of (n - k + m) w-bit data;

[0030] Assume that the (n - k + m) data output by the data shift module are respectively symbols shift_out_0, shift_out_1,..., shift_out_n-k+m-1,

[0031] For the calculation module, the (n - k) first finite field multipliers of the i-th group of calculation modules multiply the (n - k + i)-th symbol shift_in_n-k-z+i-1 by G(i - 1) to generate (n - k)×w-bit data and input it to the first finite field adder;

[0032] The operation results of the first finite field multipliers of the remaining m - k groups of calculation modules are invalid;

[0033] where z is the shift parallelism. When last_vld = 0, the shift parallelism z = p; when last_vld = 1, the shift parallelism z = a;

[0034] The first finite field addition module performs a masking operation on the m groups of (n - k)×w-bit data input by the finite field multiplier according to the variable parallelism p and the last_vld signal generated by the control module. The masked data will not undergo any operation, while other data is added to the data shift_out to obtain (n - k)×w-bit second encoded data, which is input to the parity generation module;

[0035] The shift_out data includes:

[0036] shift_out_0, shift_out_1, …, shift_out_n-k-1, which are (n - k)×w-bit data.

[0037] Preferably, the parity generation module includes a register module and a selection module;

[0038] The parity generation module is used to judge the first_vld. If first_vld = 1 is valid, the first encoded data output by the parallel encoding module will be stored in the register module; otherwise, the first encoded data will be added in the finite field with the second encoded data output by the iterative module and then stored in the register module.

[0039] Preferably, the working method of the RS code parallel generation polynomial coefficient calculation module is as follows:

[0040] Based on the required RS code parallelism p and the shift register constructed with the coefficients of the RS code generation polynomial g(x), calculate the required parallel generation coefficients;

[0041] The shift register is a linear feedback shift register, including registers R0 to R with a width of w bits n-k-1 , the number of registers is n - k, and the feedback coefficients are the values of the registers. The feedback coefficients are multiplied by the multipliers g0 to g of n - k finite field multipliers respectively. Here, n is the RS code length, and k is the number of RS code information symbols; n-k-1 The steps for the linear feedback shift register to generate parallel polynomial coefficients are as follows:

[0042] After the system completes initialization and receives the valid enable signal for generating coefficients, R0 to R

[0043] are initialized to the coefficients g0 to g of the generation polynomial g(x) n-k-1 ; n-k-1 ;

[0044] Perform linear feedback shift calculations. The number of shift calculations is set to the p-depth value. In each calculation, registers R0 to R n-k-1 will output corresponding values. When the p-depth polynomial coefficient calculation is completed, registers R0 to R n-k-1 will output a total of p groups of polynomial coefficients. Each group of polynomial coefficients corresponds to the actual values of the parallel polynomial coefficients at depths from 0 to p; p is the variable parallelism;

[0045] After p shift calculations are completed, output p groups of generated polynomial coefficients to the configurable parallel RS coding module.

[0046] Preferably, there are (n - k) second finite field multipliers and (n - k - 1) second finite field adders in the RS coding parallel generated polynomial coefficient calculation module;

[0047] The second finite field multiplier is used to perform finite field multiplication calculations on the feedback value of the register and the polynomial coefficient;

[0048] The second finite field adder is used to perform finite field addition calculations on the output value of the finite field multiplier and the output value of the upper-level register.

[0049] The present invention also provides a parallelism configuration method, which is applied to the above RS and 64B / 66B coding combined circuit, and includes the following steps:

[0050] Input configuration information. The control module configures the variable parallelism p and calculates the number a of the last group of valid w-bit data;

[0051] Generate polynomials g0 to g n-k-1 , and input them into the RS coding parallel generated polynomial coefficient calculation module. The generated polynomial counter is reset to gen_counter = 0;

[0052] When the generation of polynomials is completed, the parallel coefficient generation enable signal becomes valid. The RS coding parallel generated polynomial coefficient calculation module starts to operate, and gen_counter starts to increment. When the RS coding parallel generated polynomial coefficient calculation module receives the parallel coefficient generation enable signal, it starts to calculate the parallel coefficients and outputs 1 parallel coefficient per clock cycle. When gen_counter = p, the parallel coefficient generation enable signal becomes invalid, gen_counter is cleared, and p is the variable parallelism;

[0053] The input 64-bit data passes through the 64B / 66B coding module, is registered and outputs 66-bit data;

[0054] The 66-bit data enters the bit-width conversion module. If there is sufficient data, it is stored and p×w-bit pre-coded data is output, and at the same time, a valid signal trans_vld is generated. Otherwise, no data and valid signal are output;

[0055] The control module receives trans_vld and run_counter starts counting; when trans_vld arrives and run_counter = 0, a first_vld signal is generated and sent to the configurable RS parallel encoding module; when trans_vld arrives, a last_vld signal is generated and sent to the configurable RS parallel encoding module; if a check output valid signal is generated; [.] means rounding down, and k is the number of information symbols of the RS code;

[0056] When trans_vld is valid, the pre-coded data is input to the configurable RS parallel encoding module and the output module;

[0057] The output module receives the pre-coded data from the bit-width module and the check data from the configurable RS parallel encoding module, and under the control of the control module, outputs the data and the check data.

[0058] Preferably, the configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iterative module, and a check generation module. The configuration methods of the configurable RS parallel encoding module and the control module are as follows:

[0059] By inputting configuration information, the variable parallelism p is configured;

[0060] The data transposition module and the parallel encoding module are combined to complete the operation of the first encoded data of p paths of data in each clock cycle;

[0061] The iterative module completes the operation of the second encoded data of p paths of data in each clock cycle;

[0062] The check generation module completes the iterative operation of p paths of data in each clock cycle;

[0063] If k is divisible by p, after cycles, the check generation module outputs check data;

[0064] If k is not divisible by p and the number of data in the last group is a, the control module will generate a last_vld signal during the operation of the last group of a paths of data, and complete the parallel operation and iterative operation of a paths of data through the transposition operation of the data transposition module, the masking operation of the first finite field adder and the second finite field adder in the parallel encoding module, and the shifting operation of the data shift module; after During a period, the checksum generation module outputs checksum data.

[0065] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0066] The present invention adopts a combination of RS coding and 64B / 66B coding. The original data is appended with 2-bit prefixes according to relevant control information to form 66-bit coded data, thereby solving the synchronization problem in traditional coding methods;

[0067] The present invention realizes a configurable circuit for the parallelism of RS coding by deriving the iterative coding calculation formula for parallel RS coding, improving the flexibility of data processing;

[0068] The present invention is easy to configure, easy to build and apply, and has strong adaptability, a wide range of application scenarios, high cost performance and popularity. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 It is a schematic circuit diagram of a combined circuit of RS and 64B / 66B coding;

[0070] Figure 2 It is a schematic diagram of the principle of calculating the coefficients of the parallel generation polynomial of RS coding;

[0071] Figure 3 It is the definition relationship between the 66-bit code block indicator bit and the RS coding symbol;

[0072] Figure 4 It is a method for configuring parallelism under the control of a control module;

[0073] Figure 5 It is a schematic diagram of the principle of performing RS parallel coding operation. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0074] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0075] Embodiment 1

[0076] This embodiment provides a combined circuit of RS and 64B / 66B coding. Refer to Figure 1 , which includes a 64B / 66B coding module, an RS coding parallel generation polynomial coefficient calculation module, a bit width conversion module, a configurable RS parallel coding module, a control module and an output buffer module;

[0077] The 64B / 66B encoding module is used to encode the input 64-bit data to generate 66-bit data and output the 66-bit data to the bit width conversion module;

[0078] The bit width conversion module is used to adjust the bit width of the 66-bit data to obtain w-bit data and output the w-bit data to the configurable RS parallel encoding module, where w is the bit width of the RS code symbol;

[0079] The RS encoding parallel generating polynomial coefficient calculation module is used to output parallel coefficients to the configurable RS parallel encoding module according to the configuration information;

[0080] The configurable RS parallel encoding module is used to complete configuration and encoding based on the w-bit data and the parallel coefficients and output the encoding result to the output buffer module;

[0081] The output buffer module realizes the output of data and check data

[0082] The control module is used to control and adjust the operation of each module.

[0083] As a preferred solution, the 64B / 66B encoding module includes a first counter module, an encoding module, and a splicing module;

[0084] The method for encoding the input data to generate 66-bit data is as follows:

[0085] For each encoding of the input 64-bit data by the 64B / 66B encoding module, the first counter performs counting, and according to different counting states, the encoding module encodes two different synchronization headers for the input 64-bit data;

[0086] The synchronization header and the input 64-bit data are spliced by the splicing module;

[0087] When the count reaches k, the control module generates a control signal to control the 64B / 66B encoding module to encode the synchronization header 11 for the next 64-bit data and end the current encoding, where k is the number of information symbols of the RS code.

[0088] Specifically, when encoding, the control module controls the 64B / 66B encoding module to start encoding. When the first 64-bit data is received, the 64B / 66B encoding module encodes the synchronization header 00 for the first 64-bit data, and the subsequent input 64-bit data are sequentially encoded with the synchronization header 01;

[0089] If the 64-bit input data stops before the RS encoding is completed, the 64B / 66B encoding module generates 64-bit all-zero data for padding and encodes a synchronization header 10 for the 64-bit all-zero data;

[0090] In the current clock cycle when the 64B / 66B encoding module finishes encoding a data, an internal counter counts. When the count reaches a certain value, a control signal is immediately generated to encode a synchronization header 11 for the next 64-bit data. After the 64-bit data is encoded, the 64B / 66B encoding module pauses this 64B / 66B encoding.

[0091] On the other hand, the method for performing bit-width adjustment to obtain w-bit data is as follows:

[0092] Pad bit 0 in the output module and then receive the 66-bit data output by the 64B / 66B encoding module and convert it into w-bit data;

[0093] The output order is: first output the padding bits, and then output the w-bit data, where [.] means taking the integer, and k is the number of RS code information symbols;

[0094] The counter inside the bit-width conversion module counts the converted w-bit data. After the count reaches p, p w-bit data to be encoded and m - p invalid data are output in parallel to the configurable RS parallel encoding module, and a valid signal for this encoding is issued. Then the counter is cleared, where p is the variable parallelism and m is the maximum parallelism.

[0095] That is to say, the bit-width conversion module is mainly used to pad multiple bits 0 in the output module according to the actual encoding situation, then receive the 66-bit data output by the 64B / 66B encoding module and convert it into w-bit data, and count the w-bit data through a counter. After the count reaches p, p×w-bit data to be encoded are output in parallel to the configurable RS parallel encoding module, and a valid signal for this encoding is issued, and the counter is cleared.

[0096] In this embodiment, the configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iterative module, and a parity generation module;

[0097] The data transposition module is used to receive m w-bit data to be encoded and the control information output by the control module, perform a transposition operation on the m w-bit data, and output m groups of data, where m is the maximum parallelism;

[0098] The parallel encoding module is used to perform parallel encoding operations on the input data from the data transposition module, obtaining first encoded data of (n - k)×w bits, and inputting it to the parity generation module, where n is the length of the RS code and k is the number of information symbols of the RS code;

[0099] The parity generation module is used to directly store the first encoded data in the register module according to the control information of the control module, or perform a finite field addition with the second encoded data output by the iteration module and then input it into the register module;

[0100] The iteration module is used to receive the (n - k)×w - bit data in the register module and the control information of the control module, generate second encoded data of (n - k)×w bits, and input it to the parity generation module.

[0101] Further, the iteration module includes a data shift module and m groups of calculation modules. The calculation module includes (n - k) first finite field multipliers and one first finite field adder;

[0102] The data shift module performs a shift operation on the (n - k) w - bit data input by the parallel encoding module according to the variable parallelism p, the last group flag bit last_vld input by the control module, and the number a of valid w - bit data in the last group, and outputs a total of (n - k + m) w - bit data;

[0103] Assume that the (n - k + m) data output by the data shift module are respectively symbols shift_out_0, shift_out_1,..., shift_out_n - k + m - 1,

[0104] For the calculation module, the (n - k) first finite field multipliers of the i - th group of calculation modules multiply the (n - k + i) - th symbol shift_in_n - k - z + i - 1 by G(i - 1) to generate (n - k)×w - bit data and input it to the first finite field adder;

[0105] The operation results of the first finite field multipliers of the remaining m - k groups of calculation modules are invalid;

[0106] The z is the shift parallelism. When last_vld = 0, the shift parallelism z = p; when last_vld = 1, the shift parallelism z = a;

[0107] The first finite field adder module performs a masking operation on the m groups of (n - k)×w - bit data input by the finite field multipliers according to the variable parallelism p and the last_vld signal generated by the control module. The masked data will not perform any operations, and the other data and the data shift_out perform an addition operation to obtain (n - k)×w - bit second encoded data and input it to the parity generation module;

[0108] The said shift_out data includes:

[0109] shift_out_0, shift_out_1, …, shift_out_n-k-1, which is (n-k)×w-bit data.

[0110] As a preferred solution, the said checksum generation module includes a register module and a selection module;

[0111] The said checksum generation module is used to judge the first_vld. If first_vld = 1 is valid, the first encoded data output by the parallel encoding module will be stored in the register module. Otherwise, the first encoded data will be added in the finite field with the second encoded data output by the iterative module and then stored in the register module.

[0112] As can be seen from the above solution, in the configurable RS parallel encoding module, the said iterative module includes a data shift module and m groups of calculation modules. The calculation module includes (n-k) first finite field multipliers and a first finite field adder. Its specific working mode is as follows:

[0113] First, the m×w-bit data output by the data transposition module is divided into m-way symbols for output;

[0114] The (n-k) first finite field multipliers in the first group multiply the first-way w-bit symbol mout_0 by G(p-1) to generate (n-k)×w-bit data and input it into the first finite field adder; the (n-k) first finite field multipliers in the second group multiply the second-way w-bit symbol mout_1 by G(p-1) to generate (n-k)×w-bit data and input it into the first finite field adder; and so on. The n-k finite field multipliers in the pth group multiply the pth-way w-bit symbol mout_p-1 by G(0) to obtain (n-k)×w-bit data and input it into the finite field adder; the operation results of the remaining m-k groups of first finite field multipliers are invalid;

[0115] Wherein the said G(x) is the coefficient of the parallel generating polynomial of RS coding.

[0116] The first finite field adder module can perform a masking operation on the m groups of (n-k)×w-bit data output by the m groups of (n-k) first finite field multipliers. The masked data will not perform any operation, and other data will perform an addition operation to obtain (n-k)×w-bit first encoded data and input it into the checksum generation module.

[0117] The following is the description of the transposition operation and the masking operation:

[0118] The data transposition module receives p w-bit data inputs from the bit-width conversion module. The p w-bit data are trans_out_0, trans_out_1, …, trans_out_p-1 respectively, where trans_out_0 is the first w-bit data. The outputs of the data transposition module are mout_0, mout_1, …, mout_p-1 respectively, where mout_0 is the first w-bit data. The input data of the first finite field adder are adder_0, adder_1, …, adder_m-1, and the masking values corresponding to each group of data are mask_0, mask_1, …, mask_m-1; when mask_x = 0, the corresponding (x + 1)-th data is masked.

[0119] The total input codewords are 64·U. After passing through the bit-width conversion module, the number of w-bit data outputs is k, and the maximum parallelism of the RS parallel encoding module is m.

[0120] When k is divisible by p, the data input to the configurable RS parallel encoding module by the data cache module is fixed at p w-bit data. x represents the data sequence number. The correspondence table of mout_x, adder_x, and mask_x with trans_out_x is shown in Table 1:

[0121] Table 1

[0122]

[0123]

[0124] Among them, NC represents nocare, that is, the data value is not used or cared about later.

[0125] When k is not divisible by p, the number of valid data in the last group of data input to the configurable RS parallel encoding module will be less than p. Assume that a is the number of valid data in the last group of data input to the configurable RS parallel encoding module. At this time, the correspondence table of mout_x, adder_x, and mask_x with trans_out_x is shown in Table 2:

[0126] Table 2

[0127]

[0128]

[0129] The verification generation module determines the input first_vld of the control module. If first_vld is valid (first_vld = 1), the first encoded data output by the parallel encoding module will be stored in the register module. Otherwise, the first encoded data will be input to the register module after performing a finite field addition with the second encoded data output by the iterative module. The iterative module receives (n - k) w-bit data output by the register module in the verification generation module, the last group flag bit last_vld input by the control module, and the number of valid w-bit data a in the last group; the (n - k) w-bit data received by the iterative module in each clock cycle, after operations by the data shift module, the second finite field multiplier, and the second finite field adder, generates (n - k) w-bit second encoded data and outputs it to the verification generation module. The data shift module performs a shift operation on the (n - k) w-bit data input by the parallel encoding module according to the shift parallelism z and the last group flag bit last_vld input by the control module, and outputs a total of (n - k + m) w-bit data.

[0130] When last_vld = 0, the shift parallelism z = p; when last_vld = 1, the shift parallelism z = a;

[0131] The (n - k) w-bit data input by the parallel encoding module are respectively shift_in_0, shift_in_1,..., shift_in_n - k - 1, and the (n - k) w-bit data output by the data shift module are respectively shift_out_0, shift_out_1,..., shift_out_n - k - 1; the relationship between the data shift_out_x output by the data shift module and shift_in_x in each clock cycle is shown in Table 3:

[0132] Table 3

[0133]

[0134]

[0135] Then, as in the previous steps, m·(n - k) first finite field multipliers multiply the (n - k)th to (n - k + m - 1)th data output by the data shift module with G(0) to G(p - 1) to obtain m groups of (n - k) w-bit data, which are input to the first finite field adder. The first finite field addition module, according to the variable parallelism p and the last group flag bit last_vld input by the control module, performs a masking operation on the m groups of (n - k)×w-bit data input to this module by the m groups of (n - k) finite field multipliers. The masked data will not perform any operations, and the other data and the data shift_out perform a finite field addition operation to obtain (n - k)×w-bit second encoded data, which are input to the verification generation module;

[0136] When last_vld = 0, the shift parallelism z = p; when last_vld = 1, the shift parallelism z = a.

[0137] In the parity generation module, the (n - k)×w-bit data output by the register module are respectively reg_out_0, reg_out_1, …, reg_out_p-1, where reg_out_0 is the first w-bit data; the outputs of the data shift module are respectively shift_out_0, shift_out_1, …, shift_out_p-1, where shift_out_0 is the first w-bit data; the input data of the second finite field adder are adder2_0, adder2_1, …, adder2_m-1, and the corresponding masking values for each group of data are mask2_0, mask2_1, …, mask2_m-1; when mask2_x = 0, the corresponding (x + 1)-th data is masked. Table 4 shows the correspondence between shift_out_x, adder2_x, mask2_x and reg_out_x

[0138] Table 4

[0139]

[0140] Briefly speaking, the configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iteration module and a parity generation module. The configuration methods for the configurable RS parallel encoding module and the control module are as follows:

[0141] By inputting configuration information, configure the variable parallelism p;

[0142] The data transposition module and the parallel encoding module are combined to complete the operation of the first encoded data for p paths of data in each clock cycle;

[0143] The iteration module completes the operation of the second encoded data for p paths of data in each clock cycle;

[0144] The parity generation module completes the iterative operation for p paths of data in each clock cycle;

[0145] If k is divisible by p, after cycles, the parity generation module outputs parity data;

[0146] If k cannot be divided evenly by p and the number of data in the last group is a, the control module will generate a last_vld signal during the operation of the last group of a-channel data. Through the transposition operation of the data transposition module, the masking operations of the first finite field adder and the second finite field adder, and the shifting operation of the data shifting module, the parallel operation and iterative operation of a-channel data are completed; after a period, the checksum generation module outputs checksum data.

[0147] As a further preferred solution, the working method of the RS code parallel generation polynomial coefficient calculation module is as follows:

[0148] According to the required RS code parallelism p and the shift register constructed with the coefficients of the RS code generation polynomial g(x), calculate the required parallel generation parallel coefficients;

[0149] The shift register is a linear feedback shift register, including registers R0 to R with a width of w n-k-1 , the number of registers is n - k, the feedback coefficient is the value of the register, and the feedback coefficients are multiplied by the multipliers g0 to g of n - k finite field multipliers respectively n-k-1 ; n is the RS code length, and k is the number of RS code information symbols;

[0150] The steps for the linear feedback shift register to generate parallel polynomial coefficients are as follows:

[0151] After the system completes initialization and receives the generation coefficient valid enable signal, R0 to R n-k-1 are initialized to the coefficients g0 to g of the generation polynomial g(x) n-k-1 ;

[0152] Perform linear feedback shift calculations. The number of shift calculations is the set p depth value. Each time the calculation is performed, registers R0 to R n-k-1 will output corresponding values. When the p-depth polynomial coefficient calculation is completed, registers R0 to R n-k-1 will output a total of p groups of polynomial coefficients. Each group of polynomial coefficients corresponds to the actual values of the parallel polynomial coefficients at depths 0 to p; p is the variable parallelism;

[0153] After p shift calculations are completed, output p groups of generation polynomial coefficients to the configurable parallel RS coding module.

[0154] Furthermore, there are (n - k) second finite field multipliers and (n - k - 1) second finite field adders in the RS code parallel generation polynomial coefficient calculation module;

[0155] The second finite field multiplier is used to perform finite field multiplication calculations on the feedback value of the register and the polynomial coefficient;

[0156] The second finite field adder is used to perform finite field addition calculation on the output value of the finite field multiplier and the output value of the previous-level register.

[0157] Embodiment 2

[0158] Based on the solution of Embodiment 1, as a specific case, refer to Figure 2 , in this embodiment, the calculation of the RS coding parallel generation polynomial coefficients is completed by a linear feedback shift register. A 30-stage linear feedback shift register is used in this embodiment to calculate the generation polynomial coefficients. After the initialization of the shift register is completed, registers R0 to R 29 are initialized to g0 to g 29 , and then linear feedback shift calculation is performed according to the set parallelism p. During the shift calculation, the value of R 29 is used as the feedback value and enters 30 finite field multipliers respectively for multiplication operations. The result value is subjected to finite field addition calculation with the output value of the previous-level register, and the result is output to the current position register; each time the shift calculation updates the values of registers R0 to R 29 and outputs them. The 30 values output in each group are the coefficients of the parallel generation polynomial at the current depth (0 to p).

[0159] The mathematical derivation process of the generation polynomial coefficients with parallelism p is as follows:

[0160] For the coefficient matrix of the initial generation polynomial linear feedback shift register, it can be represented by K as:

[0161]

[0162] When the parallelism is 0, let G(p) be the expression of the generation polynomial coefficients at depth p, that is, G(0) is:

[0163]

[0164] When the parallelism is 1, that is, a multiplication operation needs to be performed on the coefficient matrix of the initial generation polynomial linear feedback shift register to represent a linear feedback shift process, that is, G(1) is:

[0165]

[0166] Similarly, when the parallelism is 2, that is, G(2) is:

[0167]

[0168] It can be deduced therefrom that when the parallelism is p, the expression of the generation polynomial coefficients G(p) at depth p is:

[0169]

[0170] That is:

[0171] G(0) = G

[0172] G(1) = K × G

[0173] G(2) = K × (K × G) = K 2 × G

[0174] ……

[0175] G(p) = K p × G

[0176] In a 30 - stage linear feedback shift register, the values of G(0) to G(p) corresponding to R0 to R 29 are shown in Table 5 as follows:

[0177] Table 5

[0178]

[0179] Therefore, G(p) = K p × G is the coefficient expression of the generating polynomial at the p - depth.

[0180] The calculation steps of the RS - coding parallel generating polynomial coefficient calculation module are as follows:

[0181] Step 1: By configuring the input initial polynomial and other configuration parameters, construct the n - k - stage linear feedback shift registers R0 to R n-k-1 , with the register width being w and the coefficients of the finite - field multipliers being g0 to g n-k-1 , and the result is as Figure 2 shown; go to Step 2;

[0182] Step 2: Initialize the linear feedback shift register, and the values of registers R0 to R n-k-1 are initialized to g0 to g n-k-1 , and the updated R0 to R n-k-1 at this time are obtained to get G(0); and perform linear feedback shift calculation according to whether the start - calculation enable is received; go to Step 3;

[0183] Step 3: Start the linear feedback shift calculation. The values of the registers R n-k-1 are used as feedback values and are respectively multiplied with the finite - field multipliers to obtain the multiplication result values O0 ~ O n-k-1 . O0 is directly shifted into R0, and O1 ~ O n-k-1 correspond to the output values of R0 to R n-k-2 respectively for finite - field addition, and the result value updates the registers R1 to R n-k-1; and output the updated R0 to R n-k-1 to obtain G(1); go to step 4;

[0184] Step 4: Register R n-k-1 is used as the feedback value again for the calculation operation in step 3 until the shift calculation operation ends after p times of shift calculations, otherwise keep step 4;

[0185] Figure 3 defines the relationship between the 66-bit code block indicator bit and the RS coding symbol. When the 64B / 66B coding module performs 64B / 66B coding operations, the 64B / 66B coding module first receives the start enable signal; after the coding starts, it waits to receive the first 64-bit data, encodes the synchronization header 00 for this data, and at the same time the control module receives the start coding information sent by the 64B / 66B coding module and starts counting; the subsequent 64-bit inputs are its synchronization headers 01 in turn. If the RS coding is not completed and the 64-bit input data stops, then at this time the 64B / 66B coding module will generate 64-bit all-zero data for filling and encode its synchronization header 10; each time the 64B / 66B coding module encodes a data, the control module will count. When the count reaches immediately generate the relevant signal, encode the synchronization header 11 of this 64-bit data. After the encoding is completed, pause this encoding and wait for the control module to start encoding again or end the encoding.

[0186] The following is the RS parallel coding mathematical principle based on this embodiment:

[0187]

[0188] Among them, the first formula represents the mathematical principle based on which the RS coding calculation is performed. Among them, g0 to g n-k-1 represents the coefficients of the generating polynomial of this RS coding, represents the state variable in each coding calculation, and c(n) represents the input data at time n. Denote the matrix composed of the coefficients of the generating polynomial of RS coding as G(0), and denote the square matrix composed of the coefficients of the generating polynomial of RS coding and constants as K. Then the first formula in the figure can be simplified to the second formula.

[0189] The third formula is the coding calculation formula of the multiple parallel RS coding calculation algorithm.

[0190] The following is the mathematical principle of the iteration module of this embodiment:

[0191]

[0192]

[0193]

[0194] Where G(1) is K 2 The last column vector of the square matrix, G(2) is K 3 The last column vector of the square matrix, G(p-1) is K p The last column vector of the square matrix, K y(n), K 2 y(n), K 3 Expand y(n) and derive K p The coding calculation formula of y(n).

[0195] like Figure 5 As shown, the RS parallel encoding module of the present invention can be configured to perform RS parallel encoding operations according to the following steps:

[0196] Step 1: Determine the variable parallelism p according to the configuration;

[0197] Step 2: Receive G(0)~G(p-1) generated by the RS coding parallel generator polynomial coefficient calculation module, and fix the multiplier G of the finite field multiplier in the parallel coding module and the iteration module. One multiplier is fixed in each clock cycle, and all multipliers are fixed in p cycles.

[0198] Step 3, 64B / 66B module, encodes the input 64B data into 66B data, stores and outputs it;

[0199] Step 4: The bit width conversion module converts the 66B data into p×w bit symbols, stores them and outputs a valid signal trans_vld;

[0200] Step 5, the trans_vld signal is 1, and the RS parallel encoding module can be configured to receive the p×w bit symbols output by the bit width conversion module and perform p-way parallel encoding; the data transposition module performs a transposition operation on the p×w bit symbol data according to the variable parallelism p and the last group of flag bits last_vld of the control signal of the control module and the number a of the last group of valid w-bit data, and outputs a total of m×w bit data, of which the last mk groups of data are invalid;

[0201] The m×w-bit data output by the data transposition module is divided into m channels of data output. In the parallel encoding module, the first (n-k) first finite field multipliers in the first group multiply the first w-bit symbol mout_0 of the first channel by G(p-1) to generate (n-k)×w-bit data, which is input to the finite field adder. The second (n-k) first finite field multipliers in the second group multiply the second w-bit symbol mout_1 of the second channel by G(p-1) to generate (n-k)×w-bit data, which is input to the finite field adder. And so on. The n-k finite field multipliers in the p-th group multiply the p-th w-bit symbol mout_p-1 of the p-th channel by G(0) to obtain (n-k)×w-bit data, which is input to the finite field adder. The operation results of the remaining m-k groups of first finite field multipliers are invalid. The finite field addition module performs an addition operation on the first p groups of (n-k)×w-bit data input to this module by the m groups of (n-k) finite field multipliers to obtain (n-k)×w-bit first encoded data, which is input to the parity check generation module;

[0202] The parity check generation module judges the flag bit first_vld input by the control module. If first_vld = 1, the first encoded data is directly stored in the register. Otherwise, the first encoded data is stored in the register after performing a finite field addition operation with the output data of the iteration module;

[0203] Step 6: The data shift module in the iteration module performs a data shift operation on the (n-k)×w-bit parity check intermediate value output by the register of the parity check generation module according to the last group of flag bits last_vld and the number a of valid w-bit data in the last group output by the control module. The m groups of (n-k) second finite field multipliers perform finite field multiplication on the (n-k+m)×w-bit data output by the data shift module;

[0204] The (n-k+m)×w-bit data output by the data shift module is divided into n-k+m channels of data output. The first to n-k-th w-bit data are concatenated to form (n-k)×w-bit data shift_out. The first group of n-k second finite field multipliers multiply the (n-k+1)-th w-bit data shift_out_n-k of the n-k+1-th channel by G(0) to generate (n-k)×w-bit data, which is input to the second finite field adder. The second group of n-k second finite field multipliers multiply the (n-k+2)-th w-bit data shift_out_n-k+1 of the n-k+2-th channel by G(1) to generate (n-k)×w-bit data, which is input to the second finite field adder. And so on. The p-th group of n-k second finite field multipliers multiply the (n-k+p)-th w-bit data shift_out_n-k+p-1 of the n-k+p-th channel by G(p-1) to generate (n-k)×w-bit data, which is input to the second finite field adder. The remaining m-k groups of second finite field multipliers multiply with the remaining m-k channels of w-bit data, and the operation results do not participate in the subsequent operations;

[0205] The second finite field adder module performs an addition operation on the 1st to p groups of (n-k)×w-bit data output by m groups of (n-k) first finite field multiplier, and the (n-k)×w-bit shift_out data output by the data shift module, to obtain (n-k)×w-bit second encoded data, which is input to the parity generation module;

[0206] The parity generation module judges the flag bit first_vld input by the control module. If first_vld = 1, the second encoded data is not processed. Otherwise, the second encoded data is subjected to a finite field addition operation with the first encoded data and then stored in a register;

[0207] Step 7, every time the data transposition module outputs a valid signal trans_vld, the counter run_counter of the control module will count and generate a control signal. When run_counter = 1, first_vld is generated; when run_counter = k, the last_vld signal is generated. In the next clock cycle, the counter resets run_counter = 0 and generates a parity output valid signal to the output buffer module;

[0208] Step 8, when the parity output valid signal is 1, the output buffer module receives the n-k×w-bit parity data in the register of the parity generation module, and at this time the RS parallel encoding is completed.

[0209] Step 9, under the control of the control module, the output buffer module outputs the data and the parity data.

[0210] In a specific application, this example is based on the 64B / 66B encoding format as Figure 3 shown, uses the RS(384, 354) code group, the finite field is (2 9 ), the RS encoding primitive polynomial is p(x) = x 9 +x 4 +1, and the generating polynomial is taken as:

[0211]

[0212] a i is an element in the finite field (2 9 ), and the initial generating polynomial coefficients (g0 to g 29 ) are obtained through matlab calculation as shown in Table 6, and are successively:

[0213] Table 6

[0214] g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 344 486 179 54 332 510 434 302 414 389 490 190 113 463 328 g15 g16 g17 g18 g19 g20 g21 g22 g23 g24 g25 g26 g27 g28 g29 138 362 37 122 93 157 154 503 454 100 414 382 472 296 202

[0215] The maximum parallelism p of the parallel RS encoding of this circuit is set to 8.

[0216] For the addition operation in a finite field, the addition is an exclusive OR operation. Take any two elements I and J in GF(2 9 )

[0217] I = I8a 8 + I7a 7 + I6a 6 + I5a 5 + I4a 4 + I3a 3 + I2a 2 + I1a 1 + I0

[0218] J = J8a 8 + J7a 7 + J6a 6 + J5a 5 + J4a 4 + Ja 3 + J2a 2 + J1a 1 + J0

[0219] I + J = (I8 + J8)a 8 +(I7 + J7)a 7 +……+(I1 + J1)a 1 + I0 + J0

[0220] For the multiplication operation in a finite field, take any two elements I and J in GF(2 9 )

[0221] I = I8a 8 + I7a 7 + I6a 6 + I5a 5 + I4a 4 + I3a 3 + I2a 2 + I1a 1 + I0

[0222] J = J8a 8 + J7a 7 + J6a 6 + J5a 5 + J4a 4 + Ja 3 + J2a 2 + J1a 1 + J0

[0223]

[0224] The external input RS encoding generation polynomial coefficients are sent to the RS encoding parallel generation polynomial coefficient calculation module. The generation polynomial coefficients are calculated through a linear feedback shift register. First, registers R0 to R 29 are initialized to g0 to g 29 , and then the values of R 29 are used as feedback values and enter 30 finite field multipliers respectively for multiplication operations. The result values are subjected to finite field addition calculations with the output values of the upper-level registers, and the results are output to the position registers at the next level of the multipliers; each shift calculation updates the values of registers R0 to R 29 and outputs them. For each group of 30 output values, 8 shift calculations are performed in total, and the parallel generation polynomial coefficients of groups G(0) to G(8) are output to the configuration RS parallel encoding module.

[0225] The 64B / 66B encoding module will receive the start enable signal sent by the control module; after the encoding is started, it waits to receive the first 64-bit data and encodes the synchronization header 00 for this data. At the same time, the control module receives the start encoding information sent by the 64B / 66B encoding module and starts counting; the subsequent input 64-bit data is sequentially encoded with the synchronization header 01. If the RS encoding is not completed and the 64-bit input data stops, then at this time, the 64B / 66B encoding module will generate 64-bit all-zero data for filling and encode the synchronization header 10 for it; each time the 64B / 66B encoding module encodes a data, the control module will count. When the count reaches 47, relevant signals are immediately generated to encode the synchronization header 11 of the next 64-bit data, that is, the 48th 64-bit data. After the encoding is completed, this encoding is paused and it waits for the control module to start encoding again or end the encoding.

[0226] The 66-bit data is converted into 8×9-bit data in the bit width conversion module and is output in parallel to the configurable RS parallel encoding module for encoding;

[0227] In the configurable RS parallel encoding module, the parallel encoding module performs parallel encoding operations on the 8×9-bit data output by the bit width conversion module and outputs the first encoded data of 30x9 bits to the parity generation module every clock cycle; the iteration module receives the 30x9-bit data output by the parity generation module and outputs the second encoded data of 30x9 bits to the parity generation module every clock cycle; the parity generation module directly stores the first encoded data in the register module, or stores the first encoded data and the second encoded data in the register module after performing finite field addition operations; in the first 44 effective cycles, 8-way parallel encoding is performed, and 2-way parallel encoding is performed in the 45th effective cycle; after the 45th effective cycle, the parity data generation of the RS encoding of 48 64-bit data is completed and stored in the output buffer module. Finally, the output buffer module is controlled by the control module for output.

[0228] Embodiment 3

[0229] This embodiment provides a parallelism configuration method, which is applied to the above RS and 64B / 66B encoding combined circuit. Refer to Figure 4 , and includes the following steps:

[0230] Step 1: Input configuration information. The control module configures the variable parallelism p and calculates the number a of the last group of valid w-bit data;

[0231] Step 2: Generate polynomials g0 to g n-k-1 , and input them into the RS encoding parallel generation polynomial coefficient calculation module, and generate a polynomial counter reset gen_counter = 0;

[0232] When the generation of polynomials is completed, the parallel coefficient generation enable signal becomes valid. The RS encoding parallel generation polynomial coefficient calculation module starts to operate, and gen_counter starts to increment; when the RS encoding parallel generation polynomial coefficient calculation module receives the parallel coefficient generation enable signal, it starts to calculate the parallel coefficients and outputs 1 parallel coefficient per clock cycle; when gen_counter = p, the parallel coefficient generation enable signal becomes invalid, gen_counter is cleared, and p is the variable parallelism;

[0233] Step 4: The input 64-bit data passes through the 64B / 66B encoding module, is registered and outputs 66-bit data;

[0234] The 66-bit data enters the bit width conversion module. If the data is sufficient, it is registered and outputs p×w-bit pre-encoded data, and at the same time generates a valid signal trans_vld. Otherwise, no data and valid signal will be output;

[0235] The control module receives trans_vld, and run_counter starts to count; if run_counter = 0 when trans_vld arrives, a first_vld signal is generated and sent to the configurable RS parallel encoding module; if run_counter when trans_vld arrives, then a last_vld signal is generated and sent to the configurable RS parallel encoding module; if

[0236] then a check output valid signal is generated; [.] means rounding down, and k is the number of information symbols of the RS code;

[0237] Step 6: The output module receives the precoded data from the bit width module and the parity data from the configurable RS parallel encoding module, and under the control of the control module, outputs the data and the parity data.

[0238] Specifically, the configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iterative module, and a parity generation module. The configuration methods for the configurable RS parallel encoding module and the control module are as follows:

[0239] Through the input of configuration information, configure the variable parallelism p;

[0240] The data transposition module and the parallel encoding module work together to complete the operation of the first encoded data for p paths of data in each clock cycle;

[0241] The iterative module completes the operation of the second encoded data for p paths of data in each clock cycle;

[0242] The parity generation module completes the iterative operation for p paths of data in each clock cycle;

[0243] If k is divisible by p, after cycles, the parity generation module outputs the parity data;

[0244] If k is not divisible by p and the number of data in the last group is a, the control module will generate a last_vld signal during the operation of the last group of a paths of data, and complete the parallel operation and iterative operation of a paths of data through the transposition operation of the data transposition module, the masking operations of the first finite field adder and the second finite field adder in the parallel encoding module, and the shift operation of the data shift module; after cycles, the parity generation module outputs the parity data.

[0245] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An RS and 64B / 66B encoding combined circuit, characterized in that It includes a 64B / 66B encoding module, an RS encoding parallel generating polynomial coefficient calculation module, a bit-width conversion module, a configurable RS parallel encoding module, a control module, and an output buffer module; The 64B / 66B encoding module is used to encode the input 64-bit data to generate 66-bit data, and output the 66-bit data to the bit-width conversion module; The bit-width conversion module is used to adjust the bit-width of the 66-bit data to obtain w-bit data, and output the w-bit data to the configurable RS parallel encoding module, where w is the bit-width of the RS code symbol; The RS encoding parallel generating polynomial coefficient calculation module is used to output parallel coefficients to the configurable RS parallel encoding module according to the configuration information; The configurable RS parallel encoding module is used to complete configuration and encoding based on the w-bit data and the parallel coefficients, and output the encoding result to the output buffer module; The output buffer module realizes the output of data and parity data; The control module is used to control and adjust the operation of each module.

2. The RS and 64B / 66B encoding combined circuit according to claim 1, characterized in that, The 64B / 66B encoding module includes a first counter module, an encoding module, and a splicing module; The method for encoding the input data to generate 66-bit data is as follows: For each encoding of the input 64-bit data by the 64B / 66B encoding module, the first counter performs counting, and according to different counting states, the encoding module encodes two different synchronization headers for the input 64-bit data; The synchronization header and the input 64-bit data are spliced through the splicing module; When the count reaches , the control module generates a control signal to control the 64B / 66B encoding module to encode the synchronization header 11 for the next 64-bit data and end the current encoding, where k is the number of RS code information symbols.

3. The RS and 64B / 66B encoding combined circuit according to claim 1, characterized in that The method for adjusting the bit-width to obtain w-bit data is as follows: Fill in the output module with bit 0, then receive the 66-bit data output by the 64B / 66B encoding module and convert it into w-bit data; The output order is: first output the padding bits, and then output the w-bit data, where [.] means rounding, and k is the number of information symbols of the RS code; The counter inside the bit-width conversion module counts the converted w-bit data. After counting reaches p, p w-bit data to be encoded and m - p invalid data are output in parallel to the configurable RS parallel encoding module, and a valid signal for this encoding is sent, and then the counter is cleared, where p is the variable parallelism and m is the maximum parallelism.

4. The RS and 64B / 66B encoding combined circuit according to claim 1, characterized in that, The configurable RS parallel encoding module includes a data transposition module, a parallel encoding module, an iteration module, and a parity generation module; The data transposition module is used to receive m w-bit data to be encoded and the control information output by the control module, perform a transposition operation on the m w-bit data, and output m groups of data, where m is the maximum parallelism; The parallel encoding module is used to perform parallel encoding operations on the input data from the data transposition module to obtain the first encoded data of (n - k)×w bits, and input it to the parity generation module, where n is the code length of the RS code and k is the number of information symbols of the RS code; The parity generation module is used to directly store the first encoded data in the register module or perform finite field addition with the second encoded data output by the iteration module and then input it into the register module according to the control information of the control module; The iterative module is used to receive the (n-k)×w-bit data in the register module and the control information of the control module, generate (n-k)×w-bit second encoded data, and input it to the parity generation module.

5. The RS and 64B / 66B encoding combined circuit according to claim 4, characterized in that The iterative module includes a data shift module and m groups of calculation modules. The calculation module includes (n-k) first finite field multipliers and a first finite field adder; The data shift module performs a shift operation on the (n-k) w-bit data input by the parallel encoding module according to the variable parallelism p, the last group flag bit last_vld input by the control module, and the number a of valid w-bit data in the last group, and outputs a total of (n-k+m) w-bit data; Assume that the (n-k+m) data output by the data shift module are respectively the symbols shift_out_0, shift_out_1,..., shift_out_n-k+m-1, Execute the following for the calculation module: The (n-k) first finite field multipliers of the i-th group of calculation modules multiply the (n-k+i)-th symbol shift_in_n-k-z+i-1 by G(i-1) to generate (n-k)×w-bit data and input it to the first finite field adder; The operation results of the first finite field multipliers of the remaining m-k groups of calculation modules are invalid; The z is the shift parallelism. When last_vld = 0, the shift parallelism z = p. When last_vld = 1, the shift parallelism z = a; The first finite field adder module performs a masking operation on the m groups of (n-k)×w-bit data input by the finite field multiplier according to the variable parallelism p and the last_vld signal generated by the control module. The masked data will not perform any operation, and the other data and the data shift_out perform an addition operation to obtain (n-k)×w-bit second encoded data and input it to the parity generation module; The shift_out data includes: shift_out_0, shift_out_1,..., shift_out_n-k-1, which are (n-k)×w-bit data.

6. The RS and 64B / 66B encoding combined circuit according to claim 5, characterized in that The parity generation module includes a register module and a selection module; The parity generation module is used to judge the first_vld. If the first_vld = 1 is valid, the first encoded data output by the parallel encoding module will be stored in the register module. Otherwise, the first encoded data will be added in the finite field with the second encoded data output by the iterative module and then stored in the register module.

7. The RS and 64B / 66B encoding combined circuit according to claim 1, wherein The working method of the RS encoding parallel generation polynomial coefficient calculation module is: According to the required RS code parallelism p and the shift register constructed with the coefficients of the RS code generation polynomial g(x), calculate the required parallel generation parallel coefficients; The shift register is a linear feedback shift register, including registers R0 to R with a width of w bits n-k-1 , the number of the registers is n - k, and the feedback coefficient is the value of the register. The feedback coefficients are respectively multiplied by multipliers g0 to g of n - k finite field multipliers n-k-1 . n is the length of the RS code, and k is the number of information symbols of the RS code; The steps for the linear feedback shift register to generate parallel polynomial coefficients are: After the system completes initialization and receives the valid enable signal for generating coefficients, R0 to R n-k-1 are initialized to the coefficients g0 to h of the generating polynomial g(x) n-k-1 ; Perform linear feedback shift calculations. The number of shift calculations is the set p depth value. Each time, registers R0 to R n-k-1 will output corresponding values. When the p-depth polynomial coefficient calculation is completed, registers R0 to R n-k-1 will output a total of p groups of polynomial coefficients. Each group of polynomial coefficients respectively corresponds to the actual values of the parallel polynomial coefficients at depths from 0 to p; p is the variable parallelism; After p shift calculations are completed, p groups of generation polynomial coefficients are output to the configurable parallel RS encoding module.

8. The RS and 64B / 66B encoding combined circuit according to claim 7, characterized in that There are (n - k) second finite field multipliers and (n - k - 1) second finite field adders in the RS coding parallel generating polynomial coefficient calculation module; The second finite field multiplier is used to perform finite field multiplication calculation on the feedback value of the register and the polynomial coefficient; The second finite field adder is used to perform finite field addition calculation on the output value of the finite field multiplier and the output value of the upper-level register.

9. A parallelism configuration method, applied to the RS and 64B / 66B encoding combined circuit according to any one of claims 1-8, characterized in that, It includes the following steps: Input configuration information, the control module configures the variable parallelism p and calculates the number a of valid w-bit data in the last group; Generate polynomials g0 to g n-k-1 , and input them into the RS coding parallel polynomial coefficient calculation module. Set the polynomial counter reset gen_counter = 0; When the polynomial input is completed, the parallel coefficient generation enable signal becomes valid, and the RS coding parallel generating polynomial coefficient calculation module starts to operate, and gen_counter starts to increment; when the RS coding parallel generating polynomial coefficient calculation module receives the parallel coefficient generation enable signal, it starts to calculate the parallel coefficient and outputs 1 parallel coefficient per clock cycle; when gen_counter = p, the parallel coefficient generation enable signal becomes invalid, gen_counter is cleared, and p is the variable parallelism; The input 64-bit data passes through the 64B / 66B coding module, is registered and outputs 66-bit data; The 66-bit data enters the bit width conversion module. If the data is sufficient, it is registered and outputs p×w-bit precoded data, and at the same time generates a valid signal trans_vld. Otherwise, no data and valid signal will be output; The control module receives trans_vld and the run_counter starts counting; when trans_vld arrives, if run_counter = 0, a first_vld signal is generated and sent to the configurable RS parallel encoding module; when trans_vld arrives, a last_vld signal is generated and sent to the configurable RS parallel encoding module; if a check output valid signal is generated; [.] means rounding down, and k is the number of RS code information symbols; When trans_vld is valid, the precoded data is input to the configurable RS parallel coding module and the output module; The output module receives the precoded data from the bit width module and the check data from the configurable RS parallel coding module, and under the control of the control module, realizes the output of the data and the check data.

10. A parallelism configuration method according to claim 9, characterized in that, The configurable RS parallel coding module includes a data transposition module, a parallel coding module, an iterative module and a check generation module. The configuration methods of the configurable RS parallel coding module and the control module are as follows: Configure the variable parallelism p through configuration information input; The data transposition module and the parallel coding module are combined to complete the operation of the first encoded data of p channels per clock cycle; The iterative module completes the operation of the second encoded data of p channels per clock cycle; The check generation module completes the iterative operation of p channels of data per clock cycle; If k is divisible by p, after cycles, the checksum generation module outputs checksum data; If k cannot be divided evenly by p and the number of data in the last group is a, then the control module will generate a last_vld signal during the operation of the last group of a-channel data. Through the transposition operation of the data transposition module, the masking operations of the first finite field adder and the second finite field adder in the parallel encoding module, and the shifting operation of the data shifting module, the parallel operation and iterative operation of a-channel data are completed; after a period, the parity generation module outputs parity data.

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