Chip, chip cascade structure, calibration method, radar device and electronic equipment

Abstract

The invention relates to the technical field of wireless communication, in particular to a chip, a chip cascade structure, a calibration method, a radar device and electronic equipment, and the chip structure comprises a cascade interface circuit which is configured to be controlled to adjust the power of a transmitted cascade synchronization signal in a calibration mode, the power of the cascade synchronization signal is enabled to meet a preset power range; the detection circuit is coupled with the cascade interface circuit and is configured to convert the power of the cascade synchronization signal into a power detection signal and output the power detection signal; and the signal processing circuit is coupled with the detection circuit and is configured to detect the power detection signal so as to determine power amplification parameters of the cascade interface circuit, and is used for input and output matching of chip cascade and reducing the occupied area of the chip on the basis of keeping the signal accuracy.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless communication technologies, and particularly relates to a chip, a chip cascading structure, a calibration method, a radar device, and an electronic device. Background Art

[0002] A sensor is an important device that can help intelligent devices detect the surrounding environment. With the improvement of the intelligence level of various intelligent devices including automotive autopilot systems and industrial equipment, the demand for the detection ability of sensors is getting higher and higher. In some application scenarios, a single-chip sensor is difficult to obtain detection information with a larger range and higher real-time performance. Therefore, sensors using multiple cascaded chips have become the choice of more and more intelligent devices.

[0003] However, for a chip with a cascading function, it cannot cover various circuit scenarios of cascading. Summary of the Invention

[0004] Embodiments of the present disclosure provide a chip, a chip cascading structure, a calibration method, a radar device, and an electronic device for input and output matching of chip cascading and reducing the occupied area of the chip while maintaining signal accuracy.

[0005] An embodiment of the present disclosure provides a chip structure, including: a cascading interface circuit configured to, in a calibration mode, controllably adjust the power of the transmitted cascading synchronization signal so that the power of the cascading synchronization signal satisfies a preset power range; a detection circuit coupled to the cascading interface circuit and configured to convert the power of the cascading synchronization signal into a power detection signal and output it; a signal processing circuit coupled to the detection circuit and configured to detect the power detection signal to determine the power amplifier parameters of the cascading interface circuit.

[0006] In some embodiments, the signal processing circuit is further coupled to the cascading interface circuit and, in a working mode, controls the cascading interface circuit based on the power amplifier parameters to adjust the power of the transmitted cascading synchronization signal.

[0007] In some embodiments, the cascading interface circuit is connected to the cascading input end of the chip structure or the cascading output end of the chip structure.

[0008] In some embodiments, the cascading interface circuit includes an adjustable power amplifier; wherein, the adjustable power amplifier at least includes: a direct-current controlled adjustable power amplifier, or an array of controllable adjustable power amplifiers.

[0009] In some embodiments, the cascading interface circuit includes: a fixed power amplifier connected to the adjustable power amplifier.

[0010] In some embodiments, the detection circuit is coupled to the last-stage output circuit of the cascading interface circuit.

[0011] In some embodiments, the cascaded synchronization signal at least includes one of the following: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

[0012] Another embodiment of the present disclosure provides a chip cascading structure, including: a master chip and slave chips; wherein, at least one of the master chip and each slave chip is the chip structure provided in the above embodiment, and the cascaded output end of the master chip is connected to the cascaded input ends of the master chip and each slave chip.

[0013] In some embodiments, the chip cascading structure further includes: a first signal transmission line configured to connect the cascaded output end of the master chip and the cascaded input end of the master chip; a second signal transmission line configured to connect the cascaded output end of the master chip and the cascaded input end of the slave chip; wherein, the lengths of the first signal transmission line and the second signal transmission line are the same.

[0014] In some embodiments, the master chip adopts the chip structure provided in the above embodiment. In the calibration mode of the chip cascading structure, the signal processing circuit in the master chip is further configured to: receive a first detection signal reflecting the signal power in the cascaded receiving link of the slave chip; and detect the first detection signal based on a preset power range, and accordingly determine the power amplifier parameters of the cascaded interface circuit located in the cascaded transmitting link or the cascaded receiving link of the master chip.

[0015] In some embodiments, the slave chip adopts the chip structure provided in the above embodiment. In the calibration mode of the chip cascading structure, the signal processing circuit in the slave chip is further configured to: receive a second detection signal reflecting the signal power in the cascaded transmitting link of the master chip; and detect the second detection signal based on a preset power range, and accordingly determine the power amplifier parameters of the cascaded interface circuit located in the cascaded receiving link of the slave chip.

[0016] In some embodiments, in the working mode of the chip cascading structure, the signal processing circuit in the chip structure controls the cascaded interface circuit in the chip cascading structure according to the calibrated power amplifier parameters; wherein, the power amplifier parameters are obtained based on the detection in the calibration mode of the chip structure in the chip cascading structure.

[0017] Another embodiment of the present disclosure provides a calibration method applied to a chip cascading structure, including: detecting the power deviation between the signal power of at least one cascaded link of the chip cascading structure and a preset power range; and determining the power parameters of at least one cascaded interface circuit on the cascaded link according to the power deviation, so that the signal power transmitted by the corresponding cascaded interface circuit in the working mode of the chip cascading structure conforms to the preset power range.

[0018] In some embodiments, the cascaded output terminal of the master chip in the chip cascading structure is connected to the cascaded input terminal of the master chip and the cascaded input terminal of the slave chip to form a cascaded link; wherein, the cascaded output terminal of the master chip is connected to the first cascaded interface circuit, the cascaded input terminal of the master chip is connected to the second cascaded interface circuit, and the cascaded input terminal of the slave chip is connected to the third cascaded interface circuit; the steps of detecting the power deviation between the signal power of at least one cascaded link of the chip cascading structure and the preset power range include: obtaining a power detection signal from at least one of the first cascaded interface circuit, the second cascaded interface circuit, and the third cascaded interface circuit; wherein, the power detection signal represents the signal power to be detected; detecting the power detection signal according to the preset power range to obtain the power deviation.

[0019] In some embodiments, the steps of determining the power parameters of at least one cascaded interface circuit on the cascaded link according to the power deviation include: converting the power deviation into power parameters; or judging whether the power deviation obtained in each iteration conforms to the preset power range according to the preset step unit multiple times until the power detection signal that conforms to the preset power range is determined, so as to cumulatively obtain the power parameters.

[0020] Another embodiment of the present disclosure provides a radar device, which includes the chip structure provided in the above embodiment or the chip cascading structure provided in the above embodiment.

[0021] Another embodiment of the present disclosure provides an electronic device, which at least includes the radar device provided in the above embodiment. Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of the chip structure provided by an embodiment of the present disclosure;

[0024] Figure 2 It is a schematic structural diagram of the cascaded interface circuit connecting the cascaded input terminal of the chip structure provided by an embodiment of the present disclosure;

[0025] Figure 3 It is a schematic structural diagram of the cascaded interface circuit connecting the cascaded output terminal of the chip structure provided by an embodiment of the present disclosure;

[0026] Figure 4 Structural schematic diagram of a chip cascade structure provided by another embodiment of the present disclosure;

[0027] Figure 5 Flow schematic diagram of a calibration method provided by another embodiment of the present disclosure;

[0028] Figure 6 Structural example of an amplifier circuit provided by an embodiment of the present disclosure;

[0029] Figure 7 Structural schematic diagram of a self - biased inverter provided by an embodiment of the present disclosure;

[0030] Figure 8 Structural schematic diagram of an amplifier with a transformer provided by an embodiment of the present disclosure;

[0031] Figure 9 Structural example of a self - biased inverting amplifier for single - ended input or differential input provided by an embodiment of the present disclosure. Detailed implementation manners

[0032] In a chip cascade structure, if the signal power output by the previous - stage chip is too large, then both the cascade output circuit of the previous - stage chip and the cascade input circuit of the subsequent - stage chip need to have high voltage resistance characteristics. At the same time, if the signal power output by the previous - stage chip is too large, it is difficult to ensure signal leakage between cascaded chips. On the contrary, if the signal power output by the previous - stage chip is too small, or there are abnormalities in the inter - board circuit in the chip cascade structure, etc., it will make it difficult for the subsequent - stage chip to obtain an effective signal, resulting in the chip cascade structure being difficult to meet expectations during operation.

[0033] An embodiment of the present disclosure provides a chip structure for adjusting the power of a cascaded synchronization signal transmitted by a chip so that the power of the cascaded synchronization signal meets a preset power range.

[0034] Those of ordinary skill in the art can understand that in various embodiments of the present disclosure, many technical details are presented for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present disclosure can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present disclosure. Each embodiment can be combined with each other and cross - referenced on the premise of no contradiction.

[0035] The chip structure provided in this embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:

[0036] It should be noted that the chip structure can be exemplified as a radar chip, and the chip structure has at least a working mode and a calibration mode. Among them, the working mode is used to make the chip structure operate to realize the real-time collection of physical data. The working mode can include a cascaded master mode, a cascaded slave mode, or a single-chip working mode, etc., to adapt to the needs of different applications. The calibration mode can be used for factory calibration of the chip in a test environment, or self-calibration or self-detection during use; the calibration mode can include: a cascaded calibration mode, a single-chip calibration mode, etc., to achieve the purpose of knowing whether the chip structure can work properly and even determining the compensation parameters of the chip structure.

[0037] Reference Figure 1 , the chip structure 100 includes a cascaded interface circuit 101, a detection circuit 102, and a signal processing circuit 103. Among them, the cascaded interface circuit 101 is used to controllably adjust the power of the transmitted cascaded synchronization signal in the calibration mode, so that the power of the cascaded synchronization signal meets a preset power range. Among them, the preset power range is used to ensure that the cascaded interface circuit 101 will not be damaged due to instantaneous or long-term overload; nor will the subsequent circuit be unable to respond to the cascaded synchronization signal due to instantaneous or long-term underload, resulting in abnormal operation of the chip in the cascaded working mode. The detection circuit 102 is coupled to the cascaded interface circuit 101 and is used to convert the power of the cascaded synchronization signal into a power detection signal and output it. Among them, the power detection signal is used to characterize the power of the cascaded synchronization signal. The signal processing circuit 103 is coupled to the detection circuit 102 and is used to detect the power detection signal to determine the power amplifier parameters of the cascaded interface circuit 101.

[0038] Specifically, the cascaded interface circuit 101 includes an amplifier, and the amplifier amplifies the received cascaded synchronization signal and then outputs it.

[0039] For the chip structure provided in this embodiment, by adjusting the bias current and supply voltage provided to the amplifier, the gain of the cascaded interface circuit 101 is changed, thereby changing the power of the cascaded synchronization signal, so that the power of the cascaded synchronization signal meets the preset power range, ensuring the stability of the chip operation.

[0040] Reference Figure 2 and Figure 3 , among which, Figure 2 shows a cascaded interface circuit 111 for receiving a cascaded synchronization signal. Reference Figure 2 , the cascaded interface circuit 111 is connected to the cascaded input end MuxIN of the chip structure. In this example, the cascaded synchronization signal is a cascaded input signal, and the cascaded input signal represents a signal input from other chip structures to this chip structure. Figure 3 shows a cascaded interface circuit 121 for transmitting a cascaded synchronization signal. Reference Figure 3, the cascaded interface circuit 121 is connected to the cascaded output terminal MuxOUT of the chip structure. In this example, the cascaded synchronization signal is the cascaded output signal, and the cascaded output signal is generated by the circuit inside the chip structure and output to other chips. Examples of the circuit inside the chip include a phase-locked loop (PLL) 104; or a clock generator (not shown), a controller (not shown), etc.

[0041] The cascaded interface circuits (101, 111, 121) include adjustable power amplifiers; in some embodiments, the adjustable power amplifier at least includes: a DC-controlled adjustable power amplifier. For example, adjusting the bias current of the power amplifier can affect the amplification ability of the power amplifier. Also, adjusting the supply voltage of the power amplifier can affect the amplification ability of the power amplifier. In other embodiments, the adjustable power amplifier at least includes a controllable adjustable power amplifier array, where each power amplifier in the controllable adjustable power amplifier array is the DC-controlled adjustable power amplifier described above. It should be noted that Figure 2 and Figure 3 is an example structure of the cascaded interface circuit for the adjustable power amplifier array.

[0042] In some embodiments, the cascaded interface circuits (101, 111, 121) further include a fixed power amplifier in addition to the adjustable power amplifier, and the fixed power amplifier is connected to the adjustable power amplifier. Among them, the fixed power amplifier can be a follower circuit or a stage power amplifier in a power amplification array. For example, the cascaded interface circuit includes cascaded adjustable power amplifiers and fixed power amplifiers to improve the stability of the cascaded interface circuit.

[0043] In some other examples, the cascaded interface circuit 101 further includes a signal driving circuit, and the cascaded power amplifiers are connected to the signal driving circuit to drive the signal driving circuit to output a cascaded synchronization signal with a swing within a preset power range.

[0044] Taking the chip structure as a radar chip as an example, in the cascaded mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascaded synchronization signal at least includes: one of the local oscillator signal, the clock signal of the analog-to-digital converter, or the local oscillator control signal. Among them, the local oscillator control signal is used to power on and operate the transceiver circuits of the cascaded multiple radar chips to realize the transceiver of radar signals. The cascaded multiple radar chips frequency-convert and amplify the received local oscillator signal to form a radar signal and transmit it into free space; or use the local oscillator signal to perform down-conversion processing on the received reflected signal to obtain an intermediate-frequency signal. The clock signal of the ADC enables the cascaded multiple radar chips to synchronously convert the intermediate-frequency signal into a digital signal, thereby reducing the phase difference of the intermediate-frequency signals of each chip and reducing the possibility of false target detection. In this way, the detection purpose of a large range and high accuracy is achieved.

[0045] For a single Lida chip, the radar chip has multiple cascade interface circuits that support sending cascade synchronization signals and / or receiving cascade synchronization signals in the cascade mode. Specifically, multiple cascade interface circuits may exist in the same chip structure, and different cascade interface circuits are used to receive different types of cascade synchronization signals. For example, the same chip structure includes a cascade interface circuit for sending a local oscillator signal and a cascade interface circuit for receiving a local oscillator signal.

[0046] In some embodiments, to accurately determine the power of the cascade synchronization signal, the detection circuit 102 is coupled to the output circuit of the last stage in the cascade interface circuits (101, 111, 121). For example, the detection circuit 102 is coupled to the output end of the cascade interface circuits (101, 111, 121), or the input end of the output circuit of the last stage.

[0047] It should be noted that the detection circuit 102 determines its circuit structure according to the type of the cascade synchronization signal to be detected. For example, if the cascade synchronization signal is a local oscillator signal, the detection circuit 102 includes, for example, a directional coupler (or inductive coupler) and a power conversion circuit, etc. Among them, the local oscillator signal is sampled by the coupler, and the power conversion circuit converts the amplitude of the local oscillator signal into a DC signal (i.e., the power detection signal), so that the power of the local oscillator signal is reflected by the current / voltage of the DC signal. Another example is that if the cascade synchronization signal is a local oscillator control signal or the clock signal of an analog-to-digital converter, the detection circuit 102 includes, for example, a sampling circuit with a switch circuit and a resistor, etc. Among them, the detection circuit 102 samples the voltage of the cascade synchronization signal proportionally to output the power detection signal.

[0048] In some embodiments, the signal processing circuit 103 includes a storage unit and a detection unit, etc. In one example, the storage unit includes a register, a non-volatile memory, or a capacitor, etc., to store a preset power range or provide a voltage threshold corresponding to the power range. The preset power range is directly set by the manufacturer based on the applicable scenario of the chip. The detection unit is, for example, a comparison circuit, an MCU, or a dedicated hardware computing circuit, etc. The detection unit performs deviation detection on the received power detection signal and the preset power range. The deviation detection methods include:

[0049] 1) Computational detection, digitize the power detection signal, and perform calculations with the preset power range to determine whether the power detection signal falls within the power range, or the deviation value of the power detection signal being higher or lower than the power range threshold.

[0050] When the deviation value is determined through detection, the signal processing circuit 103 converts the deviation value into power amplifier parameters and stores them. Among them, the power amplifier parameters correspond to the control parameters of the adjustable power amplifier in the cascaded interface circuit 101, including but not limited to: the DC voltage / current parameters of the adjustable power amplifier, the switching parameters of the power amplifier array in the adjustable power amplifier, etc. In this way, when the chip structure switches to the cascaded working mode, the adjustable power amplifier in the cascaded interface circuit provides the power of the transmitted cascaded synchronization signal according to the power amplifier parameters, achieving the purpose of controlling the power of the cascaded synchronization signal within the preset power range.

[0051] 2) Comparison detection, to determine whether the power detection signal is higher than, lower than, or within the power range by comparing voltage values. In this example, the signal processing circuit 103 is also connected to the cascaded interface circuit 101. The power amplifier parameters stored in the signal processing circuit 103 include: the step unit for adjusting the adjustable power amplifier, and the step coefficient; or the control parameters mentioned in 1) determined based on the step unit and the step coefficient. Among them, the step unit is exemplified as a unit of DC voltage / current, and the N-way switches (N≥1) of the power amplifier array in the adjustable power amplifier. The step coefficient is determined by the signal processing circuit to gradually adjust the cascaded interface circuit according to the detection result of each comparison detection.

[0052] For example, when the power of the cascaded synchronization signal is greater than the preset power range, the signal processing circuit 103 reduces the power amplifier parameters provided to the cascaded interface circuit 101 according to the step unit. At this time, the gain of the cascaded interface circuit 101 decreases, and the power of the amplified cascaded synchronization signal decreases accordingly until it adapts to the preset power range. The signal processing circuit 103 determines the step coefficient according to the number of iterations and saves the product of the step coefficient and the step unit as the power amplifier parameter. Conversely, when the power of the cascaded synchronization signal is less than the preset power range, the signal processing circuit 103 increases the power amplifier parameters provided to the cascaded interface circuit 101 according to the step unit. At this time, the gain of the cascaded interface circuit 101 increases, and the power of the amplified cascaded synchronization signal increases accordingly until it adapts to the preset power range. The signal processing circuit 103 determines the step coefficient according to the number of iterations and saves the product of the step coefficient and the step unit as the power amplifier parameter.

[0053] In some embodiments, the signal processing circuit 103 is also coupled to the cascaded interface circuit 101, and is used to control the cascaded interface circuit 101 based on the power parameters in the working mode to adjust the power of the transmitted cascaded synchronization signal, so that the power of the cascaded synchronization signal conforms to the preset power range.

[0054] It should be noted that the power of the cascaded synchronization signal also depends on the frequency of the cascaded synchronization signal. At this time, the signal processing circuit 103 is still in the calibration mode to calibrate the cascaded synchronization signals of different frequencies, so as to obtain the power amplifier parameter table corresponding to the frequency. Taking the cascaded synchronization signal as the local oscillator signal as an example, the power amplifier parameter corresponding to the frequency range f1 of the local oscillator signal is c1; the power amplifier parameter corresponding to the frequency range f2 of the local oscillator signal is c2, etc. In the subsequent working mode, the signal processing circuit 103 provides the power amplifier parameters to the cascaded interface circuit 101 based on the frequency range - power parameter table of the cascaded synchronization signal, so that the power of the cascaded synchronization signal meets the preset power range.

[0055] It should be noted that Figure 2 the detection circuit 152 shown in Figure 3 and the structure of the detection circuit 162 shown in Figure 1 are the same as the detection circuit 102 shown in Figure 2 For the relevant description, reference can be made to the description of the detection circuit 102 in the above - mentioned embodiment, and details will not be repeated in this embodiment; similarly, Figure 2 the signal processing circuit 153 shown in Figure 3 and the structure of the signal processing circuit 163 shown in Figure 1 are the same as the signal processing circuit 103 shown in

[0056] It should also be noted that the features disclosed in the chip structure provided in the above - mentioned embodiment can be arbitrarily combined without conflict to obtain a new chip structure embodiment.

[0057] Another embodiment of the present disclosure also provides a chip cascading structure for input and output matching of chip cascading.

[0058] The following will describe the chip cascading structure provided in this embodiment in detail with reference to the accompanying drawings, as follows:

[0059] Referring to Figure 4 , the chip cascading structure includes a main chip 201 and at least one slave chip 202. Among them, at least one of the main chip 201 and each slave chip 202 is arranged according to the chip structure provided in the above - mentioned embodiment, and the cascaded output terminal MuxOUT of the main chip 201 is connected to the cascaded input terminal MuxIN of the main chip 201 and the slave chip 202. Among them, the master - slave relationship of each chip in this chip cascading structure is configured. For example, each chip is a radar chip, and the master - slave relationship of each radar chip in the chip cascading structure can be configured by the upper - layer application.

[0060] It should be noted that the connection relationship between each slave chip 202 and the main chip 201 among the multiple slave chips 202 can be as Figure 4 shown.

[0061] To ensure the synchronization of the cascaded synchronization signals received by each chip, the chip cascading structure further includes a first signal transmission line and a second signal transmission line. The first signal transmission line and the second signal transmission line can be configured on the PCB board. Among them, the first signal transmission line connects the cascaded output end MuxOUT of the main chip 201 and the cascaded input end MuxIN of the main chip 201, and the second signal transmission line connects the cascaded output end MuxOUT of the main chip 201 and the cascaded input end MuxIN of the slave chip 202. Moreover, the lengths of the first signal transmission line and the second signal transmission line are the same, so that the time for the cascaded synchronization signal to be transmitted in the first signal transmission line and the second signal transmission line is the same, and the phases of the cascaded synchronization signals received by the cascaded input end MuxIN of the main chip 201 and the cascaded input end MuxIN of the slave chip 202 are the same.

[0062] In some embodiments, the main chip can also output the cascaded synchronization signal to an off-chip common node first, and then output the cascaded synchronization signal to the cascaded output end MuxOUT of the main chip 201 and the cascaded input end MuxIN of the slave chip 202 through the first signal transmission line and the second signal transmission line connected to the common node.

[0063] In some examples, in the calibration mode of the chip cascading structure, each chip calibrates its own cascaded interface circuit according to the cascaded synchronization signal sent by the main chip. The cascaded interface circuits to be calibrated include but are not limited to: the cascaded interface circuits in the cascaded synchronization signal transmission link and the cascaded interface circuits in the cascaded synchronization signal reception link. For example, the cascaded interface circuit connected to MuxIN, or the cascaded interface circuit connected to MuxOUT. Among them, the cascaded synchronization signal transmission link includes a signal link formed by connecting in series a pre-stage circuit in the chip, a cascaded interface circuit, the MuxOUT end, and a signal transmission line connected to the MuxOUT end. Among them, the pre-stage circuit includes a signal generator for the corresponding cascaded synchronization signal. Such as a phase-locked loop circuit, a crystal oscillator circuit, etc. in a radar chip. The cascaded synchronization signal reception link includes a signal link formed by connecting in series a signal transmission line, the MuxIN end, a cascaded interface circuit, and a post-stage circuit in the chip. Among them, the post-stage circuit includes a circuit in the chip that is driven to operate by the cascaded synchronization signal, such as a transceiver circuit, an ADC, etc. in a radar chip.

[0064] In other examples, since the first signal transmission line and the second signal transmission line between chips may be damaged during use, or because the lengths of the first signal transmission line and the second signal transmission line affect the power parameters of the connected cascaded interface circuits, or because any part of the above-mentioned transmission link circuit is abnormal, making it difficult to calibrate the cascaded interface circuit in the connected reception link, therefore, in the calibration mode of the chip cascading structure, each chip can also perform calibration control through other interconnected interfaces.

[0065] For example, the main chip 201 adopts the chip structure provided in the above embodiment. In the calibration mode of the chip cascade structure, the signal processing circuit in the main chip 201 is further configured to receive a first detection signal reflecting the signal power in the cascade receiving link of the slave chip 202; and detect the first detection signal based on a preset power range to determine the power amplifier parameters of the cascade interface circuit in the cascade transmitting link or the cascade receiving link of the main chip 201. That is, the main chip 201 adjusts the power amplifier parameters of the cascade interface circuit in the main chip 201 based on the power feedback of the cascade synchronization signal in the slave chip 202 to achieve effective transmission of the cascade synchronization signal between the main chip 201 and the slave chip 202.

[0066] For another example, the slave chip 202 adopts the chip structure provided in the above embodiment. In the calibration mode of the chip cascade structure, the signal processing circuit in the slave chip 202 is further configured to receive a second detection signal reflecting the signal power in the cascade transmitting link of the main chip 201; and detect the second detection signal based on a preset power range to determine the power amplifier parameters of the cascade interface circuit in the cascade receiving link of the slave chip 202. That is, the slave chip 202 adjusts the power amplifier parameters of the cascade interface circuit in the slave chip 202 based on the power feedback of the cascade synchronization signal in the main chip 201 to achieve effective transmission of the cascade synchronization signal between the main chip 201 and the slave chip 202.

[0067] Among them, the detection signals in the above examples can come from the cascade interface circuit inside the chip or be obtained by using a detection circuit arranged outside the chip.

[0068] In some other embodiments, in the working mode of the chip cascade structure, the signal processing circuit in the chip structure controls the cascade interface circuit in the chip cascade structure according to the power amplifier parameters determined by calibration; wherein, the power amplifier parameters are obtained based on the monitoring of the chip structure in the calibration mode of the chip cascade structure. That is, in the working mode of the chip cascade structure, the cascade interface circuit is adjusted based on the power amplifier parameters obtained in the calibration mode of the chip cascade structure so that the power of the cascade synchronization signal transmitted between the chip cascade structures conforms to the preset power range to match the transmission of the cascade synchronization signal between the main chip 201 and the slave chip 202.

[0069] It is not difficult to find that this embodiment can be implemented in cooperation with the chip structure provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment. To avoid repetition, they are not elaborated here. In addition, the features disclosed in the chip cascade structure provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the chip cascade structure.

[0070] Another embodiment of the present disclosure further provides a calibration method, which is applied to a chip cascade structure to make the power of the cascade synchronization signal transmitted between the chip cascade structures conform to a preset power range, or can also be applied to a chip structure to make the power of the cascade synchronization signal transmitted in the chip structure conform to a preset power range.

[0071] The calibration method provided in this embodiment will be described in detail below with reference to the accompanying drawings, specifically as follows:

[0072] The calibration method includes: detecting the power deviation between the signal power of at least one cascade link of the chip cascade structure and the preset power range; determining the power parameters of at least one cascade interface circuit on the cascade link according to the power deviation, so that the signal power transmitted by the corresponding cascade interface circuit of the chip cascade structure in the working mode conforms to the preset power range. Specifically, the calibration method includes steps 401 to 405.

[0073] Step 401, detecting the power deviation between the signal power of at least one cascade link of the chip cascade structure and the preset power range.

[0074] In some embodiments, the cascade output end of the main chip in the chip cascade structure is connected to the cascade input end of the main chip and the cascade input end of the slave chip to form a cascade link. Among them, the cascade output end of the main chip is connected to the first cascade interface circuit, the cascade input end of the main chip is connected to the second cascade interface circuit, and the cascade input end of the slave chip is connected to the third cascade interface circuit; the step of detecting the power deviation between the signal power of at least one cascade link of the chip cascade structure and the preset power range includes: obtaining a power detection signal from at least one of the first cascade interface circuit, the second cascade interface circuit, and the third cascade interface circuit; among them, the power detection signal represents the signal power to be detected. According to the preset power range, the power detection signal is detected to obtain the power deviation. Among them, the power detection signal can be an analog voltage signal or a converted digital signal.

[0075] Among them, the method of detecting the power detection signal according to the preset power range to obtain the power deviation can be as shown in steps 402 to 405; or steps 412 to 413 (not shown) are executed.

[0076] Step 402, determining whether the power detection signal conforms to the preset power range. If the signal power conforms to the preset power range, record the current power parameters for use in controlling the cascade interface circuit in the working mode.

[0077] If the signal power does not conform to the preset power range, execute steps 403 to 405 to generate new power parameters based on the deviation between the power detection signal and the preset power range, so that the signal power transmitted by the cascade interface circuit of the chip in the subsequent cascade working mode meets the preset power range.

[0078] Specifically, in step 403, it is determined whether the power detection signal is greater than the upper limit of the preset power range. If it is greater, step 405 is executed, that is, the power parameter of the cascaded interface circuit is decreased according to a preset step unit. If it is less, step 404 is executed, that is, the power parameter of the cascaded interface circuit is increased according to a preset step unit. For example, increasing or decreasing the amplification power of the cascaded interface circuit is achieved by providing the bias current and supply voltage to the amplifier.

[0079] According to the preset step unit, it is determined multiple times whether the power deviation obtained in each iteration conforms to the preset power range until a power detection signal that conforms to the preset power range is determined, so as to cumulatively obtain the power parameter. In other words, this power parameter is determined according to the step unit and the number of iterations (also known as the step coefficient).

[0080] In another example, as in step 412, it is determined whether the power detection signal exceeds the preset power range. If it exceeds, the deviation between the power detection signal and the preset power upper limit or lower limit is calculated, and step 413 is executed; otherwise, the power parameter is not adjusted.

[0081] In step 413, the calculated deviation is converted into a power parameter. Among them, according to the mapping relationship between the power parameter of the adjustable power amplifier and the power deviation, the deviation is converted into a power parameter so that the power of the cascaded synchronization signal transmitted through the cascaded interface circuit conforms to the preset power range.

[0082] This embodiment can be implemented in cooperation with the chip structure or chip cascading structure provided in the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. To avoid repetition, they will not be elaborated here.

[0083] An embodiment of the present disclosure provides an amplification circuit to reduce the chip occupation area while maintaining signal accuracy. For example, this amplification circuit can be used to transmit the local oscillator signal (i.e., LO signal) in the cascaded synchronization signal in a radar chip. Among them, the LO signal of the radar chip is a frequency-modulated continuous wave signal (i.e., FMCW signal).

[0084] The following will describe in detail the amplification circuit provided in this embodiment with reference to the accompanying drawings, specifically as follows:

[0085] Refer to Figures 6 - 8 , the amplification circuit includes at least one amplifier 501. At least one amplifier 501 is used to amplify the transmitted radio frequency signal. Among them, the radio frequency signal is the cascaded synchronization signal mentioned in the above embodiment. In some embodiments, the radio frequency signal includes an FMCW signal. At least one amplifier 501 includes: a cascaded inverting amplification circuit and a transformer coil assembly; wherein, the transformer coil assembly filters out the out-of-band signals introduced by the amplification circuit.

[0086] The principle of the transformer coil assembly filtering out the out-of-band signals introduced by the amplification circuit is as follows: The inverting amplification circuit amplifies the signals within the bandwidth in the range from 0 to a certain frequency point (0~finv). The inverting amplification circuit is based on an inverter and has the advantage of small area. However, if multiple inverters are introduced into the circuit, the loop formed by the inverters will also cause oscillation even without an input signal, but the oscillation frequency is relatively low, denoted as fosc. The transformer coil assembly involves an inductor group (main coil and secondary coil), and the amplification effect of the transformer is good. However, since the circuit involves inductors, it will cause a large occupied area of the circuit. The transformer coil assembly has an amplification effect within a certain frequency range (the minimum frequency fL to the maximum frequency fH), and the frequency value of the minimum frequency fL is much greater than fosc, that is, the transformer coil assembly attenuates the oscillation introduced by the inverter. In this embodiment, by arranging the inverting amplification circuit and the transformer coil assembly in the same amplifier, compared with an amplifier configured entirely with transformer coil assemblies, the circuit area is greatly reduced. And compared with an amplifier configured entirely with inverting amplification circuits, the oscillation interference caused when the inverters form a loop is eliminated, improving the accuracy of amplifying the input signal. In some examples, if the transformer coil assembly is placed at the rear stage of the inverting amplification circuit, the out-of-band signals introduced by the inverting amplification circuit can be effectively filtered out.

[0087] As Figure 6 shown, in some embodiments, the amplification circuit may only include one amplifier 501, and the amplifier performs two-stage amplification on the transmitted radio frequency signal. In some embodiments, the amplification circuit may also include multiple (the number is N) amplifiers, and the amplification circuit is used to perform 2N-stage amplification on the transmitted radio frequency signal. In some embodiments, the multiple amplifiers are connected in cascade, such as Figure 6 the cascaded amplification circuit shown. It should be noted that Figure 6 taking the cascading of two amplifiers as an example to illustrate the cascading setting method of the amplifier 501. In specific applications, those skilled in the art can set more amplifiers 501 in the amplification circuit according to Figure 6 the cascading connection method of the amplifiers shown.

[0088] Referring to Figure 6 and Figure 7 , in some embodiments, the inverting amplification circuit includes a self-biased inverting amplifier, and the specific structure of the self-biased inverting amplifier is as shown in Figure 7 (a). The structure shown in Figure 7 (a) can also be exemplified by the structural schematic diagram shown in Figure 7 (b). In addition, Figure 6 the structure diagram that conforms to Figure 7 (b) is set as the structure shown in Figure 7 (a) in actual settings.

[0089] In some embodiments, referring to Figure 6 、 Figure 7 and Figure 9 , the self - biased inverting amplifier includes: at least one self - biased inverter connected in cascade, and each self - biased inverter includes: a P - type transistor M1, whose gate is used to receive a radio - frequency signal, source is used to receive a power supply voltage, and drain is used to output the amplified radio - frequency signal; an N - type transistor M0, whose gate is connected to the gate of the P - type transistor, drain is connected to the drain of the P - type transistor, and source is grounded; a bias resistor R0, whose first end is connected to the drain of the P - type transistor and second end is connected to the drain of the P - type transistor. It should be noted that, in this example, Figure 9 the structure of each self - biased inverter in Figure 7 is as shown in Figure 9 (a), and the overall structure shown in Figure 7 (a) constitutes the schematic diagram shown in

[0090] For the self - biased amplifier, the gain of the self - biased inverter can be adjusted by the magnitude of the bias current introduced through the first end of the bias resistor R0, or the magnitude of the power supply voltage received by the source of the P - type transistor M1.

[0091] In some embodiments, the amplifier is a differential amplifier. Referring to Figure 9 (b), at this time, the inverting amplifier circuit has differential paths with the same configuration to be respectively used for transmitting differentially - set radio - frequency signals.

[0092] It should be noted that, since the inverting amplifier circuit is used to invert - amplify the input signal, in some embodiments, the amplifier includes an even number of cascaded inverting amplifiers so that the amplified input signal is in the same phase as the input signal. Specifically, in the amplifier circuit, the total number of self - biased inverting amplifiers is even, or the total number of self - biased inverters is even.

[0093] In some embodiments, referring to Figure 8 , the transformer coil assembly includes: a main coil, whose first end is connected to the drain of the first transistor M2 and second end is connected to the drain of the second transistor M3, and the mid - point of the main coil is used to receive a power supply voltage; the gate of the first transistor M2 is used to receive a first signal and source is grounded; the gate of the second transistor M3 is used to receive a second signal and source is grounded; the first signal and the second signal are differentially - set radio - frequency signals; a secondary coil, which is coupled to the main coil to form a transformer T1, the first end of the secondary coil is used to output a third signal, and the second end is used to output a fourth signal; the third signal and the fourth signal are differentially - set amplified radio - frequency signals.

[0094] In some embodiments, the primary coil may be configured to be exactly the same as the first coil and the second coil, where the first end of the first coil is connected to the drain of the first transistor M2, the second end of the first coil is connected to the first end of the second coil and is used to receive the power supply voltage, and the second end of the second coil is connected to the drain of the second transistor M3. It should be noted that "exactly the same" in the above description means that the winding and laying, coil length, and coil material of the first coil and the second coil are the same.

[0095] For the transformer coil assembly, the magnitude of the power supply voltage received through the midpoint of the coil of the primary coil can adjust the gain of the amplifier with a transformer.

[0096] In this embodiment, by arranging the inverting amplifier circuit and the transformer coil assembly in the same amplifier, compared with the amplifier that uses only the transformer coil assembly, the circuit area is greatly reduced, and compared with the amplifier that uses only the inverting amplifier circuit, the oscillation interference caused when the inverter forms a loop is cancelled, improving the accuracy of amplifying the input signal.

[0097] It should be noted that the features disclosed in the amplifier circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the amplifier circuit.

[0098] Another embodiment of the present disclosure provides a chip structure. Referring to Figure 1 and Figures 6 - 8 , the chip structure includes a cascaded interface circuit 101, and the cascaded interface circuit 101 is arranged based on the amplifier circuit provided in the previous embodiment to reduce the occupied area of the chip while maintaining signal accuracy. The cascaded interface circuit 101 is used to transmit and amplify the cascaded synchronization signal; the cascaded interface circuit 101 is used to controllably adjust the power of the transmitted cascaded synchronization signal in the calibration mode so that the power of the cascaded synchronization signal meets the preset power range.

[0099] In some embodiments, the chip structure further includes: a detection circuit 102 coupled to the cascaded interface circuit 101 for converting the power of the cascaded synchronization signal into a power detection signal and outputting it. The power detection signal is used to characterize the power of the cascaded synchronization signal. A signal processing circuit 103, coupled to the detection circuit 102, for detecting the power detection signal to determine the power amplifier parameters of the cascaded interface circuit 101.

[0100] In some embodiments, the cascaded interface circuit includes an adjustable power amplifier. The adjustable power amplifier includes a separate amplifier and a cascaded amplifier circuit, or the adjustable power amplifier includes an amplifier circuit. The signal processing circuit controls the power of the cascaded synchronization signal by applying an adjusted power supply voltage to the cascaded interface circuit, or the signal processing circuit controls the power of the cascaded synchronization signal by applying an adjusted bias current to the cascaded interface circuit.

[0101] For the chip structure provided in this embodiment, by adjusting the bias current and supply voltage provided to the amplifier, the gain of the cascaded interface circuit 101 is changed, thereby changing the power of the cascaded synchronization signal, so that the power of the cascaded synchronization signal meets the preset power range, ensuring the stability of the chip operation; and the cascaded interface circuit is set based on the amplifier circuit provided in the previous embodiment to reduce the occupied area of the chip while maintaining signal accuracy.

[0102] It should be noted that the chip structure provided in this embodiment is a new chip structure example formed by applying the amplifier circuit provided in the above embodiment to the chip structure provided in the above embodiment. For relevant descriptions, please refer to the descriptions of the above embodiments, and this embodiment will not be elaborated herein.

[0103] In addition, it should be noted that if the amplifier circuit provided in the above embodiment is applied to the chip structure provided in the above embodiment, the "radio frequency signal" mentioned in the amplifier circuit embodiment is the "cascaded synchronization signal" input to the cascaded interface circuit in the chip structure embodiment.

[0104] Another embodiment of the present disclosure provides a chip cascading structure for input and output matching of chip cascading, and reducing the occupied area of the chip while maintaining signal accuracy.

[0105] Specifically, the chip cascading structure includes a main chip and at least one slave chip. Among them, at least one of the main chip and each slave chip is set as the chip structure provided in the previous embodiment, and the cascaded output end of the main chip is connected to the cascaded input end of the main chip and the slave chip.

[0106] It should be noted that the chip cascading structure provided in this embodiment is a chip cascading structure established based on the chip structure provided in the previous embodiment. For relevant descriptions, please refer to the descriptions of the above embodiments, and this embodiment will not be elaborated herein.

[0107] In addition, in some embodiments, the structures of the amplifier circuits in the cascaded interface circuits of the main chip and the slave chip in the chip cascading structure are the same, so that the gains of the cascaded interface circuits of the main chip and the slave chip are the same, which is convenient for applying to the power adjustment of the cascaded synchronization signal to further ensure the input and output matching of the cascaded synchronization signal in chip cascading.

[0108] Another embodiment of the present disclosure provides a radar device. The radar device includes the chip structure provided in the above embodiment, or the chip cascading structure provided in the above embodiment, for input and output matching of chip cascading, or the radar device includes the amplifier circuit provided in the above embodiment to reduce the occupied area of the chip while maintaining signal accuracy.

[0109] Specifically, the radar chip includes: a signal generator, a local oscillator circuit, and a power amplifier circuit connected in sequence; among them, the signal generator is used to generate signals for radar detection, such as pulse signals, FMCW signals, etc.

[0110] Among them, the radar chip is a circuit constructed based on the Doppler effect formed between electromagnetic waves and speed, and is a detection device that converts physical quantities in physical space into electrical signals.

[0111] Regarding the circuit principle of the radar chip, the radar chip includes a transmitter, a receiver, an analog-to-digital converter, and a digital circuit. Among them, the transmitter includes a signal generator, a local oscillator circuit, a radio frequency transmission circuit (including a power amplifier circuit), and a transmitting antenna, etc. The receiver includes: a receiving antenna (Antenna), a mixer (Mixer), and an analog-to-digital converter (ADC), etc. Among them, the signal generator generates a signal with continuously changing frequency and outputs it to the local oscillator circuit to form an LO signal in the transmission frequency band; the radio frequency transmission circuit can drive and amplify the LO signal, and even perform phase control adjustment to form a chirp signal and convert it into an electromagnetic wave through the transmitting antenna. The electromagnetic wave is reflected by an object to form an echo, the receiving antenna converts the echo into an echo signal, and the mixer uses the LO signal to down-convert the echo signal into an intermediate frequency signal; the analog-to-digital converter converts the intermediate frequency signal into a digital signal. Among them, the digital signal corresponding to each chirp output by the analog-to-digital converter is also called a digital sequence.

[0112] In a radar device with multiple cascaded radar chips, the LO signal of the main radar chip is sent to the MUXOUT terminal through the first cascaded interface circuit, and is transmitted back to its own MUXIN terminal and the second cascaded interface circuit through a signal transmission line, and then transmitted to the radio frequency transmission circuit and the receiving circuit; on the other hand, it is transmitted to the MUXIN terminal and the third cascaded interface circuit of the slave radar chip to be transmitted to the radio frequency transmission circuit and the receiving circuit in the slave radar chip. Synchronously, the LO control signal and clock signal of the main radar chip are also transmitted to each cascaded radar chip through their respective cascaded interface circuits to achieve the synchronous operation of the cascaded radar chips.

[0113] Using the above cascaded radar device, more independent transceiver ports can be integrated to form MIMO channels in cooperation with the antenna array. In this way, not only can a larger range of detection be carried out using the antenna array, but also the detection accuracy can be improved. The digital signal processor processes the digital sequences of each received port that have been accumulated to locate the relative position between the target and the radar chip. Among them, the digital signal processor is such as a DSP (Digital Signal Processor), or a dedicated hardware accelerator, etc. The digital signal processor performs signal processing including at least one of the following: improving SNR, signal processing based on FFT, CFAR, target estimation based on MIMO, etc., to obtain the relative position.

[0114] The radar device further includes: an antenna array, wherein the transmitting antenna in the antenna array is connected to the output end of the radio frequency amplification circuit to radiate millimeter wave signals into free space; and receiving the reflected signal (also known as the echo signal) reflected by an object and obtaining a digital signal.

[0115] Another embodiment of the present disclosure provides an electronic device, which includes the radar device provided in the above embodiment, and is used for input and output matching of chip cascading, and reducing the occupied area of the chip on the basis of maintaining signal accuracy.

[0116] In one example, the electronic device includes traditional computing devices, such as desktop computers, laptop computers, smart phones, wearable devices such as smart watches, Internet services, etc. However, the electronic device also includes other types of computing devices, such as personal voice assistants, programmable thermostats, automotive electronic components, robots, smart devices embedded in other machines, such as refrigerators and industrial tools, Internet of Things devices, etc.

[0117] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A chip structure, characterized in that, Comprising: A cascaded interface circuit, configured to controllably adjust the power of the transmitted cascaded synchronization signal in a calibration mode so that the power of the cascaded synchronization signal meets a preset power range; A detection circuit, coupled to the cascaded interface circuit, configured to convert the power of the cascaded synchronization signal into a power detection signal and output it; A signal processing circuit, coupled to the detection circuit, configured to detect the power detection signal to determine the power amplifier parameters of the cascaded interface circuit.

2. The chip structure according to claim 1, wherein The signal processing circuit is further coupled to the cascaded interface circuit, and in an operating mode, controls the cascaded interface circuit based on the power amplifier parameters to adjust the power of the transmitted cascaded synchronization signal.

3. The chip structure according to claim 1, characterized in that, The cascaded interface circuit is connected to the cascaded input end of the chip structure or the cascaded output end of the chip structure.

4. The chip structure according to claim 1 or 3, characterized in that, The cascaded interface circuit includes an adjustable power amplifier; wherein, the adjustable power amplifier at least includes: a direct current controlled adjustable power amplifier or a controlled adjustable power amplifier array.

5. The chip structure according to claim 4, characterized in that The cascaded interface circuit includes: a fixed power amplifier, connected to the adjustable power amplifier.

6. The chip structure according to claim 1, wherein, The detection circuit is coupled to the last-stage output circuit of the cascaded interface circuit.

7. The chip structure according to claim 1, wherein The cascaded synchronization signal at least includes: one of a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

8. A chip cascade structure, characterized in that, Comprising: A main chip and slave chips; wherein, at least one of the main chip and each of the slave chips is the chip structure as described in any one of claims 1 to 7, and the cascaded output end of the main chip is connected to the cascaded input ends of the main chip and each of the slave chips.

9. The chip cascade structure according to claim 8, wherein, Further comprising: A first signal transmission line, configured to connect the cascaded output end of the main chip and the cascaded input end of the main chip; A second signal transmission line, configured to connect the cascaded output end of the main chip and the cascaded input end of the slave chip; Wherein, the length of the first signal transmission line is the same as the length of the second signal transmission line.

10. The chip cascade structure according to claim 8, wherein, The main chip adopts the chip structure as described in any one of claims 1 to 7. In the calibration mode of the chip cascaded structure, the signal processing circuit in the main chip is further configured to: Receive a first detection signal reflecting the signal power in the cascaded receiving link of the slave chip; And Detect the first detection signal based on a preset power range, and accordingly determine the power amplifier parameters of the cascaded interface circuit located in the cascaded transmitting link or the cascaded receiving link of the main chip.

11. The chip cascade structure according to claim 8, characterized in that, The slave chip adopts the chip structure as described in any one of claims 1 to 7. In the calibration mode of the chip cascaded structure, the signal processing circuit in the slave chip is further configured to: Receive a second detection signal reflecting the signal power in the cascaded transmitting link of the main chip; And Detect the second detection signal based on a preset power range, and accordingly determine the power amplifier parameters of the cascaded interface circuit located in the cascaded receiving link of the slave chip.

12. The chip cascade structure according to any one of claims 8 to 11, characterized in that, In the operating mode of the chip cascade structure, the signal processing circuit in the chip structure controls the cascade interface circuit in the chip cascade structure according to the power amplifier parameters determined by calibration; wherein, the power amplifier parameters are obtained according to the detection of the chip structure in the calibration mode of the chip cascade structure.

13. A calibration method, characterized in that, Applied to a chip cascade structure, including: Detecting the power deviation between the signal power of at least one cascade link of the chip cascade structure and a preset power range; Determining the power parameters of at least one cascade interface circuit on the cascade link according to the power deviation, so that the signal power transmitted by the corresponding cascade interface circuit of the chip cascade structure in the operating mode conforms to the preset power range.

14. The calibration method according to claim 13, wherein, The cascade output end of the main chip in the chip cascade structure is connected to the cascade input end of the main chip and the cascade input end of the slave chip to form the cascade link; wherein, the cascade output end of the main chip is connected to the first cascade interface circuit, the cascade input end of the main chip is connected to the second cascade interface circuit, and the cascade input end of the slave chip is connected to the third cascade interface circuit; The step of detecting the power deviation between the signal power of at least one cascade link of the chip cascade structure and a preset power range includes: Obtaining a power detection signal from at least one of the first cascade interface circuit, the second cascade interface circuit, and the third cascade interface circuit; wherein, the power detection signal represents the signal power to be detected; Detecting the power detection signal according to the preset power range to obtain the power deviation.

15. The calibration method according to claim 13, characterized in that, The step of determining the power parameters of at least one cascade interface circuit on the cascade link according to the power deviation includes: Converting the power deviation into power parameters; or Judging whether the power deviation obtained in each iteration conforms to the preset power range multiple times according to a preset step unit until a power detection signal that conforms to the preset power range is determined, so as to cumulatively obtain the power parameters.

16. A radar device, characterized in that, The radar device includes the chip structure according to any one of claims 1 to 7, or the chip cascade structure according to any one of claims 8 to 12.

17. An electronic device, characterized in that, The electronic device at least includes the radar device according to claim 16.

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