Radio frequency transceiver chip calibration method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a radio frequency transceiver chip calibration method and device, electronic equipment and a readable storage medium, and relates to the technical field of communication. The method comprises the following steps: sending a first continuous sine wave signal to a radio frequency transceiver chip; receiving a second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal; sampling the second continuous sine wave signal to obtain respective phases of a plurality of sampling points; judging whether the phases are continuous or not according to the phases of the sampling points; under the condition of determining that the phases are continuous, determining that the current delay value is a target delay value and the calibration is completed; and under the condition that the phase is determined to be discontinuous, the current delay value is adjusted, and calibration is carried out again. Therefore, the calibration efficiency can be improved, and meanwhile, the problem that the phase continuity requirement cannot be met after calibration can be avoided.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and more particularly, to a calibration method, apparatus, electronic device, and readable storage medium for a radio frequency transceiver chip. Background Art

[0002] Currently, due to various requirements, it is necessary to calibrate the delay value of a radio frequency transceiver chip (i.e., a radio frequency transceiver chip based on AD and DA, such as AD9361). The current general calibration method is as follows: Use the pre-configured delay values for verification, obtain the verification results corresponding to the respective delay values, and then determine the optimal delay value based on the verification results of the respective delay values, thereby completing the calibration. In the above method, only the pseudo-random binary sequence (PRBS) is used to verify the data correctness to determine the verification result, and the calibration efficiency is low because all the set delay values need to be traversed during calibration. Summary of the Invention

[0003] Embodiments of this application provide a calibration method, apparatus, electronic device, and readable storage medium for a radio frequency transceiver chip, which determine whether the calibration is completed according to the phase continuity judgment result corresponding to the current delay value, thereby improving the calibration efficiency and avoiding the inability to meet the phase continuity requirement after calibration.

[0004] Embodiments of this application may be implemented as follows:

[0005] In a first aspect, embodiments of this application provide a calibration method for a radio frequency transceiver chip, the method including:

[0006] Send a first continuous sine wave signal to the radio frequency transceiver chip;

[0007] Receive a second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal;

[0008] Sample the second continuous sine wave signal to obtain the phases of multiple sampling points;

[0009] Judge whether the phase is continuous according to the phases of multiple sampling points;

[0010] When it is determined that the phase is continuous, determine the current delay value as the target delay value and the calibration is completed;

[0011] When it is determined that the phase is not continuous, adjust the current delay value and perform calibration again.

[0012] In a second aspect, embodiments of this application provide a calibration apparatus for a radio frequency transceiver chip, the apparatus including:

[0013] A sending module, configured to send a first continuous sine wave signal to the radio frequency transceiver chip;

[0014] A receiving module, configured to receive a second continuous sine wave signal returned by the radio frequency transceiver chip based on a current delay value and the first continuous sine wave signal;

[0015] An analysis module, configured to sample the second continuous sine wave signal to obtain the phase of each of a plurality of sampling points;

[0016] The analysis module is further configured to determine whether the phases are continuous according to the phases of each of the plurality of sampling points;

[0017] The analysis module is further configured to, when determining that the phases are continuous, determine the current delay value as the target delay value and the calibration is completed;

[0018] The analysis module is further configured to, when determining that the phases are not continuous, adjust the current delay value; after adjusting the current delay value, the sending module is configured to send the first continuous sine wave signal again and perform calibration again.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the radio frequency transceiver chip calibration method described in the foregoing embodiments.

[0020] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the radio frequency transceiver chip calibration method described in the foregoing embodiments is implemented.

[0021] The radio frequency transceiver chip calibration method, device, electronic device, and readable storage medium provided by the embodiments of the present application send a first continuous sine wave signal to the radio frequency transceiver chip, and receive a second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal; then, sample the received second continuous sine wave signal to obtain the phase of each of a plurality of sampling points; then, determine whether the phases are continuous according to the phases of each of the plurality of sampling points; if it is determined that they are continuous, determine the current delay value as the target delay value and the calibration is completed; if it is determined that they are not continuous, adjust the current delay value and perform calibration again. In this way, it is possible to determine whether the calibration has been completed according to the phase continuity judgment result corresponding to the current delay value, thereby improving the calibration efficiency and avoiding the inability to meet the phase continuity requirement after calibration. Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a block diagram of the electronic device provided by the embodiment of the present application;

[0024] Figure 2 It is one of the flow diagrams of the radio frequency transceiver chip calibration method provided by the embodiment of the present application;

[0025] Figure 3 It is another flow diagram of the radio frequency transceiver chip calibration method provided by the embodiment of the present application;

[0026] Figure 4 It is Figure 2 a flow diagram of the sub-steps included in step S150 in

[0027] Figure 5 It is a schematic diagram of a calibration system for radio frequency transceiver chip calibration provided by the embodiment of the present application;

[0028] Figure 6 It is for Figure 5 a process diagram of one round of calibration under the calibration system shown;

[0029] Figure 7 It is a block diagram of the radio frequency transceiver chip calibration device provided by the embodiment of the present application.

[0030] Icons: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication unit; 200 - radio frequency transceiver chip calibration device; 210 - sending module; 220 - receiving module; 230 - analysis module. Specific embodiments

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Accordingly, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0033] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0034] Regarding the timing calibration problem when the radio frequency transceiver AD9361 module communicates with the FPGA module, the following solutions are currently provided. Its technical solutions are divided into two parts: receiving path (RX) and transmitting path (TX) calibration. The receiving path calibration method is as follows: 1. Configure the internal register 0x3F4 of AD9361 to 0x09 to generate a pseudo-random binary sequence (PRBS), and transmit it through the receiving channel to the FPGA input port. 2. Traverse the clock / data delay value (0 - 15) of the AD9361 register 0x006 and / or the delay value (0 - 31) of the FPGA input delay unit. After each configuration, verify the correctness of the PRBS through the FPGA. 3. Screen out the delay parameter combinations with correct verification, and select the best configuration located at the center of the available value distribution from them, and write it into the register or delay unit. The transmitting path calibration method is as follows: 1. Configure the AD9361 register 0x3F5 to 0x81 to loop back the transmitting channel signal to the receiving channel. 2. The FPGA generates a new sequence similar to the PRBS, transmits it through the transmitting channel and receives it through the loopback path. 3. Traverse the delay value of the AD9361 register 0x007 and / or the delay value of the FPGA output delay unit, and verify the loopback signal. 4. Select the best parameter configuration at the center position to complete the timing calibration of the transmitting path.

[0035] As a general communication link calibration method, the above solution has significant defects in terms of efficiency, scenario adaptability, signal quality correlation, etc., and in particular cannot meet the requirements of radar systems for phase continuity and high-precision timing. Among them, the efficiency defect is that before determining the optimal delay value each time, it is necessary to completely traverse the values in the registers (0-15) of 0x006 and the registers (0-15) of 0x007. The signal quality correlation defect means that after calibration, there may be obvious phase discontinuity.

[0036] In view of the above situation, the embodiments of the present application provide a calibration method, device, electronic device and readable storage medium for a radio frequency transceiver chip, which can determine whether the calibration is completed according to the phase continuity judgment result corresponding to the current delay value, thereby improving the calibration efficiency, and at the same time can avoid not meeting the phase continuity requirement after calibration, and can meet the requirements of radar systems for phase continuity and high-precision timing.

[0037] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0038] Please refer to Figure 1 , Figure 1 which is a block diagram of the electronic device 100 provided by the embodiments of the present application. The electronic device 100 may be, but is not limited to, a computer, a server, etc. The electronic device 100 may include a memory 110, a processor 120, and a communication unit 130. The elements of the memory 110, the processor 120, and the communication unit 130 are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, these elements may be electrically connected to each other through one or more communication buses or signal lines.

[0039] Among them, the memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), etc.

[0040] The processor 120 is used to read / write data or programs stored in the memory 110 and perform corresponding functions. For example, a radio frequency transceiver chip calibration device 200 is stored in the memory 110. The radio frequency transceiver chip calibration device 200 includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running software programs and modules stored in the memory 110, such as the radio frequency transceiver chip calibration device 200 in the embodiments of the present application, thereby implementing the radio frequency transceiver chip calibration method in the embodiments of the present application.

[0041] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through a network and is used to transmit and receive data through the network.

[0042] It should be understood that Figure 1 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may further include more or fewer components than those shown Figure 1 in the figure, or have a different configuration from that shown Figure 1 in the figure. Figure 1 Each component shown in the figure can be implemented by hardware, software, or a combination thereof.

[0043] Please refer to Figure 2 , Figure 2 which is one of the flow schematic diagrams of the radio frequency transceiver chip calibration method provided by the embodiments of the present application. The method can be applied to the above-mentioned electronic device. The specific process of the radio frequency transceiver chip calibration method will be elaborated in detail below. In this embodiment, the method may include step S120 to step S170.

[0044] Step S120: Send a first continuous sine wave signal to the radio frequency transceiver chip.

[0045] The radio frequency transceiver chip is a radio frequency transceiver chip for AD (Analog-to-Digital Conversion) and DA (Digital-to-Analog Conversion). For example, it can be an AD9361 chip or an AD9371 chip, etc., and can be specifically determined according to actual requirements. Among them, the AD chip represents a chip that receives analog signals, and the DA chip is a chip that transmits analog signals. The radio frequency transceiver chip includes AD and DA inside. A first continuous sine wave signal can be sent to the radio frequency transceiver chip. The continuous sine wave signal sent is a signal of a trigonometric function, specifically, it can be a sine signal or a cosine signal.

[0046] Step S130: Receive the second continuous sine wave signal returned by the RF transceiver chip based on the current delay value and the first continuous sine wave signal.

[0047] A delay value is set in the RF transceiver chip. The RF transceiver chip can process the received first continuous sine wave signal according to the currently set delay value (i.e., the current delay value) to obtain a second continuous sine wave signal, and return the second continuous sine wave signal to the electronic device. Among them, the first continuous sine wave signal and the second continuous sine wave signal are time-domain signals, with the horizontal axis being time and the vertical axis being amplitude. Since the first continuous sine wave signal is processed based on the current delay value, the time range corresponding to the second continuous sine wave signal is different from the time range corresponding to the first continuous sine wave signal, but the amplitudes of the second continuous sine wave signal and the first continuous sine wave signal are the same. That is, compared with the first sine wave signal, only the corresponding time range of the second continuous sine wave signal has changed.

[0048] Step S140: Sample the second continuous sine wave signal to obtain the phases of multiple sampling points.

[0049] In the case of receiving the second continuous sine wave signal returned by the RF transceiver chip, sample the second continuous sine wave signal, that is, determine multiple sampling points from the second continuous sine wave signal, and calculate the phases of multiple sampling points.

[0050] Step S150: Determine whether the phases are continuous according to the phases of multiple sampling points.

[0051] In the case where it is determined that the phases are continuous, execute Step S160: Determine that the current delay value is the target delay value and the calibration is completed.

[0052] In the case where it is determined that the phases are not continuous, execute Step S170: Adjust the current delay value and perform calibration again.

[0053] After obtaining the phases of multiple sampling points, it is possible to determine whether the phases of multiple sampling points are continuous in any way. If the phases of multiple sampling points are continuous, the current delay value in the RF transceiver chip can be directly used as the target delay value obtained when the calibration is completed, that is, the result of the calibration completion, and it is determined that the calibration is completed, and the calibration of the RF transceiver chip is no longer performed. If the phases of the multiple sampling points are not continuous, it is determined that the current delay value is inaccurate, the current calibration is not completed, and the target delay value that can be obtained when the calibration is completed is not obtained. In this case, the current delay value in the RF transceiver chip is adjusted, and then based on the adjusted current delay value, jump to Step S120 to perform verification again.

[0054] In this way, it is possible to determine whether the calibration has been completed according to the phase continuity judgment result corresponding to the current delay value, thereby improving the calibration efficiency and avoiding the inability to meet the phase continuity requirement after calibration.

[0055] Please refer to Figure 3 , Figure 3 FIG. 2 is a second schematic flowchart of the radio frequency transceiver chip calibration method provided by the embodiment of the present application. In this embodiment, before step S120, the method may further include steps S101 to S110.

[0056] Step S101, initialize the radio frequency transceiver chip.

[0057] Step S110, configure the radio frequency transceiver chip into the digital loopback mode.

[0058] In this embodiment, when calibrating the radio frequency transceiver chip for the first time, an initialization instruction may be first sent to the radio frequency transceiver chip to initialize the radio frequency transceiver chip, thereby setting the sampling rate, gain mode, etc. For example, the sampling rate can be set to 61.44 MHz.

[0059] The radio frequency transceiver chip is a chip with a digital loopback function. After initialization is completed, the radio frequency transceiver chip can be configured into the digital loopback mode, that is, the digital loopback mode is activated. In the digital loopback mode, the TX interface and the RX interface of the radio frequency transceiver chip are directly connected internally.

[0060] The electronic device includes a first transmission port and a first reception port, and the radio frequency transceiver chip includes a second transmission port and a second reception port. When the digital loopback mode of the radio frequency transceiver chip is activated, the electronic device sends the first continuous sine wave signal to the second transmission port of the radio frequency transceiver chip through the first transmission port, the second transmission port sends the received signal to the second reception port, and the second reception port sends the second continuous sine wave signal obtained based on the signal sent by the second transmission port to the first reception port of the electronic device.

[0061] In this embodiment, the current delay value includes the current transmission delay value and the current reception delay value. After the second transmission port of the radio frequency transceiver chip receives the first continuous sine wave signal, it can process the first continuous sine wave signal based on the current transmission delay value to obtain a third continuous sine wave signal, and send the third continuous sine wave signal to the second reception port of the radio frequency transceiver chip. The second reception port of the radio frequency transceiver chip can process the third continuous sine wave signal based on the current reception delay value to obtain the second continuous sine wave signal, and send the second continuous sine wave signal to the first reception port of the electronic device. Thus, the electronic device receives the second continuous sine wave signal obtained by processing the first continuous wave signal based on the current transmission delay value and the current reception delay value and sent by the radio frequency transceiver chip.

[0062] The above-mentioned first continuous sine wave signal, second continuous sine wave signal, and third continuous sine wave signal are sine wave signals with the same amplitude (i.e., the same amplitude information is reflected), and the only difference is the time ranges corresponding to the three. For example, the time range corresponding to the first continuous sine wave signal is 0 to 10 s; the second transmission port of the radio frequency transceiver chip processes the time range corresponding to the first continuous sine wave signal based on the current transmission delay value, and the time range corresponding to the obtained third continuous sine wave signal is 1 to 11 s; the second reception port of the radio frequency transceiver chip processes the time range corresponding to the third continuous sine wave signal based on the current reception delay value, and the time range corresponding to the obtained second continuous sine wave signal is 3 to 13 s; except for the different corresponding time ranges, the other contents of the above three continuous sine wave signals are the same.

[0063] When the electronic device receives the second continuous sine wave signal, it can sample the second continuous sine wave signal according to the time sequence and calculate the phases of multiple sampling points. Then, it can Figure 4 judge whether the phase is continuous in the manner shown. Please refer to Figure 4 , Figure 4 is Figure 2 The flowchart of the sub-steps included in step S150 in

[0064] Sub-step S151: Calculate the phase difference between adjacent sampling points according to the phases of multiple sampling points.

[0065] Sub-step S152: Judge whether the phase is continuous according to the obtained phase difference.

[0066] In this embodiment, adjacent sampling points among multiple sampling points can be determined based on the sampling time, and then the phase difference between the adjacent sampling points can be calculated. The phase difference can be the absolute value of the difference between two phases. For example, if sampling points A, B, and C are obtained based on the sequence of sampling times, then sampling points A and B are adjacent sampling points, and sampling points B and C are adjacent points. Then, based on the obtained multiple phase differences, it can be determined whether the phase is continuous, and the specific method can be determined according to actual requirements. For example, if the number of phase differences greater than a preset value is greater than a preset number (this value can be greater than or equal to 2), it is determined that the phase is discontinuous; otherwise, it is determined that the phase is continuous.

[0067] As a possible implementation, it can be determined whether each obtained phase difference is greater than a preset difference. Among them, the preset difference can be specifically determined according to actual requirements. For example, it can be set to 45°. If there is a phase difference greater than the preset difference among the obtained phase differences, it is determined that the phase is discontinuous; if there is no phase difference greater than the preset difference among the obtained phase differences, it is determined that the phase is continuous.

[0068] When it is determined that the phase is continuous, it can be determined that the current delay value in the radio frequency transceiver chip is the target delay value to be obtained when calibration is completed, and it is determined that the calibration is completed, and calibration is no longer performed based on steps S120 to S150.

[0069] Please refer to again Figure 3 , the method may further include step S161.

[0070] Step S161, when the calibration is completed, configure the radio frequency transceiver chip to turn off the digital loopback mode.

[0071] When the target delay value has been obtained (i.e., the calibration is completed) and the digital loopback mode of the radio frequency transceiver chip is activated, the digital loopback mode of the radio frequency transceiver chip can be turned off to facilitate the subsequent normal operation of the radio frequency transceiver chip.

[0072] When it is determined that the phase is discontinuous, it can be determined that the calibration is not completed. In this case, an adjusted current delay value can be determined within a preset delay value range, and then jump to step S110: configure the radio frequency transceiver chip to the digital loopback mode. Among them, when the current delay value includes a transmission delay value and a reception delay value, the transmission delay value and the reception delay value used for the first time can both be 0, and the increment of the transmission delay value before and after adjustment and the increment of the reception delay value before and after adjustment can be the same or different.

[0073] Please refer to again Figure 3 , the method may further include step S180.

[0074] Step S180, when the delay values within the delay value range have all been used for calibration and the calibration is not completed, an error record is generated.

[0075] In this embodiment, if the delay values within the preset delay value range have all been used for calibration but the corresponding results are all calibration failures, an error record corresponding to this situation can be generated for subsequent reference. Optionally, in this case, calibration may no longer be performed, that is, the entire calibration process ends.

[0076] Optionally, please refer to Figure 3 again, and the method may further include steps S191 to S193.

[0077] Step S191, when the delay values within the delay value range have all been used for calibration and the calibration is not completed, it is determined that one round of calibration has been performed, and the current calibrated round number is updated.

[0078] Step S192, determine whether the current calibrated round number reaches the preset round number.

[0079] If the current calibrated round number reaches the preset round number, step S193 is executed.

[0080] Step S193, stop calibration and give an alarm.

[0081] If the current calibrated round number does not reach the preset round number, jump to step S101: Initialize the radio frequency transceiver chip to calibrate again.

[0082] In this embodiment, when the delay values within the delay value range have all been used for calibration and the calibration is not completed, it is determined that one round of calibration has been performed, and the saved current calibrated round number is updated by incrementing it by 1. Then, it is determined whether the current calibrated round number is equal to the preset round number. If it is equal, calibration is stopped and an alarm is given. For example, a fault can be marked and an alarm can be triggered. If the current calibrated round number is not equal to the preset round number, the radio frequency transceiver chip can be initialized, that is, the radio frequency transceiver chip is reset, and then the calibration process is repeated to perform calibration again.

[0083] The following combines Figure 5 and Figure 6 to give an example of the above radio frequency transceiver chip calibration method.

[0084] In the following example, the electronic device is a ZYNQ chip, and the radio frequency transceiver chip is an AD9361 chip (also referred to as an AD9361 module).

[0085] As Figure 5As shown in the figure, the ZYNQ chip may include a PS side and a PL side. PS side (ARM processor): Connects to the configuration ports (SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, etc.) of the AD9361 through the SPI interface, and is responsible for initializing the AD9361, configuring the digital loopback mode, and dynamically adjusting the delay parameters. PL side (FPGA): Includes a DDS module, a CORDIC IP core, an AXI bus controller, etc., and is directly connected to the transceiver ports of the AD9361 through digital interfaces (TX_DATA11:0, TX_CLK, TX_FRAME, RX_DATA11:0, RX_CLK, RX_FRAME). The AXI bus connects the PS side and the PL side to transfer control commands (such as loopback mode status, calibration results) and real-time data (such as phase detection results).

[0086] The digital transmit port (TX2) in the AD9361 chip receives the continuous sine wave generated by the PL side, and the digital receive port (RX2) sends the signal back to the PL side in the loopback mode. The AD9361 chip also includes: tx_delay (register 0x007) and rx_delay (register 0x006); these two registers delay the phase of the clock signal relative to the parallel data lines, one is the phase of the clock relative to the transmitted data, and the other is the phase of the clock relative to the received data; these two registers are dynamically configured by the PS side through SPI.

[0087] First, perform initialization and loopback mode configuration.

[0088] S1. The PS side initializes the AD9361.

[0089] The PS side sends initialization instructions to the AD9361 through SPI (such as setting the sampling rate to 61.44 MHz, gain mode).

[0090] S2. Configure the digital loopback mode.

[0091] After initialization, the PS side writes register 0x3F5 = 0x81 to activate the digital loopback mode (TX→RX internal direct connection). Among them, register 0x3F5 is a register in the AD9361.

[0092] S3. The PS side notifies the PL side to start calibration.

[0093] The PS side sends a 32-bit status word (0x00000001) to the PL side through the AXI bus to notify the PL side to enter the calibration stage.

[0094] In the commonly used calibration schemes described above, an external computer is required to control SPI, and there is no integrated status notification mechanism, so the calibration process is fragmented. However, this scheme realizes fully automated control through direct interaction between the ZYNQ PS-PL.

[0095] Then, signal transmission and phase detection are carried out.

[0096] The S4.PL terminal transmits a continuous sine wave.

[0097] The S5.PL terminal receives the signal and detects the phase.

[0098] The DDS module at the PL terminal generates a 1MHz continuous sine wave, and the specific implementation is as follows: Use the Xilinx DDS Compiler IP core, configured in single-frequency mode (Phase Increment = 1,073,741,824, corresponding to \(f_{\text{out}}=\frac{1,073,741,824}{2^{32}}\times61.44\text{MHz}\approx1\text{MHz}\)); then, output a 12-bit signed integer (i.e., the continuous sine wave signal), and send it to the AD9361 TX port through TX_DATA11:0. That is, the PL terminal sends the continuous sine wave to the TX2 port of the AD9361 through its own TX1 port, and TX_CLK is synchronized with the 61.44MHz system clock.

[0099] After the AD9361 RX port (i.e., the RX2 port) receives the signal, it sends it to the PL terminal. The PL terminal calculates the phase of the sampling point through the CORDIC IP core: CORDIC is configured in Arctan mode, inputs I / Q data (12-bit signed), and outputs the phase value (16-bit fixed-point number, 0 - 360° corresponding to 0x0000 - 0xFFFF).

[0100] The phase difference between adjacent sampling points can be calculated in real time. If a phase difference greater than the preset difference is calculated, it is determined that the phase is discontinuous. If a phase difference greater than the preset difference is not calculated, it is determined that the phase is continuous.

[0101] In the common calibration scheme described above, PRBS verification is used to only verify the data correctness (CRC verification), and it cannot detect phase jumps (a key index of the radar). However, this scheme realizes phase continuity detection through the CORDIC algorithm, directly ensuring the quality of the radar signal.

[0102] Then, dynamic adjustment and closed-loop calibration can be carried out.

[0103] The S6.PL terminal feeds back the result to the PS terminal.

[0104] The S7.PS terminal determines whether the calibration is successful. If it is successful, it ends; if it is not successful, it adjusts the delay value and jumps to step S2.

[0105] If the phase is continuous, the PL side sends 0x00000001 to the PS side through the AXI bus to trigger the PS to close the loopback mode (0x3F5 = 0x00), and the calibration is completed.

[0106] If the phase is discontinuous, the PL side sends 0x00000000 to the PS side to notify the PS side that the phase is discontinuous. The PS side can adjust the delay parameter according to the following logic:

[0107] Incremental adjustment: When the first failure occurs, both tx_delay and rx_delay are incremented by 1 (e.g., from 0x0A → 0x0B).

[0108] After initialization, the delay values in register 0x007 and register 0x006 can both default to 0. When the first calibration fails, the delay values can be increased. For example, the delay values in register 0x007 and register 0x006 are both increased by 1. It is also possible for the increments of the delay values in the two registers to be different, which can be determined specifically according to actual requirements.

[0109] When adjusting the delay value, the adjustment is made within a certain range of the delay value. For example, the adjustment is made within 0 to 15. If the delay value after incremental adjustment exceeds 0x0F (decimal 15), it is reset to 0x00 and an error is recorded.

[0110] A retry mechanism can also be set, that is, a preset number of rounds greater than 1 is set. This preset number of rounds represents the maximum number of calibration rounds. For example, it can be set to 10. When a new delay value cannot be determined through incremental adjustment, it can be determined that one round of calibration has been performed, and the currently calibrated round number saved can be updated by adding 1. If the currently calibrated round number reaches the preset number of rounds, it is determined to be out of limit, a fault is marked, and a system alarm is triggered.

[0111] After each delay adjustment, the PS side notifies the PL side through AXI to resend the signal, and the loop continues until success or out of limit.

[0112] The above calibration process of the distance can be regarded as a signal acquisition and calibration method based on zynq + AD9361 hardware.

[0113] In the common calibration scheme described above, only the correctness of data is verified through a pseudo-random binary sequence (PRBS), and the phase continuity and timing accuracy of the signal cannot be detected. This results in the disconnection between the calibration result and the actual radar signal requirements. Moreover, the hardware dependence is complex. An external computer is required to control the FPGA and AD9361 through SPI, and the system has poor cross-platform adaptability (for example, when the FPGA is replaced, the program needs to be recompiled). Manual intervention is required after calibration fails, and no automatic retry or degradation mechanism is designed. In contrast, in this scheme, a continuous sine wave + phase continuity detection (the CORDIC IP core is used to calculate the phase in real time) is adopted to directly verify the core quality indicators of the radar signal and ensure the phase synchronization of the transceiver link. Additionally, it is fully integrated into the Zynq platform (the PS side controls AD9361 through SPI, and the PL side processes the signal), eliminating the need for external devices. The delay parameters are dynamically configured (adjusted in real time on the PS side), supporting seamless switching of the hardware platform. It also has an automatic retry mechanism, where the PS-PL collaborates to retry in real time and automatically adjusts the parameters until success. Through closed-loop control, dynamic phase detection, and radar scene orientation optimization on the ZYNQ platform, this scheme realizes a more efficient, accurate, and reliable calibration process.

[0114] The common calibration scheme described above has deficiencies in the radar application field, such as low efficiency, low scene adaptability, and poor signal quality correlation (that is, there may be obvious phase discontinuity after calibration). This scheme solves the defects in terms of efficiency, scene adaptability, and signal verification dimension through ZYNQ software-hardware collaboration, phase continuity detection, and closed-loop dynamic adjustment, providing a high-precision and high-reliability calibration method for the radar system.

[0115] To execute the corresponding steps in the above embodiments and each possible manner, an implementation of a radio frequency transceiver chip calibration device 200 is given below. Optionally, the radio frequency transceiver chip calibration device 200 may adopt the device structure of the electronic device 100 shown above. Further, please refer to Figure 1 the following figure, Figure 7 which Figure 7 is a block diagram of the radio frequency transceiver chip calibration device 200 provided by the embodiments of the present application. It should be noted that for the radio frequency transceiver chip calibration device 200 provided in this embodiment, its basic principle and the technical effects generated are the same as those in the above embodiments. For the sake of brief description, for the parts not mentioned in this embodiment, reference may be made to the corresponding content in the above embodiments. In this embodiment, the radio frequency transceiver chip calibration device 200 may include: a transmission module 210, a reception module 220, and an analysis module 230.

[0116] The transmission module 210 is configured to send a first continuous sine wave signal to the radio frequency transceiver chip.

[0117] The receiving module 220 is configured to receive the second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal.

[0118] The analysis module 230 is configured to sample the second continuous sine wave signal to obtain the phase of each of a plurality of sampling points.

[0119] The analysis module 230 is further configured to determine whether the phases are continuous according to the phases of each of the plurality of sampling points.

[0120] The analysis module 230 is further configured to, when determining that the phases are continuous, determine the current delay value as the target delay value and complete the calibration.

[0121] The analysis module 230 is further configured to, when determining that the phases are not continuous, adjust the current delay value; after adjusting the current delay value, the sending module is configured to send the first continuous sine wave signal again and perform calibration again.

[0122] Optionally, the above modules may be stored in the form of software or firmware in Figure 1 the shown memory 110 or solidified in the operating system (OS) of the electronic device 100, and can be executed by Figure 1 the processor 120 therein. Meanwhile, the data, program code, etc. required for executing the above modules may be stored in the memory 110.

[0123] An embodiment of the present application further provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the radio frequency transceiver chip calibration method described above is implemented.

[0124] In summary, an embodiment of the present application provides a radio frequency transceiver chip calibration method, device, electronic device, and readable storage medium, which send a first continuous sine wave signal to a radio frequency transceiver chip and receive a second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal; then, sample the received second continuous sine wave signal to obtain the phase of each of a plurality of sampling points; then, determine whether the phases are continuous according to the phases of each of the plurality of sampling points; if it is determined that they are continuous, determine the current delay value as the target delay value and complete the calibration; if it is determined that they are not continuous, adjust the current delay value and perform calibration again. In this way, it is possible to determine whether the calibration has been completed according to the phase continuity judgment result corresponding to the current delay value, thereby improving the calibration efficiency and avoiding the inability to meet the phase continuity requirement after calibration.

[0125] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0126] In addition, in each embodiment of the present application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0127] If the above functions are implemented in the form of software function modules and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0128] The above are only optional embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A calibration method for a radio frequency transceiver chip, characterized in that The method includes: Sending a first continuous sine wave signal to a radio frequency transceiver chip; Receiving a second continuous sine wave signal returned by the radio frequency transceiver chip based on a current delay value and the first continuous sine wave signal; Sampling the second continuous sine wave signal to obtain the phase of each of a plurality of sampling points; Judging whether the phases are continuous according to the phases of each of the plurality of sampling points; When it is determined that the phases are continuous, determining the current delay value as the target delay value and completing the calibration; When it is determined that the phases are not continuous, adjusting the current delay value and performing calibration again.

2. The method according to claim 1, wherein The judging whether the phases are continuous according to the phases of each of the plurality of sampling points includes: Calculating the phase difference between adjacent sampling points according to the phases of each of the plurality of sampling points; Judging whether the phases are continuous according to the obtained phase differences.

3. The method according to claim 2, wherein The judging whether the phases are continuous according to the obtained phase differences includes: If there is a phase difference greater than a preset difference among the obtained phase differences, determining that the phases are not continuous; If there is no phase difference greater than the preset difference among the obtained phase differences, determining that the phases are continuous.

4. The method according to claim 1, characterized in that, Before sending the first continuous sine wave signal to the radio frequency transceiver chip, the method further includes: Configuring the radio frequency transceiver chip into a digital loopback mode; When the calibration is completed, configuring the radio frequency transceiver chip to turn off the digital loopback mode; The sending the first continuous sine wave signal to the radio frequency transceiver chip includes: sending the first continuous sine wave signal to a second sending port of the radio frequency transceiver chip; The receiving the second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal includes: receiving the second continuous sine wave signal sent by a second receiving port of the radio frequency transceiver chip.

5. The method according to claim 1, wherein The current delay value includes a current sending delay value and a current receiving delay value, and the receiving the second continuous sine wave signal returned by the radio frequency transceiver chip based on the current delay value and the first continuous sine wave signal includes: Receiving the second continuous sine wave signal obtained after processing the first continuous wave signal by the radio frequency transceiver chip based on the current sending delay value and the current receiving delay value.

6. The method according to any one of claims 1 to 4, characterized in that The adjusting the current delay value includes: determining an adjusted current delay value within a preset delay value range; The method further includes: Generating an error record when all delay values within the delay value range have been used for calibration and the calibration is not completed.

7. The method according to claim 6, wherein The method further includes: When all delay values within the delay value range have been used for calibration and the calibration is not completed, determining that one round of calibration has been performed and updating the current calibrated round number; Judging whether the current calibrated round number reaches a preset round number; If the current calibrated round number reaches the preset round number, stopping the calibration and giving an alarm; If the current calibrated round number does not reach the preset round number, initializing the radio frequency transceiver chip and performing calibration again.

8. A radio frequency transceiver chip calibration device, characterized in that, The device includes: A sending module, configured to send a first continuous sine wave signal to a radio frequency transceiver chip; A receiving module, configured to receive a second continuous sine wave signal returned by the radio frequency transceiver chip based on a current delay value and the first continuous sine wave signal; An analysis module for sampling the second continuous sine wave signal to obtain the phase of each of a plurality of sampling points; The analysis module is further configured to determine whether the phases are continuous according to the phases of the plurality of sampling points; The analysis module is further configured to, when it is determined that the phases are continuous, determine the current delay value as the target delay value and calibration is completed; The analysis module is further configured to, when it is determined that the phases are not continuous, adjust the current delay value; after adjusting the current delay value, the sending module is configured to send the first continuous sine wave signal again and perform calibration again.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the radio frequency transceiver chip calibration method according to any one of claims 1-7.

10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the radio frequency transceiver chip calibration method according to any one of claims 1-7.

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