JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation

Abstract

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

Description

Technical Field

[0001] The present invention relates to the field of high-speed digital interface technologies, and more particularly to a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation. Background Art

[0002] As an important standard for high-speed data transmission, the JESD204B protocol is widely used in many fields. However, the traditional JESD204B system relying on the SYNC~ signal synchronization method has many inherent defects. Limitations of Fixed Phase Compensation In an actual complex working environment, the continuous change of temperature will change the physical characteristics of electronic components, resulting in the drift of the propagation delay of the clock signal. For example, in a high-temperature environment, the electron migration phenomenon inside the chip intensifies, increasing the equivalent resistance of the signal transmission path and the propagation delay. At the same time, the fluctuation of the power supply voltage will also directly affect the working frequency and phase of the clock circuit. The traditional fixed phase compensation method presets the compensation value according to specific and idealized working conditions. Once the environmental parameters deviate from the preset range, the fixed compensation value cannot adapt to this dynamic change, resulting in a deviation between the clock phase and the actual requirement, and then reducing the synchronization accuracy of the system. Multi-Device Cascade Error Accumulation Problem In a multi-device cascade architecture, each device will introduce a certain synchronization error. These errors will continuously accumulate during the cascade process. As the number of cascaded devices increases, the final synchronization error will be significantly amplified. For example, in a system with 10 cascaded devices, assuming that the initial synchronization error of each device is 1 ns, due to the error accumulation effect, the total synchronization error of the last device may reach 10 ns or even higher. This accumulated error will seriously affect the overall synchronization performance of the system. Especially in application scenarios with extremely high requirements for synchronization accuracy, such as high-resolution phased array radars, it may lead to a decrease in beam scanning accuracy and an inability to accurately detect the target position. Impact of Calibration Process on Services When the traditional calibration method performs phase calibration, it must interrupt the transmission of service data. This is because the calibration process requires the system to temporarily switch to the calibration mode and occupy the data transmission channel to send and receive calibration signals. For applications with extremely high real-time requirements, such as real-time video surveillance data transmission and financial transaction data processing, even a very short interruption of the service may result in serious consequences such as data loss and transaction failure. Taking real-time video surveillance as an example, interrupting the service may miss key surveillance images and fail to detect security hazards in a timely manner.

[0003] Based on this, the present invention proposes a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation to solve the above problems. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art, the present invention provides a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation to solve the problems existing in the above-mentioned background technology.

[0005] The present invention provides the following technical solutions: A JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, including: Master node: Generate and dynamically allocate clock signals, and construct a dynamic clock tree structure; Slave device: Achieve cascaded error elimination through a distributed compensation mechanism; Dynamic phase compensation engine: Adopt a hybrid phase detection architecture, combining a digital time-to-digital converter (TDC) and an analog phase-locked loop (PLL); Environmental parameter compensation module: Real-time collect temperature, voltage, and operating duration, and calculate the phase compensation amount through the formula Δφ = α*(T - T0) + β*(V - V0) + γ*Δt; Phase prediction module based on LSTM neural network: Use historical phase data and environmental parameters to predict the future phase change trend; Time-Sensitive Network (TSN) cooperative control module: Achieve deterministic transmission of synchronization information and control instructions between multiple devices; Online calibration module: Includes service traffic feature recognition, interruption-free phase fine-tuning, and dynamic priority scheduling mechanism.

[0006] Further, in the hybrid phase detection architecture: The digital TDC realizes picosecond-level phase measurement; The analog PLL completes fast phase tracking and locking; Both achieve real-time detection and compensation of dynamic phase errors through a parallel processing mechanism.

[0007] Further, in the environmental parameter compensation module: α, β, and γ are compensation coefficients obtained through regression analysis of experimental data; The compensation coefficients are dynamically optimized by a neural network model according to historical data; The temperature sensor accuracy reaches ±0.1°C, and the voltage sensor accuracy reaches ±0.01V.

[0008] Further, the LSTM neural network model: The input includes the phase deviation data of the previous 100 clock cycles and the corresponding environmental parameters; The output is the phase prediction value for the next 5 clock cycles; The Adam optimizer is used for model training, and the loss function is the root mean square error (RMSE).

[0009] Furthermore, the master node dynamic clock tree structure: It includes a 3-level clock distribution network, and each level is equipped with a programmable delay line (PDL); The delay line resolution reaches 50 ps, and the maximum delay adjustment range is 10 ns; The dynamic adjustment algorithm optimizes the clock transmission path based on the Dijkstra shortest path algorithm.

[0010] Furthermore, the slave device distributed compensation mechanism: Each slave device independently implements phase detection and compensation; The compensation amount includes local environmental parameter compensation and cascaded error compensation; The cascaded error compensation adopts a recursive cancellation algorithm, and the compensation coefficient is 0.8^(n - 1) (n is the number of cascaded levels).

[0011] Furthermore, the online calibration module: The service traffic feature recognition adopts a convolutional neural network (CNN) model, and the recognition accuracy rate is ≥99.5%; The non-interrupt phase fine-tuning step size is 1 / 128 of a clock cycle.

[0012] Furthermore, the system synchronization accuracy: The phase error of a single device ≤ ±200 ps; The total error of 10-level cascaded devices ≤ ±500 ps; When the temperature change range is -40°C to +85°C, the error drift ≤ ±150 ps / °C.

[0013] Furthermore, a JESD204B multi-device deterministic delay synchronization method based on dynamic clock phase compensation is provided, including the following steps: S1: The dynamic phase compensation engine detects the phase deviation in real time and calculates the compensation amount in combination with environmental parameters; S2: The master node dynamically adjusts the clock tree structure to optimize the clock distribution path; S3: The slave devices distribute and compensate the cascaded errors; S4: The TSN network collaboratively transmits synchronization control instructions; S5: The online calibration module identifies the service traffic characteristics and performs non-interrupt phase fine-tuning.

[0014] Furthermore, the online calibration steps include: S51: The CNN model identifies the training sequence; S52: Detecting the idle period of the training sequence; S53: Calculate the phase fine adjustment amount; S54: Perform fine-tuning through dynamic priority scheduling.

[0015] Technical effects and advantages of the present invention: In terms of synchronization accuracy, the present invention can achieve a single-device phase error of ≤±200ps, effectively meeting the requirements of stringent scenarios. It has strong environmental adaptability and can overcome the defects of traditional fixed compensation. Through distributed compensation from the device, it can effectively suppress the accumulation of cascade errors. In terms of real-time performance, the online calibration module can be calibrated in real time without interrupting business, meeting scenarios with high real-time requirements such as financial transactions. In addition, the master node clock tree structure is flexible, based on TSN collaborative control, combined with neural network optimization, so that the system has both flexibility and intelligent self-adaptation capabilities, which improves the overall system reliability and stability.

[0016] Specifically, excellent synchronization accuracy: the dynamic phase compensation engine captures phase deviation in real time and accurately, combined with the environmental parameter compensation module's precise consideration of temperature, voltage and operating time, and uses the LSTM neural network model to predict future phase change trends, and then cooperates with the master node's dynamic clock tree structure and the slave device's distributed compensation mechanism to greatly reduce the phase error. The single device phase error is ≤±200ps, and the total error of 10-level cascaded devices is ≤±500ps. Even when the temperature changes from -40℃ to +85℃, the error drift can be controlled at ≤±150ps / ℃, which can meet the strict requirements of synchronization accuracy in scenarios such as phased array radar and large-scale MIMO communications, ensuring the stable operation of the system in complex environments.

[0017] Strong environmental adaptability: The environmental parameter compensation module collects environmental parameters in real time and accurately calculates the phase compensation amount through dynamically optimized compensation coefficients. In the face of continuous changes in environmental factors such as temperature and voltage, the system can adaptively adjust to overcome the limitations of traditional fixed phase compensation, effectively avoid clock phase deviation caused by environmental parameters deviating from the preset range, and ensure the synchronization performance of the system in various dynamic environments.

[0018] Efficient cascade error suppression: The slave devices use a distributed compensation mechanism. Each slave device performs phase detection and compensation independently. The cascade error compensation uses a recursive elimination algorithm. As the number of cascade levels increases, the compensation coefficient decreases reasonably, effectively suppressing error accumulation. In the multi-device cascade architecture, high-precision synchronization between devices at all levels is ensured, synchronization performance deterioration caused by error accumulation is avoided, and the overall reliability and stability of the system are improved.

[0019] Real-time performance and business continuity: The online calibration module uses a convolutional neural network model to identify service traffic characteristics, with an accuracy rate of ≥99.5%, capable of accurately distinguishing training sequences from payloads. It utilizes the idle period of the training sequence for uninterrupted phase fine-tuning, with a step size as fine as 1 / 128 clock cycles. Meanwhile, combined with a dynamic priority scheduling mechanism, it achieves real-time calibration without interrupting service data transmission, meeting application scenarios with extremely high real-time requirements, such as real-time video surveillance data transmission and financial transaction data processing, and avoiding serious consequences such as data loss and transaction failures caused by service interruptions.

[0020] Flexible and intelligent system architecture: The dynamic clock tree structure of the master node is dynamically adjusted based on the Dijkstra shortest path algorithm, and combined with a programmable delay line to achieve precise distribution of clock signals, capable of flexibly adapting to different system layouts and device connection situations. The collaborative control module based on the Time-Sensitive Network (TSN) enables deterministic transmission of synchronization information and control instructions between multiple devices, ensuring the coordinated operation of each device. Meanwhile, the neural network model dynamically optimizes the compensation coefficient and phase prediction, enabling the system to have intelligent adaptive capabilities and automatically optimizing performance according to the actual operating conditions. Brief Description of the Drawings

[0021] Figure 1 It is the system architecture diagram of the present invention; Figure 2 It is the method flow diagram of the present invention. Detailed Embodiment

[0022] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] It can be understood that the terms "first", "second", etc. used in this application may be used in this document to describe various elements, but unless otherwise specified, these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0024] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application. Embodiment

[0025] The JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation provided by the present invention aim to solve the problems existing in the traditional JESD204B system in multi-device synchronization, such as the inability of fixed phase compensation to adapt to dynamic environmental changes, error accumulation during multi-device cascading, and the need to interrupt services during the calibration process. The following elaborates on each component of the system in detail.

[0026] Master node The master node plays a core role in the entire synchronization system, ensuring the coordinated and orderly operation of the entire system. Its core tasks include generating and dynamically allocating clock signals, and constructing a dynamic clock tree structure, which will be elaborated in more depth below.

[0027] High-precision clock source In practical application scenarios, a high-precision clock source is integrated inside the master node. Among them, the oven-controlled crystal oscillator (OCXO) is a typical representative. The reason why OCXO is widely used is that it has extremely low phase noise and excellent frequency stability. Phase noise is a key indicator to measure the quality of the clock signal. Low phase noise means less jitter in the clock signal, which can provide a more stable time reference for the system. And frequency stability ensures that the frequency of the clock signal can remain relatively stable under different environmental conditions (such as temperature and humidity changes), without obvious drift.

[0028] For example, in some communication systems with extremely high requirements for time accuracy, such as the synchronization system of 5G communication base stations, tiny clock deviations may lead to problems such as signal transmission errors and data loss. The high-precision characteristics of OCXO can effectively avoid the occurrence of these problems, providing a high-quality clock reference for the entire system and ensuring that each slave device can work under a unified time reference.

[0029] Dynamic clock tree structure The dynamic clock tree structure of the master node is the key to achieving precise distribution of clock signals. This structure includes a three-level clock distribution network, and each level is equipped with a programmable delay line (PDL). These PDLs are like precise "time regulators" that can finely adjust the delay of the clock signal.

[0030] The resolution of the programmable delay line reaches 50 ps, which means it can adjust the delay of the clock signal with very high precision. The maximum delay adjustment range is 10 ns, which provides sufficient flexibility for the distribution of the clock signal and can adapt to the needs of different slave devices and changes in the system environment. For example, in a large data center, different servers may be located in different positions, at different distances from the master node, and the signal transmission delays will also vary. Through the precise adjustment of the PDL, the master node can ensure that the clock signals received by each server are highly consistent in time.

[0031] Dynamic adjustment based on Dijkstra's algorithm The dynamic adjustment algorithm is based on Dijkstra's shortest path algorithm, which is a classic graph algorithm used to find the shortest paths from a node to all other nodes in a graph. In the clock distribution network of the master node, the core idea of Dijkstra's algorithm is to find the shortest paths from the master node to each slave device in a complex network structure, so as to ensure that the clock signal can reach each slave device with the minimum delay and jitter.

[0032] Specifically, the master node will collect data such as the location information, working status, and current clock synchronization status of the slave devices in real time. These data are the basis for constructing the clock distribution graph model. In the graph model, nodes represent each device (including the master node, slave devices, and intermediate clock distribution points), edges represent the transmission paths of the clock signal, and the weights of the edges represent the delays on these paths. This weight value is affected by various factors, such as line length, signal attenuation, interference, etc.

[0033] The master node uses the collected data to continuously update the structure of the graph model and the weights of the edges. Then, it calculates the shortest paths from the master node to each slave device through Dijkstra's algorithm. During the calculation process, the algorithm starts from the master node and gradually expands to other nodes, each time selecting the node closest to the master node for expansion until the shortest paths to all slave devices are found.

[0034] Once the shortest paths are calculated, the master node will adjust the delay values of the programmable delay line according to the delay conditions on the paths. For example, if the delay on a certain path is large, the master node will increase the delay value of the PDL to balance the delays of other paths, so that the clock signals received by each slave device are consistent in time. This dynamic adjustment mechanism can adapt to changes in the system environment in real time, such as the addition, removal of devices, or line failures, etc., and ensure that the clock synchronization performance of the entire system always remains in the best state.

[0035] Real-time data collection and processing The master node collects data such as the location information, working status, and current clock synchronization status of slave devices in real time. This process requires an efficient data acquisition and processing mechanism. In practical applications, the master node can interact with slave devices through network communication protocols (such as Ethernet, fiber optic communication, etc.). Slave devices will periodically send their own status information to the master node, including parameters such as the current clock phase, temperature, and voltage.

[0036] After receiving this data, the master node will process and analyze it in real time. For example, by monitoring the clock phase of slave devices, the master node can judge the synchronization status of each slave device, timely detect synchronization errors, and take corresponding adjustment measures. At the same time, the master node can also predict possible problems based on the working status and location information of slave devices, and make optimization adjustments in advance.

[0037] Fault Tolerance and Reliability Design To ensure the reliability and stability of the system, the master node also needs to have fault tolerance capabilities. During actual operation, various faults may occur, such as clock source faults, network communication faults, programmable delay line faults, etc. The master node needs to be able to detect these faults in a timely manner and take corresponding fault tolerance measures.

[0038] For example, when the master node detects a clock source fault, it can automatically switch to a backup clock source to ensure that the clock signal of the system will not be interrupted. At the same time, the master node can also use redundant design, such as using multiple programmable delay lines for backup. When a certain PDL fails, it can quickly switch to the backup PDL to ensure the normal distribution of the clock signal.

[0039] In addition, the master node can also adopt a distributed architecture, distributing some computing and control tasks to multiple nodes for processing, improving the fault tolerance and processing capabilities of the system. In this way, even if a certain node fails, other nodes can still continue to work, ensuring the normal operation of the entire system.

[0040] Cooperative Work with Other Modules The master node does not exist in isolation. It needs to cooperate with other modules in the system (such as the dynamic phase compensation engine, environmental parameter compensation module, etc.) to jointly achieve the clock synchronization function of the system.

[0041] For example, data interaction is required between the master node and the dynamic phase compensation engine. The dynamic phase compensation engine will monitor the phase deviation of the clock signal in real time and feedback this information to the master node. The master node adjusts the distribution and delay of the clock signal based on this information to compensate for the phase deviation. At the same time, the master node will also transfer the status information of the slave device to the dynamic phase compensation engine to help it perform phase compensation more accurately.

[0042] The master node also needs to cooperate closely with the environmental parameter compensation module. The environmental parameter compensation module will collect environmental parameters such as temperature and voltage in real time, and calculate the phase compensation amount based on these parameters. The master node will adjust the delay value of the programmable delay line according to the compensation amount provided by the environmental parameter compensation module to offset the influence of environmental factors on the clock signal.

[0043] By collaborating with other modules, the master node can better adapt to different working environments and system requirements, ensuring that the clock synchronization performance of the entire system always remains in the best state.

[0044] Slave device In the JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation, the slave device plays a crucial role. It eliminates cascading errors through a distributed compensation mechanism to ensure the synchronization accuracy of the entire system. The relevant characteristics of the slave device will be further explored below.

[0045] Overview of the distributed compensation mechanism The distributed compensation mechanism is the core strategy for the slave device to achieve high-precision synchronization. Different from the traditional centralized compensation method, distributed compensation allows each slave device to independently perform phase detection and compensation. This method has higher flexibility and adaptability, and can better cope with complex and changing actual application scenarios. In an actual system, the physical locations, environmental conditions, and hardware characteristics of each slave device may vary. The distributed compensation mechanism enables each slave device to perform personalized compensation according to its actual situation, thereby improving the synchronization performance of the entire system.

[0046] Independent phase detection and compensation capabilities Each slave device is equipped with a dedicated phase detection circuit and compensation module, which can monitor the phase of the clock signal received by itself in real time and accurately. The phase detection circuit usually uses a high-precision time-to-digital converter (TDC), which can convert the phase information of the clock signal into a digital quantity for subsequent processing and analysis. This high-precision detection ability enables the slave device to promptly detect the phase deviation in the clock signal and provide an accurate data basis for subsequent compensation operations.

[0047] After detecting the phase deviation, the slave device will perform corresponding compensation according to the local environmental parameters and cascading position. Local environmental parameters include temperature, voltage, humidity, etc. These factors will all affect the propagation and processing of the clock signal. For example, a change in temperature will cause the frequency of the crystal oscillator to drift, thereby affecting the phase of the clock signal. The slave device will use the environmental parameter compensation module to sense these environmental changes in real time and calculate the corresponding compensation amount according to the pre-established compensation model.

[0048] Composition of the compensation amount The compensation amount of the slave device mainly consists of two parts: local environmental parameter compensation and cascading error compensation.

[0049] Local environmental parameter compensation Local environmental parameter compensation is achieved through an environmental parameter compensation module. This module usually integrates multiple sensors for real-time collection of environmental parameters such as temperature and voltage. The collected data will be transmitted to the compensation algorithm module, where the influence of environmental factors on the phase of the clock signal is calculated according to a pre-established mathematical model, and the corresponding compensation amount is generated.

[0050] For example, regarding the influence of temperature, through a large number of experiments and data analysis, a temperature-phase compensation model can be established. This model can be expressed as a function, with the input being the current temperature value and the output being the corresponding phase compensation amount. In actual applications, the slave device will calculate the corresponding compensation amount according to the real-time collected temperature value through this model and adjust the phase of the clock signal.

[0051] Cascading error compensation Cascading error compensation uses a recursive cancellation algorithm, and the compensation coefficient is ( is the number of cascading levels). The core idea of this algorithm is that when each slave device calculates its own cascading error compensation amount, it will refer to the compensation situation of the previous-level slave device and make adjustments according to its own cascading position.

[0052] As the number of cascading levels increases, the compensation coefficient gradually decreases. This is because in a cascading system, errors will gradually accumulate as the signal is transmitted, but the accumulation speed will gradually slow down. By gradually decreasing the compensation coefficient, the accumulation of errors can be effectively suppressed to ensure the synchronization accuracy of the entire cascading system.

[0053] Principle and implementation of the recursive cancellation algorithm The recursive cancellation algorithm is the key to cascading error compensation. Taking a system with multiple cascaded slave devices as an example, assume that the clock signal sent by the master node is the reference signal.

[0054] After the first slave device receives the clock signal from the master node, it first performs local environmental parameter compensation. It will calculate the local environmental parameter compensation amount according to the environmental parameters it collects and adjust the phase of the clock signal. The adjusted clock signal is then transmitted to the next-level slave device as a new reference signal.

[0055] When the second slave device receives the clock signal forwarded by the first slave device, it will perform the following operations: Local environmental parameter compensation: The second slave device calculates the local environmental parameter compensation amount according to the environmental parameters it collects and makes the first adjustment to the received clock signal.

[0056] Cascaded error compensation: The second slave device will refer to the compensation situation of the first slave device and calculate the cascaded error compensation amount according to the recursive cancellation algorithm. The compensation coefficient is . Assume that the compensation amount of the first slave device is , and the cascaded error compensation amount calculated by the second slave device is . Then, the second slave device applies the cascaded error compensation amount to the clock signal after local environmental parameter compensation for the second adjustment.

[0057] And so on, each slave device performs local environmental parameter compensation and cascaded error compensation according to the above steps until the last slave device. In this recursive way, each slave device can independently compensate the clock signal, effectively eliminating the cascaded error and ensuring the synchronization accuracy of the entire cascaded system.

[0058] Hardware implementation and optimization of slave devices To implement the distributed compensation mechanism, the hardware design of the slave device needs to consider multiple aspects. First, the phase detection circuit needs to have high precision and high sensitivity to accurately detect small phase deviations. Second, the environmental parameter sensor needs to have high resolution and fast response ability to collect the changes of environmental parameters in real time.

[0059] In the hardware design, some optimization strategies can also be adopted to improve the performance of the slave device. For example, low-power chips and circuit designs are used to reduce the power consumption of the slave device and extend its service life. At the same time, anti-interference design is adopted to improve the stability and reliability of the slave device in a complex electromagnetic environment.

[0060] Cooperation of slave devices with the master node and other modules The slave device needs to work closely with the master node and other modules in the system. The slave device will regularly feedback information such as its own working status, phase detection results, and compensation situation to the master node. The master node adjusts and optimizes the clock distribution and synchronization strategy of the entire system based on this information.

[0061] In addition, the slave device also needs to perform data interaction and cooperate with other modules such as the dynamic phase compensation engine and the environmental parameter compensation module. For example, the slave device will transfer the collected environmental parameters to the environmental parameter compensation module, and this module will calculate a more accurate local environmental parameter compensation amount. At the same time, the slave device will also receive control instructions sent by the dynamic phase compensation engine to make finer adjustments to the phase of the clock signal.

[0062] By cooperating with the master node and other modules, the slave device can better adapt to the overall requirements of the system and improve the synchronization performance and reliability of the entire system.

[0063] Dynamic Phase Compensation Engine In a JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation, the dynamic phase compensation engine is a key component to ensure the synchronization accuracy of the system. It adopts a unique hybrid phase detection architecture, which combines a digital time-to-digital converter (TDC) with an analog phase-locked loop (PLL) to achieve efficient real-time detection and compensation of dynamic phase errors. The following will expand on it in detail.

[0064] Advantages of the Hybrid Phase Detection Architecture Traditional phase detection and compensation methods often struggle to meet the requirements of both high-precision measurement and fast response simultaneously. The hybrid phase detection architecture adopted by the dynamic phase compensation engine cleverly combines the advantages of digital TDC and analog PLL. The digital TDC provides an accurate data basis for phase compensation with its high-precision phase measurement ability; the analog PLL, with its fast response and tracking ability, can quickly adjust the phase of the clock signal. This complementary design enables the system to achieve high-precision and fast compensation in the face of complex and changing dynamic phase errors, thus significantly improving the synchronization accuracy and stability of the system.

[0065] Digital Time-to-Digital Converter (TDC) Principle of High-Precision Phase Measurement The digital TDC is a device that can accurately measure time intervals. In the dynamic phase compensation engine, it is mainly used for high-precision measurement of the phase of the clock signal. Its working principle is based on precisely timing the rising and falling edges of the clock signal. When the input clock signal arrives, the TDC starts the timing process and records the time points of the rising and falling edges of the clock signal. By precisely measuring these time points, the TDC can calculate the period and phase information of the clock signal and convert it into a digital signal for output.

[0066] Due to the advanced timing technology and high-precision clock source adopted by the TDC, it can achieve picosecond-level phase measurement accuracy. This high-precision measurement ability enables the system to detect extremely small phase deviations and provides accurate data support for subsequent compensation calculations.

[0067] Challenges and Solutions in Practical Applications In practical applications, the digital TDC may be affected by factors such as noise and temperature changes, resulting in an increase in measurement errors. To overcome these challenges, the following methods are usually adopted: Noise suppression technology: A low-noise amplifier and filter are adopted at the input stage of the TDC to preprocess the input signal to reduce noise interference. At the same time, digital filtering algorithms are used to process the measurement results to further improve the measurement accuracy.

[0068] Temperature compensation technology: By integrating a temperature sensor inside the TDC, the change of the ambient temperature is monitored in real time. According to the pre-established temperature-measurement error model, temperature compensation is performed on the measurement result to eliminate the influence of temperature change on the measurement accuracy.

[0069] Analog Phase-Locked Loop (PLL) Fast response and tracking ability The analog PLL is a circuit widely used in the fields of clock synchronization and frequency synthesis. In the dynamic phase compensation engine, it is mainly used to quickly adjust the phase of the clock signal. The basic principle of the PLL is to compare the phases of the input signal and the feedback signal to generate an error signal, process the error signal through a loop filter, and then input the processed signal into a Voltage-Controlled Oscillator (VCO) to adjust the output frequency and phase of the VCO to make it consistent with the phase of the input signal.

[0070] Since the PLL is implemented by using analog circuits, it has fast response and tracking ability. When the phase of the input signal changes, the PLL can quickly adjust the output phase of the VCO to make it track the phase change of the input signal. This fast response ability enables the system to compensate for the phase deviation within a short time and ensure the synchronization accuracy of the system.

[0071] Performance optimization and stability guarantee To improve the performance and stability of the analog PLL, the following methods are usually adopted: Loop filter design: Reasonably designing the parameters of the loop filter can optimize the dynamic response characteristics and stability of the PLL. For example, adopting a second-order or third-order loop filter can improve the tracking accuracy and anti-interference ability of the PLL.

[0072] VCO optimization: Selecting a high-performance VCO and performing optimized design on it can improve the output frequency stability and phase noise performance of the PLL. For example, adopting a VCO with low noise and high linearity can reduce the generation of phase noise and improve the synchronization accuracy of the system.

[0073] Parallel processing mechanism Collaborative work process In actual work, the digital TDC and the analog PLL work together through a parallel processing mechanism. The specific process is as follows: Phase deviation monitoring: The digital TDC monitors the phase deviation of the clock signal in real time and feeds back the measurement result to the control unit.

[0074] Compensation amount calculation: The control unit calculates the compensation amount that needs to be adjusted according to the phase deviation measurement result, combined with the synchronization requirements of the system and the pre-set compensation algorithm.

[0075] Control signal generation: The control unit converts the calculated compensation amount into a control signal and sends it to the analog PLL.

[0076] Phase adjustment: The analog PLL quickly adjusts the phase of the clock signal according to the control signal to eliminate the phase deviation.

[0077] Advantages of parallel processing This parallel processing mechanism enables the dynamic phase compensation engine to respond to phase changes in a short time. The digital TDC is responsible for high-precision phase measurement, providing accurate data for compensation calculation; the analog PLL is responsible for fast phase adjustment to ensure that the system can keep up with phase changes in a timely manner. The two work in parallel without interfering with each other, greatly improving the system's response speed and compensation efficiency, thus ensuring the synchronization accuracy of the system.

[0078] Environmental parameter compensation module In the JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation, the environmental parameter compensation module plays a crucial role. Since environmental factors (such as temperature, voltage, operating duration, etc.) can have a significant impact on the phase of the clock signal, thereby reducing the synchronization accuracy of the system, this module aims to monitor these environmental parameters in real time and, through precise calculation and dynamic optimization mechanisms, effectively compensate the phase of the clock signal to ensure that the system can maintain high-precision synchronization performance under different environmental conditions.

[0079] The change of environmental parameters is one of the important reasons for the phase drift of the clock signal. Taking temperature as an example, the frequency of the clock source (such as a crystal oscillator) will drift with the change of temperature, which is determined by the physical properties of the crystal material. Generally speaking, an increase in temperature will change the vibration frequency of the crystal, thereby causing a change in the phase of the clock signal. Similarly, voltage fluctuations will also affect the working state of the clock circuit, causing phase deviation. And the increase in operating duration may lead to the aging and performance degradation of electronic components, which will also have an impact on the clock phase.

[0080] The change of environmental parameters is often complex and dynamic, and may be affected by a variety of factors. For example, in a large data center, the temperature and voltage at different locations may vary greatly, and these parameters will also change continuously over time and with the operating state of the equipment. In addition, factors such as electromagnetic interference and noise in the environment may also affect the measurement accuracy of the sensor.

[0081] Role of high-precision sensors To ensure the accuracy of compensation, the environmental parameter compensation module adopts high-precision temperature sensors and voltage sensors. The accuracy of the temperature sensor reaches ±0.1°C, and the accuracy of the voltage sensor reaches ±0.01V. Such high-precision sensors can collect minute changes in environmental parameters in real time and accurately, providing a reliable data basis for subsequent phase compensation calculations.

[0082] High-precision temperature sensors usually adopt advanced sensing technologies and calibration methods, and can maintain high-precision measurements within a wide temperature range. For example, some temperature sensors use thermistors or thermocouples as sensing elements and correct the measurement results through digital calibration algorithms to improve measurement accuracy. Similarly, high-precision voltage sensors also adopt high-precision resistive voltage dividers and analog-to-digital converters, and can accurately measure minute changes in voltage.

[0083] Calculation of Phase Compensation Amount The environmental parameter compensation module calculates the phase compensation amount through the formula Δφ = α*(T - T0) + β*(V - V0) + γ*Δt. Wherein, T is the current temperature, T0 is the reference temperature; V is the current voltage, V0 is the reference voltage; Δt is the running duration. α, β, and γ are compensation coefficients obtained through regression analysis of experimental data, and these coefficients reflect the influence degrees of temperature, voltage, and running duration on the clock phase.

[0084] Regression analysis of experimental data is a method of establishing mathematical relationships between variables through statistical analysis of a large amount of experimental data. In this system, by measuring and recording the phase changes of the clock signal under different temperature, voltage, and running duration conditions, and then using the regression analysis algorithm, the three compensation coefficients α, β, and γ are fitted. These coefficients are determined according to the specific characteristics of the system and experimental data, and thus can accurately reflect the influence of environmental parameters on the clock phase.

[0085] Dynamic Optimization of Compensation Coefficients Based on Neural Network Model Although the compensation coefficients obtained through regression analysis of experimental data can reflect the influence of environmental parameters on the clock phase to a certain extent, due to the complexity of the environment and the dynamic changes of the system, these coefficients may need to be continuously adjusted to adapt to different working environments and system states. Therefore, the environmental parameter compensation module adopts a neural network model to dynamically optimize the compensation coefficients.

[0086] The neural network model has powerful learning and adaptive capabilities and can learn and analyze a large amount of historical environmental parameter data and corresponding phase change data. During the training process, the neural network model continuously adjusts its own weights and biases to minimize the error between the predicted phase change and the actual measured phase change. Through continuous learning and optimization, the neural network model can gradually find the optimal compensation coefficient value to make the phase compensation more accurate.

[0087] For example, when the system operates under a new environmental temperature or voltage condition, the neural network model will predict the optimal compensation coefficient value based on historical data and current environmental parameters. The control unit will calculate the phase compensation amount according to these optimized compensation coefficients and adjust the phase of the clock signal, thereby improving the synchronization accuracy of the system under different environmental conditions.

[0088] Workflow in practical applications During the operation of the system, the workflow of the environmental parameter compensation module is as follows: Parameter acquisition: The temperature sensor and voltage sensor collect the current temperature and voltage data in real time and record the running duration of the system simultaneously.

[0089] Data transmission: The collected environmental parameter data is transmitted to the control unit, and the control unit calculates T - T0, V - V0, and Δt according to the current environmental parameters and the preset reference values.

[0090] Compensation amount calculation: The control unit calculates the phase compensation amount using the formula Δφ = α*(T - T0)+β*(V - V0)+γ*Δt according to the current compensation coefficients α, β, γ and the calculated T - T0, V - V0, and Δt.

[0091] Phase adjustment: The control unit sends the calculated phase compensation amount to the clock signal processing module to adjust the phase of the clock signal to offset the influence of environmental factors on the clock phase.

[0092] Coefficient optimization: The neural network model will regularly analyze the historical environmental parameter data and corresponding phase change data and dynamically adjust the values of the compensation coefficients α, β, γ according to the analysis results to improve the accuracy of phase compensation.

[0093] Phase prediction module based on LSTM neural network The phase prediction module based on LSTM neural network uses historical phase data and environmental parameters to predict the future phase change trend. The LSTM neural network has powerful time series data processing capabilities and can capture long-term dependencies and complex patterns in time series.

[0094] The input of this module includes the phase deviation data of the first 100 clock cycles and the corresponding environmental parameters, and the output is the phase prediction values for the next 5 clock cycles. During the training process, the Adam optimizer is used for model training, and the loss function is the root mean square error (RMSE). By continuously adjusting the parameters of the model, the model can accurately predict the future phase change trend.

[0095] In practical applications, the phase prediction module will collect historical phase data and environmental parameters in real time and input them into the trained LSTM neural network model. The model will predict the phase change situation for the next 5 clock cycles based on this data and feedback the prediction results to the control unit. The control unit will adjust the phase compensation strategy in advance according to the prediction results to improve the synchronization accuracy and response speed of the system.

[0096] Time-Sensitive Network (TSN) Cooperative Control Module The Time-Sensitive Network (TSN) Cooperative Control Module realizes the deterministic transmission of synchronization information and control instructions between multiple devices. TSN technology is an emerging network technology that provides strict time determinism and low latency guarantee for network communication through a series of standards and protocols.

[0097] In this system, the TSN Cooperative Control Module adopts the IEEE802.1AS time synchronization protocol to ensure clock synchronization between devices. The synchronization message period is 1 μs, and the transmission delay jitter is less than 100 ns, ensuring that synchronization information and control instructions can be transmitted in a timely and accurate manner. At the same time, this module supports credit-based shaping (CBS) and time-aware shaping (TAS) scheduling mechanisms, which can reasonably schedule and manage network traffic according to different service requirements and priorities.

[0098] For example, when the master node needs to send a synchronization control instruction to a slave device, the TSN Cooperative Control Module will select an appropriate scheduling mechanism according to the current network status and service priority to ensure that the instruction can reach the slave device within the specified time. After receiving the instruction, the slave device will perform corresponding operations according to the requirements of the instruction to achieve cooperative work and synchronization between multiple devices.

[0099] Online Calibration Module The Online Calibration Module includes service traffic feature recognition, interruption-free phase fine-tuning, and dynamic priority scheduling mechanisms, aiming to achieve real-time calibration of the system without interrupting services.

[0100] The identification of service traffic characteristics uses a Convolutional Neural Network (CNN) model, and the identification accuracy is ≥99.5%. The CNN model has a powerful feature extraction ability and can accurately identify and classify the characteristics of service traffic. By training with a large amount of service traffic data, the CNN model can learn the feature patterns of training sequences and payloads, so as to accurately distinguish training sequences and payloads during real-time monitoring of service traffic.

[0101] The non-interruptible phase fine-tuning step size is 1 / 128 clock cycles, ensuring that it will not have an obvious impact on the normal transmission of service data during the fine-tuning process. When the service traffic feature identification module detects an idle period in the training sequence, it will trigger a non-interruptible phase fine-tuning operation. The control unit will calculate the phase fine-tuning amount to be adjusted according to the current clock phase detection result and the preset synchronization target, and fine-tune the clock phase with an extremely small step size.

[0102] The dynamic priority scheduling mechanism is based on a fuzzy logic algorithm, and the input parameters include device importance, service urgency, and synchronization error. This mechanism can dynamically allocate compensation priorities according to the actual situations of different devices. When multiple devices request compensation simultaneously, the system will process the compensation requests of high-priority devices first according to the priority order of the devices, ensuring the overall synchronization performance of the system and the normal operation of key services.

[0103] System synchronization accuracy This system has excellent performance in terms of synchronization accuracy. The phase error of a single device is ≤±200ps, the total error of 10-level cascaded devices is ≤±500ps, and the error drift is ≤±150ps / ℃ when the temperature change range is -40℃~+85℃. These high-precision synchronization indicators benefit from the collaborative work and innovative design of each module in the system and can meet the application scenarios with strict requirements for multi-channel synchronization accuracy such as phased array radars and large-scale MIMO communications.

[0104] JESD204B Multi-Device Deterministic Delay Synchronization Method Based on Dynamic Clock Phase Compensation The present invention also provides a JESD204B multi-device deterministic delay synchronization method based on dynamic clock phase compensation, which specifically includes the following steps: S1: The dynamic phase compensation engine detects the phase deviation in real time and calculates the compensation amount in combination with environmental parameters The digital TDC in the dynamic phase compensation engine monitors the phase deviation of the clock signal in real time and feeds back the measurement result to the control unit. At the same time, the environmental parameter compensation module collects environmental parameters such as temperature, voltage, and operation duration, and calculates the phase compensation amount according to the formula Δφ=α*(T-T0)+β*(V-V0)+γ*Δt. The control unit combines the phase deviation and the environmental parameter compensation amount to calculate the final compensation amount.

[0105] S2: The master node dynamically adjusts the clock tree structure to optimize the clock distribution path The master node collects data such as the location information, working status, and current clock synchronization status of slave devices in real time. Using the Dijkstra shortest path algorithm, a graph model for clock distribution is constructed to calculate the shortest paths from the master node to each slave device. According to the calculation results, the delay values of programmable delay lines are adjusted to optimize the clock distribution path, ensuring a high degree of synchronization of the clock signals received by each slave device.

[0106] S3: Slave devices perform distributed compensation for cascading errors Each slave device independently implements phase detection and compensation. First, local environmental parameter compensation is performed, and the clock signal is adjusted according to the compensation amount calculated by the environmental parameter compensation module. Then, a recursive cancellation algorithm is used to calculate the cascading error compensation amount, and the clock signal is further adjusted. Through this distributed compensation mechanism, cascading errors are eliminated, and the synchronization accuracy during multi-device cascading is improved.

[0107] S4: The TSN network collaboratively transmits synchronization control instructions The TSN collaborative control module adopts the IEEE802.1AS time synchronization protocol to ensure clock synchronization between devices. The synchronization message period is 1 μs, and the transmission delay jitter is less than 100 ns. The master node sends synchronization control instructions to slave devices through the TSN network. After receiving the instructions, the slave devices perform corresponding operations according to the requirements of the instructions. At the same time, the slave devices also feedback their own operating status and synchronization status to the master node to achieve collaborative work and synchronization among multiple devices.

[0108] S5: The online calibration module identifies service traffic characteristics and performs non-interruptive phase fine-tuning The service traffic characteristic identification module adopts a convolutional neural network (CNN) model to monitor service traffic in real time and accurately distinguish training sequences and payloads. When an idle period in the training sequence is detected, a non-interruptive phase fine-tuning operation is triggered. The control unit calculates the phase fine-tuning amount to be adjusted based on the current clock phase detection result and the preset synchronization target, and fine-tunes the clock phase in steps of 1 / 128 clock cycles. At the same time, the dynamic priority scheduling mechanism dynamically assigns compensation priorities according to factors such as device importance, service urgency, and synchronization error, ensuring the overall synchronization performance of the system and the normal operation of critical services.

[0109] Detailed description of the online calibration steps S51: The CNN model identifies the training sequence: The CNN model extracts features and classifies real-time service traffic, and accurately identifies the training sequence according to the trained feature patterns.

[0110] S52: Detect the idle period of the training sequence: After identifying the training sequence, further detect the idle period in the training sequence to provide an opportunity for uninterrupted phase fine-tuning.

[0111] S53: Calculate the phase fine-tuning amount: The control unit calculates the phase fine-tuning amount to be adjusted according to the current clock phase detection result and the preset synchronization target.

[0112] S54: Execute fine-tuning through dynamic priority scheduling: The dynamic priority scheduling mechanism dynamically assigns compensation priorities based on factors such as the importance of the device, the urgency of the service, and the synchronization error. After determining the priority of the current device, perform the uninterrupted phase fine-tuning operation in the order of priority to ensure the overall synchronization performance of the system and the normal operation of critical services.

[0113] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0114] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

[0115] The above is only the preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation, characterized in that It includes: Master node: Generates and dynamically allocates clock signals, and constructs a dynamic clock tree structure; Slave device: Achieves cascaded error cancellation through a distributed compensation mechanism; Dynamic phase compensation engine: Adopts a hybrid phase detection architecture, combining a digital time-to-digital converter (TDC) and an analog phase-locked loop (PLL); Environmental parameter compensation module: Real-time collects temperature, voltage, and operation duration, and calculates the phase compensation amount through the formula Δφ = α*(T - T0) + β*(V - V0) + γ*Δt; Phase prediction module based on LSTM neural network: Utilizes historical phase data and environmental parameters to predict future phase change trends; Time-Sensitive Network (TSN) cooperative control module: Enables deterministic transmission of synchronization information and control instructions among multiple devices; Online calibration module: Includes service traffic feature recognition, interruption-free phase fine-tuning, and dynamic priority scheduling mechanism.

2. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, wherein: In the said hybrid phase detection architecture: Digital TDC realizes picosecond-level phase measurement; Analog PLL completes fast phase tracking and locking; Both achieve real-time detection and compensation of dynamic phase errors through a parallel processing mechanism.

3. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, characterized in that: In the said environmental parameter compensation module: α, β, and γ are compensation coefficients obtained through regression analysis of experimental data; The compensation coefficients are dynamically optimized by a neural network model according to historical data; The temperature sensor has an accuracy of ±0.1°C, and the voltage sensor has an accuracy of ±0.01V.

4. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, characterized in that: The said LSTM neural network model: The input includes phase deviation data of the previous 100 clock cycles and corresponding environmental parameters; The output is the phase prediction value for the next 5 clock cycles; The Adam optimizer is used for model training, and the loss function is the root mean square error (RMSE).

5. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, wherein: The master node dynamic clock tree structure: Includes a three-level clock distribution network, with each level equipped with a programmable delay line (PDL); The delay line resolution reaches 50ps, and the maximum delay adjustment range is 10ns; The dynamic adjustment algorithm optimizes the clock transmission path based on the Dijkstra shortest path algorithm.

6. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, characterized in that: The slave device distributed compensation mechanism: Each slave device independently realizes phase detection and compensation; The compensation amount includes local environmental parameter compensation and cascaded error compensation; The cascaded error compensation adopts a recursive cancellation algorithm, and the compensation coefficient is 0.8^(n - 1) (n is the number of cascaded levels).

7. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, wherein: The said online calibration module: Service traffic feature recognition adopts a convolutional neural network (CNN) model, and the recognition accuracy is ≥99.5%; The interruption-free phase fine-tuning step size is 1 / 128 of a clock cycle; Dynamic priority scheduling is based on a fuzzy logic algorithm, and the input parameters include device importance, service urgency, and synchronization error.

8. The JESD204B multi-device deterministic delay synchronization system based on dynamic clock phase compensation according to claim 1, characterized in that: The system synchronization accuracy: The phase error of a single device ≤ ±200ps; The total error of 10-level cascaded devices ≤ ±500ps; When the temperature change range is -40°C to +85°C, the error drift ≤ ±150ps / °C.

9. A JESD204B multi-device deterministic delay synchronization method based on dynamic clock phase compensation, characterized in that, It includes the following steps: S1: The dynamic phase compensation engine real-time detects the phase deviation and calculates the compensation amount in combination with environmental parameters; S2: The master node dynamically adjusts the clock tree structure and optimizes the clock distribution path; S3: The slave devices distributively compensate for cascaded errors; S4: The TSN network cooperatively transmits synchronization control instructions; S5: The online calibration module identifies the service traffic characteristics and performs uninterrupted phase fine-tuning.

10. The method for deterministic delay synchronization of multiple JESD204B devices based on dynamic clock phase compensation according to claim 9, characterized in that: The online calibration steps include: S51: The CNN model identifies the training sequence; S52: Detects the idle period of the training sequence; S53: Calculates the phase fine-tuning amount; S54: Performs fine-tuning through dynamic priority scheduling.

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