Semiconductor memory device

Abstract

A semiconductor memory device includes a conductive pattern disposed on a substrate and a lower electrode connected to the conductive pattern and extending in a first direction. The lower electrode includes a lower pattern and an upper pattern. The lower pattern is disposed between the upper pattern and the conductive pattern. The device further includes a capacitor dielectric film disposed on the lower electrode and an upper electrode disposed on the capacitor dielectric film. The lower pattern includes a lower inner interface extending in the first direction, wherein the upper pattern does not have an inner interface extending in the first direction.

Description

Technical Field

[0001] The present disclosure provides a semiconductor memory device including a capacitor that can increase capacitance. Background Art

[0002] Recently, as the capacity of semiconductor devices has become larger and the integration degree has become higher, their design rules have been continuously reduced. This trend also appears in DRAM, which is one of the memory semiconductor devices. To operate a DRAM device, each cell requires a certain level of capacitance.

[0003] The increase in capacitance increases the amount of charge stored in the capacitor, thereby improving the refresh characteristics of the semiconductor device. The improved refresh characteristics of the semiconductor device can increase the yield of the semiconductor device.

[0004] To increase capacitance, research is being conducted on using a dielectric film having a high dielectric constant in the capacitor or increasing the contact area between the lower electrode and the dielectric film of the capacitor. Summary of the Invention

[0005] According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a conductive pattern disposed on a substrate; a lower electrode connected to the conductive pattern and extending in a first direction, wherein the lower electrode includes a lower pattern and an upper pattern, and the lower pattern is disposed between the upper pattern and the conductive pattern; a capacitor dielectric film disposed on the lower electrode; and an upper electrode disposed on the capacitor dielectric film, wherein the lower pattern includes a lower inner interface extending in the first direction, and the upper pattern does not have an inner interface extending in the first direction.

[0006] According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a conductive pattern disposed on a substrate; a lower electrode connected to the conductive pattern and extending in a first direction, wherein the lower electrode includes a lower pattern and an upper pattern, and the lower pattern is disposed between the upper pattern and the conductive pattern; a lower electrode support supporting the lower electrode and in contact with a sidewall of the lower pattern; a capacitor dielectric film disposed on the lower electrode and the lower electrode support; and an upper electrode disposed on the capacitor dielectric film, wherein the lower electrode support includes an upper surface and a bottom surface opposite to each other in the first direction, the bottom surface of the lower electrode support faces the conductive pattern, the upper pattern protrudes beyond the upper surface of the lower electrode support in the first direction, and at a boundary between the lower pattern and the upper pattern, a first crystal orientation of the lower pattern is different from a second crystal orientation of the upper pattern.

[0007] According to one aspect of the present disclosure, there is provided a semiconductor memory device, comprising: a substrate including an active region defined by an element isolation film and extending in a first direction, wherein the active region includes a first portion and second portions defined on each of two opposite sides of the first portion; a word line disposed in the substrate and the element isolation film and extending in a second direction different from the first direction, wherein the word line extends across a region between the first portion of the active region and the second portions of the active region; a bit line contact connected to the first portion of the active region; a bit line disposed on the bit line contact and connected to the bit line contact, wherein the bit line extends in a third direction different from the first direction and the second direction; a landing pad connected to the second portion of the active region; and a capacitor, wherein the capacitor includes a lower electrode connected to the landing pad and extending in the third direction, a capacitor dielectric film disposed on the lower electrode, and an upper electrode disposed on the capacitor dielectric film, wherein the lower electrode includes a lower pattern connected to the landing pad and an upper pattern disposed on the lower pattern, wherein the lower pattern includes a lower inner interface extending in the third direction, and wherein the upper pattern does not have an inner interface extending in the third direction.

[0008] The objects according to the present disclosure are not limited to the above objects. Other objects and advantages not mentioned according to the present disclosure can be understood based on the following description and can be more clearly understood based on the implementations according to the present disclosure. In addition, it will be readily understood that the objects and advantages according to the present disclosure can be achieved by using the means shown in the claims or combinations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by referring to the following detailed description of illustrative implementations of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is an exemplary diagram for showing a semiconductor memory device according to some implementations. Figure 2 is Figure 1 an enlarged view of part P of Figure 3 is Figure 1 an enlarged view of part Q of Figure 4 is for showing Figure 2 the crystal orientation of the conductive material in the R portion of

[0011] Figure 5 and Figure 6 are respectively diagrams for showing a semiconductor memory device according to some implementations.

[0012] Figures 7 to 9 are respectively diagrams for showing a semiconductor memory device according to some implementations.

[0013] Figure 10 and Figure 11These are diagrams for showing semiconductor memory devices according to some implementations.

[0014] Figure 12 And Figure 13 is a diagram for showing a semiconductor memory device according to some implementations.

[0015] Figure 14 And Figure 15 is a diagram for showing a semiconductor memory device according to some implementations.

[0016] Figure 16 is the layout of a semiconductor memory device according to some implementations. Figure 17 Only shows Figure 16 the layout of the word lines and cell active regions in Figure 18 is Figure 16 a cross-sectional view taken along A-A in

[0017] Figure 19 And Figure 20 is a diagram for showing a semiconductor memory device according to some implementations.

[0018] Figure 21 is a layout diagram for showing a semiconductor memory device according to some implementations. Figure 22 is a perspective view for showing a semiconductor memory device according to some implementations. Figure 23 is Figure 21 a cross-sectional view taken along lines B-B and C-C in

[0019] Figure 24 is a layout diagram for showing a semiconductor memory device according to some implementations. Figure 25 is a perspective view for showing a semiconductor memory device according to some implementations. Figure 26 is a diagram for showing a semiconductor memory device according to some implementations.

[0020] Figures 27 to 31 is a diagram of an intermediate structure corresponding to an intermediate step of a semiconductor memory device manufacturing method according to some implementations.

[0021] Figures 32 to 35 is a diagram of an intermediate structure corresponding to an intermediate step of a semiconductor memory device manufacturing method according to some implementations. Detailed implementation manners

[0022] For simplicity and clarity of illustration, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings denote the same or similar elements and thus perform similar functions. In addition, for simplicity of description, the description and details of well-known steps and elements are omitted. Further, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure. Examples of various implementations are further shown and described below. It will be understood that the description herein is not intended to limit the claims to the specific implementations described. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure as defined by the appended claims.

[0023] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the implementations of the present disclosure are illustrative, and the present disclosure is not limited thereto. Here, the same reference numerals refer to the same elements. In addition, for simplicity of description, the description and details of well-known steps and elements are omitted. Further, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

[0024] The terms used herein are for the purpose of describing particular implementations only and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "includes," and "including" when used in this specification, specify the presence of the stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." when following a list of elements may modify the entire list of elements and not individual elements in the list. When referring to "C to D," unless otherwise specified, this means C (including C) to D (including D).

[0025] It will be understood that, although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the spirit and scope of the present disclosure.

[0026] In addition, it will be understood that when a first element or layer is referred to as being “on” or “under” a second element or layer, the first element may be directly disposed on or under the second element, or may be indirectly disposed on or under the second element with a third element or layer disposed between the first element or layer and the second element or layer. It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it may be directly on the other element or layer, directly connected to or coupled to the other element or layer, or there may be one or more intervening elements or layers. In addition, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0027] In addition, as used herein, when a layer, film, region, plate, etc. can be disposed “on” or “on top of” another layer, film, region, plate, etc., the former may directly contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed “on” or “on top of” another layer, film, region, plate, etc., the former directly contacts the latter and no other layer, film, region, plate, etc. is disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. can be disposed “under” or “beneath” another layer, film, region, plate, etc., the former may directly contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is directly disposed “under” or “beneath” another layer, film, region, plate, etc., the former directly contacts the latter and no other layer, film, region, plate, etc. is disposed between the former and the latter.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0029] In one example, when an implementation can be implemented differently, the functions or operations specified in a particular block may occur in a different order than that specified in the flowchart. For example, two consecutive blocks can actually be executed simultaneously. Depending on the relevant functions or operations, these blocks can be executed in the reverse order.

[0030] In the description of temporal relationships, for example, the temporal precedence relationship between two events, such as "after", "subsequent to", "before", etc., unless specified as "immediately after", "immediately following", or "immediately before", another event may occur in between. The features of various implementations of the present disclosure can be combined with each other partially or entirely, and can be technically related or operable with each other. These implementations can be implemented independently of each other, and can be implemented together in an associated relationship. For ease of illustration, spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. can be used here to describe the relationship of one element or feature to another element or feature shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relationship terms are intended to cover other different orientations of the device during use or operation. For example, when the device in the drawings can be flipped, an element described as "under" or "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the example terms "under" and "below" can cover both the upper and lower orientations. The device can be oriented in other ways, such as rotated 90 degrees or in other orientations, and the spatial relationship descriptors used here should be interpreted accordingly.

[0031] Reference Figures 1 to 4 describes a semiconductor memory device according to some implementations.

[0032] Figure 1 is an example diagram for showing a semiconductor memory device according to some implementations. Figure 2 is Figure 1 an enlarged view of part P of Figure 3 is Figure 1 an enlarged view of part Q of Figure 4 is for showing Figure 2 the crystal orientation of the conductive material in the R part of

[0033] Reference Figures 1 to 4 According to some implementations, a semiconductor memory device can include a conductive pattern 30, a lower electrode 191, a capacitor dielectric film 192, an upper electrode 193, at least one lower electrode support 50 and 55, and a first upper electrode support 60.

[0034] The conductive pattern 30 may be disposed on the substrate 100. The conductive pattern 30 is shown isolated from the substrate 100. This is for illustrative purposes only and the present disclosure is not limited thereto. Different from what is shown, the conductive pattern 30 may be electrically connected to a conductive region formed on or within the substrate 100.

[0035] The interlayer insulating film 20 may be disposed on the substrate 100. The conductive pattern 30 may be disposed within the interlayer insulating film 20.

[0036] The substrate 100 may be made of bulk silicon or SOI (silicon-on-insulator). Optionally, the substrate 100 may be a silicon substrate or may include materials other than silicon, such as but not limited to silicon germanium, SGOI (silicon-germanium-on-insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, an example in which the substrate 100 is implemented as a silicon substrate is described.

[0037] For example, the interlayer insulating film 20 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), a silicon carbonitride film (SiCN), and combinations thereof.

[0038] The conductive pattern 30 includes a conductive material. The conductive pattern 30 may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material (2D material), and a metal. In a semiconductor memory device according to some implementations, the two-dimensional material may be a metal material and / or a semiconductor material. The two-dimensional material may include two-dimensional allotropes or two-dimensional compounds. For example, the two-dimensional material may include at least one of but not limited to graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, the above two-dimensional materials are listed only as examples. The two-dimensional materials that may be included in the semiconductor device according to the present disclosure are not limited to the above materials.

[0039] The first etch stop film 25 may be disposed on the interlayer insulating film 20. The first etch stop film 25 may not cover at least a portion of the conductive pattern 30, thereby allowing a portion of the conductive pattern 30 to be exposed.

[0040] In one example, the first etch stop film 25 may be disposed on the conductive pattern 30. The first etch stop film 25 may include a lower electrode hole that exposes at least a portion of the conductive pattern 30.

[0041] For example, the first etch stop film 25 may include at least one of a silicon nitride film, a silicon carbonitride film, a silicon boron nitride film (SiBN), a silicon carbonate film (SiCO), a silicon oxynitride film, and a silicon oxycarbonitride film. For example, the silicon carbonate film (SiCO) refers to a film containing silicon (Si), carbon (C), and oxygen (O), but does not imply a ratio between the contents of silicon (Si), carbon (C), and oxygen (O).

[0042] The data storage pattern DSP may be disposed on the conductive pattern 30. The data storage pattern DSP may be electrically connected to the conductive pattern 30.

[0043] In one example, the data storage pattern DSP may be a capacitor. The data storage pattern DSP may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193.

[0044] A plurality of lower electrodes 191 may be disposed on the conductive pattern 30. The lower electrode 191 may be connected to the conductive pattern 30. A portion of the lower electrode 191 may be disposed within the first etch stop film 25.

[0045] For example, each lower electrode 191 may have a column shape. The lower electrode 191 may extend in a manner elongated in a fourth direction DR4, which is the thickness direction of the substrate 100. The length of the lower electrode 191 extending in the fourth direction DR4 is greater than the length of the lower electrode 191 extending in each of the first direction DR1 and the second direction DR2 parallel to the upper surface of the substrate 100. For example, the first direction DR1 and the second direction DR2 may be perpendicular to the fourth direction DR4.

[0046] For example, the plurality of lower electrodes 191 may be repeatedly arranged along the first direction DR1. Although not shown, the lower electrodes 191 may be repeatedly arranged along the second direction DR2. The first direction DR1 and the second direction DR2 may be orthogonal to each other. The present disclosure is not limited thereto. The first direction DR1 and the second direction DR2 may be directions parallel to the surface of the substrate 100 and may be perpendicular to the fourth direction DR4.

[0047] The lower electrode 191 may include a lower pattern 191B and an upper pattern 191U. Each of the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode may extend in a manner elongated in the fourth direction DR4.

[0048] The lower pattern 191B of the lower electrode is connected to the conductive pattern 30. The lower pattern 191B of the lower electrode is disposed between the conductive pattern 30 and the upper pattern 191U of the lower electrode. For example, the lower pattern 191B and the upper pattern 191U of the lower electrode may be in contact with each other.

[0049] The lower pattern 191B of the lower electrode may include an upper surface 191B_US and a bottom surface 191B_BS that are opposite to each other in the fourth direction DR4. The bottom surface 191B_BS of the lower pattern of the lower electrode faces the conductive pattern 30. The bottom surface 191B_BS of the lower pattern of the lower electrode is connected to the conductive pattern 30.

[0050] The upper pattern 191U of the lower electrode may include an upper surface 191U_US and a bottom surface 191U_BS that are opposite to each other in the fourth direction DR4. The bottom surface 191U_BS of the upper pattern of the lower electrode faces the conductive pattern 30. The bottom surface 191U_BS of the upper pattern of the lower electrode is connected to the upper surface 191B_US of the lower pattern of the lower electrode. The bottom surface 191U_BS of the upper pattern of the lower electrode may contact the upper surface 191B_US of the lower pattern of the lower electrode.

[0051] The bottom surface 191B_BS of the lower pattern of the lower electrode may be the bottom surface of the lower electrode 191. The upper surface 191U_US of the upper pattern of the lower electrode may be the upper surface of the lower electrode 191.

[0052] For example, at the boundary between the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode, the width W11 of the lower pattern 191B of the lower electrode in the first direction DR1 may be equal to the width W12 of the upper pattern 191U of the lower electrode in the first direction DR1.

[0053] The width of the lower pattern 191B of the lower electrode is shown as being constant as the lower pattern extends away from the conductive pattern 30. This is only for ease of illustration, and the present disclosure is not limited thereto. Different from what is shown, the width of the lower pattern 191B of the lower electrode may vary as it extends away from the conductive pattern 30. In a semiconductor memory device according to some implementations, the width of the upper pattern 191U of the lower electrode may be constant as it extends away from the conductive pattern 30.

[0054] The lower pattern 191B of the lower electrode includes a lower inner interface 191B_IF. The lower inner interface 191B_IF may extend in an elongated manner in the fourth direction DR4 and within the lower pattern 191B of the lower electrode.

[0055] The lower inner interface 191B_IF may extend to the upper surface 191B_US of the lower pattern of the lower electrode. The lower inner interface 191B_IF may extend to the bottom surface 191U_BS of the upper pattern of the lower electrode.

[0056] The lower inner interface 191B_IF may not extend to the bottom surface 191B_BS of the lower pattern of the lower electrode. The lower inner interface 191_IF may not extend to the upper surface of the conductive pattern 30. The upper surface of the conductive pattern 30 may contact the lower pattern 191B of the lower electrode.

[0057] When the lower pattern 191B of the lower electrode is formed within the lower electrode hole ( Figure 27 191H therein), the lower inner interface 191B_IF can be formed. When the lower patterns 191B of the lower electrode deposited on two opposite sidewalls of the lower electrode hole 191H meet each other, the lower inner interface 191B_IF can be formed.

[0058] The upper pattern 191U of the lower electrode does not include an inner interface extending in the fourth direction DR4. The method of depositing the upper pattern 191U of the lower electrode is different from the method of depositing the lower pattern 191B of the lower electrode. Due to this difference in the deposition method, the upper pattern 191U of the lower electrode does not include an inner interface extending in the fourth direction DR4.

[0059] At the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the crystal orientation of the lower pattern 191B of the lower electrode is different from the crystal orientation of the upper pattern 191U of the lower electrode. For example, the crystal orientation of the upper pattern 191U of the lower electrode can mean the direction along which the crystal of the conductive material included in the upper pattern 191U of the lower electrode grows.

[0060] In Figure 4 the lower pattern 191B of the lower electrode can include a plurality of lower conductive material crystals 191B_CX. The lower pattern 191B of the lower electrode can be a collection of a plurality of lower conductive material crystals 191B_CX. At the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the lower conductive material crystal 191B_CX can grow in the first crystal orientation CX_DR1. At the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the crystal orientation of the lower pattern 191B of the lower electrode can be the first crystal orientation CX_DR1. For example, at the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the crystal orientation CX_DR1 of the lower pattern 191B of the lower electrode can be the first direction DR1.

[0061] The upper pattern 191U of the lower electrode can include a plurality of upper conductive material crystals 191U_CX. The upper pattern 191U of the lower electrode can be a collection of a plurality of upper conductive material crystals 191U_CX. At the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the upper conductive material crystal 191U_CX can grow in the second crystal orientation CX_DR2. At the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the crystal orientation of the upper pattern 191U of the lower electrode can be the second crystal orientation CX_DR2. For example, at the boundary between the upper pattern 191U of the lower electrode and the lower pattern 191B of the lower electrode, the crystal orientation CX_DR2 of the upper pattern 191U of the lower electrode can be the fourth direction DR4.

[0062] Through various analyses, those skilled in the art of the present disclosure can easily identify the crystal orientations of the lower conductive material crystal 191B_CX and the upper conductive material crystal 191U_CX.

[0063] The lower pattern 191B of the lower electrode may include, for example, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (such as iridium oxide or niobium oxide), etc. The present disclosure is not limited thereto. In a semiconductor memory device according to some implementations, the lower pattern 191B of the lower electrode may include titanium nitride (TiN). Additionally, in a semiconductor memory device according to some implementations, the lower pattern 191B of the lower electrode may include niobium nitride (NbN).

[0064] The upper pattern 191U of the lower electrode may include a conductive material capable of selective growth. The upper pattern 191U of the lower electrode may include, for example, one of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), ruthenium (Ru), and cobalt (Co). The present disclosure is not limited thereto.

[0065] In one example, the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode may include the same material. For example, the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode may include titanium nitride (TiN). In this case, in Figure 4 each of the lower conductive material crystal 191B_CX and the upper conductive material crystal 191U_CX may be a titanium nitride crystal.

[0066] In another example, the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode may include different materials.

[0067] After forming the lower electrode hole in the mold insulating film, the lower electrode may be formed by filling the lower electrode hole with a conductive material. When forming the lower electrode using this method, in order to increase the vertical dimension of the lower electrode, the vertical dimension of the mold insulating film should be increased. As the vertical dimension of the mold insulating film increases, the bowing of the lower electrode hole may become more severe. Additionally, the area of the conductive pattern 30 exposed through the lower electrode hole may be reduced, thereby reducing the contact area between the lower electrode and the conductive pattern. As a result, the performance and reliability of the semiconductor memory device may deteriorate.

[0068] When forming the upper pattern 191U of the lower electrode using selective growth, the problems caused by increasing the vertical dimension of the mold insulating film can be reduced or prevented. The vertical dimension of the lower electrode 191 in the fourth direction DR4 can be increased without the above problems, thereby increasing the capacitance of the capacitor. Therefore, the performance and reliability of the semiconductor memory device can be improved.

[0069] At least one of the lower electrode supports 50 and 55 may be provided on the first etch stop film 25. At least one of the lower electrode supports 50 and 55 may support the lower electrode 191.

[0070] For example, a plurality of lower electrode supports 50 and 55 may be provided on the first etch stop film 25. The plurality of lower electrode supports 50 and 55 may include a first lower electrode support 50 and a second lower electrode support 55 that are sequentially provided on the first etch stop film 25.

[0071] The first lower electrode support 50 and the second lower electrode support 55 may be spaced apart from the first etch stop film 25 in a fourth direction DR4. The first lower electrode support 50 and the second lower electrode support 55 may be spaced apart from each other in the fourth direction DR4.

[0072] For example, the second lower electrode support 55 may be the lower electrode support among the lower electrode supports 50 and 55 that is the farthest from the conductive pattern 30 in the fourth direction DR4. The second lower electrode support 55 may be the uppermost lower electrode support.

[0073] Each of the first lower electrode support 50 and the second lower electrode support 55 may be in contact with the lower electrode 191. Each of the first lower electrode support 50 and the second lower electrode support 55 may be in contact with the lower pattern 191B of the lower electrode. Each of the first lower electrode support 50 and the second lower electrode support 55 may contact a part of the sidewall 191B_SW of the lower pattern of the lower electrode.

[0074] The number of lower electrode supports in contact with the sidewall 191B_SW of the lower pattern of the lower electrode is shown as two. However, this is only for ease of explanation, and the present disclosure is not limited thereto.

[0075] The first lower electrode support 50 may include an upper surface 50US and a bottom surface 50BS that are opposite to each other in the fourth direction DR4.

[0076] The second lower electrode support 55 may include an upper surface 55US and a bottom surface 55BS that are opposite to each other in the fourth direction DR4. Each of the bottom surface 50BS of the first lower electrode support and the bottom surface 55BS of the second lower electrode support may face the conductive pattern 30.

[0077] For example, each of the bottom surface 50BS of the first lower electrode support and the bottom surface 55BS of the second lower electrode support may be flat tantalum in a cross-sectional view. Each of the upper surface 50US of the first lower electrode support and the upper surface 55US of the second lower electrode support may be flat in a cross-sectional view.

[0078] The upper pattern 191U of the lower electrode protrudes beyond the lower electrode supports 50 and 55 in the fourth direction DR4. The upper pattern 191U of the lower electrode may protrude beyond the upper surface 55US of the second lower electrode support in the fourth direction DR4.

[0079] Each of the first lower electrode support 50 and the second lower electrode support 55 may include at least one of, for example, silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon oxycarbonitride. In Figure 1 the second lower electrode support 55 is shown to have a thickness equal to that of the first lower electrode support 50 in the fourth direction DR4. The present disclosure is not limited thereto. Different from what is shown, the thickness of the second lower electrode support 55 in the fourth direction DR4 may be different from that of the first lower electrode support 50.

[0080] The first upper electrode support 60 may be disposed on the lower electrode 191. The first upper electrode support 60 may support the lower electrode 191.

[0081] The first upper electrode support 60 may be disposed on the upper pattern 191U of the lower electrode. The first upper electrode support 60 may be in contact with the upper pattern 191U of the lower electrode.

[0082] The first upper electrode support 60 may be disposed on the second lower electrode support 55. The first upper electrode support 60 may be spaced apart from the second lower electrode support 55 in the fourth direction DR4.

[0083] In a semiconductor memory device according to some implementations, the first upper electrode support 60 may contact the upper surface 191U_US and the sidewall 191U_SW of the upper pattern of the lower electrode.

[0084] The first upper electrode support 60 may cover a part of the sidewall 191U_SW of the upper pattern of the lower electrode.

[0085] The first upper electrode support 60 does not contact the sidewall 191B_SW of the lower pattern of the lower electrode.

[0086] For example, the first upper electrode support 60 may include a plate portion 60PL and a protrusion 60PP. The protrusion 60PP of the first upper electrode support may protrude from the plate portion 60PL of the first upper electrode support in the fourth direction DR4.

[0087] The plate portion 60PL of the first upper electrode support can contact the upper surface 191U_US of the upper pattern of the lower electrode. The protrusion 60PP of the first upper electrode support can contact the sidewall 191U_SW of the upper pattern of the lower electrode. For example, the protrusion 60PP and the plate portion 60PL of the first upper electrode support can be distinguished from each other based on the upper surface 191U_US of the upper pattern of the lower electrode.

[0088] The thickness of the protrusion 60PP of the first upper electrode support in the fourth direction DR4 can vary as the protrusion 60PP extends away from the upper pattern 191U of the lower electrode. For example, the thickness of the protrusion 60PP of the first upper electrode support in the fourth direction DR4 can decrease and then increase as it extends away from the first sidewall of the upper pattern 191U of the lower electrode.

[0089] Assume that the first upper electrode support 60 contacts the first lower electrode and the second lower electrode adjacent to each other. In a cross-sectional view, the thickness of the protrusion 60PP of the first upper electrode support can be minimized at the central portion of the space between the first lower electrode and the second lower electrode.

[0090] The first upper electrode support 60 can include an upper surface 60US and a bottom surface 60BS opposite to each other in the fourth direction DR4. The bottom surface 60BS of the first upper electrode support can face the second lower electrode support 55.

[0091] The plate portion 60PL of the first upper electrode support can include the upper surface 60US of the first upper electrode support. The protrusion 60PP of the first upper electrode support can include the bottom surface 60BS of the first upper electrode support.

[0092] For example, in a cross-sectional view, the upper surface 60US of the first upper electrode support can be flat. In a cross-sectional view, the bottom surface 60BS of the first upper electrode support can include a plurality of inclined surfaces. The bottom surface 60BS of the first upper electrode support can include a first bottom inclined surface 60BS1 and a second bottom inclined surface 60BS2. Each of the first bottom inclined surface 60BS1 and the second bottom inclined surface 60BS2 can be an inclined curved surface. Different from that shown, each of the first bottom inclined surface 60BS1 and the second bottom inclined surface 60BS2 can be an inclined flat surface.

[0093] The first upper electrode support 60 can include at least one of, for example, silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon oxycarbonitride.

[0094] The capacitor dielectric film 192 can be disposed on the lower electrode 191. The capacitor dielectric film 192 can be disposed on the lower electrode supports 50 and 55 and the first upper electrode support 60.

[0095] The capacitor dielectric film 192 may extend along the sidewalls 191U_SW, 191B_SW of the lower electrode, the upper surface 60US of the first upper electrode support, and the bottom surface 60BS of the first upper electrode support. Since the upper surface 191U_US of the upper pattern of the lower electrode contacts the first upper electrode support 60, the capacitor dielectric film 192 may not extend along the upper surface 191U_US of the upper pattern of the lower electrode.

[0096] The capacitor dielectric film 192 may extend along the upper surface 50US of the first lower electrode support, the bottom surface 50BS of the first lower electrode support, the upper surface 55US of the second lower electrode support, and the bottom surface 55BS of the second lower electrode support.

[0097] For example, the capacitor dielectric film 192 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, zirconium hafnium oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lead zirconium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. However, the present disclosure is not limited thereto.

[0098] In one example, the capacitor dielectric film 192 may include a stacked film structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are stacked in sequence. In another example, the capacitor dielectric film 192 may include a hafnium (Hf)-containing dielectric film. The description of the capacitor dielectric film 192 as described above is only an example, and the present disclosure is not limited thereto.

[0099] The capacitor dielectric film 192 may include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric film 192 may include at least one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0100] Different from those described above, the data storage pattern DSP may be implemented as a variable resistance pattern, which may switch between two resistance states when an electrical pulse is applied to the storage element. For example, the data storage pattern DSP may include a phase change material (whose crystalline state changes according to the amount of current), a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0101] The upper electrode 193 may be disposed on the capacitor dielectric film 192. The upper electrode 193 may fill the space between adjacent lower electrodes 191. The upper electrode 193 may fill the space between the first upper electrode support 60 and the second lower electrode support 55 and the space between the lower electrode supports 50 and 55 adjacent to each other in the fourth direction DR4. The upper electrode 193 may fill the space between the first lower electrode support 50 and the interlayer insulating film 20.

[0102] The upper electrode 193 may include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride, etc.), a metal (such as ruthenium, iridium, titanium, or tantalum, etc.), or a conductive metal oxide (such as iridium oxide or niobium oxide, etc.). The present disclosure is not limited thereto.

[0103] Figure 5 and Figure 6 are diagrams for showing a semiconductor memory device according to some implementations. For convenience, the following description focuses on the differences therefrom with the description used above Figures 1 to 4 described.

[0104] For reference, Figure 5 and Figure 6 each of which is Figure 1 an enlarged view of a part P of

[0105] Referring to Figure 5 , in a semiconductor memory device according to some implementations, the width of the upper pattern 191U of the lower electrode may vary as the upper pattern 191U extends away from the conductive pattern 30.

[0106] For example, the width of the upper pattern 191U of the lower electrode may decrease and then become constant as the upper pattern 191U extends away from the conductive pattern 30.

[0107] Different from that shown, in one example, the width of the upper pattern 191U of the lower electrode may increase and then become constant as the upper pattern 191U extends away from the conductive pattern 30. In another example, the width of the upper pattern 191U of the lower electrode may decrease as it extends away from the conductive pattern 30.

[0108] Referring to Figure 6 , in a semiconductor memory device according to some implementations, at the boundary between the lower pattern 191B of the lower electrode and the upper pattern 191U of the lower electrode, the width W11 of the lower pattern 191B of the lower electrode in the first direction DR1 may be smaller than the width W12 of the upper pattern 191U of the lower electrode in the first direction DR1.

[0109] The width of the upper pattern 191U of the lower electrode may be constant as it extends away from the conductive pattern 30. The present disclosure is not limited thereto.

[0110] Figures 7 to 9 These are diagrams for showing a semiconductor memory device according to some implementations. For convenience, the following description focuses on the differences from the description used above Figures 1 to 4 described. For reference, Figure 8 and Figure 9 each in Figure 7 is an enlarged view of part P of

[0111] Referring to Figures 7 to 9 , in a semiconductor memory device according to some implementations, the bottom surface 60BS of the first upper electrode support does not include a plurality of inclined surfaces.

[0112] In Figure 8 , in a cross-sectional view, the bottom surface 60BS of the first upper electrode support may be flat. As the protrusion 60PP of the first upper electrode support extends away from the upper pattern 191U of the lower electrode, the thickness of the protrusion 60PP of the first upper electrode support in the fourth direction DR4 may be constant.

[0113] In Figure 9 , in a cross-sectional view, the bottom surface 60BS of the first upper electrode support may be a convex curved surface. As the protrusion extends away from the upper pattern 191U of the lower electrode (i.e., in the first direction DR1), the thickness of the protrusion 60PP of the first upper electrode support in the fourth direction DR4 may increase and then decrease.

[0114] Figure 10 and Figure 11 These are diagrams for showing a semiconductor memory device according to some implementations. For convenience, the following description focuses on the differences from the description used above Figures 1 to 9 described.

[0115] Referring to Figure 10 and Figure 11 , in a semiconductor memory device according to some implementations, the first upper electrode support 60 does not cover the upper surface 191U_US of the upper pattern of the lower electrode.

[0116] The first upper electrode support 60 does not contact the upper surface 191U_US of the upper pattern of the lower electrode. The first upper electrode support 60 does not include the plate portion of the first upper electrode support ( Figure 1 and Figure 7 60PL in

[0117] The capacitor dielectric film 192 may extend along the upper surface 191U_US of the upper pattern of the lower electrode. The capacitor dielectric film 192 may contact the upper surface 191U_US of the upper pattern of the lower electrode.

[0118] Figure 12 and Figure 13 is a diagram for illustrating a semiconductor memory device according to some implementations. For convenience, the following description focuses on the differences from the description used above Figures 1 to 4 described

[0119] For reference Figure 13 is Figure 12 an enlarged view of part P of

[0120] Referring to Figure 12 and Figure 13 in a semiconductor memory device according to some implementations, an upper pattern 191U of a lower electrode may include a plurality of sub-upper patterns 191U1 and 191U2 that are stacked in a fourth direction DR4 while being disposed on a lower pattern 191B of the lower electrode

[0121] The upper pattern 191U of the lower electrode may include a first sub-upper pattern 191U1 and a second sub-upper pattern 191U2. The upper pattern 191U of the lower electrode is shown as including two sub-upper patterns. This is only for ease of illustration, and the present disclosure is not limited thereto

[0122] The first sub-upper pattern 191U1 may be disposed between the lower pattern 191B and the second sub-upper pattern 191U2. The first sub-upper pattern 191U1 may contact the lower pattern 191B and the second sub-upper pattern 191U2

[0123] The first upper electrode support 60 may contact the second sub-upper pattern 191U2. The first upper electrode support 60 may not contact the first sub-upper pattern 191U1

[0124] Sidewalls 191U_SW of the upper pattern of the lower electrode may include a first portion 191U_SW1 defined by the first sub-upper pattern 191U1 and a second portion 191U_SW2 defined by the second sub-upper pattern 191U2

[0125] The first upper electrode support 60 may not contact the first portion 191U_SW1 of the sidewalls of the upper pattern of the lower electrode. The first upper electrode support 60 may contact the second portion 191U_SW2 of the sidewalls of the upper pattern of the lower electrode

[0126] Each of the first sub-upper pattern 191U1 and the second sub-upper pattern 191U2 may include a conductive material capable of selective growth. In one example, the first sub-upper pattern 191U1 and the second sub-upper pattern 191U2 may include the same conductive material. In another example, the first sub-upper pattern 191U1 and the second sub-upper pattern 191U2 may include different conductive materials

[0127] Figure 14 and Figure 15is a diagram for showing a semiconductor memory device according to some implementations. For convenience, the following description focuses on its differences from the description used above Figures 1 to 4 , Figure 12 and Figure 13 described.

[0128] For reference, Figure 15 is Figure 14 an enlarged view of part P of

[0129] Referring to Figure 14 and Figure 15 , a semiconductor memory device according to some implementations may further include a second upper electrode support 65 disposed between the first upper electrode support 60 and the conductive pattern 30.

[0130] The second upper electrode support 65 may be disposed between the first upper electrode support 60 and the second lower electrode support 55. The second upper electrode support 65 may support the lower electrode 191.

[0131] The second upper electrode support 65 may be spaced apart from the first upper electrode support 60 in the fourth direction DR4. The second upper electrode support 65 may be spaced apart from the second lower electrode support 55 in the fourth direction DR4.

[0132] The second upper electrode support 65 may be in contact with the upper pattern 191U of the lower electrode. For example, the second upper electrode support 65 may contact the first sub-upper pattern 191U1.

[0133] The second upper electrode support 65 may be in contact with the sidewall 191U_SW of the upper pattern of the lower electrode. The second upper electrode support 65 may be in contact with the first part 191U_SW1 of the sidewall of the upper pattern of the lower electrode. The second upper electrode support 65 may not be in contact with the second part 191U_SW2 of the sidewall of the upper pattern of the lower electrode.

[0134] The thickness of the second upper electrode support 65 in the fourth direction DR4 may vary as the second upper electrode support 65 extends away from the upper pattern 191U of the lower electrode. As the second upper electrode support 65 extends away from the upper pattern 191U of the lower electrode (i.e., in the first direction DR1), the thickness of the second upper electrode support 65 in the fourth direction DR4 may decrease and then increase.

[0135] The second upper electrode support 65 may include an upper surface 65US and a bottom surface 65BS opposite to each other in the fourth direction DR4. The bottom surface 65BS of the second upper electrode support may face the second lower electrode support 55.

[0136] The second sub-top pattern 191U2 may protrude beyond the upper surface 65US of the second upper electrode support in the fourth direction DR4. For example, in a cross-sectional view, the upper surface 65US of the second upper electrode support may be flat.

[0137] In a cross-sectional view, the bottom surface 65BS of the second upper electrode support may include a plurality of inclined surfaces. The bottom surface 65BS of the second upper electrode support may include a third bottom inclined surface 65BS1 and a fourth bottom inclined surface 65BS2. Each of the third bottom inclined surface 65BS1 and the fourth bottom inclined surface 65BS2 may be a curved inclined surface. Different from that shown, each of the third bottom inclined surface 65BS1 and the fourth bottom inclined surface 65BS2 may be a flat inclined surface.

[0138] The second upper electrode support 65 may include at least one of, for example, silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon oxycarbonitride.

[0139] Figure 16 is a layout of a semiconductor memory device according to some implementations. Figure 17 only shows Figure 16 the layout of the word lines and cell active regions in Figure 18 is a cross-sectional view taken along Figure 16 A-A in

[0140] For reference, Figure 16 shows an example layout of a DRAM (Dynamic Random Access Memory) other than the data storage pattern DSP. The present disclosure is not limited thereto.

[0141] In addition, Figure 16 the first direction DR1 in Figure 1 corresponds to the first direction DR1 in Figure 16 the second direction DR2 in Figure 1 may correspond to the second direction DR2 in Figure 16 The present disclosure is not limited thereto. Different from that described above, Figure 1 the first direction DR1 in Figure 16 may correspond to the second direction DR2 in Figure 1 and the second direction DR2 in

[0142] Referring to Figure 16 and Figure 17 a semiconductor memory device according to some implementations may include a plurality of cell active regions ACT.

[0143] The cell active region ACT may be formed by a substrate ( Figure 18The unit element isolation film 105 formed within (100) defines. According to the simplification of the design rules of the semiconductor memory device, the unit active region ACT can extend in the form of a strip extending diagonally or obliquely, as shown in the figure. For example, the unit active region ACT can extend in the third direction DR3.

[0144] A plurality of gate electrodes can extend in the first direction DR1 across the unit active region ACT. The plurality of gate electrodes can extend parallel to each other. For example, the plurality of gate electrodes can be a plurality of word lines WL. The word lines WL can be spaced apart from each other at equal intervals. The width of each word line WL or the spacing between the word lines WL can be determined according to the design rules.

[0145] Two word lines WL extending in the first direction DR1 can divide each unit active region ACT into three parts. The unit active region ACT can include a storage connection region 103b and a bit line connection region 103a. The bit line connection region 103a can be located in the middle part of the unit active region ACT, while the storage connection region 103b can be located at each of the two opposite ends of the unit active region ACT.

[0146] For example, the bit line connection region 103a can be a region connected to the bit line BL, and the storage connection region 103b can be a region connected to the data storage pattern ( Figure 18 DSP in). In other words, the bit line connection region 103a can correspond to the common drain region, and the storage connection region 103b can correspond to the source region. Each word line WL and the adjacent bit line connection region 103a and storage connection region 103b can form a transistor.

[0147] On the word line WL, a plurality of bit lines BL extending in the second direction DR2 orthogonal to the word line WL can be provided. The plurality of bit lines BL can extend parallel to each other. The bit lines BL can be spaced apart from each other at equal intervals. The width of the bit line BL or the spacing between the bit lines BL can be determined according to the design rules.

[0148] The fourth direction DR4 can be perpendicular to the first direction DR1, the second direction DR2, and the third direction DR3.

[0149] The semiconductor memory device according to some implementations can include various contact arrangements formed on the unit active region ACT. The various contact arrangements can include, for example, a direct contact DC, a buried contact BC, and a landing pad LP.

[0150] In this regard, the direct contact DC can mean a contact that electrically connects the unit active region ACT and the bit line BL to each other. The buried contact BC can mean a contact that connects the unit active region ACT to the lower electrode ( Figure 18 191 in) of the data storage pattern ( Figure 18 DSP in).

[0151] Due to the layout structure, the contact area between the buried contact BC and the cell active region ACT may be small. Therefore, a conductive landing pad LP can be introduced to increase its contact area with the cell active region ACT and its contact area with the lower electrode of the data storage pattern ( Figure 18 in 191).

[0152] In a semiconductor memory device according to some implementations, the landing pad LP can be disposed between the buried contact BC and the lower electrode of the data storage pattern ( Figure 18 of 191). The contact area can be increased by introducing the landing pad LP, so that the contact resistance between the cell active region ACT and the lower electrode of the data storage pattern ( Figure 18 in 191) can be reduced.

[0153] For example, Figure 1 , Figure 7 , Figures 10 to 12 and Figure 14 the conductive pattern 30 in can correspond to the landing pad LP.

[0154] In a semiconductor memory device according to some implementations, the direct contact DC can be set to overlap with the central portion of the cell active region ACT. The buried contact BC can be set to overlap with each of two opposite ends of the cell active region ACT. The direct contact DC can be connected to the bit line connection region 103a. The buried contact BC can be connected to the storage connection region 103b.

[0155] Since the buried contact BC is set to overlap with each of two opposite ends of the cell active region ACT, the landing pad LP can be set to be adjacent to each of two opposite ends of the cell active region ACT and can overlap with a part of the buried contact BC. In other words, the buried contact BC can be formed to overlap with a part of the cell active region ACT and a part of the cell element isolation film ( Figure 18 in 105) between adjacent word lines WL and between adjacent bit lines BL.

[0156] The word line WL can be buried in the substrate 100. The word line WL can extend across the portion of the cell active region ACT between the direct contact DC and the buried contact BC.

[0157] As shown, two word lines WL can extend across one cell active region ACT. Since the cell active region ACT extends in the diagonal direction, the word line WL can have an angle less than 90 degrees with respect to the cell active region ACT.

[0158] The direct contacts DC can be symmetrically arranged. The buried contacts BC can be symmetrically arranged. Accordingly, the direct contacts DC can be arranged in a straight line along each of a first direction DR1 and a second direction DR2. The buried contacts BC can be arranged in a straight line along each of the first direction DR1 and the second direction DR2.

[0159] In one example, different from the direct contacts DC and the buried contacts BC, the landing pads LP can be arranged in a zigzag pattern in the second direction DR2 in which the bit lines BL extend. Additionally, the landing pads LP can be arranged in a first direction DR1 (along which the word lines WL extend) so as to overlap the same sides of the corresponding bit lines BL, respectively.

[0160] For example, the landing pads LP arranged in a first row in the first direction can overlap the left portions of the corresponding bit lines BL, respectively. The landing pads LP arranged in a second row in the first direction can overlap the right portions of the corresponding bit lines BL, respectively.

[0161] Reference Figures 16 to 18 , a semiconductor memory device according to some implementations can include a plurality of bit line structures 140ST, a plurality of memory contacts 120, a plurality of bit line contacts 146, and a data storage pattern DSP.

[0162] The cell element isolation film 105 can be disposed within the substrate 100. The cell element isolation film 105 can have a STI (shallow trench isolation) structure having excellent element isolation capabilities. The cell element isolation film 105 can define a cell active region ACT in the memory cell region.

[0163] The cell active region ACT defined by the cell element isolation film 105 can have an elongated island shape that includes a short axis and a long axis, as Figure 16 and Figure 17 shown. The cell active region ACT can have an inclined shape with an angle less than 90 degrees with respect to the word line WL formed in the cell element isolation film 105. Additionally, the cell active region ACT can have an inclined shape with an angle less than 90 degrees with respect to the bit line BL formed on the cell element isolation film 105.

[0164] The cell element isolation film 105 can include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. However, the present disclosure is not limited thereto.

[0165] The cell element isolation film 105 is shown as being formed as one insulating film. However, this is for illustrative purposes only. The present disclosure is not limited thereto. Depending on the spacing between adjacent cell active regions ACT, the cell element isolation film 105 can be formed as one insulating film or can be formed as a plurality of insulating films.

[0166] In Figure 18In [the figure], the upper surface of the unit element isolation film 105 and the upper surface of the substrate 100 are shown to be coplanar with each other. However, this is only for ease of illustration. The present disclosure is not limited thereto.

[0167] The bit line structure 140ST may include a unit conductive wire 140, a unit wire capping film 144, and a bit line spacer 150.

[0168] The unit conductive wire 140 may be disposed on the substrate 100 and the unit element isolation film 105 in which the word line WL is formed. The unit conductive wire 140 may intersect the unit element isolation film 105 and the unit active region ACT defined by the unit element isolation film 105. The unit conductive wire 140 may intersect the word line WL. In this regard, the unit conductive wire 140 may correspond to the bit line BL. For example, the unit conductive wire 140 may be Figure 16 the bit line BL in [the figure].

[0169] For example, the unit conductive wire 140 may include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a two-dimensional material (2D material), and a metal.

[0170] The unit conductive wire 140 is shown as being implemented as a single film. This is only for ease of illustration, and the present disclosure is not limited thereto. That is, different from what is shown, the unit conductive wire 140 may include a stack of multiple conductive films.

[0171] The unit wire capping film 144 may be disposed on the unit conductive wire 140. The unit wire capping film 144 may extend along the upper surface of the unit conductive wire 140 and in the second direction DR2. For example, the unit wire capping film 144 may include at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.

[0172] In a semiconductor memory device according to some implementations, the unit wire capping film 144 may include a silicon nitride film. Although the unit wire capping film 144 is shown as being implemented as a single film, the present disclosure is not limited thereto.

[0173] The bit line spacer 150 may be disposed on sidewalls of each of the unit conductive wire 140 and the unit wire capping film 144. The bit line spacer 150 extends in a manner elongated in the second direction DR2.

[0174] The bit line spacer 150 is shown as a single film. This is only for ease of illustration, and the present disclosure is not limited thereto. That is, in another example, different from what is shown, the bit line spacer 150 may have a multi-layer structure. The bit line spacer 150 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, or a combination thereof. However, the present disclosure is not limited thereto.

[0175] The cell insulating film 130 may be disposed on the substrate 100 and the cell element isolation film 105. More specifically, the cell insulating film 130 may be disposed on the upper surfaces of the cell element isolation film 105 and the substrate 100 in an area where the bit line contact 146 and the storage contact 120 are not formed. The cell insulating film 130 may be formed between the substrate 100 and the cell conductive line 140 and between the cell element isolation film 105 and the cell conductive line 140.

[0176] The cell insulating film 130 may be a single film. However, as shown, the cell insulating film 130 may be implemented as a stack of films including a first cell insulating film 131 and a second cell insulating film 132. For example, the first cell insulating film 131 may include a silicon oxide film, and the second cell insulating film 132 may include a silicon nitride film. The present disclosure is not limited thereto. Different from what is shown, the cell insulating film 130 may be implemented as a stack of three-layer films including a silicon oxide film, a silicon nitride film, and a silicon oxide film. The present disclosure is not limited thereto.

[0177] The bit line contact 146 may be disposed between the cell conductive line 140 and the substrate 100. The cell conductive line 140 may be disposed on the bit line contact 146.

[0178] The bit line contact 146 may be disposed between the bit line connection region 103a of the cell active region ACT and the cell conductive line 140. The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100 to each other. The bit line contact 146 may be connected to the bit line connection region 103a.

[0179] The bit line contact 146 may include an upper surface 146US connected to the cell conductive line 140. It is shown that as the bit line contact extends away from the upper surface 146US of the bit line contact, the width of the bit line contact 146 in the first direction DR1 is constant. This is only for ease of illustration, and the present disclosure is not limited thereto.

[0180] The bit line contact 146 may correspond to a direct contact DC. For example, the bit line contact 146 may include at least one of a doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a metal, and a metal alloy.

[0181] In an area where the cell conductive line 140 overlaps with the bit line contact 146, the bit line spacer 150 may be disposed on the substrate 100 and the cell element isolation film 105. The bit line spacer 150 may be disposed on the sidewalls of each of the cell conductive line 140, the cell line cover film 144, and the bit line contact 146.

[0182] In the remaining region where the unit conductive wire 140 does not overlap with the bit line contact 146, the bit line spacer 150 may be provided on the unit insulating film 130. The bit line spacer 150 may be provided on the sidewalls of each of the unit conductive wire 140 and the unit wire cover film 144.

[0183] The storage contact 120 may be provided between the unit conductive wires 140 adjacent to each other in the first direction DR1. The storage contact 120 may be provided on each of the two opposite sides of the unit conductive wire 140. More specifically, the storage contact 120 may be provided between the bit line structures 140ST. The storage contact 120 may be provided between the word lines WL adjacent to each other in the second direction DR2.

[0184] The storage contact 120 may overlap with the substrate 100 and the unit element isolation film 105 in the region between the adjacent unit conductive wires 140. The storage contact 120 may be connected to the unit active region ACT. More specifically, the storage contact 120 may be connected to the storage connection region 103b. In this regard, the storage contact 120 may correspond to a buried contact ( Figure 16 BC in

[0185] For example, the storage contact 120 may include at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a conductive metal oxide, and a metal.

[0186] The storage pad 160 may be provided on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may be connected to the storage connection region 103b of the unit active region ACT. In this regard, the storage pad 160 may correspond to a landing pad ( Figure 16 LP in

[0187] The storage pad 160 may overlap with a part of the upper surface of the bit line structure 140ST. For example, the storage pad 160 may include at least one of a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a metal.

[0188] The pad isolation insulating film 180 may be provided on the storage pad 160 and the bit line structure 140ST. For example, the pad isolation insulating film 180 may be provided on the unit wire cover film 144.

[0189] The pad isolation insulating film 180 can define the storage pads 160 into each of a plurality of isolated regions. The pad isolation insulating film 180 may not cover the upper surface 160US of the storage pads. For example, the vertical level of the upper surface 160US of the storage pads based on the upper surface of the substrate 100 may be equal to the vertical level of the upper surface 180US of the pad isolation insulating film based on the upper surface of the substrate 100.

[0190] The pad isolation insulating film 180 includes an insulating material and can electrically insulate the plurality of storage pads 160 from each other. For example, the pad isolation insulating film 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbonitride film, and a silicon carbonitride film. The present disclosure is not limited thereto.

[0191] The second etch stop film 195 may be disposed on the upper surface 160US of the storage pads and the upper surface 180US of the pad isolation insulating film. For example, the second etch stop film 195 may correspond to Figure 1 , Figure 7 , Figures 10 to 12 , Figure 14 the first etch stop film 25 among

[0192] For example, the second etch stop film 195 may include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), and silicon boron nitride (SiBN).

[0193] The data storage pattern DSP may be disposed on the storage pads 160. The data storage pattern DSP is electrically connected to the storage pads 160. A part of the data storage pattern DSP may be disposed within the second etch stop film 195.

[0194] The data storage pattern DSP may include, for example, a capacitor. The data storage pattern DSP includes a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. The lower electrode 191 may include a lower pattern 191B of the lower electrode and an upper pattern 191U of the lower electrode.

[0195] The first lower electrode support 50 and the second lower electrode support 55 may support the lower electrode 191. The first lower electrode support 50 and the second lower electrode support 55 may contact the lower pattern 191B of the lower electrode.

[0196] The first upper electrode support 60 may be disposed on the lower electrode 191. The first upper electrode support 60 may contact the upper pattern 191U of the lower electrode.

[0197] The description of the lower electrode 191, the capacitor dielectric film 192, and the upper electrode 193 may be the same as that used above Figures 1 to 15Those described above are substantially the same and are thus omitted below.

[0198] The description of the first lower electrode support 50, the second lower electrode support 55, and the first upper electrode support 60 can be substantially the same as those used above Figures 1 to 15 and are thus omitted below.

[0199] Figure 19 and Figure 20 are diagrams for showing a semiconductor memory device according to some implementations. For convenience, the following description is based on the differences from those used above Figures 16 to 18 described.

[0200] For reference, Figure 19 is a layout of a semiconductor memory device according to some implementations. Figure 20 is Figure 19 a cross-sectional view taken along A-A in

[0201] Referring to Figure 17 , Figure 19 and Figure 20 , a semiconductor memory device according to some implementations may include a node pad XP disposed on a substrate 100.

[0202] The node pad XP may be provided to replace Figure 16 the buried contact BC in

[0203] Due to the structural arrangement, the contact area between the node pad XP and the cell active region ACT may be small. Thus, a conductive landing pad LP may be introduced to expand the contact area with the cell active region ACT and the lower electrode 191 of the data storage pattern DSP.

[0204] Since the node pad XP is provided to overlap with each of two opposite ends of the cell active region ACT, the landing pad LP may be provided to be adjacent to each of two opposite ends of the cell active region ACT and overlap at least a part of the node pad XP. In other words, the node pad XP may be formed to overlap with the cell active region ACT and the cell element isolation film 105 in a region between adjacent word lines WL and a region between adjacent bit lines BL.

[0205] The word line WL can extend across the portion of the unit active region ACT between the direct contact DC and the node pad XP. The direct contacts DC can be symmetrically arranged. The node pads XP can be symmetrically arranged. Accordingly, the direct contacts DC can be arranged in a straight line in each of the first direction DR1 and the second direction DR2. The node pads XP can be arranged in a straight line in each of the first direction DR1 and the second direction DR2.

[0206] The node contact pad 125 can be disposed on the substrate 100 and the unit element isolation film 105. The node contact pad 125 can be disposed on the upper surface of the unit element isolation film 105.

[0207] The bottom surface of the node contact pad 125 can be disposed on the upper surface of the unit element isolation film 105. The bottom surface of the node contact pad 125 can contact the upper surface of the unit element isolation film 105. For example, the entire node contact pad 125 can be disposed on the upper surface of the substrate 100. In this regard, the node contact pad 125 can correspond to the node pad XP.

[0208] Based on the upper surface of the unit element isolation film 105, the vertical level of the upper surface 125US of the node contact pad can be lower than the vertical level of the upper surface 146US of the bit line contact. Based on the upper surface of the unit element isolation film 105, the vertical level of the upper surface 125 of the node contact pad can be lower than the vertical level of the bottom surface of the unit conductive line 140.

[0209] The contact isolation structure 145ST can separate the node contact pads 125 adjacent to each other in the first direction DR1 from each other. Although not shown, the contact isolation structure 145ST can separate the node contact pads 125 adjacent to each other in the second direction DR2 from each other. The contact isolation structure 145ST covers the upper surface 125US of the node contact pad.

[0210] The contact isolation structure 145ST can include a contact isolation pattern 145 and an upper unit insulating film 135. The upper unit insulating film 135 can be disposed on the contact isolation pattern 145.

[0211] When the node contact pad 125 includes a first node contact pad and a second node contact pad spaced apart from each other in the first direction DR1, the contact isolation pattern 145 can isolate the first node contact pad and the second node contact pad from each other in the first direction DR1. Although not shown, the contact isolation pattern 145 can isolate the node contact pads 125 adjacent to each other in the second direction DR2 from each other.

[0212] The entire upper surface 125US of the node contact pad may not be in contact with the entire storage pad 160. In other words, the width of the interface between the node contact pad 125 and the storage pad 160 in the first direction DR1 may be less than the width of the upper surface 125US of the node contact pad in the first direction DR1.

[0213] The bit line spacer 150 may be disposed on the upper surface 125US of the node contact pad.

[0214] The upper cell insulating film 135 covers the upper surface 125US of the node contact pad. When the node contact pad 125 includes a first node contact pad and a second node contact pad spaced apart from each other in the first direction DR1, the upper cell insulating film 135 may cover the upper surface of the first node contact pad and the upper surface of the second node contact pad.

[0215] The upper surface 135US of the upper cell insulating film may be coplanar with the upper surface 146US of the bit line contact. That is, based on the upper surface of the cell element isolation film 105, the vertical level of the upper surface 135US of the upper cell insulating film may be equal to the vertical level of the upper surface 146US of the bit line contact.

[0216] The cell conductive line 140 may be disposed on the upper surface of the contact isolation structure 145ST. The cell conductive line 140 may be disposed on the upper surface 135US of the upper cell insulating film. The upper surface of the contact isolation structure 145ST may be the upper surface 135US of the upper cell insulating film. The upper surface of the contact isolation structure 145ST may be coplanar with the bottom surface of the cell conductive line 140.

[0217] For example, the contact isolation pattern 145 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The upper cell insulating film 135 may be a single film. However, as shown, the upper cell insulating film 135 may be implemented as a stack of films including a first upper cell insulating film 136 and a second upper cell insulating film 137. For example, the first upper cell insulating film 136 may include a silicon oxide film, and the second upper cell insulating film 137 may include a silicon nitride film. The present disclosure is not limited thereto. The width of the upper cell insulating film 135 in the first direction DR1 is shown to decrease as the upper cell insulating film 135 extends away from the substrate 100. The present disclosure is not limited thereto.

[0218] Figure 21 is a layout diagram for showing a semiconductor memory device according to some implementations. Figure 22 is a perspective view for showing a semiconductor memory device according to some implementations. Figure 23 is along Figure 21Cross-sectional views taken along lines B-B and C-C.

[0219] For ease of explanation, Figure 23 the first lower electrode support 50, the second lower electrode support 55, and the first upper electrode support 60 are not included.

[0220] Referring to Figures 21 to 23 , according to some implementations, a semiconductor memory device may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a data storage pattern DSP.

[0221] According to some implementations, a semiconductor memory device may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel layer 430 extends in a vertical direction from the substrate 100.

[0222] The lower insulating layer 412 may be disposed on the substrate 100. A plurality of first conductive lines 420 may be disposed on the lower insulating layer 412, and may be spaced apart from each other in a first direction DR1 and extend in a second direction DR2. A plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 so as to fill the space between adjacent first conductive lines among the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend in the second direction DR2. The upper surfaces of the plurality of first insulating patterns 422 may be at the same vertical level as the upper surfaces of the plurality of first conductive lines 420. Each of the plurality of first conductive lines 420 may be used as a bit line.

[0223] Each of the plurality of first conductive lines 420 may include at least one of a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, and a combination thereof. For example, each of the plurality of first conductive lines 420 may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and a combination thereof, but is not limited thereto. Each of the plurality of first conductive lines 420 may include a single layer or a multi-layer made of the foregoing materials. In some implementations, each of the plurality of first conductive lines 420 may include graphene, a carbon nanotube, or a combination thereof.

[0224] The channel layer 430 may have a matrix form, in which the channels are spaced apart from each other in each of a first direction DR1 and a second direction DR2, and are respectively disposed on a plurality of first conductive lines 420. Each channel of the channel layer 430 may have a first width in accordance with the first direction DR1 and a first vertical dimension in accordance with a fourth direction DR4, where the first vertical dimension may be greater than the first width. In this regard, the fourth direction DR4 may intersect the first direction DR1 and the second direction DR2, and may be, for example, a direction perpendicular to the upper surface of the substrate 100. For example, the first vertical dimension may be about 2 to 10 times the first width. However, the present disclosure is not limited thereto. The bottom portion of each channel of the channel layer 430 may be used as a third source / drain region (not shown), while the top portion of each channel of the channel layer 430 may be used as a fourth source / drain region (not shown). A portion of each channel of the channel layer 430 between the third source / drain region and the fourth source / drain region may be used as a channel region (not shown).

[0225] In one example, the channel layer 430 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yO or a combination thereof. The channel layer 430 may include a single layer or multiple layers made of an oxide semiconductor. In some examples, the channel layer 430 may have a bandgap energy greater than that of silicon. For example, the channel layer 430 may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, when the channel layer 430 has a bandgap energy of about 2.0 eV to 4.0 eV, the channel layer 430 may have optimal channel performance. For example, the channel layer 430 may be made of a polycrystalline material or an amorphous material (e.g., amorphous silicon), but is not limited thereto. In another example, the channel layer 430 may include graphene, carbon nanotubes, or a combination thereof. In yet another example, the channel layer 430 may include a silicon-based semiconductor material. The channel layer 430 may include a single-crystal semiconductor material. For example, the channel layer 430 may include single-crystalline silicon or single-crystalline silicon germanium. The present disclosure is not limited thereto.

[0226] The gate electrode 440 may extend in a first direction DR1 and may be formed on two sidewalls of each channel of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing a first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing a second sidewall of the channel layer 430 opposite to the first sidewall. Since one channel of the channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device may have a double-gate transistor structure. However, the present disclosure is not limited thereto. The second sub-gate electrode 440P2 may be omitted, and thus only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 may be formed, thereby realizing a single-gate transistor structure.

[0227] The gate electrode 440 may include at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The gate electrode 440 may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO x 、RuO x and at least one of their combinations. The present disclosure is not limited thereto.

[0228] The gate insulating film 450 surrounds the sidewalls of each channel of the channel layer 430 and may be interposed between each channel of the channel layer 430 and the gate electrode 440. For example, asFigure 21 As shown, the entire sidewall of each channel of the channel layer 430 can be surrounded by the gate insulating film 450, and a part of the sidewall of the gate electrode 440 can contact the gate insulating film 450. In other implementations, the gate insulating film 450 can extend in the extending direction of the gate electrode 440 (i.e., the first direction DR1), and only two sidewalls among all the sidewalls of each channel of the channel layer 430 that face the gate electrode 440 can contact the gate insulating film 450.

[0229] For example, the gate insulating film 450 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material can include, for example, at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. However, the implementations of the present disclosure are not limited thereto.

[0230] The plurality of second insulating patterns 432 can extend along the second direction DR2 and can be respectively disposed on the plurality of first insulating patterns 422. Each channel of the channel layer 430 can be disposed between two adjacent second insulating patterns 432 among the plurality of second insulating patterns 432. In addition, the first buried layer 434 and the second buried layer 436 can be disposed between two adjacent second insulating patterns 432 and in the space between two adjacent channels of the channel layer 430. The first buried layer 434 can occupy the bottom portion of the space between two adjacent channels of the channel layer 430. The second buried layer 436 can be formed to fill the remaining portion of the space between the two adjacent channels of the channel layer 430 and can be disposed on the first buried layer 434. The upper surface of the second buried layer 436 can be coplanar with the upper surface of the channel layer 430, and the second buried layer 436 can cover the upper surface of the gate electrode 440. Optionally, each of the plurality of second insulating patterns 432 and each of the plurality of first insulating patterns 422 can form a continuous material layer and thus can be monolithic. Optionally, the second buried layer 436 and the first buried layer 434 can form a continuous material layer and thus can be monolithic.

[0231] Each capacitor contact 460 may be disposed over each channel of the channel layer 430. Each capacitor contact 460 may vertically overlap each channel of the channel layer 430. Accordingly, the capacitor contacts 460 may be arranged in a matrix form, in which the capacitor contacts 460 are spaced apart from each other in each of a first direction DR1 and a second direction DR2. The capacitor contacts 460 may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x and combinations thereof, but is not limited thereto. The upper insulating layer 462 may surround sidewalls of each capacitor contact 460 and may be disposed over the plurality of second insulating patterns 432 and the second buried layer 436.

[0232] A third etch stop film 470 may be disposed over the upper insulating layer 462. A data storage pattern DSP may be disposed over the third etch stop film 470. The data storage pattern DSP may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. The lower electrode 191 may extend through the third etch stop film 470 and may be electrically connected to an upper surface of the capacitor contact 460.

[0233] In an illustrative implementation, the lower electrode 191 may vertically overlap the capacitor contact 460. The lower electrodes 191 may be arranged in a matrix form, in which the lower electrodes 191 are spaced apart from each other in each of the first direction DR1 and the second direction DR2. Optionally, landing pads (not shown) may be further disposed between the capacitor contacts 460 and the lower electrodes 191, and accordingly, the lower electrodes 191 may be arranged in a hexagonal shape.

[0234] The description of the lower electrode 191, the capacitor dielectric film 192, and the upper electrode 193 may be substantially the same as those described above using Figures 1 to 15 and thus is omitted below.

[0235] Although in Figure 23 the first lower electrode support 50, the second lower electrode support 55, and the first upper electrode support 60 are not shown, the description of the first lower electrode support 50, the second lower electrode support 55, and the first upper electrode support 60 may be substantially the same as those described above using Figures 1 to 15 and thus is omitted.

[0236] Figure 24 is a layout diagram for illustrating a semiconductor memory device according to some implementations. Figure 25is a perspective view for showing a semiconductor memory device according to some implementations. Figure 26 is a view for showing a semiconductor memory device according to some implementations.

[0237] Reference Figure 24 and Figure 25 According to some implementations, a semiconductor memory device may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a data storage pattern DSP. The semiconductor memory device according to some implementations may be a memory device including a vertical channel transistor (VCT).

[0238] A plurality of active regions AC may be defined in the substrate 100 by a first element isolation pattern 412A and a second element isolation pattern 414A. The channel structure 430A may be disposed in each active region AC. The channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2 extending in a vertical direction and a connection member 430L connecting a bottom portion of the first active pillar 430A1 and a bottom portion of the second active pillar 430A2. A first source / drain region SD1 may be disposed in the connection member 430L. A second source / drain region SD2 may be disposed in a top portion of each of the first active pillar 430A1 and the second active pillar 430A2. Each of the first active pillar 430A1 and the second active pillar 430A2 may constitute an independent unit memory cell.

[0239] A plurality of first conductive lines 420A may extend in a direction intersecting the plurality of active regions AC. For example, the plurality of first conductive lines 420A may extend in a second direction DR2. One of the plurality of first conductive lines 420A may be disposed on the connection member 430L and between the first active pillar 430A1 and the second active pillar 430A2. One first conductive line 420A may be disposed on the first source / drain region SD1. Another first conductive line 420A adjacent to the one first conductive line 420A may be disposed between two channel structures 430A. One of the plurality of first conductive lines 420A may be used as a common bit line that commonly includes two unit memory cells respectively corresponding to the first active pillar 430A1 and the second active pillar 430A2 disposed on both sides of the one first conductive line 420A.

[0240] A contact gate electrode 440A can be disposed between two channel structures 430A adjacent to each other in a second direction DR2. For example, the contact gate electrode 440A can be disposed between a first active pillar 430A1 included in one channel structure 430A and a second active pillar 430A2 of the channel structure 430A adjacent to the said one channel structure 430A. A contact gate electrode 440A can be shared by the first active pillar 430A1 and the second active pillar 430A2 respectively disposed on its two sidewalls. A gate insulating film 450A can be disposed between the contact gate electrode 440A and the first active pillar 430A1 and between the contact gate electrode 440A and the second active pillar 430A2. A plurality of second conductive lines 442A can extend in a first direction DR1. Each of the plurality of second conductive lines 442A can be disposed on the upper surface of each contact gate electrode 440A. Each of the plurality of second conductive lines 442A can serve as a word line of the semiconductor memory device.

[0241] A capacitor contact 460A can be disposed on the channel structure 430A. The capacitor contact 460A can be disposed on a second source / drain region SD2. A data storage pattern DSP can be disposed on the capacitor contact 460A.

[0242] Reference Figure 26 , according to some implementations, a semiconductor memory device can have a COP (Cell On Periphery) structure, in which a cell array region CA is disposed on a peripheral structure region PA.

[0243] The cell array region CA can include Figures 21 to 25 vertical channel transistors VCT therein. In the peripheral structure region PA, sense transistors, transfer transistors, drive transistors, etc. connected to Figures 21 to 25 the vertical channel transistors can be disposed.

[0244] Figures 27 to 31 is a diagram of an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor memory device according to some implementations. For convenience, content that is repetitive with the content described using Figures 1 to 11 is briefly described, or its description is omitted.

[0245] Reference Figure 27 , an interlayer insulating film 20 can be formed on a substrate 100.

[0246] A conductive pattern 30 can be formed in the interlayer insulating film 20. A first etch stop film 25 can be formed on the conductive pattern 30 and the interlayer insulating film.

[0247] A first mold insulating film 31, a first lower electrode support film 50L, a second mold insulating film 32, and a second lower electrode support film 55L can be sequentially formed on the first etch stop film 25.

[0248] Each of the first mold insulating film 31 and the second mold insulating film 32 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The present disclosure is not limited thereto.

[0249] Each of the first lower electrode support film 50L and the second lower electrode support film 55L may include at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon oxycarbonitride. The present disclosure is not limited thereto.

[0250] Lower electrode holes 191H may be formed in the first lower electrode support film 50L and the second lower electrode support film 55L, and the first mold insulating film 31 and the second mold insulating film 32.

[0251] The lower electrode holes 191H may extend through the first etch stop film 25. The lower electrode holes 191H may expose the conductive pattern 30.

[0252] Reference Figure 27 and Figure 28 , a lower pattern 191B of the lower electrode may be formed on the conductive pattern 30.

[0253] The lower pattern 191B of the lower electrode may be formed within the lower electrode holes 191H. The lower pattern 191B of the lower electrode fills the lower electrode holes 191H. While forming the lower pattern 191B of the lower electrode, a lower inner interface 191B_IF may be formed within the lower pattern 191B of the lower electrode.

[0254] The lower pattern 191B of the lower electrode may be formed, for example, by atomic layer deposition (ALD). The present disclosure is not limited thereto. The lower pattern 191B of the lower electrode may be formed along the sidewalls and bottom surface of the lower electrode holes 191H and may then finally fill the entire lower electrode holes 191H. When forming the lower pattern 191B of the lower electrode, the thickness of each of the two lower patterns 191B of the lower electrode formed on two opposite sidewalls of the lower electrode holes 191H increases such that the two lower patterns 191B of the lower electrode meet each other. In a cross-sectional view, the lower patterns 191B of the lower electrode are respectively formed on opposite sidewalls of the lower electrode holes 191H. Where the lower patterns 191B meet each other, the lower inner interface 191B_IF is formed.

[0255] Reference Figure 29 and

[0256] The upper pattern 191U of the lower electrode may protrude beyond the second lower electrode support film 55L in the fourth direction DR4.

[0257] The upper pattern 191U of the lower electrode can be formed using a selective growth method. The selective growth method can be, for example, a method of selectively depositing a conductive material on a conductive material.

[0258] Reference Figure 30 , a first upper electrode support film 60L can be formed on the upper pattern 191U of the lower electrode.

[0259] The first upper electrode support film 60L can contact a part of the sidewall of the upper pattern 191U of the lower electrode. In a method of manufacturing a semiconductor memory device according to some implementations, the first upper electrode support film 60L can contact the upper surface of the upper pattern 191U of the lower electrode.

[0260] In one example, the first upper electrode support film 60L can be formed using a deposition method with poor step coverage. Between the upper patterns 191U of adjacent lower electrodes, the bottom surface of the first upper electrode support film 60L facing the second lower electrode support film 55L can include a plurality of inclined surfaces. There can be a space where the insulating material is not filled between the first upper electrode support film 60L and the second lower electrode support film 55L. The present disclosure is not limited thereto.

[0261] In another example, the first upper electrode support film 60L can be formed using a deposition method with good step coverage. In this case, different from what is shown, the first upper electrode support film 60L can be formed in the same shape as the shape of the first upper electrode support 60 described using Figures 7 to 9 Before forming the first upper electrode support film 60L, a sacrificial mold insulating film can be formed on the second lower electrode support film 55L. The sacrificial mold insulating film can cover a part of the sidewall of the upper pattern 191U of the lower electrode.

[0262] Reference Figure 30 and Figure 31 , the first upper electrode support 60 can be formed by patterning the first upper electrode support film 60L.

[0263] If the sacrificial mold insulating film is formed on the second lower electrode support film 55L, the sacrificial mold insulating film can be removed.

[0264] Subsequently, the second lower electrode support film 55L can be patterned to form the second lower electrode support 55. When forming the second lower electrode support 55, the second mold insulating film 32 can be exposed.

[0265] Using wet etching, the second mold insulating film 32 can be removed. The second mold insulating film 32 can be removed so as to expose the first lower electrode support film 50L.

[0266] Subsequently, the first lower electrode support film 50L can be patterned to form the first lower electrode support 50. Accordingly, the first mold insulating film 31 can be exposed. Subsequently, using wet etching, the first mold insulating film 31 can be removed.

[0267] Subsequently, referring to Figure 1 , a capacitor dielectric film 192 and an upper electrode 193 can be formed.

[0268] Figures 32 to 35 FIG. is a diagram of an intermediate structure corresponding to an intermediate step of a method of manufacturing a semiconductor memory device according to some implementations. For convenience, content that is repetitive of that described using Figures 14 to 15 is briefly described or its description is omitted.

[0269] For reference, Figure 32 can be a manufacturing process that occurs after Figure 28 .

[0270] Referring to Figure 32 , a first sub-upper pattern 191U1 can be formed on the lower pattern 191B of the lower electrode.

[0271] The first sub-upper pattern 191U1 can protrude beyond the second lower electrode support film 55L in the fourth direction DR4. The first sub-upper pattern 191U1 can be formed using, for example, a selective growth method.

[0272] Subsequently, a second upper electrode support film 65L can be formed on the second lower electrode support film 55L.

[0273] The second upper electrode support film 65L can contact the sidewall of the first sub-upper pattern 191U1. The second upper electrode support film 65L can cover a part of the sidewall of the first sub-upper pattern 191U1.

[0274] For example, between the second upper electrode support film 65L and the second lower electrode support film 55L, there can be a space unfilled with an insulating material.

[0275] Referring to Figure 33 , a second sub-upper pattern 191U2 can be formed on the first sub-upper pattern 191U1.

[0276] The second sub-upper pattern 191U2 can protrude beyond the second upper electrode support film 65L in the fourth direction DR4. The second sub-upper pattern 191U2 can be formed using, for example, a selective growth method.

[0277] Referring to Figure 34 , a first upper electrode support film 60L can be formed on the second sub-upper pattern 191U2.

[0278] The first upper electrode support film 60L may contact a part of the sidewall of the second sub-upper pattern 191U2. In a method of manufacturing a semiconductor memory device according to some implementations, the first upper electrode support film 60L may contact the upper surface of the second sub-upper pattern 191U2.

[0279] Reference Figure 34 and Figure 35 , the first upper electrode support film 60L, the second upper electrode support film 65L, the second lower electrode support film 55L, and the first lower electrode support film 50L may be patterned, so that the first upper electrode support 60, the second upper electrode support 65, the second lower electrode support 55, and the first lower electrode support 50 may be formed.

[0280] In the process of forming the first upper electrode support 60, the second upper electrode support 65, the second lower electrode support 55, and the first lower electrode support 50, the first mold insulating film 31 and the second mold insulating film 32 may be removed by wet etching.

[0281] Different from that shown in Figures 32 to 35 , a sacrificial electrode support film may be formed instead of the second upper electrode support film 65L. The sacrificial electrode support film may be removed in the process of removing the second mold insulating film 32. In this case, the second upper electrode support 65 may not be formed near the boundary between the first sub-upper pattern 191U1 and the second sub-upper pattern 191U2, as shown in Figure 12 and Figure 13 .

[0282] Although implementations of the present disclosure have been described with reference to the accompanying drawings, the implementations of the present disclosure are not limited to the above implementations, but may be implemented in various different forms. Those skilled in the art can understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above-described implementations are not restrictive in all aspects, but illustrative.

[0283] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter. Certain features described in the context of separate implementations of the present disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although the features may be described as acting in certain combinations above, one or more features from the combination may be deleted in some cases, and the combination may be directed to a sub-combination or a variant of the sub-combination.

[0284] In summarizing the detailed description, those skilled in the art will recognize that various changes and modifications can be made to the preferred implementations without materially departing from the principles of the disclosure. Accordingly, the preferred implementations of the invention disclosed are for general and descriptive purposes only and not for purposes of limitation.

Claims

1. A semiconductor memory device, comprising: A conductive pattern disposed on a substrate; A lower electrode connected to the conductive pattern and extending in a first direction, wherein the lower electrode includes a lower pattern and an upper pattern, and wherein the lower pattern is disposed between the upper pattern and the conductive pattern; A capacitor dielectric film disposed on the lower electrode; And An upper electrode disposed on the capacitor dielectric film, Wherein the lower pattern includes a lower inner interface extending in the first direction, Wherein the upper pattern does not have an inner interface extending in the first direction.

2. The semiconductor memory device according to claim 1, wherein the lower inner interface extends to a bottom surface of the upper pattern.

3. The semiconductor memory device according to claim 1, wherein the upper pattern includes a plurality of sub-upper patterns disposed on the lower pattern and stacked in the first direction.

4. The semiconductor memory device according to claim 1, wherein the lower pattern and the upper pattern include the same material.

5. The semiconductor memory device according to claim 1, further comprising a first upper electrode support member that contacts an upper surface and a sidewall of the upper pattern, Wherein the first upper electrode support member includes a plate portion and a protrusion, Wherein the plate portion of the first upper electrode support member contacts the upper surface of the upper pattern, Wherein the protrusion of the first upper electrode support member protrudes from the plate portion of the first upper electrode support member and contacts the sidewall of the upper pattern.

6. The semiconductor memory device according to claim 5, wherein, As the protrusion extends away from a first sidewall of the upper pattern, the thickness of the protrusion of the first upper electrode support member decreases and then increases in the first direction.

7. The semiconductor memory device according to claim 5, further comprising a second upper electrode support member disposed between the first upper electrode support member and the conductive pattern, wherein the second upper electrode support member contacts the sidewall of the upper pattern, Among them, As the second upper electrode support member extends away from the first sidewall of the upper pattern, the thickness of the second upper electrode support member decreases and then increases in the first direction.

8. The semiconductor memory device according to claim 7, wherein the second upper electrode support member includes an upper surface and a bottom surface opposite to each other in the first direction, Wherein the upper surface of the second upper electrode support member is flat, Wherein the bottom surface of the second upper electrode support member faces the conductive pattern and includes a plurality of inclined surfaces.

9. The semiconductor memory device according to claim 1, further comprising a lower electrode support member that supports the lower electrode, wherein the lower electrode support member contacts a sidewall of the lower pattern, Wherein the lower electrode support member includes an upper surface and a bottom surface opposite to each other in the first direction, Wherein the bottom surface of the lower electrode support member faces the conductive pattern and is flat.

10. The semiconductor memory device according to claim 1, wherein a width of an upper surface of the lower pattern in a second direction is equal to a width of the upper pattern in the second direction.

11. The semiconductor memory device according to claim 1, wherein a width of an upper surface of the lower pattern in a second direction is smaller than a width of the upper pattern in the second direction.

12. A semiconductor memory device, comprising: a conductive pattern disposed on a substrate; a lower electrode connected to the conductive pattern and extending in a first direction, wherein the lower electrode includes a lower pattern and an upper pattern, and wherein the lower pattern is disposed between the upper pattern and the conductive pattern; a lower electrode support supporting the lower electrode and contacting a sidewall of the lower pattern; a capacitor dielectric film disposed on the lower electrode and the lower electrode support; and an upper electrode disposed on the capacitor dielectric film, wherein the lower electrode support includes an upper surface and a bottom surface opposite to each other in the first direction, wherein the bottom surface of the lower electrode support faces the conductive pattern, wherein the upper pattern protrudes beyond the upper surface of the lower electrode support in the first direction, wherein at a boundary between the lower pattern and the upper pattern, a first crystal orientation of the lower pattern is different from a second crystal orientation of the upper pattern.

13. The semiconductor memory device according to claim 12, wherein the first crystal orientation is a second direction orthogonal to the first direction, wherein the second crystal orientation is the first direction.

14. The semiconductor memory device according to claim 12, wherein each of the lower pattern and the upper pattern includes titanium nitride.

15. The semiconductor memory device according to claim 12, wherein the upper pattern includes a plurality of sub-upper patterns disposed on the lower pattern and stacked in the first direction.

16. The semiconductor memory device according to claim 12, further comprising a first upper electrode support contacting an upper surface and a sidewall of the upper pattern, wherein the first upper electrode support includes a plate portion and a protrusion, wherein the plate portion of the first upper electrode support contacts the upper surface of the upper pattern, wherein the protrusion of the first upper electrode support protrudes from the plate portion of the first upper electrode support and contacts the sidewall of the upper pattern.

17. The semiconductor memory device according to claim 16, wherein the first upper electrode support includes an upper surface and a bottom surface opposite to each other in the first direction, wherein the upper surface of the first upper electrode support is flat, wherein the bottom surface of the first upper electrode support faces the lower electrode support and includes a plurality of inclined surfaces.

18. The semiconductor memory device according to claim 16, wherein the bottom surface of the lower electrode support is flat.

19. A semiconductor memory device, comprising: a substrate including an active region defined by an element isolation film and extending in a first direction, wherein the active region includes a first portion and second portions defined on each of two opposite sides of the first portion; A word line, disposed in the substrate and the element isolation film, and extending in a second direction different from the first direction, wherein the word line extends across a region between the first portion and the second portion of the active region; A bit line contact, connected to the first portion of the active region; A bit line, disposed on the bit line contact and connected to the bit line contact, wherein the bit line extends in a third direction different from the first direction and the second direction; A landing pad, connected to the second portion of the active region; And A capacitor, Wherein the capacitor includes: A lower electrode, connected to the landing pad and extending in the third direction; A capacitor dielectric film, disposed on the lower electrode; and An upper electrode, disposed on the capacitor dielectric film, Wherein the lower electrode includes a lower pattern connected to the landing pad and an upper pattern disposed on the lower pattern, Wherein the lower pattern includes a lower inner interface extending in the third direction, Wherein the upper pattern does not have an inner interface extending in the third direction.

20. The semiconductor memory device according to claim 19, wherein the upper pattern includes a plurality of sub-upper patterns disposed on the lower pattern and stacked in the third direction.

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