Semiconductor memory device and forming method thereof

Abstract

The invention provides a semiconductor memory device and a forming method thereof, relates to the technical field of semiconductors, and is used for solving the problem that the diamagnetic capability and the area utilization rate of the existing semiconductor memory device cannot be improved at the same time. The semiconductor memory device comprises a spin orbit moment layer, and a first magnetic tunnel junction, a second magnetic tunnel junction and a spacer layer which are arranged on the spin orbit moment layer, the second magnetic tunnel junction is arranged in a penetrating opening of the first magnetic tunnel junction, the spacing layer is filled in a gap between the first magnetic tunnel junction and the second magnetic tunnel junction, and the first magnetic tunnel junction surrounds the outer side of the second magnetic tunnel junction, so that the magnetic interference resistance of the second magnetic tunnel junction is greatly improved; moreover, the pattern defined by the side wall, far away from the spacing layer, of the first magnetic tunnel junction is a circle or a convex polygon, and the geometric center of the first magnetic tunnel junction does not coincide with the geometric center of the spacing layer, so that the first magnetic tunnel junction can also be used for realizing field-free flipping and multi-state storage, and the area utilization rate of the semiconductor memory device is synchronously improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor memory device and a method for forming the same. Background Art

[0002] Magnetic memories in semiconductor memories are considered to be one of the main candidates for next-generation memory technologies. The core storage unit of a magnetic memory is a sandwich structure formed by a "ferromagnetic layer / oxide barrier layer / ferromagnetic layer". The magnetization direction of one ferromagnetic layer remains unchanged and is called the fixed layer; the magnetization direction of the other ferromagnetic layer can be changed by an external excitation and is called the free layer. When the magnetization direction of the free layer is parallel or antiparallel to that of the fixed layer, the magnetic tunnel junction is in a low-resistance state or a high-resistance state respectively, and the two resistance states can represent binary data "0" and "1" respectively.

[0003] According to different data writing mechanisms, the development of magnetic memories has undergone three generations of changes. Among them, spin-orbit torque magnetic memories are expected to be a key technology to break through the power consumption bottleneck of integrated circuits in the post-Moore era due to their advantages such as non-volatility, high-speed and low-power data writing, and high device durability. The basic storage unit structure is to add a spin-orbit torque layer adjacent to the free layer, and use the spin-polarized current generated by the current flowing through the spin-orbit torque layer to flip the magnetization direction of the free layer, thereby realizing data writing.

[0004] Since the information in spin-orbit torque magnetic memories is stored in the form of magnetic signals, in order to avoid interference from magnetic signals during writing by other components or magnetic signals in the environment to their data writing, it is necessary to improve the anti-magnetic interference ability of magnetic memories. However, in the prior art, in order to enhance the anti-magnetic ability of the device, it is generally considered to wrap a material with high magnetic permeability around a single chip for magnetic shielding during packaging. This cannot solve the mutual interference between multiple storage units inside the chip, and will also lead to an increase in chip area and it is difficult to improve the integration density; if anti-ferromagnetic and ferromagnetic materials are wrapped around the magnetic tunnel junction, although the anti-magnetic ability can be improved, the materials used for wrapping have no other functions except magnetic shielding, which increases the device area for no reason. Summary of the Invention

[0005] To solve the above problems, embodiments of the present application provide a semiconductor memory device and a method for forming the same, which can improve the anti-magnetic interference ability of the semiconductor memory device while improving its area utilization rate.

[0006] According to some embodiments, an embodiment of the present application provides a semiconductor memory device, including a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer; the first magnetic tunnel junction is provided with a through opening, the second magnetic tunnel junction is disposed in the through opening, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein, the figure formed by surrounding the sidewalls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygonal, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

[0007] In some possible implementation manners, the first magnetic tunnel junction has a first switching current, the second magnetic tunnel junction has a second switching current, and the magnitudes of the first switching current and the second switching current are different; wherein, by adjusting the sidewall width of the spacer layer, the magnitudes of the first switching current and the second switching current are made different.

[0008] In some possible implementation manners, a first conductive terminal and a second conductive terminal are respectively disposed above the first magnetic tunnel junction and the second magnetic tunnel junction, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series; based on the different magnitudes of the first switching current and the second switching current, by changing the magnitude and / or direction of the write current applied to the spin-orbit torque layer, the semiconductor memory device has multiple resistance values.

[0009] In some possible implementation manners, a common third conductive terminal is disposed on the first magnetic tunnel junction and the second magnetic tunnel junction, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in parallel; based on the different magnitudes of the first switching current and the second switching current, by changing the magnitude and / or direction of the write current applied to the spin-orbit torque layer, the semiconductor memory device has multiple resistance values.

[0010] In some possible implementation manners, the spacer layer is formed of an insulating material, or, the first magnetic tunnel junction and the second magnetic tunnel junction are in direct contact, and by performing ion implantation treatment on the transition region of the direct contact, the material of the transition region is made magnetically ineffective and insulating to form the spacer layer.

[0011] The semiconductor memory device provided by the embodiment of the present application has at least the following advantages: The semiconductor memory device in the embodiments of the present application includes a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction and filling the spacer layer in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction, the anti-magnetic interference ability of the second magnetic tunnel junction is greatly improved. Moreover, the pattern formed by the side walls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygonal, so that the magnetic moment of the first magnetic tunnel junction is annularly distributed, enhancing the anti-magnetic ability. And the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, breaking the magnetic symmetry between the first magnetic tunnel junction and the second magnetic tunnel junction, enabling the field-free switching of the first magnetic tunnel junction and the field-free switching of the out-of-plane magnetized second magnetic tunnel junction. At the same time, the reading methods of the first magnetic tunnel junction and the second magnetic tunnel junction can be designed, enabling the semiconductor memory device to have multiple resistance states and realizing the function of multi-state storage, improving the area utilization rate of the semiconductor memory device while enhancing its anti-magnetic interference ability.

[0012] According to some embodiments, the embodiments of the present application further provide a semiconductor memory device, including a spin-orbit torque layer, a first magnetic tunnel junction, at least one second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer. The first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is disposed in the through-opening, and the spacer layer is filled in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction. Among them, the geometric centers of the first magnetic tunnel junction and the spacer layer coincide. By adjusting the sidewall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, which can be used as a self-reference device.

[0013] In some possible implementation manners, the first magnetic tunnel junction has a first resistance value, the second magnetic tunnel junction has a second resistance value, and by simultaneously reading the first resistance value and the second resistance value and comparing them, the read data of the semiconductor memory device is defined based on the comparison result.

[0014] The semiconductor memory device provided by the embodiments of the present application has at least the following advantages: The semiconductor memory device in the embodiments of the present application includes a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction and filling the spacer layer in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction, the anti-magnetic interference ability of the second magnetic tunnel junction is greatly improved. Among them, the geometric centers of the first magnetic tunnel junction and the spacer layer coincide, avoiding the flipping of the first magnetic tunnel junction to generate a fixed resistance value, and by adjusting the sidewall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, which can be used to realize the self-reference function of the device, improving the area utilization rate of the semiconductor memory device while enhancing its anti-magnetic interference ability.

[0015] According to some embodiments, the present application further provides a method for forming a semiconductor memory device, including the following steps: forming an initial magnetic tunnel junction on a spin-orbit torque layer; forming a spacer layer inside the initial magnetic tunnel junction, a part of the initial magnetic tunnel junction located outside the spacer layer forms a first magnetic tunnel junction, and a part of the initial magnetic tunnel junction located inside the spacer layer forms a second magnetic tunnel junction; wherein, the spacer layer is annular and penetrates the initial magnetic tunnel junction; the shape of the initial magnetic tunnel junction is circular or convex polygon, and the geometric centers of the initial magnetic tunnel junction and the spacer layer do not coincide.

[0016] In some possible implementation manners, the formed first magnetic tunnel junction has a first switching current, the formed second magnetic tunnel junction has a second switching current, and the magnitudes of the first switching current and the second switching current are different; wherein, by adjusting the sidewall width of the spacer layer, the magnitudes of the first switching current and the second switching current are made different.

[0017] According to some embodiments, the present application further provides another method for forming a semiconductor memory device, including the following steps: forming a spacer layer on a spin-orbit torque layer; depositing a magnetic tunnel junction film layer to cover at least the region surrounded by the outer sidewall and the inner sidewall of the spacer layer; etching the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and the magnetic tunnel junction film layer in the region surrounded by the inner sidewall of the spacer layer forms a second magnetic tunnel junction; wherein, the spacer layer is annular; the figure surrounded by the sidewalls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

[0018] In some possible implementation manners, the formed first magnetic tunnel junction has a first switching current, the formed second magnetic tunnel junction has a second switching current, and the magnitudes of the first switching current and the second switching current are different; wherein, by adjusting the sidewall width of the spacer layer, the magnitudes of the first switching current and the second switching current are made different.

[0019] The method for forming a semiconductor memory device in the embodiments of the present application has at least the following advantages: In the method for forming a semiconductor memory device according to an embodiment of the present application, by forming a spin-orbit torque layer and forming a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer on the spin-orbit torque layer, wherein the second magnetic tunnel junction is formed in a through-opening of the first magnetic tunnel junction, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction, the anti-magnetic interference ability of the second magnetic tunnel junction is greatly improved; moreover, the pattern formed by the side walls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygonal, such that the magnetic moment of the first magnetic tunnel junction is annularly distributed, enhancing the anti-magnetic ability; and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, breaking the magnetic symmetry between the first magnetic tunnel junction and the second magnetic tunnel junction, enabling the field-free switching of the first magnetic tunnel junction and the field-free switching of the out-of-plane magnetized second magnetic tunnel junction; meanwhile, the reading methods of the first magnetic tunnel junction and the second magnetic tunnel junction can also be designed, enabling the semiconductor memory device to have multiple resistance states, realizing the function of multi-state storage, and improving the area utilization rate of the semiconductor memory device while enhancing its anti-magnetic interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 6 is a top view of a first semiconductor memory device according to an embodiment of the present application.

[0021] Figure 2 FIG. 10 is a cross-sectional schematic view of a first semiconductor memory device according to an embodiment of the present application.

[0022] Figure 3 FIG. 14 is a cross-sectional schematic view of a second semiconductor memory device according to an embodiment of the present application.

[0023] Figure 4 FIG. 18 is a top view of a third semiconductor memory device according to an embodiment of the present application.

[0024] Figure 5 FIG. 22 is a flowchart of a method for forming a first semiconductor memory device according to an embodiment of the present application.

[0025] Figure 6 FIG. 26 is a top view of forming an initial magnetic tunnel junction on a spin-orbit torque layer in the method for forming a first semiconductor memory device according to an embodiment of the present application.

[0026] Figure 7 FIG. 30 is a cross-sectional schematic view of forming an initial magnetic tunnel junction on a spin-orbit torque layer in the method for forming a first semiconductor memory device according to an embodiment of the present application.

[0027] Figure 8 FIG. 34 is a flowchart of a method for forming a second semiconductor memory device according to an embodiment of the present application.

[0028] Figure 9A top view of forming a spacer layer on a spin-orbit torque layer in a method for forming a second semiconductor memory device according to an embodiment of the present application.

[0029] Figure 10 A cross-sectional schematic diagram of forming a spacer layer on a spin-orbit torque layer in a method for forming a second semiconductor memory device according to an embodiment of the present application.

[0030] Description of reference numerals: 10 - Spin-orbit torque layer; 20 - First magnetic tunnel junction; 30 - Second magnetic tunnel junction; 40 - Spacer layer; 50 - First conductive terminal; 60 - Second conductive terminal; 70 - Third conductive terminal; 80 - Initial magnetic tunnel junction. Detailed implementation manners

[0031] Spin-orbit torque magnetic memories are expected to be a key technology to break through the power consumption bottleneck of integrated circuits in the post-Moore era due to their advantages such as non-volatility, high-speed and low-power data writing, and high device durability. The basic storage unit structure is to add a spin-orbit torque layer at the adjacent position of the free layer in the magnetic tunnel junction, and use the spin-polarized current generated by the current flowing through the spin-orbit torque layer to flip the magnetization direction of the free layer, thereby realizing data writing.

[0032] Since the information in the spin-orbit torque magnetic memory is stored in the form of magnetic signals, in order to avoid the interference of the magnetic signals during the writing of other components or the magnetic signals in the environment on its data writing, it is necessary to improve the anti-magnetic interference ability of the magnetic memory. However, in the prior art, in order to enhance the anti-magnetic ability of the device, generally, when packaging, it is considered to wrap a material with high magnetic permeability around a single chip for magnetic shielding. In this way, the mutual interference between multiple storage units inside the chip cannot be solved, and it will also lead to an increase in the chip area, making it difficult to improve the integration density; if anti-ferromagnetic and ferromagnetic materials are wrapped around the magnetic tunnel junction, although the anti-magnetic ability can be improved, the materials used for wrapping have no other functions except magnetic shielding, which increases the device area for no reason.

[0033] The semiconductor memory device in the embodiment of the present application includes a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer. By forming the second magnetic tunnel junction in the through-opening of the first magnetic tunnel junction, and filling the spacer layer in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction, the anti-magnetic interference ability of the second magnetic tunnel junction is greatly improved. Moreover, the figure formed by the sidewalls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygon, so that the magnetic moment of the first magnetic tunnel junction is annularly distributed, enhancing the anti-magnetic ability. And the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide, breaking the magnetic symmetry between the first magnetic tunnel junction and the second magnetic tunnel junction, enabling the field-free switching of the first magnetic tunnel junction and the field-free switching of the out-of-plane magnetized second magnetic tunnel junction. At the same time, the reading methods of the first magnetic tunnel junction and the second magnetic tunnel junction can be designed, so that the semiconductor memory device has multiple resistance states, realizing the function of multi-state storage, and improving the area utilization rate of the semiconductor memory device while enhancing its anti-magnetic interference ability.

[0034] In order to make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0035] The embodiment of the present application provides a semiconductor memory device, including a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer; the first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is disposed in the through-opening, and the spacer layer is filled in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; wherein, the figure formed by the sidewalls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

[0036] Refer to Figure 1 and Figure 2 , which are the top view and cross-sectional schematic diagram of the first semiconductor memory device provided by the embodiment of the present application. The semiconductor memory device includes a spin-orbit torque layer 10, a first magnetic tunnel junction 20, a second magnetic tunnel junction 30, and a spacer layer 40 disposed on the spin-orbit torque layer 10; the first magnetic tunnel junction 20 is provided with a through-opening, the second magnetic tunnel junction 30 is disposed in the through-opening, and the spacer layer 40 is filled in the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30; wherein, the figure formed by the sidewalls of the first magnetic tunnel junction 20 away from the spacer layer 40 is circular or convex polygon, and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide.

[0037] Among them, the spin-orbit torque layer 10 is a material capable of generating the spin-orbit torque effect, including heavy metal materials such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium, and their alloys; or topological insulators, including bismuth selenide (Bi x Se 1-x ), bismuth antimonide (Bi x Sb 1-x ), bismuth telluride-based materials (Bi,Sb)2Te3, etc., where 0 < x < 1; it can also be a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten ditelluride (WTe2), etc.; the spin-orbit torque layer 10 can be a single-layer film or a multi-layer composite film, including a combination of two or more of the above materials.

[0038] A substrate (not shown in the figure) can also be provided below the spin-orbit torque layer 10 to support the device. The material of the substrate can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, aluminum nitride, etc., or an insulating material, such as germanium; it can also be a logic substrate containing logic circuits inside; the spin-orbit torque layer 10 can completely cover the substrate or partially cover the substrate; conductive vias can also be provided in the substrate to pass a write current into the spin-orbit torque layer 10, thereby generating a spin-orbit torque effect in the spin-orbit torque layer 10, causing the free layer magnetic moments in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to flip.

[0039] Both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are multi-layer composite structures (not shown in the figure), including, from bottom to top: a free layer, a barrier layer, and a reference layer. The free layer is adjacent to the spin-orbit torque layer 10. The materials of the free layer and the reference layer can be ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum, and their alloys, or antiferromagnetic materials; the free layer and the reference layer can be single-layer or multi-layer composite film layers; the material of the barrier layer is an insulating material, such as magnesium oxide, aluminum oxide, silicon oxide, etc.; a pinning layer can also be provided in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, located on the side of the reference layer away from the barrier layer to fix the magnetization direction of the reference layer. A functional layer, such as metal Hf or non-metal MgO, etc., can also be inserted between the spin-orbit torque layer 10 and the free layer to regulate the magnetic anisotropy of the free layer or regulate the interfacial Rashba effect, thereby reducing the write power consumption of the free layer; in addition, a capping layer can be provided above the reference layer to achieve electrical connection with the outside. The capping layer is generally a metal material, including conductive metals such as Ta, Ru, Pt, etc.

[0040] A through-opening is provided in the first magnetic tunnel junction 20, and the through-opening vertically extends through all the film layers of the first magnetic tunnel junction 20. The second magnetic tunnel junction 30 is disposed in the through-opening, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the anti-magnetic ability of the semiconductor memory device.

[0041] The shape formed by the side walls of the first magnetic tunnel junction 20 away from the spacer layer 40 is circular or convex polygon. The convex polygon is a polygon with all interior angles less than 180 degrees, such as an equilateral triangle, a rectangle, a regular pentagon, etc., so that the magnetic moment of the first magnetic tunnel junction 20 is distributed in a ring shape. Due to the characteristics of closed magnetic circuit and low demagnetization factor of the ring-shaped magnet, it is more difficult to undergo magnetization reversal, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit torque layer 10, the side of the first magnetic tunnel junction 20 away from the spacer layer 40 is first flipped, causing the first magnetic tunnel junction 20 to undergo deterministic flipping. The flipping process does not require an external field assistance, realizing the field-free flipping of the first magnetic tunnel junction 20; and, the greater the degree of deviation of the geometric center of the first magnetic tunnel junction 20 from the geometric center of the spacer layer 40, the smaller the flipping current of the first magnetic tunnel junction 20 and the easier it is to be flipped.

[0042] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and its magnetic moment direction can be in-plane magnetization or out-of-plane magnetization. Figure 1 The second magnetic tunnel junction 30 shown in the top view in the figure is elliptical only as an example and does not limit its shape. When the second magnetic tunnel junction 30 is a device with out-of-plane magnetization, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, which can break the magnetic symmetry of the second magnetic tunnel junction 30, thereby realizing the field-free flipping of the second magnetic tunnel junction 30.

[0043] The spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, and its material is formed by an insulating material, such as silicon oxide, silicon nitride, etc. Or, when forming the semiconductor memory device, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are directly contacted, and the material of the transition region is made magnetically ineffective and insulated by ion implantation treatment of the directly contacted transition region to form the spacer layer 40. Those skilled in the art can select an appropriate formation method according to actual needs during the actual formation process, and no limitation is made on the formation method of the spacer layer 40 here.

[0044] The spacer layer 40 is annular, such as a circular ring, a square ring, etc. The shapes of the inner and outer sidewalls of the annular spacer layer 40 can be inconsistent, and its specific shape depends on the shapes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. Preferably, the areas of the second magnetic tunnel junction 30 and the spacer layer 40 do not exceed half of the total area composed of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40, so as to ensure that the magnetic moment of the first magnetic tunnel junction 20 on the outside is annularly distributed and has a good field-free switching effect.

[0045] Continue to refer to Figure 1 and Figure 2 , the first magnetic tunnel junction 20 has a first switching current, denoted as I1, and the second magnetic tunnel junction 30 has a second switching current, denoted as I2. When the total area composed of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40 remains unchanged, the areas of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be adjusted by adjusting the sidewall width w of the spacer layer 40, so that the first switching current I1 is different from the second switching current I2 in magnitude.

[0046] In the semiconductor memory device of this embodiment, the reading methods of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 for magnetic shielding can also be designed to improve their area utilization rate. As Figure 2 shown, a first conductive terminal 50 and a second conductive terminal 60 can be respectively arranged above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to respectively realize data reading of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. The functions of the first conductive terminal 50 and the second conductive terminal 60 are to conduct electricity to form a reading path, and their shapes can be various shapes such as rectangular, trapezoidal, triangular, etc. Figure 2 shown is only an example of the arrangement positions of the first conductive terminal 50 and the second conductive terminal 60, and is not a limitation on their shapes; based on the fact that the first switching current I1 is different from the second switching current I2 in magnitude, by changing the magnitude and / or direction of the writing current I applied to the spin-orbit torque layer 10, the semiconductor memory device has multiple resistance values and can achieve multi-state storage.

[0047] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2. By changing the magnitude or direction of the writing current I applied to the spin-orbit torque layer 10, the semiconductor memory device has at least 3 resistance values; by simultaneously adjusting the magnitude and direction of the writing current I, the semiconductor memory device has at least 4 resistance values. The specific process of the semiconductor memory device obtaining multiple resistance values is as follows: In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in the low-resistance state, and the resistance values are respectively R P1 and R P2; When a write current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value is R P1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a high-resistance state, with a resistance value of R AP2 ; Continuing to increase the write current I in the first direction such that I > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R AP1 , and the resistance value of the second magnetic tunnel junction 30 remains R AP2 ; When a write current I in the second direction opposite to the first direction is applied to the spin-orbit torque layer 10 反向 , such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value remains R AP1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a low-resistance state, with a resistance value of R P2 ; Continuing to increase the write current I in the second direction 反向 , such that I 反向 > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R P1 , and the resistance value of the second magnetic tunnel junction 30 remains R P2 .

[0048] Similarly, by adjusting the sidewall width w of the spacer layer 40, such that the first flip current I1 is less than the second flip current I2, based on the difference in magnitudes between the first flip current I1 and the second flip current I2, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device can also have multiple resistance values. The write principle and specific process can refer to the above description and will not be elaborated here.

[0049] In addition, the first conductive terminal 50 and the second conductive terminal 60 above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be connected in series. Based on the difference in magnitudes between the first flip current I1 and the second flip current I2, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device has multiple resistance values, and the total resistance of the semiconductor memory device is the series resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0050] Specifically, by adjusting the sidewall width w of the spacer layer 40, such that the first flip current I1 is greater than the second flip current I2, the read current flows between the first conductive terminal 50 and the second conductive terminal 60, forming a series read circuit. In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in a low-resistance state, with resistance values of R P1 and R P2 , and the total resistance R of the semiconductor memory device = R P1 + R P2; When a write current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value is R P1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a high-resistance state, with a resistance value of R AP2 , the total resistance R of the semiconductor memory device is R P1 + R AP2 ; Continuing to increase the write current I in the first direction such that I > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R AP1 , the resistance value of the second magnetic tunnel junction 30 remains R AP2 , the total resistance R of the semiconductor memory device is R AP1 + R AP2 ; When a write current I in the second direction opposite to the first direction is applied to the spin-orbit torque layer 10 反向 , such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value remains R AP1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a low-resistance state, with a resistance value of R P2 , the total resistance R of the semiconductor memory device is R AP1 + R P2 ; Continuing to increase the write current I in the second direction 反向 , such that I 反向 > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R P1 , the resistance value of the second magnetic tunnel junction 30 remains R P2 , at this time the semiconductor memory device returns to the initial state, and the total resistance R is R P1 + R P2 .

[0051] In addition, a common third conductive terminal 70 can be provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, so that the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in parallel. The cross-sectional view of the second semiconductor memory device finally formed is referenced Figure 3 as shown. The function of the third conductive terminal 70 is to conduct electricity to form a read path, and its shape can be various shapes such as rectangular, trapezoidal, triangular, etc., Figure 3 as shown is only an example of the setting position of the third conductive terminal 70 and does not limit its shape; based on the different magnitudes of the first flip current I1 and the second flip current I2, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device can have multiple resistance values. Among them, the total resistance R of the semiconductor memory device is the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0052] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2, and the read current flows between one end of the spin-orbit torque layer 10 and the third conductive terminal 70 to form a read path, and the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 is read. In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in the low-resistance state, with resistances of R P1 and R P2 , and the total resistance of the semiconductor memory device ; when a write current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not switch, with a resistance of R P1 , the free layer of the second magnetic tunnel junction 30 switches and becomes a high-resistance state, with a resistance of R AP2 , and the total resistance of the semiconductor memory device ; continuing to increase the write current I in the first direction, such that I > I2, the free layer of the first magnetic tunnel junction 20 switches, with a resistance of R AP1 , and the resistance of the second magnetic tunnel junction 30 remains R AP2 , and the total resistance of the semiconductor memory device ; when a write current I 反向 in the opposite second direction is applied to the spin-orbit torque layer 10, such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not switch, and the resistance remains R AP1 , the free layer of the second magnetic tunnel junction 30 switches and becomes a low-resistance state, with a resistance of R P2 , and the total resistance of the semiconductor memory device ; continuing to increase the write current I 反向 in the second direction, such that I 反向 > I2, the free layer of the first magnetic tunnel junction 20 switches, with a resistance of R P1 , and the resistance of the second magnetic tunnel junction 30 remains R P2 , and at this time the semiconductor memory device returns to the initial state, with a total resistance .

[0053] The first semiconductor memory device and the second semiconductor memory device provided by the embodiments of the present application include a spin-orbit torque layer 10, a first magnetic tunnel junction 20, a second magnetic tunnel junction 30, and a spacer layer 40 disposed on the spin-orbit torque layer 10. By forming the second magnetic tunnel junction 30 in the through-opening of the first magnetic tunnel junction 20 and filling the spacer layer 40 in the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, the anti-magnetic interference ability of the second magnetic tunnel junction 30 is greatly improved. Moreover, by setting the pattern formed by surrounding the side wall of the first magnetic tunnel junction 20 away from the spacer layer 40 to be circular or convex polygon, the magnetic moment of the first magnetic tunnel junction 20 is distributed in a ring shape. The ring-shaped magnet is more difficult to undergo magnetization reversal due to characteristics such as closed magnetic circuit and low demagnetization factor, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced. In addition, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, breaking the magnetic symmetry between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, enabling field-free switching of the first magnetic tunnel junction 20 and field-free switching of the out-of-plane magnetized second magnetic tunnel junction 30. Furthermore, the reading methods of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be designed, enabling the semiconductor memory device to have multiple resistance states and realizing the function of multi-state storage, while improving the anti-magnetic interference ability of the semiconductor memory device and its area utilization rate.

[0054] The embodiments of the present application also provide a third semiconductor memory device, including a spin-orbit torque layer, a first magnetic tunnel junction, at least one second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer. The first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is disposed in the through-opening, and the spacer layer is filled in the gap between the first magnetic tunnel junction and the second magnetic tunnel junction. Wherein, the geometric centers of the first magnetic tunnel junction and the spacer layer coincide. By adjusting the side wall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, and it can be used as a self-reference device.

[0055] Reference Figure 4 Referring to the top view shown, different from the first semiconductor memory device of the embodiments of the present application, in the third semiconductor memory device provided by the embodiments of the present application, the through-opening of the first magnetic tunnel junction 20 includes at least one second magnetic tunnel junction 30, and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 coincide. By adjusting the side wall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, and it can be used as a self-reference device.

[0056] Among them, since the first magnetic tunnel junction 20 is used as a reference device, there is no need to flip the magnetization direction of the free layer of the first magnetic tunnel junction 20. By setting the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 to coincide, the magnetic moment of the first magnetic tunnel junction 20 does not shift, and thus its free layer will not be flipped, and its resistance value will not change with the changes of the external field and the write current. The shape of the first magnetic tunnel junction 20 is not limited, such as circular, elliptical, square, etc. are all acceptable, and preferably circular, so that the first magnetic tunnel junction 20 can generate a uniform annular magnetic moment and the resistance value has better stability.

[0057] By adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 can be adjusted so that its resistance value is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, so as to achieve self-reference of the semiconductor memory device.

[0058] Specifically, the resistance value of the first magnetic tunnel junction 20 is denoted as the first resistance value, and the size of the first resistance value is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30. The second magnetic tunnel junction 30 has a second resistance value. When reading, the first resistance value and the second resistance value are read simultaneously and compared. Based on the comparison result, the read data of the semiconductor memory device is defined: if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in the low-resistance state, and the semiconductor memory device reads the data as "1"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in the high-resistance state, and the semiconductor memory device reads the data as "0"; or, if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in the low-resistance state, and the semiconductor memory device reads the data as "0"; if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in the high-resistance state, and the semiconductor memory device reads the data as "1". It is also possible to define the read data of the semiconductor memory device based on the comparison result according to actual usage requirements.

[0059] The number of the second magnetic tunnel junctions 30 can be one or more. The multiple second magnetic tunnel junctions 30 can be arranged in an array or designed according to actual requirements. Conductive terminals (not shown in the figure) are respectively arranged above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to be electrically connected to an external circuit to realize data reading. When there are multiple second magnetic tunnel junctions 30, each second magnetic tunnel junction 30 can compare its resistance value with the same first magnetic tunnel junction 20. Compared with the existing self-reference devices where each memory cell needs to be respectively provided with a reference device, it not only saves the cell area but also reduces the number of openings of the top electrode, which not only simplifies the formation process but also is beneficial to the integration of the device.

[0060] The third semiconductor memory device provided by the embodiments of the present application forms a second magnetic tunnel junction 30 in the through-opening of the first magnetic tunnel junction 20, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, greatly improving the anti-magnetic interference ability of the second magnetic tunnel junction 30. Among them, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 coincide, avoiding the flipping of the first magnetic tunnel junction 20 to generate a fixed resistance value. By adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, which can be used to implement a self-reference function, improving the anti-magnetic interference ability of the semiconductor memory device while increasing its area utilization rate. In addition, multiple second magnetic tunnel junctions 30 can all be compared with the same first magnetic tunnel junction 20, which not only saves the cell area but also reduces the number of openings of the top electrode, simplifies the formation process and is conducive to device integration.

[0061] On the other hand, the embodiments of the present application also provide a method for forming a semiconductor memory device. For the flowchart of the method for forming the first semiconductor memory device, see Figure 5 , including the following steps: Step S10: Form an initial magnetic tunnel junction on the spin-orbit torque layer; Step S20: Form a spacer layer inside the initial magnetic tunnel junction. A part of the initial magnetic tunnel junction located outside the spacer layer forms a first magnetic tunnel junction, and a part of the initial magnetic tunnel junction located inside the spacer layer forms a second magnetic tunnel junction. Among them, the spacer layer is annular and penetrates the initial magnetic tunnel junction. The shape of the initial magnetic tunnel junction is circular or convex polygon, and the geometric centers of the initial magnetic tunnel junction and the spacer layer do not coincide.

[0062] For step S10, refer to Figure 6 and Figure 7 , the specific steps are as follows: Deposit a magnetic tunnel junction film layer (not shown in the figure) above the spin-orbit torque layer 10, and etch the magnetic tunnel junction film layer to form an initial magnetic tunnel junction 80. The formed initial magnetic tunnel junction 80 has a circular or convex polygon shape.

[0063] Among them, the spin-orbit torque layer 10 is a material that can generate the spin-orbit torque effect, including heavy metal materials such as platinum, palladium, hafnium, gold, tantalum, tungsten, iridium and their alloys; or topological insulators, including bismuth selenide (Bi x Se 1-x ), bismuth antimonide (Bi x Sb 1-x ), bismuth telluride-based materials (Bi,Sb)2Te3, etc., 0 < x < 1; it can also be a two-dimensional material, such as molybdenum disulfide (MoS2), tungsten ditelluride (WTe2), etc. The spin-orbit torque layer 10 can be a single-layer film or a multi-layer composite film, including a combination of two or more of the above materials.

[0064] The initial magnetic tunnel junction 80 is a multi-layer composite structure (not shown in the figure), which includes, from bottom to top: a free layer, a barrier layer, and a reference layer. The free layer is adjacent to the spin-orbit torque layer 10. The materials of the free layer and the reference layer can be ferromagnetic materials, such as cobalt, iron, boron, nickel, ruthenium, iridium, platinum and other materials and their alloys, or can be antiferromagnetic materials; the free layer and the reference layer can be single-layer or multi-layer composite film layers; the material of the barrier layer is an insulating material, such as magnesium oxide, aluminum oxide, silicon oxide, etc.; a pinning layer can also be provided in the initial magnetic tunnel junction 80, and the pinning layer is located on the side of the reference layer away from the barrier layer to fix the magnetization direction of the reference layer. Other functional layers, such as metal Hf or non-metal MgO and other materials, can be inserted between the spin-orbit torque layer 10 and the free layer to regulate the magnetic anisotropy of the free layer or regulate the interfacial Rashba effect, thereby reducing the writing power consumption of the free layer; in addition, a covering layer can be provided above the reference layer to achieve electrical connection with the outside, and the covering layer is generally a metal material, including conductive metals such as Ta, Ru, Pt, etc.

[0065] Regarding step S20, the top view and cross-sectional schematic diagram of the finally formed semiconductor memory device can be respectively referred to Figure 1 and Figure 2 As shown, by forming a spacer layer 40 inside the initial magnetic tunnel junction 80, a part of the initial magnetic tunnel junction 80 located outside the spacer layer 40 forms the first magnetic tunnel junction 20, and a part of the initial magnetic tunnel junction 80 located inside the spacer layer 40 forms the second magnetic tunnel junction 30; wherein, the spacer layer 40 is annular and penetrates the initial magnetic tunnel junction 80; the geometric centers of the initial magnetic tunnel junction 80 and the spacer layer 40 do not coincide.

[0066] The method of forming the spacer layer 40 inside the initial magnetic tunnel junction 80 can be etching. First, an air gap where the spacer layer 40 is located is formed inside the initial magnetic tunnel junction 80 through an etching process. The air gap is annular and penetrates the initial magnetic tunnel junction 80. Then, an insulating material, such as silicon oxide, silicon nitride and other materials, is filled in the air gap to form the spacer layer 40; or, a target area where the spacer layer 40 is located is preset inside the initial magnetic tunnel junction 80, and the target area is subjected to ion implantation treatment to make the material of the target area magnetically ineffective and insulating to form the spacer layer 40. Those skilled in the art can reasonably select the forming method according to actual needs during actual manufacturing, and no restrictions are imposed on the forming method of the spacer layer 40 here. The spacer layer 40 is filled in the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the anti-magnetic ability of the semiconductor memory device.

[0067] The formed spacer layer 40 is in a ring shape, such as a circular ring, a square ring, etc. The shapes of the inner and outer sidewalls of the annular spacer layer 40 can be inconsistent, and its specific shape depends on the shapes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. Preferably, the area of the second magnetic tunnel junction 30 and the spacer layer 40 does not exceed half of the total area composed of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40, so as to ensure that the magnetic moment of the first magnetic tunnel junction 20 is in an annular distribution and has a good field-free switching effect.

[0068] Continue to refer to Figure 1 and Figure 2 , since the initial magnetic tunnel junction 80 is circular or convex polygon, the figure formed by the sidewalls of the first magnetic tunnel junction 20 far from the spacer layer 40 is circular or convex polygon. A convex polygon is a polygon with all interior angles less than 180 degrees, such as an equilateral triangle, a rectangle, a regular pentagon, etc., so that the magnetic moment of the first magnetic tunnel junction 20 is in an annular distribution. The annular magnet is more difficult to magnetize and flip due to characteristics such as closed magnetic circuit and low demagnetization factor, and the diamagnetic ability of the first magnetic tunnel junction 20 is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit torque layer 10, the side of the first magnetic tunnel junction 20 far from the spacer layer 40 is first flipped, causing the first magnetic tunnel junction 20 to undergo deterministic switching. The switching process does not require an external field assistance, realizing the field-free switching of the first magnetic tunnel junction 20; and, the greater the degree of deviation of the geometric center of the first magnetic tunnel junction 20 from the geometric center of the spacer layer 40, the smaller the switching current of the first magnetic tunnel junction 20 and the easier it is to be flipped.

[0069] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and its magnetic moment direction can be in-plane magnetization or out-of-plane magnetization. Figure 1 The second magnetic tunnel junction 30 shown in the top view in

[0070] is elliptical only as an example, not a limitation on its shape. When the second magnetic tunnel junction 30 is a device with out-of-plane magnetization, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, which can break the magnetic symmetry of the second magnetic tunnel junction 30, thus realizing the field-free switching of the second magnetic tunnel junction 30. A substrate (not shown in the figure) can also be provided under the spin-orbit torque layer 10 to support the device. The material of the substrate can be a semiconductor material, such as silicon, silicon carbide, gallium nitride, aluminum nitride, etc., or an insulating material, such as germanium; it can also be a logic substrate containing logic circuits; the spin-orbit torque layer 10 can completely cover the substrate or partially cover the substrate; conductive vias can also be provided in the substrate to apply a write current to the spin-orbit torque layer 10, thereby generating a spin-orbit torque effect in the spin-orbit torque layer 10 and causing the free layer magnetic moments in the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to flip.

[0071] Continue to refer to Figure 1 and Figure 2 The first magnetic tunnel junction 20 has a first switching current, denoted as I1, and the second magnetic tunnel junction 30 has a second switching current, denoted as I2. Without changing the overall area composed of the first magnetic tunnel junction 20, the second magnetic tunnel junction 30, and the spacer layer 40, the areas of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be changed by adjusting the sidewall width w of the spacer layer 40, so that the first switching current I1 and the second switching current I2 are of different magnitudes.

[0072] In the method for forming the semiconductor memory device of this embodiment, the reading methods of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 for magnetic shielding can be designed to improve the anti-magnetic interference ability of the semiconductor memory device while improving its area utilization rate. As Figure 2 shown, a first conductive terminal 50 and a second conductive terminal 60 can be respectively formed above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to respectively realize data reading of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30. The functions of the first conductive terminal 50 and the second conductive terminal 60 are to conduct electricity to form a reading path, and their shapes can be various shapes such as rectangular, trapezoidal, triangular, etc. Figure 2 shown is only an example of the setting positions of the first conductive terminal 50 and the second conductive terminal 60, and is not a limitation on their shapes; based on the fact that the first switching current I1 and the second switching current I2 are of different magnitudes, by changing the magnitude and / or direction of the writing current I applied to the spin-orbit torque layer 10, the semiconductor memory device has multiple resistance values and can realize multi-state storage.

[0073] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2. By changing the magnitude or direction of the writing current I applied to the spin-orbit torque layer 10, the semiconductor memory device has at least 3 resistance values; by simultaneously adjusting the magnitude and direction of the writing current I, the semiconductor memory device has at least 4 resistance values. The specific process for the semiconductor memory device to obtain multiple resistance values is as follows: In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in the low-resistance state, and the resistance values are respectively R P1 and R P2 ; when a writing current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value is R P1 , the free layer of the second magnetic tunnel junction 30 flips and becomes the high-resistance state, and the resistance value is R AP2 ; continue to increase the writing current I in the first direction, such that I > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R AP1, the resistance of the second magnetic tunnel junction 30 remains R AP2 ; when a write current I in the opposite second direction is applied to the spin-orbit torque layer 10 反向 , such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance remains R AP1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a low-resistance state with a resistance of R P2 ; continue to increase the write current I in the second direction 反向 , such that I 反向 > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance is R P1 , the resistance of the second magnetic tunnel junction 30 remains R P2 .

[0074] Similarly, by adjusting the sidewall width w of the spacer layer 40 to make the first flip current I1 less than the second flip current I2, based on the difference in the magnitudes of the first flip current I1 and the second flip current I2, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device can also have multiple resistances. The write principle and specific process can refer to the above description and will not be elaborated here.

[0075] In addition, the first conductive terminal 50 and the second conductive terminal 60 above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can be connected in series. Based on the difference in the magnitudes of the first flip current I1 and the second flip current I2, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device has multiple resistances, and the total resistance of the semiconductor memory device is the series resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0076] Specifically, by adjusting the sidewall width w of the spacer layer 40 to make the first flip current I1 greater than the second flip current I2, the read current flows between the first conductive terminal 50 and the second conductive terminal 60 to form a series read circuit. In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in a low-resistance state with resistances of R P1 and R P2 , and the total resistance R of the semiconductor memory device = R P1 + R P2 ; when a write current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance is R P1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a high-resistance state with a resistance of R AP2 , and the total resistance R of the semiconductor memory device = R P1 + R AP2; Continue to increase the write current I in the first direction such that I > I2, causing the free layer of the first magnetic tunnel junction 20 to flip, with a resistance value of R AP1 , and the resistance of the second magnetic tunnel junction 30 remains R AP2 , and the total resistance R of the semiconductor memory device is R AP1 + R AP2 ; When a write current I in the second direction opposite to the first direction is applied to the spin-orbit torque layer 10 反向 , such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and its resistance remains R AP1 , the free layer of the second magnetic tunnel junction 30 flips to a low-resistance state, with a resistance value of R P2 , and the total resistance R of the semiconductor memory device is R AP1 + R P2 ; Continue to increase the write current I in the second direction 反向 , such that I 反向 > I2, causing the free layer of the first magnetic tunnel junction 20 to flip, with a resistance value of R P1 , and the resistance of the second magnetic tunnel junction 30 remains R P2 , and at this time the semiconductor memory device returns to its initial state, with a total resistance R = R P1 + R P2 .

[0077] In addition, a common third conductive terminal can be provided above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, such that the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in parallel. The cross-sectional view of the second semiconductor memory device finally formed is shown in reference to Figure 3 . The function of the third conductive terminal 70 is to conduct electricity to form a read path, and its shape can be various shapes such as rectangular, trapezoidal, triangular, etc., Figure 3 as shown is only an example of the setting position of the third conductive terminal 70, and does not limit its shape; based on the fact that the first switching current I1 and the second switching current I2 are different in magnitude, by changing the magnitude and / or direction of the write current I applied to the spin-orbit torque layer 10, the semiconductor memory device can have multiple resistance values. Among them, the total resistance R of the semiconductor memory device is the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30.

[0078] Specifically, by adjusting the sidewall width w of the spacer layer 40, the first switching current I1 is made greater than the second switching current I2. The read current flows between one end of the spin-orbit torque layer 10 and the third conductive terminal 70 to form a read path, and the parallel resistance of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 is read. In the initial state, both the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are in a low-resistance state, with resistance values of R P1 and R P2 , and the total resistance of the semiconductor memory device ; When a write current I in the first direction is applied to the spin-orbit torque layer 10, such that I1 < I < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value is R P1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a high-resistance state, with a resistance value of R AP2 , the total resistance of the semiconductor memory device ; Continuing to increase the write current I in the first direction, such that I > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R AP1 , the resistance value of the second magnetic tunnel junction 30 remains R AP2 , the total resistance of the semiconductor memory device ; When a write current I in the second direction opposite to the first direction is applied to the spin-orbit torque layer 10 反向 , such that I1 < I 反向 < I2, the free layer of the first magnetic tunnel junction 20 does not flip, and the resistance value remains R AP1 , the free layer of the second magnetic tunnel junction 30 flips and becomes a low-resistance state, with a resistance value of R P2 , the total resistance of the semiconductor memory device ; Continuing to increase the write current I in the second direction 反向 , such that I 反向 > I2, the free layer of the first magnetic tunnel junction 20 flips, and the resistance value is R P1 , the resistance value of the second magnetic tunnel junction 30 remains R P2 , at this time the semiconductor memory device returns to the initial state, and the total resistance .

[0079] To form a device as described in the formation method of the first semiconductor memory device, an embodiment of the present application also provides another formation method of a semiconductor memory device. The flowchart of the formation method of the second semiconductor memory device is shown in Figure 8 , and includes the following steps: Step S10: Form a spacer layer on the spin-orbit torque layer, where the spacer layer is annular; Step S20: Deposit a magnetic tunnel junction film layer, covering at least the region surrounded by the outer sidewall and the inner sidewall of the spacer layer; Step S30: Etch the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and the magnetic tunnel junction film layer in the region surrounded by the inner sidewall of the spacer layer forms a second magnetic tunnel junction; wherein, the shape surrounded by the sidewalls of the first magnetic tunnel junction far from the spacer layer is circular or convex polygonal, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

[0080] For step S10, a ring-shaped spacer layer is formed on the spin-orbit torque layer. The forming method adopted can be to first form an overall insulating material and then etch the insulating material to form the spacer layer, or to first cover the areas where the spacer layer is not required to be formed with a photoresist, and after depositing the insulating material, remove the photoresist and the insulating material on the photoresist to form the spacer layer. The top view and the device cross-sectional view of the semiconductor memory device formed in this step can be referred to respectively in Figure 9 and Figure 10 .

[0081] The magnetic tunnel junction film layer deposited in step S20 is the same as the magnetic tunnel junction film layer deposited when forming the initial magnetic tunnel junction in the forming method of the first semiconductor memory device, and will not be elaborated here; the deposited magnetic tunnel junction film layer covers at least the area surrounded by the outer sidewall and the inner sidewall of the spacer layer to form the first magnetic tunnel junction and the second magnetic tunnel junction in the subsequent manufacturing process.

[0082] The top view and the device cross-sectional view of the semiconductor memory device finally formed by the forming method of this embodiment can be referred to in Figure 1 shown in the top view and Figure 2 shown in the device cross-sectional view. Among them, the shape surrounded by the sidewalls of the first magnetic tunnel junction 20 far from the spacer layer 40 is circular or convex polygon, so that the magnetic moment of the first magnetic tunnel junction 20 is annularly distributed. Due to the characteristics of closed magnetic circuit and low demagnetization factor of the annular magnet, it is more difficult to undergo magnetization reversal, and the diamagnetic resistance of the first magnetic tunnel junction 20 is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, so that the magnetic symmetry of the first magnetic tunnel junction 20 is broken. When a write current is applied to the spin-orbit torque layer 10, the side of the first magnetic tunnel junction 20 far from the spacer layer 40 is first flipped, causing the first magnetic tunnel junction 20 to undergo deterministic flipping. The flipping process does not require external field assistance, realizing the field-free flipping of the first magnetic tunnel junction 20; and, the greater the degree of deviation of the geometric center of the first magnetic tunnel junction 20 from the geometric center of the spacer layer 40, the smaller the flipping current of the first magnetic tunnel junction 20 and the easier it is to be flipped.

[0083] The shape of the second magnetic tunnel junction 30 can be circular, elliptical, rectangular, etc., and its magnetic moment direction can be in-plane magnetization or out-of-plane magnetization. When the device of the second magnetic tunnel junction 30 is out-of-plane magnetization, the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, which can break the magnetic symmetry of the second magnetic tunnel junction 30, thereby realizing the field-free flipping of the second magnetic tunnel junction 30.

[0084] For the semiconductor memory device formed by the formation method of this embodiment, the read modes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can also be designed, such as the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are read separately, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are read in series, the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 are read in parallel, etc., so as to realize the multi-state storage of the semiconductor memory device, improve the anti-magnetic interference ability of the semiconductor memory device while improving its area utilization rate. The specific implementation methods and related mechanisms have been elaborated in detail when describing the formation method of the first semiconductor memory device, and will not be repeated here.

[0085] For the formation methods of the first and second semiconductor memory devices of the embodiments of the present application, by filling the spacer layer 40 into the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, the anti-magnetic interference ability of the second magnetic tunnel junction 30 is greatly improved; and by setting the pattern formed by surrounding the side wall of the first magnetic tunnel junction 20 away from the spacer layer 40 to be circular or convex polygon, so that the magnetic moment of the first magnetic tunnel junction 20 is distributed in a ring shape. The ring-shaped magnet is more difficult to undergo magnetization reversal due to characteristics such as closed magnetic circuit and low demagnetization factor, and the anti-magnetic ability of the first magnetic tunnel junction 20 is enhanced; and the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 do not coincide, breaking the magnetic symmetry between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30, and enabling the field-free reversal of the first magnetic tunnel junction 20 and the field-free reversal of the out-of-plane magnetized second magnetic tunnel junction 30; moreover, the read modes of the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 can also be designed, so that the semiconductor memory device has multiple resistance states and realizes the function of multi-state storage, improving the anti-magnetic interference ability of the semiconductor memory device while improving its area utilization rate.

[0086] The embodiments of the present application also provide a formation method of a third semiconductor memory device, which is different from the formation method of the first semiconductor memory device in that: after forming the initial magnetic tunnel junction, a spacer layer is formed inside the initial magnetic tunnel junction, and the spacer layer penetrates through the initial magnetic tunnel junction so that a part of the initial magnetic tunnel junction located outside the spacer layer forms the first magnetic tunnel junction, and a part of the initial magnetic tunnel junction located inside the spacer layer forms at least one second magnetic tunnel junction; wherein, the geometric centers of the initial magnetic tunnel junction and the spacer layer coincide; by adjusting the side wall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, and it can be used as a self-reference device.

[0087] The semiconductor memory device finally formed by the formation method of this embodiment can be referred to Figure 4The top view shown, wherein the spacer layer 40 penetrates through the first magnetic tunnel junction 20, that is, the spacer layer 40 vertically extends through all the film layers of the first magnetic tunnel junction 20, at least one second magnetic tunnel junction 30 is disposed in the through-opening formed by the spacer layer 40, and the spacer layer 40 fills the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to protect the second magnetic tunnel junction 30 and improve the anti-magnetic ability of the semiconductor memory device.

[0088] Since the first magnetic tunnel junction 20 is used as a reference device, there is no need to flip the free layer magnetic moment direction of the first magnetic tunnel junction 20. By setting the geometric centers of the first magnetic tunnel junction 20 and the spacer layer 40 to coincide, the magnetic moment of the first magnetic tunnel junction 20 does not shift and thus its free layer will not be flipped, and its resistance value will not change with the change of the external field and the write current; the shape of the first magnetic tunnel junction 20 is not limited, such as circular, elliptical, square, etc., preferably circular, so that the first magnetic tunnel junction 20 generates a circular and uniform magnetic moment and its resistance value has better stability.

[0089] By adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 can be adjusted to make its resistance value between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30 to achieve self-reference of the semiconductor memory device.

[0090] Specifically, the resistance value of the first magnetic tunnel junction 20 is denoted as the first resistance value, and the size of the first resistance value is between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, and the second magnetic tunnel junction 30 has a second resistance value; when reading, the first resistance value and the second resistance value are read simultaneously and compared, and the read data of the semiconductor memory device is defined based on the comparison result: if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in the low resistance state, and the semiconductor memory device reads as data "1", if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in the high resistance state, and the semiconductor memory device reads as data "0"; or, if the first resistance value is greater than the second resistance value, the second magnetic tunnel junction 30 is in the low resistance state, and the semiconductor memory device reads as data "0", if the first resistance value is less than the second resistance value, the second magnetic tunnel junction 30 is in the high resistance state, and the semiconductor memory device reads as data "1", and the read data of the semiconductor memory device can also be defined based on the comparison result according to actual use requirements.

[0091] The number of the second magnetic tunnel junctions 30 can be one or more. The multiple second magnetic tunnel junctions 30 can be arranged in an array or designed according to actual requirements. Conductive terminals (not shown in the figure) are respectively arranged above the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30 to be electrically connected to an external circuit to realize data reading. When there are multiple second magnetic tunnel junctions 30, each second magnetic tunnel junction 30 can compare its resistance value with the same first magnetic tunnel junction 20. Compared with the existing self-reference device in which each storage unit needs to be respectively provided with a reference device, it not only saves the unit area, but also reduces the number of openings of the top electrode, simplifies the formation process and is conducive to device integration.

[0092] The embodiment of the present application also provides another method for forming Figure 4 the semiconductor storage device shown. Different from the method for forming the second semiconductor storage device, when forming the spacer layer 40 on the spin-orbit torque layer 10, there is at least one through-opening inside the spacer layer 40; depositing a magnetic tunnel junction film layer (not shown in the figure) to cover at least the outer sidewall of the spacer layer 40 and all the through-openings on the inner sidewall of the spacer layer 40; etching the magnetic tunnel junction film layer to form the first magnetic tunnel junction 20, and the magnetic tunnel junction film layer in the through-opening on the inner sidewall of the spacer layer 40 forms the second magnetic tunnel junction 30; wherein, the first magnetic tunnel junction 20 coincides with the geometric center of the spacer layer 40; by adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, which can be used as a self-reference device.

[0093] The semiconductor storage device formed by using the formation method of this embodiment can also be used as a self-reference device, which improves the anti-magnetic interference ability of the semiconductor storage device and its area utilization rate at the same time. The specific implementation manner and related mechanism have been elaborated in detail when describing the formation method of the third semiconductor storage device, and will not be repeated here.

[0094] The formation methods of the third and fourth semiconductor storage devices provided by the embodiments of the present application greatly improve the anti-magnetic interference ability of the second magnetic tunnel junction 30 by filling the spacer layer 40 into the gap between the first magnetic tunnel junction 20 and the second magnetic tunnel junction 30; wherein, the first magnetic tunnel junction 20 coincides with the geometric center of the spacer layer 40, avoiding the flipping of the first magnetic tunnel junction 20 to generate a fixed resistance value, and by adjusting the sidewall width of the spacer layer 40, the resistance value of the first magnetic tunnel junction 20 is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction 30, which can be used to realize the self-reference function, improving the anti-magnetic interference ability of the semiconductor storage device and its area utilization rate at the same time; in addition, multiple second magnetic tunnel junctions 30 can all compare their resistance values with the same first magnetic tunnel junction 20, which not only saves the unit area, but also reduces the number of openings of the top electrode, simplifies the formation process and is conducive to device integration.

[0095] In this specification, the various embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. The descriptions with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present application.

Claims

1. A semiconductor memory device, characterized in that, It includes a spin-orbit torque layer, a first magnetic tunnel junction, a second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer; The first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is disposed in the through-opening, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; Wherein, the figure formed by enclosing the side walls of the first magnetic tunnel junction away from the spacer layer is circular or convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

2. The semiconductor memory device according to claim 1, wherein The first magnetic tunnel junction has a first switching current, the second magnetic tunnel junction has a second switching current, and the first switching current and the second switching current are different in magnitude; Wherein, by adjusting the side wall width of the spacer layer, the first switching current and the second switching current are made different in magnitude.

3. The semiconductor memory device according to claim 2, wherein, A first conductive terminal and a second conductive terminal are respectively disposed above the first magnetic tunnel junction and the second magnetic tunnel junction, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series; Based on the fact that the first switching current and the second switching current are different in magnitude, by changing the magnitude and / or direction of the write current applied to the spin-orbit torque layer, the semiconductor memory device has multiple resistance values.

4. The semiconductor memory device according to claim 2, wherein, The first magnetic tunnel junction and the second magnetic tunnel junction are provided with a shared third conductive terminal, so that the first magnetic tunnel junction and the second magnetic tunnel junction are connected in parallel; Based on the fact that the first switching current and the second switching current are different in magnitude, change the magnitude and / or direction of the write current applied to the spin-orbit torque layer, so that the semiconductor memory device has multiple resistance values.

5. The semiconductor memory device according to any one of claims 1 to 4, characterized in that, The spacer layer is formed of an insulating material, or the first magnetic tunnel junction and the second magnetic tunnel junction are in direct contact, and by performing ion implantation treatment on the directly contacted transition region, the material magnetism of the transition region is made ineffective and insulated to form the spacer layer.

6. A semiconductor memory device, characterized in that, It includes a spin-orbit torque layer, a first magnetic tunnel junction, at least one second magnetic tunnel junction, and a spacer layer disposed on the spin-orbit torque layer; The first magnetic tunnel junction is provided with a through-opening, the second magnetic tunnel junction is disposed in the through-opening, and the spacer layer fills the gap between the first magnetic tunnel junction and the second magnetic tunnel junction; Wherein, the geometric centers of the first magnetic tunnel junction and the spacer layer coincide; By adjusting the side wall width of the spacer layer, the resistance value of the first magnetic tunnel junction is made to be between the maximum resistance value and the minimum resistance value of the second magnetic tunnel junction, and it can be used as a self-reference device.

7. The semiconductor memory device according to claim 6, wherein The first magnetic tunnel junction has a first resistance value, the second magnetic tunnel junction has a second resistance value, by simultaneously reading the first resistance value and the second resistance value and comparing them, the read data of the semiconductor memory device is defined based on the comparison result.

8. A method for forming a semiconductor memory device, characterized in that, It includes the following steps: Form an initial magnetic tunnel junction on the spin-orbit torque layer; Form a spacer layer inside the initial magnetic tunnel junction, a part of the initial magnetic tunnel junction located outside the spacer layer forms a first magnetic tunnel junction, and a part of the initial magnetic tunnel junction located inside the spacer layer forms a second magnetic tunnel junction; Among them, the spacer layer is annular and penetrates the initial magnetic tunnel junction; The shape of the initial magnetic tunnel junction is circular or convex polygon, and the geometric centers of the initial magnetic tunnel junction and the spacer layer do not coincide.

9. A method for forming a semiconductor memory device, characterized in that, It includes the following steps: Form a spacer layer on the spin-orbit torque layer; Deposit a magnetic tunnel junction film layer to cover at least the region surrounded by the outer sidewall and the inner sidewall of the spacer layer; Etch the magnetic tunnel junction film layer to form a first magnetic tunnel junction, and the magnetic tunnel junction film layer in the region surrounded by the inner sidewall of the spacer layer forms a second magnetic tunnel junction; Among them, the spacer layer is annular; The figure surrounded by the sidewall of the first magnetic tunnel junction away from the spacer layer is circular or convex polygon, and the geometric centers of the first magnetic tunnel junction and the spacer layer do not coincide.

10. The forming method according to claim 8 or 9, characterized in that, The formed first magnetic tunnel junction has a first switching current, the formed second magnetic tunnel junction has a second switching current, and the first switching current and the second switching current are different in magnitude; Among them, by adjusting the sidewall width of the spacer layer, the first switching current and the second switching current are different in magnitude.

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