Nonvolatile semiconductor memory array and operation method thereof
By adopting the 1T1R structure and self-aligning source line design of a common substrate for every 2N columns in the resistive variable memory, the problem of limited storage density of traditional resistive variable memory is solved, and a higher memory density and a smaller transistor gate width are achieved, thereby improving the integration of the array.
Patent Information
- Application Number
- CN202510253946.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-05
- Publication Date
- 2025-07-04
AI Technical Summary
The storage density of traditional resistive memory is limited by the gate driving capability and parasitic resistance, and the through holes and the areas on both sides of the through holes occupy a large area, making it difficult to meet the future non-volatile storage needs.
Using a 1T1R memory cell, each 2N column memory cell shares a substrate. The RESET operation is completed through the positive bias of the parasitic PN junction between the substrate and the drain, and the metal interconnection lines and their through holes in the source region are eliminated, and the source lines are divided and self-aligned by the substrate to reduce the transistor gate width limitation.
With the unchanged performance, the memory density is significantly improved, the transistor gate width limitation is reduced, the memory cell area is shortened, and the memory density and array integration is improved.
Smart Images
Figure CN120264770A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical fields of semiconductors, memories, and CMOS hybrid integrated circuits. More specifically, it relates to a non-volatile semiconductor memory array and an operation method thereof. Background Art
[0002] With the development of information technology and the popularization of applications in fields such as big data, the Internet of Things, dedicated hardware, and cloud computing, the storage density and performance requirements faced by non-volatile memories are constantly increasing. Due to the constant programming voltage of traditional flash memory, the reliability and data retention characteristics are sensitive to device size, and it is limited by physical limits such as charge discontinuity, the further improvement of its storage density and performance is restricted, and it is difficult to meet future non-volatile storage requirements. A resistive random access memory (RRAM) can switch between a high-resistance state and a low-resistance state according to the voltage difference between two electrodes, and it is an emerging non-volatile memory with great application prospects, having many advantages such as high storage density, fast erase and write speed, easy miniaturization and integration, and low power consumption.
[0003] 1T1R (1 Transistor 1 RRAM) is one of the common array structures of resistive random access memories. Each unit of this structure consists of 1 RRAM and 1 transistor connected in series. The transistor is a select transistor. When it is turned on, the RRAM is selected and can be operated; when it is turned off, the RRAM cannot be operated. This structure can achieve random access and eliminate crosstalk.
[0004] However, traditional structure resistive random access memories have high requirements for the driving ability and parasitic resistance of the select transistor, which limits the storage density. On the one hand, when the RRAM performs FORMING, SET, and RESET operations, the RRAM and the series-connected transistor form an equivalent voltage division relationship. When the total applied voltage difference is constant, the larger the equivalent on-resistance of the transistor, the larger the voltage difference between the source and the drain, and the smaller the voltage drop between the two electrodes of the RRAM. Therefore, the transistor needs to have a small enough on-resistance, which severely limits the reduction of the transistor gate width, increases the unit volume, and reduces the storage density of the resistive random access memory. On the other hand, the via hole area and the areas left empty on both sides of the via hole also occupy a considerable area in the storage unit. Since the area occupied by the RRAM itself is very small, solving the above problems to reduce the area of the select transistor and the select transistor pitch is an important means to improve the storage density of the resistive random access memory. Summary of the Invention
[0005] The present invention proposes a new type of memory array and an operation method thereof, which can improve the storage density of resistive random access memories.
[0006] The technical solution provided by the present invention is as follows:
[0007] A non-volatile semiconductor memory array, characterized in that it includes 1T1R memory cells distributed in an array, each memory cell is formed by connecting a transistor in series with a non-volatile memory, the non-volatile memory is located at the drain of the transistor, the sources of every 2 transistors in the same row share the same N-type doped source region, the top electrodes of the non-volatile memories in each row are connected through a bit line BL, the gates and sources of the transistors in each column are connected through a word line WL and a source line SL respectively; every 2N columns of memory cells share a substrate, and the substrate is made of P-type semiconductor; on each substrate, there is a strip-shaped P + doped region as the substrate contact region, and a substrate lead-out line is provided on each substrate. The substrate lead-out line is parallel to the word line and perpendicular to the direction of the substrate contact region, and is connected to all the substrate contact regions of the corresponding substrate through vias. The substrate lead-out line applies a positive voltage to each substrate separately.
[0008] Furthermore, a strip-shaped N-well is provided as a substrate partition between adjacent two substrates. The direction of the substrate partition is parallel to the direction of the word line and the substrate lead-out line, and perpendicular to the direction of the bit line and the substrate contact region.
[0009] The substrate partition is provided with an N + type doped, strip-shaped region as the substrate partition contact region. The direction of the substrate partition contact region is the same as that of the substrate partition; above each substrate partition contact region, there is a substrate partition interconnecting line. The direction of the substrate partition interconnecting line is the same as that of the substrate partition and the substrate partition contact region, and is connected to the corresponding substrate partition contact region through vias.
[0010] Furthermore, all the substrate partition interconnecting lines are connected by another horizontal interconnecting line outside the non-volatile semiconductor memory array.
[0011] Furthermore, the source line SL is a strip-shaped N-type doped region buried under the transistor isolation medium. The source line SL connects the sources of the transistors from below and is integrated with the source region. The source line SL is kept grounded.
[0012] Furthermore, the P-type semiconductor, P + doping, N-well and N + type doping are respectively and simultaneously replaced with N-type semiconductor, N + doping, P-well and P + type doping.
[0013] Furthermore, the non-volatile memory uses a phase change memory PCM, a magnetoresistive memory MRAM or an RRAM device.
[0014] The present invention further provides an operation method for the non-volatile semiconductor memory array, specifically including the following steps:
[0015] 1) During writing (SET), a high level is applied to BL and WL where the selected memory cell is located, and the remaining connections and the substrate leads are kept grounded. When the transistor in the memory cell to be written conducts, the top electrode of the RRAM is at a high level of BL and the bottom electrode is approximately grounded, and it is set to the low resistance state. Random writing can be achieved through the cross selection of BL and WL.
[0016] 2) During erasing (RESET), a high level is applied to the substrate where the memory cell to be erased is located, and the BL where it is located is grounded; the remaining BLs are all floating; WL and the remaining substrate leads are all grounded. At this time, all transistors are turned off, and the array is equivalent to a 1D1R array with a PN junction as the select transistor. The substrate voltage of the memory cell to be erased is relatively high and the top electrode of the RRAM is grounded, and the parasitic PN junction of the drain is forward biased and conducts, allowing a relatively large current to flow through. The high level of the substrate is conducted to the bottom electrode of the RRAM, and due to the relatively large current limiting, the RRAM is set to the high resistance state. Since the non-selected BL is floating, no voltage is directly applied between the two electrodes of the RRAM of the remaining memory cells; and the reverse breakdown voltage of the PN junction is relatively large, only allowing current to flow unidirectionally, cutting off the crosstalk and leakage paths. Therefore, there is no crosstalk problem in the erasing operation. Through the cross selection between the shared substrate and BL, at least 2N memory cells can be erased at a time (2N is the number of columns of the shared substrate, and the cells that share both the substrate and BL with the selected memory cell are erased).
[0017] 3) During reading, a logic level is applied to WL of the selected memory cell, and a relatively small RRAM read voltage is applied to BL, enabling random access.
[0018] Optionally, the non-selected BL can also be connected to a high level with the same voltage as the substrate voltage of the cell to be erased, replacing the floating of the non-selected BL. At this time, the remaining cells either do not change the storage state because the transistor does not conduct and the substrate is grounded, or because the voltages of the substrate and BL (i.e., the two electrodes of the RRAM) are the same.
[0019] The technical effects of the present invention are as follows:
[0020] The present invention adopts a 1T1R memory cell, proposes that every 2N columns of memory cells share a substrate, and by applying a positive voltage to the substrate, the RESET operation of the resistive memory cell is completed by the forward biasing of the parasitic PN junction between the substrate and the drain, relaxing the limitation on the minimum gate width of the transistor without changing the performance.
[0021] Furthermore, the present invention adopts a self-aligned source line (SL) buried under the source region and the isolation medium, eliminating the traditional SL metal interconnection and its vias.
[0022] Compared with the traditional storage structure, the present invention has a higher storage density when the performance is the same. Additionally, at more advanced process nodes, the array structure and operation mode in the present invention can be combined with FinFET to further improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Schematic diagram of a storage cell in the non-volatile semiconductor memory array of the present invention;
[0024] Figure 2 Top view schematic diagram of the non-volatile semiconductor memory array of the present invention;
[0025] Figure 3 Bottom view schematic diagram of the non-volatile semiconductor memory array of the present invention;
[0026] Figure 4 Cross-sectional view schematic diagram of the non-volatile semiconductor memory array of the present invention;
[0027] Figure 5 is Figures 1-4 legend description of. DETAILED DESCRIPTION OF THE INVENTION
[0028] As Figure 1 shown, the 1T1R storage cell structure of the non-volatile semiconductor memory array of the present invention is formed by connecting a transistor in series with a non-volatile memory. The non-volatile memory is an RRAM device. The RRAM device can be composed of a bottom electrode, a resistive switching layer, and a top electrode from bottom to top. The RRAM device is located at the drain of the transistor. The top electrodes of the RRAM devices in each row are connected through a bit line BL. The gates and sources of the transistors in each column are connected through a word line WL and a source line SL respectively.
[0029] The 1T1R storage cells of the non-volatile semiconductor memory array of the present invention are distributed in an array. The direction of the bit line is called "row", and the direction of the word line is perpendicular to the direction of the bit line. The direction of the word line is called "column".
[0030] Every 2N columns of storage cells share one substrate (N can be any positive integer). The substrate is made of P-type semiconductor. On each substrate, there are strip-shaped P + doped regions every M rows as horizontal substrate contact regions. Longitudinal substrate lead-out lines are provided on all substrates. The substrate contact regions on each substrate are connected to the substrate lead-out lines through vias; N wells are provided between two adjacent substrates as substrate partitions. N +The P-type doped region serves as a longitudinal substrate segmentation contact region. The longitudinal substrate segmentation contact region is connected to a transverse substrate segmentation interconnecting line through a via hole. Every two transistors in the same row share the same N-type doped source region. The source line SL is a longitudinal strip-shaped N-type doped region, which is buried under the transistor isolation dielectric and integrated with the above-mentioned N-type doped source region. The source line SL connects the sources of each transistor from below, and the source line SL is kept grounded. The substrate segmentation interconnecting lines are connected through another horizontal interconnecting line outside the non-volatile semiconductor memory array; the substrate lead-out line applies a positive voltage to each substrate separately.
[0031] As Figure 2 shown, in the top view of the non-volatile semiconductor memory array of the present invention, all metal interconnecting lines (including bit lines BL, substrate lead-out lines, substrate segmentation interconnecting lines) are omitted, and the pre-metal dielectric and the protective layer are also omitted, and it is taken as an example that each substrate has 4 columns of memory cells (i.e., N is 2). The vertically long strip-shaped regions formed by the gate material in the figure are word lines WL, and the 2nd, 3rd, 5th, and 6th gate material regions from left to right are word lines WL. The vertically long strip-shaped regions formed by N-type semiconductors and N+-type semiconductors are substrate segmentation and longitudinal substrate segmentation contact regions respectively. There are substrate segmentation contact via holes and buffer layers above the substrate segmentation contact regions; the buffer layer is located at the interface between the via hole and the substrate segmentation contact region and is used to improve the interface contact characteristics. On each substrate, there is a long strip-shaped, transverse P+-doped region as a transverse substrate contact region every M rows (M can be any positive integer less than 230, such as 64 or 128). There are substrate contact via holes and buffer layers above the substrate contact regions; the buffer layer is located at the interface between the via hole and the substrate contact region and is used to improve the interface contact characteristics.
[0032] As Figure 3 shown, the bit line BL in the non-volatile semiconductor memory array of the present invention is horizontally oriented and is connected to the top electrodes of all resistive random access memory devices in the corresponding row. The substrate lead-out line is vertically oriented and is connected to all substrate contact via holes in the corresponding column. The substrate segmentation interconnecting lines are vertically oriented and are connected to all substrate segmentation via holes in the corresponding column. All substrate segmentation interconnecting lines are connected through another horizontally oriented interconnecting line outside the memory array and can be grounded during use.
[0033] As Figure 4As shown, in the memory cell structure of the non-volatile semiconductor memory array of the present invention, the N-type semiconductor regions in the memory cell structure form the source region and the drain region of the transistor. There is a drain via and a buffer layer above the drain region, and there is no via or buffer layer above the source region. The channel region of the transistor is located between the source region and the drain region. A gate dielectric layer is provided above the channel region, and a gate region is provided above the gate dielectric layer. A protective dielectric layer is provided around the gate region. The gate region is a part of the word line WL. An RRAM device is provided above each drain via and the buffer layer, and the top electrode of the RRAM device is connected to the bit line BL above. Substrate split vias and a buffer layer are provided above all substrate split contact regions, and a substrate split interconnect line is provided above the substrate split vias and the buffer layer. The space occupied by the region below the bit line BL is entirely filled with pre-metal dielectric. Every two transistors in the same row share the same N-type doped source region. The source line SL is a vertically extending, elongated N-type doped region. The source region is a part of the source line SL, which is buried under the transistor isolation dielectric and integrated with the above-mentioned N-type doped source region. The source line SL connects the sources of each transistor from below, and the source line SL is kept grounded. Each vertical substrate split interconnect line is connected by another horizontal interconnect line outside the non-volatile semiconductor memory array; the substrate lead-out line applies a positive voltage to each substrate separately.
[0034] In this figure, the regions between the substrate split and the drain region closest to the substrate split, as well as the regions between the two drain regions, are all used as isolation regions. A gate dielectric layer is also provided above all isolation regions, and a gate is provided above the gate dielectric layer, and a protective layer is also provided around it. The gate above the isolation region has no electrical connection during use, so it does not have the function of operating the device and is also called a "dummy gate".
[0035] The operation method of the non-volatile semiconductor memory array provided by the present invention specifically includes the following steps:
[0036] 1) When writing (SET), a high level is applied to the BL and WL where the selected memory cell is located, and the other connections and the substrate lead-out are kept grounded. When the transistor in the memory cell to be written is turned on, the top electrode of the RRAM is at the high level of the BL and the bottom electrode is approximately grounded, and it is set to the low resistance state. Random writing can be achieved through the cross-selection of the BL and WL.
[0037] 2) During erasure (RESET), a high level is applied to the substrate where the memory cell to be erased is located, and the corresponding BL is grounded; the remaining BLs are floating; the WL and the leads of the remaining substrates are all grounded. At this time, all transistors are turned off, and the array is equivalent to a 1D1R array with a PN junction as the select transistor. The substrate voltage of the memory cell to be erased is relatively high while the top electrode of the RRAM is grounded, and the parasitic PN junction of the drain is forward-biased and conducts, allowing a relatively large current to flow through. The high substrate level is conducted to the bottom electrode of the RRAM, and due to the relatively large current limiting, the RRAM is set to a high-resistance state. Since the non-selected BLs are floating, no voltage is directly applied between the two electrodes of the RRAMs of the remaining memory cells; and the reverse breakdown voltage of the PN junction is relatively large, only allowing current to flow unidirectionally, cutting off the crosstalk and leakage paths. Therefore, there is no crosstalk problem during the erasure operation. By cross-selection between the shared substrate and the BL, at least 2N memory cells can be erased in a single operation (2N is the number of columns of the shared substrate, and the cells that share both the substrate and the BL with the selected memory cells are erased).
[0038] 3) During reading, a logic level is applied to the WL of the selected memory cell, and a relatively small RRAM read voltage is applied to the BL, enabling random access.
[0039] In the present invention, since no voltage needs to be applied to the SL during the RESET operation, the SL can be kept grounded during use, reducing the importance of its parasitic resistance and contact resistance. In the present invention, the SL is a vertically extending, strip-shaped N-type doped region. Its doping concentration is relatively high, buried under the isolation medium, and integrated with the N-type doped source regions of the transistors in the same column, connecting the source electrodes of the transistors in the same column from below, replacing the source via holes and the original metal SL located above. On the one hand, since the RRAM is in a low-resistance state before the RESET operation, when the on-resistance of the transistor in the traditional structure is constant, the voltage division of the RRAM is significantly smaller. Therefore, compared with the FORMING and SET operations, the traditional RESET operation requires more stringent driving ability of the transistor and more obvious restrictions on the gate width.
[0040] The present invention uses the parasitic PN junction of the transistor substrate to replace the channel for RESET operation. During RESET, the RRAM only divides the voltage with the drain parasitic PN junction with a very small on-resistance, and has nothing to do with the driving ability of the transistor. Therefore, the resistive random access memory in the present invention does not need to consider the limitation of the RESET on the transistor gate width, can greatly reduce the gate width, and significantly improve the storage density. The simulation results show that the gate width of the storage unit transistor in the present invention can be reduced to 60 nm. On the other hand, by changing the conditions of the RESET operation, the present invention eliminates the via hole above the source region, shortens the distance between the two transistors sharing the source, and further improves the storage density. And the number of cell columns (2N) sharing the substrate can be selected according to performance requirements. A smaller number of columns reduces the parasitic resistance of the substrate during RESET and at the same time reduces the minimum number of erased cells; while a larger number of columns improves the storage density, and the interval row number (M) led out by the substrate can be selected according to performance requirements. A smaller number of rows reduces the parasitic resistance of the substrate during RESET, while a larger number of rows improves the storage density. Therefore, the present invention greatly improves the storage density. Theoretical calculations show that after considering the limitation of the metal interconnection pitch, the area occupied by a single storage unit in the present invention can be reduced to 0.0379 μm 2 .
[0041] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those of ordinary skill in the art can modify or equivalently replace the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims
Claims
1. A non-volatile semiconductor memory array, characterized in that, Including 1T1R memory cells distributed in an array, each memory cell is composed of a transistor and a non-volatile memory in series, the non-volatile memory is located at the drain of the transistor, the sources of every two transistors in the same row share the same N-type doped source region, the top electrodes of the non-volatile memories in each row are connected through the bit line BL, the gates and sources of the transistors in each column are connected through the word line WL and the source line SL respectively; every 2N columns of memory cells share one substrate, and the substrate is made of P-type semiconductor; on each substrate, a strip-shaped P + doped region is provided as the substrate contact region, a substrate lead-out line is provided on each substrate, the direction of the substrate lead-out line is parallel to the word line and perpendicular to the direction of the substrate contact region, and is connected to all the substrate contact regions of the corresponding substrate through vias, and a positive voltage is applied to each substrate separately through the substrate lead-out line.
2. The non-volatile semiconductor memory array according to claim 1, wherein, A strip-shaped N-well is provided between adjacent substrates as substrate segmentation. The orientation of the substrate segmentation is parallel to the word line orientation and the substrate lead-out line orientation, and perpendicular to the bit line orientation and the substrate contact area orientation.
3. The non-volatile semiconductor memory array according to claim 2, wherein Inside the substrate division, there is an N + -type doped, strip-shaped region as the substrate division contact region, and the direction of the substrate division contact region is the same as that of the substrate division; above each substrate division contact region, there is a substrate division interconnecting line, and the direction of the substrate division interconnecting line is the same as that of the substrate division and the substrate division contact region, and is connected to the corresponding substrate division contact region through a via hole.
4. The non-volatile semiconductor memory array according to claim 3, wherein All substrate segmentation interconnections are connected through another horizontal interconnection outside the non-volatile semiconductor memory array.
5. The non-volatile semiconductor memory array according to claim 1, wherein, The source line SL is a strip-shaped N-type doped region buried under the transistor isolation dielectric. The source line SL connects the source electrodes of each transistor from below and is integrated with the source region. The source line SL remains grounded.
6. The non-volatile semiconductor memory array according to claim 1, characterized in that, Replace the P + doping, N-well, and N + -type doping with N + doping, P-well, and P + -type doping respectively and simultaneously.
7. The non-volatile semiconductor memory array according to claim 1, wherein, The non-volatile memory uses a phase change memory PCM, a magnetoresistive random access memory MRAM, or a RRAM device.
8. The method for operating a nonvolatile semiconductor memory array according to claim 1, wherein, The non-volatile memory in the memory cell uses RRAM, and specifically includes the following steps: 1) When writing SET, a high level is applied to the BL and WL where the selected memory cell is located, and the remaining connections are grounded with the substrate lead-out; when the transistor in the memory cell to be written is turned on, the top electrode of the RRAM is at a high level of BL and the bottom electrode is grounded, and it is set to a low resistance state; random writing is achieved through the cross-selection of BL and WL. 2) When erasing RESET, a high level is applied to the substrate where the memory cell to be erased is located, and the BL where it is located is grounded; the BLs of the non-selected memory cells are all floating; the WL and the remaining substrate lead-outs are all grounded. 3) When reading, a logic level is applied to the WL of the selected memory cell, and a RRAM read voltage is applied to the BL to achieve random access.
9. The method for operating a non-volatile semiconductor memory array according to claim 8, characterized in that, The floating BL of the non-selected memory cell is replaced with a high level of the same voltage as the substrate of the cell to be erased.