Integrated circuit including polysilicon resistor

Abstract

An integrated circuit including a polysilicon resistor is provided. The integrated circuit includes: a plurality of active regions on an upper surface of a semiconductor substrate and having no electrical connections on the semiconductor substrate; an isolation layer on an upper surface of the semiconductor substrate and defining the plurality of active regions; and a plurality of polysilicon resistors on the plurality of active regions and the isolation layer. The plurality of polysilicon resistors extend in a second direction perpendicular to a first direction in which the plurality of active regions extend, and are configured such that a number of active regions overlapping each of the plurality of polysilicon resistors in a vertical direction is equal.

Description

[0001] This application claims priority based on and claims the benefit of Korean Patent Application No. 10-2024-0001070, filed with the Korean Intellectual Property Office on January 3, 2024, and Korean Patent Application No. 10-2024-0011183, filed with the Korean Intellectual Property Office on January 24, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to an integrated circuit (IC), and more particularly, to an IC including a polysilicon resistor, which prevents leakage current of the IC and reduces chip size. Background Art

[0003] An IC may include one or more semiconductor devices. When the size of a semiconductor device is reduced, the size of circuit components of the semiconductor device and the pitch between the circuit components are also reduced. When the pitch between the circuit components is reduced, leakage current may occur between adjacent components.

[0004] To prevent leakage current between devices, the devices may be designed to have a large pitch between them, but this may result in an increase in the chip size of the IC. Summary of the Invention

[0005] The present disclosure provides an integrated circuit including a polysilicon resistor, which prevents leakage current of the integrated circuit (IC) and reduces chip size.

[0006] In one general aspect, an integrated circuit includes: a semiconductor substrate; a plurality of active regions on an upper surface of the semiconductor substrate, the plurality of active regions not being electrically connected on the semiconductor substrate; an isolation layer on the upper surface of the semiconductor substrate and defining the plurality of active regions; and a plurality of polysilicon resistors on the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to a first direction in which the plurality of active regions extend, wherein the plurality of polysilicon resistors are configured such that the number of active regions stacked vertically with each of the plurality of polysilicon resistors is the same.

[0007] In another general aspect, an integrated circuit includes: a semiconductor substrate of a first conductivity type; a plurality of active regions on an upper surface of the semiconductor substrate, the plurality of active regions having no electrical connection on the semiconductor substrate; an isolation layer on the upper surface of the semiconductor substrate and defining the plurality of active regions; a plurality of polysilicon resistors on the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to a first direction in which the plurality of active regions extend; and a well region of a second conductivity type on the upper surface of the semiconductor substrate and disposed adjacent to the plurality of active regions, the well region including: a first well region disposed on one side of the well region in the first direction; and a second well region disposed on the other side of the well region in the first direction, wherein the plurality of active regions under the plurality of polysilicon resistors include: a plurality of first active regions overlapping the first well region and the second well region in the first direction; and a plurality of second active regions as the remaining active regions among the plurality of active regions, and each of the plurality of active regions is cut at least once in the first direction such that the isolation layer is between the cut portions.

[0008] In another general aspect, an integrated circuit includes: a semiconductor substrate; a plurality of active regions on an upper surface of the semiconductor substrate, the plurality of active regions having no electrical connection on the semiconductor substrate; an isolation layer on the upper surface of the semiconductor substrate and defining the plurality of active regions; a plurality of polysilicon resistors on the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to a first direction in which the plurality of active regions extend; and a plurality of dummy polysilicon resistors on the upper surface of the semiconductor substrate and around the plurality of polysilicon resistors, adjacent to both sides of the plurality of polysilicon resistors in the first direction, wherein each of the plurality of active regions under the plurality of polysilicon resistors and the plurality of dummy polysilicon resistors is cut at least once in the first direction such that the isolation layer is between the cut portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a conceptual block diagram showing an example of an integrated circuit.

[0010] Figure 2A 、 Figure 2B and Figure 3 are diagrams showing examples of integrated circuits including polysilicon resistors. Figure 2C is a graph showing the leakage current characteristics of an integrated circuit.

[0011] Figure 4A and Figure 4B are diagrams showing examples of integrated circuits including polysilicon resistors. Figure 4C is showing Figure 4A andFigure 4B Graph of leakage current characteristics of a polysilicon resistor.

[0012] Figure 5A and Figure 5B are diagrams showing examples of integrated circuits including polysilicon resistors.

[0013] Figure 6A and Figure 6B are diagrams showing examples of integrated circuits including polysilicon resistors.

[0014] Figure 7A and Figure 7B are diagrams showing examples of integrated circuits including polysilicon resistors.

[0015] Figure 8A and Figure 8B are diagrams showing examples of integrated circuits including polysilicon resistors.

[0016] Figure 9A and Figure 9B are diagrams showing examples of integrated circuits including polysilicon resistors.

[0017] Figure 10 is a diagram showing an example of a memory device.

[0018] Figure 11 is a block diagram showing an example of applying a memory device to a solid state drive (SSD) system.

[0019] Figure 12 is a block diagram of a system showing an example of an electronic device including a memory device. Detailed Description

[0020] Figure 1 is a conceptual block diagram showing an example of an integrated circuit (IC) 10.

[0021] Referring to Figure 1 , IC 10 includes a circuit 12 between some components. The circuit 12 may include a resistor (e.g., a polysilicon resistor) 14 connected to perform functions such as a voltage generation circuit function. In some embodiments, IC 10 may be implemented by a memory device, which may be implemented by any memory among dynamic random access memory (DRAM), flash memory, paramagnetic random access memory (PRAM), static random access memory (SRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0022] In some embodiments, the resistor 14 may be included in the voltage generating circuit and implemented by a plurality of resistors (sometimes referred to as a resistor ladder or a resistor string) connected between a line of a power supply voltage (e.g., VDD) and a line of a ground voltage (e.g., VSS). The resistor 14 may divide a specific voltage difference between the power supply voltage VDD level and the ground voltage VSS level and output the divided voltage level.

[0023] In some embodiments, each voltage level distributed by resistor 14 can be provided as a reference voltage to circuit 12 configured to perform a comparison function. The comparison circuit can determine the logic level of the input signal by comparing the voltage level of the input signal with the reference voltage level.

[0024] In some embodiments, the resistor 14 may be included in an analog-to-digital converter (ADC) configured to convert an analog signal into a digital signal, and may be implemented by a resistor string having the same resistance value. When the resistance values ​​of a plurality of resistors connected in series between a first voltage and a second voltage are equal to each other, the ADC may be divided into equal voltage differences between the first voltage level and the second voltage level, and each divided voltage level is provided to a corresponding comparator, each comparator may output a result obtained by comparing the voltage level of the analog input signal with the corresponding allocated voltage level, and the output result may be encoded to output a digital signal. That is, by providing an equal voltage between the two ends of each resistor, the input voltage and output voltage of the ADC may maintain linearity.

[0025] Figure 2A , Figure 2B and Figure 3 is a diagram illustrating an example of an IC including a polysilicon resistor. Figure 2A , Figure 2B and Figure 3 is a top view of ICs 10 and 10a, and Figure 2C Graph showing leakage current characteristics according to the distance between an n-type well (e.g., N-well) region and an active region. For ease of understanding, the terms "upper surface / lower surface, upper part / lower part, on / below, etc." are used with reference to the directions shown in the drawings to which they are referred. Therefore, even the same surface may be referred to differently as an upper surface or a lower surface depending on the directions shown in the drawings.

[0026] Reference Figure 2A, IC 10 is formed on a semiconductor substrate 21, and the semiconductor substrate 21 may include a semiconductor material 22 extending along the upper surface 23 of the semiconductor substrate 21. The semiconductor material 22 may be, for example, a p-type of the first conductive type. An isolation layer 24 (sometimes referred to as a field oxide layer) may be formed on the upper surface 23 of the semiconductor substrate 21. The polysilicon resistor 14 may be on the boundaries in, for example, the X direction and the Y direction, the isolation layer 24, and the active region (ACT) 26, and extends in the first horizontal direction X. The active region 26 may be defined by the isolation layer 24. The isolation layer 24 may electrically isolate the active region 26. The active region 26 may extend in a second horizontal direction Y perpendicular to the first horizontal direction X and have no electrical connection on the semiconductor substrate 21 (for example, each active region 26 is electrically isolated from other components). Contacts 27 may be formed on both ends of the polysilicon resistor 14 to provide an electrical connection to each polysilicon resistor 14.

[0027] The first well region 28a and the second well region 28b may be arranged adjacent to the polysilicon resistor 14. The first well region 28a and the second well region 28b may be of the second conductive type (i.e., n-type wells). Circuit elements of the IC 10 may be in the first well region 28a and the second well region 28b, respectively. The first well region 28a and the second well region 28b may be spaced apart from the active region 26 by a first distance D1 in the second horizontal direction Y in which the active region 26 extends. Circuit elements of the IC 10 may operate to perform a given function. In this case, Figure 2A It is shown that a leakage current path LC is formed from the second well region 28b to the first well region 28a through a specific active region 26. Conversely, the leakage current path LC may be formed from the first well region 28a to the second well region 28b through a specific active region 26. This means that the first distance D1 between the first well region 28a and the second well region 28b and the active region 26 is short enough to form the leakage current path LC.

[0028] Referring to Figure 2B , the first well region 28a and the second well region 28b may be spaced apart from the active region 26 by a second distance D2 in the second horizontal direction Y in which the active region 26 extends. The second distance D2 may be greater than Figure 2A the first distance D1. Referring to Figure 2C , compared with when the distance between the first well region 28a and the second well region 28b and the active region 26 is the first distance D1, the leakage current is relatively low when the distance is the second distance D2. The leakage current decreases as the spacing distance between the first well region 28a and the second well region 28b and the active region 26 increases, but the chip size of the IC 10 also increases due to the increase in the spacing distance between the first well region 28a and the second well region 28b and the active region 26.

[0029] Referring toFigure 3 In the IC 10a, when the spacing distances between the first well region 28a and the second well region 28b and the active region 26 are as short as the first distance D1, in order to block the leakage current path LC formed from the second well region 28b to the first well region 28a through a specific active region 26, the active regions 26a and 26b under the polysilicon resistors 14a to 14h are cut to have an isolation layer 24 therebetween (for example, the active regions 26a and 26b include discontinuous portions). The leakage current path LC can be removed by cutting the active regions 26a and 26b.

[0030] For example, the polysilicon resistors 14a to 14h can also be designed to have the same resistance value. However, the polysilicon resistors 14d and 14e among the polysilicon resistors 14a to 14h are formed on the isolation layer 24, and the other polysilicon resistors 14a, 14b, 14c, 14f, 14g, 14h are formed on the active regions 26a and 26b and the isolation layer 24. This means that there is a mismatch between the resistance values of the polysilicon resistors 14d and 14e and the resistance values of the other polysilicon resistors 14a, 14b, 14c, 14f, 14g, and 14h due to the influence of different patterns under the polysilicon resistors 14a to 14h (for example, the case where only the isolation layer 24 exists and the case where the active regions 26a and 26b and the isolation layer 24 exist).

[0031] In some embodiments, due to the mismatch of the resistance values of the polysilicon resistors 14a to 14h, an incorrect distributed voltage level may be output from the voltage generation circuit. For a comparator that uses the distributed voltage level as a reference voltage level, when the reference voltage level for determining the voltage level of the input signal is incorrect, an error may occur in determining the logic level of the input signal. When the polysilicon resistors 14a to 14h are used in an ADC, the input voltage and output voltage of the ADC may not maintain linearity. To reduce the mismatch of the resistance values of the polysilicon resistors 14a to 14h, the patterns under the polysilicon resistors 14a to 14h can have the same surrounding environment.

[0032] Hereinafter, various examples of the configuration of the polysilicon resistor are described in detail.

[0033] Figure 4A and Figure 4B are diagrams showing an example of the IC 10b including the polysilicon resistor. Figure 4A and Figure 4B are top views of the IC 10b, and Figure 4C is a graph showing the leakage current characteristics according to the distance between the N-well region and the active region.

[0034] Referring to Figure 1 andFigure 4A The IC 10b is formed on a semiconductor substrate 41, and the semiconductor substrate 41 includes a semiconductor material 42 extending along an upper surface 43 of the semiconductor substrate 41. The semiconductor material 42 may be, for example, a p-type as a first conductivity type. An isolation layer 44 may be formed on the upper surface 43 of the semiconductor substrate 41. The polysilicon resistors 14a to 14h may be on the isolation layer 44 and the active regions 56a to 56f, and extend in a first horizontal direction X. The boundaries of the active regions 56a to 56f may be defined by the isolation layer 44 (e.g., the boundaries of the isolation layer 44 start where the boundaries of some portions of the active region 56 end). The active regions 56a to 56f may be cut once when extending in a second horizontal direction Y perpendicular to the first horizontal direction X such that the isolation layer 44 is between the cut portions. Additionally, the active regions 56a to 56f may not have electrical connections on the semiconductor substrate 41. The contacts 47 may be formed at both ends of the polysilicon resistors 14a to 14h to provide electrical connections to each of the polysilicon resistors 14a to 14h.

[0035] The polysilicon resistors 14a to 14h are main resistors MR for the operation of the circuit 12. A first well region 48a and a second well region 48b may be arranged adjacent to the main resistor MR. The first well region 48a and the second well region 48b may be wells of a second conductivity type (e.g., n-type). The circuit elements of the IC 10b may be in the first well region 48a and the second well region 48b, respectively. The first well region 48a and the second well region 48b may be spaced apart from the active regions 56a to 56f by a first distance D1 in the second horizontal direction Y in which the active regions 56a to 56f extend.

[0036] The IC 10b may include dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14h as the main resistor MR may be on the isolation layer 44 and the active regions 56a to 56f, and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d may be on the isolation layer 44 and the active regions 56a to 56f, and extend in the first horizontal direction X.

[0037] The polysilicon resistors 14a to 14h are electrically connected to the circuit 12, the dummy resistors DR1 and DR2 are not electrically connected to the circuit 12, and are not used in the IC 10b. For example, the dummy resistors DR1 and DR2 may be electrically isolated from the semiconductor substrate 41. The dummy resistors DR1 and DR2 may reduce the mismatch between the resistance values of the polysilicon resistors 14a to 14h that may occur due to semiconductor process differences of the main resistor MR.

[0038] The polysilicon resistors 14a and 14b among the main resistors MR are vertically stacked with five active regions 56a, 56b, 56c, 56d, and 56f (for example, the polysilicon resistors 14a and 14b are directly below the five active regions 56a, 56b, 56c, 56d, and 56f). The polysilicon resistors 14c and 14d are vertically stacked with five active regions 56a, 56b, 56c, 56e, and 56f (for example, the polysilicon resistors 14c and 14d are directly below the five active regions 56a, 56b, 56c, 56e, and 56f). The polysilicon resistors 14e and 14f are vertically stacked with five active regions 56a, 56b, 56d, 56e, and 56f (for example, the polysilicon resistors 14e and 14f are directly below the five active regions 56a, 56b, 56d, 56e, and 56f). The polysilicon resistors 14g and 14h are vertically stacked with five active regions 56a, 56c, 56d, 56e, and 56f (for example, the polysilicon resistors 14g and 14h are directly below the five active regions 56a, 56c, 56d, 56e, and 56f). Each of the polysilicon resistors 14a to 14h can be arranged to be vertically stacked with five of the active regions 56a to 56f. This arrangement ensures that the polysilicon resistors 14a to 14h have the same surrounding environment to reduce the mismatch of the resistance values among the polysilicon resistors 14a to 14h.

[0039] The active regions 56a to 56f below the polysilicon resistors 14a to 14h may not have an electrical connection to the semiconductor substrate 41 and may be cut at least once when extending in a second horizontal direction Y perpendicular to the first horizontal direction X. For example, each of the active regions 56a to 56f may have a first width W1 in the first horizontal direction X. The isolation layer 44 can be formed and placed in at least one cutting region in each of the active regions 56a to 56f. As a result, the leakage current path is blocked by at least one cutting region in each of the active regions 56a to 56f, and since the spacing between the first well region 48a and the second well region 48b and the active regions 56a to 56f can be reduced by blocking the leakage current path, the chip size of the IC 10b can be reduced.

[0040] In some embodiments, the active regions 56a to 56f below the polysilicon resistors 14a to 14h may be cut at least once when extending in a second horizontal direction Y perpendicular to the first horizontal direction X. The isolation layer 44 can be formed in at least one cutting region in each of the active regions 56a to 56f. Thus, the isolation layer 44 can be placed in each of the active regions 56a to 56f at least once.

[0041] Referring to Figure 4B, the active regions 56a to 56f below the polysilicon resistors 14a to 14h have different widths and are cut at least once. For example, each of the active regions 56a, 56c, and 56e may have a first width W1 and is separated by the isolation layer 44 in the cutting region, and each of the active regions 56b, 56d, and 56f may have a second width W2 greater than the first width W1 and is separated by the isolation layer 44 in the cutting region.

[0042] Referring to Figure 4C , regardless of whether the spacing between the first well region 48a and the second well region 48b and the active regions 56a to 56f is the second distance D2 as a long distance or the first distance D1 as a short distance, almost no leakage current flows. Figure 4C It is shown that the leakage current path is blocked by at least one cutting region in each of the active regions 56a to 56f, and since the spacing between the first well region 48a and the second well region 48b and the active regions 56a to 56f can be reduced by blocking the leakage current path, the chip size of the IC 10b can be reduced.

[0043] Figure 5A and Figure 5B is a diagram showing an example of the IC 10c including polysilicon resistors. Figure 5A and Figure 5B is a top view of the IC 10c. Hereinafter, the explanations of the polysilicon resistors 14a to 14h made with reference to Figure 4A will not be repeated for the remaining drawings.

[0044] Referring to Figure 5A , the IC 10c includes dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14h serving as the main resistor MR may be on the isolation layer 44 and the active regions 66a to 66f and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d may be on the isolation layer 44 and the active regions 66a to 66f and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 can reduce the mismatch between the resistance values of the polysilicon resistors 14a to 14h that may occur due to semiconductor process differences of the main resistor MR.

[0045] The polysilicon resistor 14a among the main resistors MR is stacked vertically with five active regions 66a, 66b, 66c, 66d, and 66e. The polysilicon resistors 14b and 14c are stacked vertically with five active regions 66a, 66b, 66c, 66d, and 66f. The polysilicon resistors 14d and 14e are stacked vertically with five active regions 66a, 66b, 66c, 66e, and 66f. The polysilicon resistor 14f is stacked vertically with five active regions 66a, 66b, 66d, 66e, and 66f. The polysilicon resistor 14g is stacked vertically with five active regions 66a, 66c, 66d, 66e, and 66f. The polysilicon resistor 14h is stacked vertically with five active regions 66b, 66c, 66d, 66e, and 66f. Each of the polysilicon resistors 14a to 14h can be arranged to be stacked vertically with five of the active regions 66a to 66f, which can reduce the mismatch between the resistance values of the polysilicon resistors 14a to 14h.

[0046] The active regions 66a to 66f below the polysilicon resistors 14a to 14h may not have electrical connections on the semiconductor substrate 41 and may be cut at least once when extending in a second horizontal direction Y perpendicular to the first horizontal direction X. For example, each of the active regions 66a to 66f may have a first width W1 in the first horizontal direction X. The isolation layer 44 may be formed and disposed in at least one cutting region in each of the active regions 66a to 66f. This means that the leakage current path is blocked by at least one cutting region in each of the active regions 66a to 66f. Since the spacing between the first well region 48a and the second well region 48b and the active regions 66a to 66f is reduced by blocking the leakage current path, the chip size of the IC 10c can be reduced.

[0047] Referring to Figure 5B , the active regions 66a to 66f below the polysilicon resistors 14a to 14h have different widths and are cut at least once. For example, each of the active regions 66a, 66c, and 66e has a first width W1 and is separated by the isolation layer 44 in the cutting region, and each of the active regions 66b, 66d, and 66f may have a second width W2 larger than the first width W1 and is separated by the isolation layer 44 in the cutting region.

[0048] Figure 6A and Figure 6B are diagrams showing examples of the IC 10d including polysilicon resistors. Figure 6A and Figure 6B are top views of the IC 10d. Hereinafter, references Figure 4A and Figure 5ARepeated description of the polysilicon resistors 14a to 14h made.

[0049] Referring to Figure 6A , the IC 10d includes dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14h serving as the main resistor MR can be on the isolation layer 44 and the active regions 76a to 76f, and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 can include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d can be on the isolation layer 44 and the active regions 76a to 76f, and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 can be set to prevent the mismatch of the resistance values of the polysilicon resistors 14a to 14h that may occur due to semiconductor process differences of the main resistor MR.

[0050] Among the main resistors MR, the polysilicon resistors 14a and 14b are stacked with five active regions 76a, 76b, 76d, 76e, and 76f in the vertical direction. The polysilicon resistor 14c is stacked with five active regions 76a, 76b, 76c, 76d, and 76e in the vertical direction. The polysilicon resistors 14d and 14e are stacked with five active regions 76a, 76b, 76c, 76e, and 76f in the vertical direction. The polysilicon resistors 14f and 14g are stacked with five active regions 76a, 76b, 76c, 76d, and 76f in the vertical direction. The polysilicon resistor 14h is stacked with five active regions 76a, 76c, 76d, 76e, and 76f in the vertical direction. Each of the polysilicon resistors 14a to 14h can be arranged to be stacked with five of the active regions 76a to 76f in the vertical direction. This arrangement ensures that the polysilicon resistors 14a to 14h have the same surrounding environment to reduce the mismatch of the resistance values of the polysilicon resistors 14a to 14h.

[0051] The active regions 76a to 76f under the polysilicon resistors 14a to 14h may not have electrical connections on the semiconductor substrate 41, and can be cut at least once when extending in the second horizontal direction Y perpendicular to the first horizontal direction X. For example, each of the active regions 76a to 76f can have a first width W1 in the first horizontal direction X. The isolation layer 44 can be formed and placed in at least one cutting region in each of the active regions 76a to 76f. This means that the leakage current path is blocked by at least one cutting region in each of the active regions 76a to 76f, and since the spacing between the first well region 48a and the second well region 48b and the active regions 76a to 76f can be reduced by blocking the leakage current path, the chip size of the IC 10d can be reduced.

[0052] Referring to Figure 6B, the active regions 76a to 76f below the polysilicon resistors 14a to 14h may have different widths and be cut at least once. For example, each of the active regions 76a, 76c, and 76e may have a first width W1 and be separated by the isolation layer 44 in the cutting region, and each of the active regions 76b, 76d, and 76f may have a second width W2 greater than the first width W1 and be separated by the isolation layer 44 in the cutting region.

[0053] Figure 7A and Figure 7B is a diagram showing an example of the IC 10e including the polysilicon resistors. Figure 7A and Figure 7B is a top view of the IC 10e. Hereinafter, the repeated descriptions of the polysilicon resistors 14a to 14h made with reference to Figure 4A and Figure 5A are omitted.

[0054] Referring to Figure 7A , the IC 10e includes dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14h serving as the main resistor MR may be on the isolation layer 44 and the active regions 86a to 86f and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d may be on the isolation layer 44 and the active regions 86a to 86f and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 reduce the mismatch between the resistance values of the polysilicon resistors 14a to 14h that may occur due to semiconductor process differences of the main resistor MR.

[0055] Among the main resistors MR, the polysilicon resistors 14a and 14b are stacked with five active regions 86a, 86b, 86c, 86d, and 86f in the vertical direction. The polysilicon resistors 14c, 14d, and 14e are stacked with five active regions 86a, 86b, 86c, 86d, and 86e in the vertical direction. The polysilicon resistors 14f, 14g, and 14h are stacked with five active regions 86a, 86b, 86c, 86e, and 86f in the vertical direction. Each of the polysilicon resistors 14a to 14h may be arranged to be stacked with five of the active regions 86a to 86f in the vertical direction. This arrangement ensures that the polysilicon resistors 14a to 14h have the same surrounding environment to reduce the mismatch of the resistance values of the polysilicon resistors 14a to 14h.

[0056] The first well region 88a and the second well region 88b may be disposed adjacent to dummy resistors DR1 and DR2. The first well region 88a and the second well region 88b may be wells of a second conductivity type (i.e., n-type). Circuit elements of the IC 10e may be in the first well region 88a and the second well region 88b, respectively. The first well region 88a may extend a first length L1 in a first horizontal direction X, and the second well region 88b may extend a second length L2 in the first horizontal direction X. In this example, the first well region 88a and the second well region 88b are horizontally stacked with each other by the second length L2. In this example, the active regions 86a to 86f may not have electrical connections on the semiconductor substrate 41, and three of the active regions 86d, 86e, and 86f among the active regions 86a to 86f may be within the second length L2 where the first well region 88a and the second well region 88b are horizontally stacked with each other. In this example, three of the active regions 86d, 86e, and 86f among the active regions 86a to 86f may be stacked with the first well region 88a and the second well region 88b in a second horizontal direction Y.

[0057] When the distances between the first well region 88a and the second well region 88b and the active regions 86d, 86e, and 86f are short, a leakage current path from the second well region 88b to the first well region 88a through any one of the active regions 86d, 86e, and 86f, or a leakage current path from the first well region 88a to the second well region 88b through any one of the active regions 86d, 86e, and 86f may be formed. To block such leakage current paths, the active regions 86d, 86e, and 86f under the polysilicon resistors 14a to 14h may be cut at least once when extending along the second horizontal direction Y. For example, each of the active regions 86a to 86f may have a first width W1 in the first horizontal direction X. The isolation layer 44 may be formed and disposed in at least one cutting region in each of the active regions 86d, 86e, and 86f. In one embodiment, the remaining active regions (e.g., the active regions 86a to 86c) among the active regions 86a to 86f may be continuous (i.e., not cut). This means that the leakage current paths are blocked by at least one cutting region in each of the active regions 86d, 86e, and 86f, and since the spacing between the first well region 88a and the second well region 88b and the active regions 86d, 86e, and 86f can be reduced by blocking the leakage current paths, the chip size of the IC 10e can be reduced.

[0058] Refer to Figure 7B, the active regions 86a to 86f below the polysilicon resistors 14a to 14h have different widths and are cut at least once. For example, the active regions 86a, 86c, and 86e may have a first width W1, the active region 86e may be separated by the isolation layer 44 in the cutting region, the active regions 86b, 86d, and 86f may have a second width W2 greater than the first width W1, and each of the active regions 86d and 86f may be separated by the isolation layer 44 in the cutting region.

[0059] Figure 8A and Figure 8B is a diagram showing an example of the IC 10f including the polysilicon resistor. Figure 8A and Figure 8B is a top view of the IC 10f. Hereinafter, the repeated description of the polysilicon resistors 14a to 14d made with reference to Figure 4A and Figure 5A is omitted.

[0060] Referring to Figure 8A , the IC 10f includes dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14d serving as the main resistor MR may be on the isolation layer 44 and the active regions 96a to 96d and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d may be on the isolation layer 44 and the active regions 96a to 96d and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may be provided to prevent a mismatch in the resistance values of the polysilicon resistors 14a to 14d that may occur due to semiconductor process differences in the main resistor MR.

[0061] Each of the polysilicon resistors 14a to 14d serving as the main resistor MR may be formed in a concavo-convex structure or a zigzag shape and is provided on the isolation layer 44 and the active regions 96a to 96d. Among the main resistors MR, the polysilicon resistor 14a overlaps three active regions 96a, 96b, and 96c in the vertical direction. The polysilicon resistor 14b overlaps three active regions 96a, 96b, and 96d in the vertical direction. The polysilicon resistor 14c overlaps three active regions 96a, 96c, and 96d in the vertical direction. The polysilicon resistor 14d overlaps three active regions 96b, 96c, and 96d in the vertical direction. Each of the polysilicon resistors 14a to 14d may be arranged to overlap three of the active regions 96a to 96d in the vertical direction. This arrangement ensures that the polysilicon resistors 14a to 14d have the same surrounding environment to reduce the mismatch in the resistance values of the polysilicon resistors 14a to 14d.

[0062] The active regions 96a to 96d below the polysilicon resistors 14a to 14d may have no electrical connection on the semiconductor substrate 41 and may be cut at least once when extending in the second horizontal direction Y. For example, each of the active regions 96a to 96d may have a first width W1 in the first horizontal direction X. The isolation layer 44 may be formed and disposed in at least one cutting region in each of the active regions 96a to 96d. This means that the leakage current path is blocked by at least one cutting region in each of the active regions 96a to 96d, and since the spacing between the first well region 48a and the second well region 48b and the active regions 96a to 96d can be reduced by blocking the leakage current path, the chip size of the IC 10f can be reduced.

[0063] Referring to Figure 8B , the active regions 96a to 96d below the polysilicon resistors 14a to 14d have different widths and are cut at least once. For example, each of the active regions 96b and 96d may have the first width W1 and be separated by the isolation layer 44 in the cutting region, and each of the active regions 96a and 96c may have a second width W2 larger than the first width W1 and be separated by the isolation layer 44 in the cutting region.

[0064] Figure 9A and Figure 9B are diagrams showing examples of the IC 10g including polysilicon resistors. Figure 9A and Figure 9B are top views of the IC 10g. Hereinafter, the repeated descriptions of the polysilicon resistors 14a to 14d made with reference to Figure 4A and Figure 5A are omitted.

[0065] Referring to Figure 9A , the IC 10g may include dummy resistors DR1 and DR2 arranged adjacent to the main resistor MR in the second horizontal direction Y. The polysilicon resistors 14a to 14d serving as the main resistor MR may be on the isolation layer 44 and the active regions 106a to 106d and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may include polysilicon resistors 55a to 55d, and the polysilicon resistors 55a to 55d may be on the isolation layer 44 and the active regions 106a to 106d and extend in the first horizontal direction X. The dummy resistors DR1 and DR2 may be provided to prevent the resistance value mismatch of the polysilicon resistors 14a to 14d that may occur due to semiconductor process differences of the main resistor MR.

[0066] Each of the polysilicon resistors 14a to 14d serving as the main resistor MR can have a large resistance value by using a plurality of polysilicon patterns extending in the first horizontal direction X between the contacts 47. The polysilicon resistors 14a to 14d can be realized by a plurality of polysilicon patterns connected in series with each other at the first side S1 and the second side S2 and are disposed on the isolation layer 44 and the active regions 106a to 106d. Among the polysilicon resistors 14a to 14d, the polysilicon resistor 14a is stacked on three active regions 106a, 106b, and 106c in the vertical direction. The polysilicon resistor 14b is stacked on three active regions 106a, 106b, and 106d in the vertical direction. The polysilicon resistor 14c is stacked on three active regions 106a, 106c, and 106d in the vertical direction. The polysilicon resistor 14d is stacked on three active regions 106b, 106c, and 106d in the vertical direction. Each of the polysilicon resistors 14a to 14d can be arranged to be stacked on three of the active regions 106a to 106d in the vertical direction. This arrangement ensures that the polysilicon resistors 14a to 14d have the same surrounding environment to reduce the mismatch between the resistance values of the polysilicon resistors 14a to 14d.

[0067] The active regions 106a to 106d under the polysilicon resistors 14a to 14d may not have electrical connections on the semiconductor substrate 41 and may be cut at least once when extending in the second horizontal direction Y. For example, each of the active regions 106a to 106d may have a first width W1 in the first horizontal direction X. The isolation layer 44 may be formed and disposed in at least one cutting region in each of the active regions 106a to 106d. This means that the leakage current path is blocked by at least one cutting region in each of the active regions 106a to 106d, and since the spacing between the first well region 48a and the second well region 48b and the active regions 106a to 106d can be reduced by blocking the leakage current path, the chip size of the IC 10g can be reduced.

[0068] Refer to Figure 9B As shown in, the active regions 106a to 106d under the polysilicon resistors 14a to 14d have different widths and are cut at least once. For example, each of the active regions 106b and 106d may have a first width W1 and is separated by the isolation layer 44 in the cutting region, and each of the active regions 106a and 106c may have a second width W2 larger than the first width W1 and is separated by the isolation layer 44 in the cutting region.

[0069] Figure 10 is a diagram showing an example of the memory device 500.

[0070] Refer to Figure 10, the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region CELL and a lower chip including a peripheral circuit region PERI may be separately manufactured. Thereafter, at least one upper chip and the lower chip may be connected to each other by a bonding method to implement a C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0071] The memory device 500 may include at least one upper chip including a cell region CELL. For example, as Figure 10 shown, the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI may be separately manufactured, and thereafter, the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined before each of the first upper chip and the second upper chip is flipped. In other words, in Figure 10 , the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion defined based on the -Z axis direction. However, other embodiments are possible. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0072] Each of the peripheral circuit region PERI of the memory device 500 and the first cell region CELL1 and the second cell region CELL2 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0073] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be disposed on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be disposed in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240a, 240b, and 240c may be formed of copper having a relatively low resistivity.

[0074] In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper having a resistivity lower than that of the aluminum of the second metal lines 240a, 240b, and 240c.

[0075] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material (such as, silicon oxide and / or silicon nitride).

[0076] Each of the first unit region CELL1 and the second unit region CELL2 may include at least one memory block. The first unit region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (e.g., the Z-axis direction). String selection lines and ground selection lines may be disposed above and below the word lines 330, and the plurality of word lines 330 may be disposed between the string selection lines and the ground selection lines. Similarly, the second unit region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (e.g., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first unit region CELL1 and the second unit region CELL2.

[0077] In some embodiments, as shown in region "A1" which is an alternative embodiment of region "A", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the word lines 330, the string selection lines, and the ground selection lines. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and is also referred to as a bit line, and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 310.

[0078] In some embodiments, as shown in region "A2" which is an alternative embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH that are connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, due to the characteristics of the manufacturing process, the difficulty of forming a channel with a substantially uniform width may increase. In this example, the memory device 500 includes a channel having improved width uniformity due to the sequentially formed lower channel LCH and upper channel UCH.

[0079] When the channel structure CH includes the lower channel LCH and the upper channel UCH as shown in region "A2", the word lines located near the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. For example, the word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the normal word lines. The level of the voltage applied to the dummy word lines may be different from the level of the voltage applied to the normal word lines, which may reduce the influence of the inconsistent channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0080] In addition, in region "A2", the number of lower word lines (e.g., 331 and 332) penetrated by the lower channel LCH is less than the number of upper word lines (e.g., 333 to 338) penetrated by the upper channel UCH. However, other embodiments are possible. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH provided in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH provided in the first cell region CELL1.

[0081] In the bit line bonding region BLBA, the first through electrode THV1 may be provided in the first cell region CELL1, and the second through electrode THV2 may be provided in the second cell region CELL2. As Figure 10As shown, the first through electrode THV1 can penetrate the common source line 320 and multiple word lines 330. In some embodiments, the first through electrode THV1 can also penetrate the second substrate 310. The first through electrode THV1 can include a conductive material. Optionally, the first through electrode THV1 can include a conductive material surrounded by an insulating material. The second through electrode THV2 can have the same shape and structure as the first through electrode THV1.

[0082] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other through the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d can be formed at the bottom end of the first upper chip including the first unit area CELL1, and the second through metal pattern 472d can be formed at the top end of the second upper chip including the second unit area CELL2. The first through electrode THV1 can be electrically connected to the first metal line 350c and the second metal line 360c. The lower via 371d can be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper via 471d can be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d can be connected to each other by a bonding method.

[0083] In addition, in the bit line bonding area BLBA, the upper metal pattern 252 can be formed in the topmost metal layer of the peripheral circuit area PERI, and the upper metal pattern 392 having the same shape as the upper metal pattern 252 can be formed in the topmost metal layer of the first unit area CELL1. The upper metal pattern 392 in the first unit area CELL1 and the upper metal pattern 252 in the peripheral circuit area PERI can be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 360c can be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 220c in the peripheral circuit area PERI can constitute a page buffer, and the bit line 360c can be electrically connected to the circuit elements 220c constituting the page buffer through the upper bonding metal pattern 370c in the first unit area CELL1 and the upper bonding metal pattern 270c in the peripheral circuit area PERI. In some embodiments, in the bit line bonding area BLBA, the first metal line 450c and the second metal line 460c can be connected to the channel structure CH.

[0084] Referring to Figure 10, in the word line bonding area WLBA, the word line 330 of the first cell area CELL1 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (341 to 347). The first metal line 350b and the second metal line 360b may be sequentially connected to the cell contact plugs 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI.

[0085] The cell contact plugs 340 may be electrically connected to a row decoder included in the peripheral circuit area PERI. For example, some of the circuit elements 220b in the peripheral circuit area PERI may constitute a row decoder, and the cell contact plugs 340 may be electrically connected to the circuit elements 220b constituting the row decoder through the upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI. In some embodiments, the operating voltage of the circuit elements 220b constituting the row decoder may be different from the operating voltage of the circuit elements 220c constituting the page buffer. For example, the operating voltage of the circuit elements 220c constituting the page buffer may be greater than the operating voltage of the circuit elements 220b constituting the row decoder.

[0086] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell area CELL2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower metal pattern, upper metal pattern, and cell contact plug 348 of the first cell area CELL1.

[0087] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0088] In the external pad bonding region PA, the lower metal pattern 371e may be formed in the lower part of the first cell region CELL1, and the upper metal pattern 472a may be formed in the upper part of the second cell region CELL2. In the external pad bonding region PA, the lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other by a bonding method. Similarly, the upper metal pattern 372a may be formed in the upper part of the first cell region CELL1, and the upper metal pattern 272a may be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0089] The common source line contact plugs 380 and 480 may be provided in the external pad bonding region PA. The common source line contact plugs 380 and 480 may be formed of a conductive material such as metal, metal compound, and / or doped polysilicon. The common source line contact plug 380 of the first cell region CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell region CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell region CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell region CELL2.

[0090] The first input / output pad to the third input / output pads 205, 405, and 406 may be provided in the external pad bonding region PA. Refer to Figure 10 , the lower insulating layer 201 covers the bottom surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a provided in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer (not shown) may be provided between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0091] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. The second input / output pad 405 and / or the third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the second input / output contact plugs 403 and 303, and the third input / output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the third input / output contact plugs 404 and 304.

[0092] In some embodiments, the third substrate 410 is not disposed in the region where the input / output contact plugs are provided. For example, as shown in the region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0093] In some embodiments, as shown in the region "B1" which is an alternative embodiment of the region "B", the third input / output contact plug 404 extends in the third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. In other words, the diameter of the channel structure CH described in the region "A1" may gradually decrease toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined to each other by a bonding method.

[0094] In some embodiments, as shown in the region "B2" which is an alternative embodiment of the region "B", the third input / output contact plug 404 may extend in the third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may gradually decrease toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are joined to each other.

[0095] In some embodiments, the input / output contact plug may be stacked with the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in the third direction (e.g., the Z-axis direction) and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure between the second input / output contact plug 403 and the second input / output pad 405 may be implemented by various methods.

[0096] In some embodiments, as shown in region "C1" which is an alternative embodiment of region "C", an opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 403 may gradually increase toward the second input / output pad 405. However, other embodiments are possible, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405.

[0097] In some embodiments, as shown in region "C2" which is an alternative embodiment of region "C", an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Accordingly, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in region "C2", the diameter of the contact 407 may gradually increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually decrease toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are joined to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined to each other.

[0098] In some embodiments, as shown in region "C3" which is an alternative embodiment of region "C", compared to the example in region "C2", the stopper 409 may also be formed on the bottom end of the opening 408 of the third substrate 410. The stopper 409 may be a metal line formed in the same layer as the common source line 420. Optionally, the stopper 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the stopper 409.

[0099] Similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 in the first cell region CELL1 may gradually decrease or gradually increase toward the lower metal pattern 371e.

[0100] In some embodiments, the slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at various positions in the external pad bonding region PA. For example, as shown in region "D", when observed in a plan view, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. Optionally, when observed in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0101] In some embodiments, as shown in region "D1" which is an alternative embodiment of region "D", the slit 411 may be formed to penetrate the third substrate 410. For example, the slit 411 may be used to prevent the third substrate 410 from cracking slightly when the opening 408 is formed. However, other embodiments are possible, and the slit 411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 410.

[0102] In some embodiments, as shown in region "D2" which is an alternative embodiment of region "D", the conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to release the leakage current that occurs when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground wire.

[0103] In some embodiments, as shown in region "D3" which is an alternative embodiment of region "D", an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 413 is formed in the slit 411, the voltage provided through the second input / output pad 405 can be prevented from affecting the metal layer on the third substrate 410 disposed in the word line bonding region WLBA.

[0104] In some embodiments, the first input / output pad to the third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0105] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after removing the substrate. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process between the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process between the first cell region CELL1 and the second cell region CELL2, and then, the upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0106] Figure 11 is a block diagram showing an example of applying a memory to a solid state drive (SSD) system 1000.

[0107] Refer to Figure 11, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may send a signal SIG to the host 1100 and receive the signal SIG from the host 1100 through a signal connector, and receive power PWR from the host 1100 through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices (MEM) 1230, 1240, and 1250. Each of the memory devices 1230, 1240, and 1250 may be a vertically stacked NAND flash memory device. Herein, the SSD 1200 may use the example implementation described above with reference to Figures 1 to 10 In some embodiments, the memory devices 1230, 1240, and 1250 may be connected to the SSD controller 1210 through channels Ch1 to Chn, respectively.

[0108] Figure 12 is a block diagram of a system 2000 showing an example of an electronic device including a memory device.

[0109] Referring to Figure 12 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, input / output (I / O) devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented by a laptop computer, a mobile terminal, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. Optionally, the system 2000 may be implemented by a server or a PC.

[0110] The camera 2100 may capture a static image or a dynamic image according to a user's control, store the captured image / video data therein, or send the captured image / video data to the display 2200. The audio processor 2300 may process audio data included in the content in the flash memories 2600a and 2600b or audio data from a network. The modem 2400 may modulate and send signals for wired / wireless data transmission and reception, and demodulate the signals into original signals on the receiving side. The I / O devices 2700a and 2700b may include devices configured to provide digital input and / or output functions (such as a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, and a touch screen).

[0111] The AP 2800 can control the overall operation of the system 2000. The AP 2800 may include a control block (or controller) 2810, an accelerator block or accelerator chip (or accelerator) 2820, and an interface block (or interface) 2830. The AP 2800 can control the display 2200 to display a part of the content stored in the flash memories 2600a and 2600b on the display 2200. If user input is received through the I / O devices 2700a and 2700b, the AP 2800 can perform a control operation corresponding to the user input. The AP 2800 may include an accelerator chip 2820 as a dedicated circuit for artificial intelligence (AI) data calculation, or the accelerator chip 2820 may be provided separately from the AP 2800. The DRAM 2500b may be additionally installed in the accelerator block or accelerator chip 2820. The accelerator is a functional block configured to execute a specific function of the AP 2800, and may include a graphics processing unit (GPU) as a functional block configured to execute graphics data processing, a neural processing unit (NPU) as a block configured to professionally execute AI calculation and inference, and a data processing unit (DPU) as a block configured to execute data transfer.

[0112] The system 2000 may include multiple DRAMs. The AP 2800 can control the DRAMs 2500a and 2500b according to the Joint Electron Device Engineering Council (JEDEC) standards through a command and mode register set (MRS), or communicate with the DRAMs 2500a and 2500b by setting a DRAM interface protocol to use company-specific functions (such as low voltage / high speed / reliability, etc. and cyclic redundancy check (CRC) / error correction code (ECC) functions). For example, the AP 2800 can communicate with the DRAM 2500a by using an interface that meets the JEDEC standards (such as low power double data rate 4 (LPDDR4) or LPDDR5), and the accelerator block or accelerator chip 2820 can communicate with the DRAM 2500b by setting a new DRAM interface protocol to control the DRAM 2500b having a higher bandwidth than the DRAM 2500a, and the DRAM 2500b is for the accelerator.

[0113] Although Figure 12Only DRAMs 2500a and 2500b are shown, but this example is not limited thereto. Any memory (such as PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM) can be used according to the requirements of the bandwidth, response speed, and voltage conditions of the AP 2800 or the accelerator chip 2820. DRAMs 2500a and 2500b have relatively less latency and relatively smaller bandwidth than the I / O devices 2700a and 2700b or the flash memories 2600a and 2600b. DRAMs 2500a and 2500b can be initialized at the power-on time point of the system 2000 and be used as a temporary storage device for the operating system and application data by loading the operating system and application data thereon, or be used as an execution space for various software codes.

[0114] In DRAMs 2500a and 2500b, four basic arithmetic operations of addition / subtraction / multiplication / division, vector operations, address calculations, or fast Fourier transform (FFT) operations can be performed. Additionally, in DRAMs 2500a and 2500b, functional functions for inference can be executed. Here, inference can be performed by using a deep learning algorithm of an artificial neural network. The deep learning algorithm can include a training operation of training the model with each piece of data and an inference operation of identifying data by using the trained model. In some embodiments, an image captured by the user through the camera 2100 can be signal-processed and stored in DRAM 2500b, and the accelerator block or the accelerator chip 2820 can perform AI data calculations for identifying data by using the data stored in DRAM 2500b and the function for inference.

[0115] The system 2000 can include multiple storage devices or flash memories 2600a and 2600b having a larger capacity than DRAMs 2500a and 2500b. The accelerator block or the accelerator chip 2820 can perform a training operation and AI data calculations by using the flash memories 2600a and 2600b. In some embodiments, each of the flash memories 2600a and 2600b can include a memory controller 2610 and a flash memory device 2620, and can relatively efficiently perform the training operation and the inference AI data calculations to be performed by the AP 2800 and / or the accelerator chip 2820 by using the computing device included in the memory controller 2610. The flash memories 2600a and 2600b can store pictures taken through the camera 2100 or data received through a data network. For example, augmented reality / virtual reality, high definition (HD), or ultra-high definition (UHD) content can be stored in the flash memories 2600a and 2600b.

[0116] The components of the system 2000 can include referring to Figures 1 to 9BThe described polysilicon resistor. The polysilicon resistor may extend in a second direction perpendicular to a first direction in which an active region extends, and may be on the active region and the isolation layer. Each of the polysilicon resistors on the active region may be configured such that the number of active regions stacked vertically with each polysilicon resistor is equivalent. Each of the active regions under the polysilicon resistor may be cut at least once in the first direction such that the isolation layer is between the cut portions. When a first well region and a second well region of a second conductivity type are disposed adjacent to the periphery of the polysilicon resistor on the upper surface of a semiconductor substrate of a first conductivity type, each of the active regions among the active regions under the polysilicon resistor that are stacked with the first well region and the second well region in the first direction may be cut at least once in the first direction such that the isolation layer is between the cut portions. A dummy polysilicon resistor on the upper surface of the semiconductor substrate may be disposed adjacent to the periphery of the polysilicon resistor on both sides of the polysilicon resistor in the first direction. Accordingly, a mismatch in the resistance value of the polysilicon resistor can be prevented, and a leakage current path can be blocked to reduce the pitch between circuit devices, thereby reducing the chip size of the IC.

[0117] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope that can be claimed. The specific features described in the context of separate implementations in the present disclosure can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately or in any suitable sub-combination in multiple implementations. In addition, although the features may be described above as acting in a specific combination, in some cases one or more features from the combination may be deleted from the combination, and the combination may be directed to a sub-combination or a variant of the sub-combination.

Claims

1. An integrated circuit, comprising: A semiconductor substrate; A plurality of active regions, on the upper surface of the semiconductor substrate and extending in a first direction; An isolation layer, on the upper surface of the semiconductor substrate and defining the boundaries of the plurality of active regions, and electrically isolating the plurality of active regions; And A plurality of polysilicon resistors, on both the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to the first direction, Wherein, the same number of active regions are stacked vertically with each of the plurality of polysilicon resistors.

2. The integrated circuit according to claim 1, wherein Each of the plurality of active regions under the plurality of polysilicon resistors includes: At least one discontinuous portion, such that the isolation layer is between the at least one discontinuous portion of each of the plurality of active regions in the first direction.

3. The integrated circuit according to claim 1, further comprising: Dummy polysilicon resistors, on the upper surface of the semiconductor substrate and adjacent to the periphery of the plurality of polysilicon resistors in the first direction.

4. The integrated circuit according to claim 3, wherein, The dummy polysilicon resistors are electrically isolated from the semiconductor substrate.

5. The integrated circuit according to any one of claims 1 to 4, wherein, The plurality of active regions include: A first active region and a second active region, the first active region having a first width in the second direction, the second active region having a second width in the second direction, and the plurality of polysilicon resistors are disposed on the first active region and the second active region.

6. The integrated circuit according to claim 5, wherein, The first width of the first active region is the same as the second width of the second active region.

7. The integrated circuit according to claim 5, wherein, The first width of the first active region is different from the second width of the second active region.

8. An integrated circuit, comprising: A semiconductor substrate of a first conductivity type; A plurality of active regions, on the upper surface of the semiconductor substrate and extending in a first direction; An isolation layer, on the upper surface of the semiconductor substrate, the isolation layer electrically isolating the plurality of active regions and defining the boundaries of the plurality of active regions; A plurality of polysilicon resistors, on the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to the first direction; And A well region of a second conductivity type, on the upper surface of the semiconductor substrate and disposed adjacent to the plurality of active regions, the well region including: A first well region, disposed on a first side of the well region in the first direction; and A second well region, disposed on a second side of the well region in the first direction, Wherein, the plurality of active regions under the plurality of polysilicon resistors include: A plurality of first active regions, stacked with the first well region and the second well region in the first direction; and A plurality of second active regions, as the remaining active regions among the plurality of active regions, and each of the plurality of first active regions is discontinuous, such that the isolation layer is disposed between the discontinuous portions of the plurality of first active regions in the first direction.

9. The integrated circuit according to claim 8, wherein, The same number of active regions are stacked vertically with each of the plurality of polysilicon resistors.

10. The integrated circuit according to claim 8, wherein, The plurality of second active regions under the plurality of polysilicon resistors are continuous in the first direction and have no isolation layer.

11. The integrated circuit according to claim 8, further comprising: Dummy polysilicon resistors, on the upper surface of the semiconductor substrate and adjacent to the periphery of the plurality of polysilicon resistors in a first direction.

12. The integrated circuit according to claim 11, wherein, The dummy polysilicon resistors are electrically isolated from the semiconductor substrate.

13. The integrated circuit according to claim 8, wherein, The plurality of first active regions and the plurality of second active regions have the same width in a second direction.

14. The integrated circuit according to claim 8, wherein, The plurality of first active regions have different widths in a second direction, and the plurality of second active regions have different widths in a second direction.

15. An integrated circuit, comprising: A semiconductor substrate; A plurality of active regions, on the upper surface of the semiconductor substrate and extending in a first direction; An isolation layer, on the upper surface of the semiconductor substrate, electrically isolating the plurality of active regions and defining the boundaries of the plurality of active regions; A plurality of polysilicon resistors, on the plurality of active regions and the isolation layer, the plurality of polysilicon resistors extending in a second direction perpendicular to the first direction; And A plurality of dummy polysilicon resistors, disposed on the upper surface of the semiconductor substrate at the periphery of the plurality of polysilicon resistors and adjacent to both sides of the plurality of polysilicon resistors in a first direction, Wherein, each of the plurality of active regions under the plurality of polysilicon resistors and the plurality of dummy polysilicon resistors includes: At least one discontinuous portion such that the isolation layer is disposed between the at least one discontinuous portion in a first direction.

16. The integrated circuit according to claim 15, wherein, The same number of active regions are stacked vertically with each of the plurality of polysilicon resistors.

17. The integrated circuit according to claim 15, wherein, The plurality of dummy polysilicon resistors are electrically isolated from the semiconductor substrate.

18. The integrated circuit according to any one of claims 15 to 17, wherein, The plurality of active regions include: a first active region and a second active region, the first active region having a first width in a second direction, the second active region having a second width in a second direction, and the plurality of polysilicon resistors are disposed on the first active region and the second active region.

19. The integrated circuit according to claim 18, wherein, The first width of the first active region is the same as the second width of the second active region.

20. The integrated circuit according to claim 18, wherein, The first width of the first active region is different from the second width of the second active region.

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